added blank project folder

blank/.gitignore

@@ -0,0 +1 @@
+build/*

blank/Makefile

@@ -0,0 +1,26 @@
+# Project setup
+PROJ      = blank
+BUILD     = ./build
+DEVICE    = 8k
+FOOTPRINT = ct256
+
+# Files
+FILES = top.v
+
+.PHONY: all clean burn
+
+all:
+	# if build folder doesn't exist, create it
+	mkdir -p $(BUILD)
+	# synthesize using Yosys
+	yosys -p "synth_ice40 -top top -blif $(BUILD)/$(PROJ).blif" $(FILES)
+	# Place and route using arachne
+	arachne-pnr -d $(DEVICE) -P $(FOOTPRINT) -o $(BUILD)/$(PROJ).asc -p pinmap.pcf $(BUILD)/$(PROJ).blif
+	# Convert to bitstream using IcePack
+	icepack $(BUILD)/$(PROJ).asc $(BUILD)/$(PROJ).bin
+
+burn:
+	iceprog $(BUILD)/$(PROJ).bin
+
+clean:
+	rm build/*

blank/pinmap.pcf

@@ -0,0 +1,10 @@
+# example.pcf
+set_io --warn-no-port led1 B5
+set_io --warn-no-port led2 B4
+set_io --warn-no-port led3 A2
+set_io --warn-no-port led4 A1
+set_io --warn-no-port led5 C5
+set_io --warn-no-port led6 C4
+set_io --warn-no-port led7 B3
+set_io --warn-no-port led8 C3
+set_io --warn-no-port hwclk J3

blank/top.v

@@ -0,0 +1,15 @@
+// Blink an LED provided an input clock
+/* module */
+module top (hwclk, led1, led2, led3, led4, led5, led6, led7, led8 );
+    /* I/O */
+    input hwclk;
+    output led1;
+    output led2;
+    output led3;
+    output led4;
+    output led5;
+    output led6;
+    output led7;
+    output led8;
+
+endmodule