diff --git a/src/coreneuron/apps/main1.cpp b/src/coreneuron/apps/main1.cpp
index 8d2e0ca688..8d3db49c63 100644
--- a/src/coreneuron/apps/main1.cpp
+++ b/src/coreneuron/apps/main1.cpp
@@ -274,11 +274,6 @@ void nrn_init_and_load_data(int argc,
         report_mem_usage("After nrn_setup ");
     }
 
-    // Invoke PatternStim
-    if (!corenrn_param.patternstim.empty()) {
-        nrn_mkPatternStim(corenrn_param.patternstim.c_str(), corenrn_param.tstop);
-    }
-
     /// Setting the timeout
     nrn_set_timeout(200.);
 
@@ -311,11 +306,17 @@ void nrn_init_and_load_data(int argc,
         // all final state, including the event queue will be sent back
         // to NEURON. Here there is some first time only
         // initialization and queue transfer.
-        direct_mode_initialize();
+        // Transfer PatternStim from NEURON only when input is not specified by --pattern.
+        direct_mode_initialize(corenrn_param.patternstim.empty());
         clear_spike_vectors();  // PreSyn send already recorded by NEURON
         (*nrn2core_part2_clean_)();
     }
 
+    // Invoke PatternStim
+    if (!corenrn_param.patternstim.empty()) {
+        nrn_mkPatternStim(corenrn_param.patternstim.c_str(), corenrn_param.tstop);
+    }
+
     if (corenrn_param.gpu) {
         // Copy nrnthreads to device only after all the data are passed from NEURON and the
         // nrnthreads on CPU are properly set up
@@ -636,7 +637,7 @@ extern "C" int run_solve_core(int argc, char** argv) {
     }
 
     if (corenrn_embedded) {
-        core2nrn_data_return();
+        core2nrn_data_return(corenrn_param.patternstim.empty());
     }
 
     {
diff --git a/src/coreneuron/io/core2nrn_data_return.cpp b/src/coreneuron/io/core2nrn_data_return.cpp
index 1ec5fc5201..c557242e98 100644
--- a/src/coreneuron/io/core2nrn_data_return.cpp
+++ b/src/coreneuron/io/core2nrn_data_return.cpp
@@ -302,7 +302,7 @@ static void core2nrn_vecplay();
  *  Copies t, voltage, i_membrane_ if it used, and mechanism param data.
  *  Copies event queue and related state, e.g. WATCH, VecPlayContinuous.
  */
-void core2nrn_data_return() {
+void core2nrn_data_return(bool return_patternstim) {
     if (!nrn2core_type_return_) {
         return;
     }
@@ -331,8 +331,12 @@ void core2nrn_data_return() {
             }
         }
 
+        int patstimtype = nrn_get_mechtype("PatternStim");
         for (NrnThreadMembList* tml = nt.tml; tml; tml = tml->next) {
             int mtype = tml->index;
+            if (!return_patternstim && mtype == patstimtype) {
+                continue;
+            }
             Memb_list* ml = tml->ml;
             n = (*nrn2core_type_return_)(mtype, tid, data, mdata);
             assert(n == size_t(ml->nodecount) && !mdata.empty());
diff --git a/src/coreneuron/io/core2nrn_data_return.hpp b/src/coreneuron/io/core2nrn_data_return.hpp
index 2d731ad9b7..e1424406d0 100644
--- a/src/coreneuron/io/core2nrn_data_return.hpp
+++ b/src/coreneuron/io/core2nrn_data_return.hpp
@@ -14,7 +14,7 @@ namespace coreneuron {
     I.e. voltage, i_membrane_, mechanism data, event queue, WATCH state,
     Play state, etc.
  */
-extern void core2nrn_data_return();
+extern void core2nrn_data_return(bool return_patternstim = true);
 
 /** @brief return first and last datum indices of WATCH statements
  */
diff --git a/src/coreneuron/io/nrn2core_data_init.cpp b/src/coreneuron/io/nrn2core_data_init.cpp
index fc7dba43ff..ba8d6eab6f 100644
--- a/src/coreneuron/io/nrn2core_data_init.cpp
+++ b/src/coreneuron/io/nrn2core_data_init.cpp
@@ -47,7 +47,7 @@ void (*nrn2core_transfer_watch_)(void (*cb)(int, int, int, int, int));
   nrn_finitialize above but without changing any simulation data. We follow
   some of the strategy of checkpoint_initialize.
 **/
-void direct_mode_initialize() {
+void direct_mode_initialize(bool send_patternstim) {
     dt2thread(-1.);
     nrn_thread_table_check();
 
@@ -90,7 +90,9 @@ void direct_mode_initialize() {
         nrn2core_PreSyn_flag_receive(tid);
     }
 
-    nrn2core_patstim_share_info();
+    if (send_patternstim) {
+        nrn2core_patstim_share_info();
+    }
 
     nrn2core_tqueue();
 }
diff --git a/src/coreneuron/sim/multicore.hpp b/src/coreneuron/sim/multicore.hpp
index 27d6569a50..95f358245e 100644
--- a/src/coreneuron/sim/multicore.hpp
+++ b/src/coreneuron/sim/multicore.hpp
@@ -190,7 +190,7 @@ extern void nrn_fixed_step_group_minimal(int total_sim_steps);
 extern void nrn_fixed_single_steps_minimal(int total_sim_steps, double tstop);
 extern void nrn_fixed_step_minimal(void);
 extern void nrn_finitialize(int setv, double v);
-extern void direct_mode_initialize();
+extern void direct_mode_initialize(bool send_patternstim = true);
 extern void nrn_mk_table_check(void);
 extern void nonvint(NrnThread* _nt);
 extern void update(NrnThread*);