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S6LX9 FPGA Build: Trigger Jitter #72
There appears to be some trigger jitter from the AES core. The jitter is a full AES core clock cycle (NOT the ADC clock which may be 4x the AES/FPGA core clock).
This happened on the CW305 example sometimes, but seems more prevalent with the LX9 build, leading me to think it's the AES core (as the CW305 has a totally different register interface). There are some other cores can try with instead, for now suggest using resync on traces.