Skip to content
Permalink
Branch: master
Find file Copy path
Find file Copy path
Fetching contributors…
Cannot retrieve contributors at this time
6695 lines (5989 sloc) 539 KB
use zero::std_types::*;
/*
* STM32F4XX Interrupt Number Definition, according to the selected device
* in Library_configuration_section
*/
pub type Enum_IRQn = c_int;
macro_rules! NonMaskableInt_IRQn {() => (-14 as c_int);}
macro_rules! MemoryManagement_IRQn {() => (-12 as c_int);}
macro_rules! BusFault_IRQn {() => (-11 as c_int);}
macro_rules! UsageFault_IRQn {() => (-10 as c_int);}
macro_rules! SVCall_IRQn {() => (-5 as c_int);}
macro_rules! DebugMonitor_IRQn {() => (-4 as c_int);}
macro_rules! PendSV_IRQn {() => (-2 as c_int);}
macro_rules! SysTick_IRQn {() => (-1 as c_int);}
macro_rules! WWDG_IRQn {() => (0 as c_int);}
macro_rules! PVD_IRQn {() => (1 as c_int);}
macro_rules! TAMP_STAMP_IRQn {() => (2 as c_int);}
macro_rules! RTC_WKUP_IRQn {() => (3 as c_int);}
macro_rules! FLASH_IRQn {() => (4 as c_int);}
macro_rules! RCC_IRQn {() => (5 as c_int);}
macro_rules! EXTI0_IRQn {() => (6 as c_int);}
macro_rules! EXTI1_IRQn {() => (7 as c_int);}
macro_rules! EXTI2_IRQn {() => (8 as c_int);}
macro_rules! EXTI3_IRQn {() => (9 as c_int);}
macro_rules! EXTI4_IRQn {() => (10 as c_int);}
macro_rules! DMA1_Stream0_IRQn {() => (11 as c_int);}
macro_rules! DMA1_Stream1_IRQn {() => (12 as c_int);}
macro_rules! DMA1_Stream2_IRQn {() => (13 as c_int);}
macro_rules! DMA1_Stream3_IRQn {() => (14 as c_int);}
macro_rules! DMA1_Stream4_IRQn {() => (15 as c_int);}
macro_rules! DMA1_Stream5_IRQn {() => (16 as c_int);}
macro_rules! DMA1_Stream6_IRQn {() => (17 as c_int);}
macro_rules! ADC_IRQn {() => (18 as c_int);}
macro_rules! CAN1_TX_IRQn {() => (19 as c_int);}
macro_rules! CAN1_RX0_IRQn {() => (20 as c_int);}
macro_rules! CAN1_RX1_IRQn {() => (21 as c_int);}
macro_rules! CAN1_SCE_IRQn {() => (22 as c_int);}
macro_rules! EXTI9_5_IRQn {() => (23 as c_int);}
macro_rules! TIM1_BRK_TIM9_IRQn {() => (24 as c_int);}
macro_rules! TIM1_UP_TIM10_IRQn {() => (25 as c_int);}
macro_rules! TIM1_TRG_COM_TIM11_IRQn {() => (26 as c_int);}
macro_rules! TIM1_CC_IRQn {() => (27 as c_int);}
macro_rules! TIM2_IRQn {() => (28 as c_int);}
macro_rules! TIM3_IRQn {() => (29 as c_int);}
macro_rules! TIM4_IRQn {() => (30 as c_int);}
macro_rules! I2C1_EV_IRQn {() => (31 as c_int);}
macro_rules! I2C1_ER_IRQn {() => (32 as c_int);}
macro_rules! I2C2_EV_IRQn {() => (33 as c_int);}
macro_rules! I2C2_ER_IRQn {() => (34 as c_int);}
macro_rules! SPI1_IRQn {() => (35 as c_int);}
macro_rules! SPI2_IRQn {() => (36 as c_int);}
macro_rules! USART1_IRQn {() => (37 as c_int);}
macro_rules! USART2_IRQn {() => (38 as c_int);}
macro_rules! USART3_IRQn {() => (39 as c_int);}
macro_rules! EXTI15_10_IRQn {() => (40 as c_int);}
macro_rules! RTC_Alarm_IRQn {() => (41 as c_int);}
macro_rules! OTG_FS_WKUP_IRQn {() => (42 as c_int);}
macro_rules! TIM8_BRK_TIM12_IRQn {() => (43 as c_int);}
macro_rules! TIM8_UP_TIM13_IRQn {() => (44 as c_int);}
macro_rules! TIM8_TRG_COM_TIM14_IRQn {() => (45 as c_int);}
macro_rules! TIM8_CC_IRQn {() => (46 as c_int);}
macro_rules! DMA1_Stream7_IRQn {() => (47 as c_int);}
macro_rules! FSMC_IRQn {() => (48 as c_int);}
macro_rules! SDIO_IRQn {() => (49 as c_int);}
macro_rules! TIM5_IRQn {() => (50 as c_int);}
macro_rules! SPI3_IRQn {() => (51 as c_int);}
macro_rules! UART4_IRQn {() => (52 as c_int);}
macro_rules! UART5_IRQn {() => (53 as c_int);}
macro_rules! TIM6_DAC_IRQn {() => (54 as c_int);}
macro_rules! TIM7_IRQn {() => (55 as c_int);}
macro_rules! DMA2_Stream0_IRQn {() => (56 as c_int);}
macro_rules! DMA2_Stream1_IRQn {() => (57 as c_int);}
macro_rules! DMA2_Stream2_IRQn {() => (58 as c_int);}
macro_rules! DMA2_Stream3_IRQn {() => (59 as c_int);}
macro_rules! DMA2_Stream4_IRQn {() => (60 as c_int);}
macro_rules! ETH_IRQn {() => (61 as c_int);}
macro_rules! ETH_WKUP_IRQn {() => (62 as c_int);}
macro_rules! CAN2_TX_IRQn {() => (63 as c_int);}
macro_rules! CAN2_RX0_IRQn {() => (64 as c_int);}
macro_rules! CAN2_RX1_IRQn {() => (65 as c_int);}
macro_rules! CAN2_SCE_IRQn {() => (66 as c_int);}
macro_rules! OTG_FS_IRQn {() => (67 as c_int);}
macro_rules! DMA2_Stream5_IRQn {() => (68 as c_int);}
macro_rules! DMA2_Stream6_IRQn {() => (69 as c_int);}
macro_rules! DMA2_Stream7_IRQn {() => (70 as c_int);}
macro_rules! USART6_IRQn {() => (71 as c_int);}
macro_rules! I2C3_EV_IRQn {() => (72 as c_int);}
macro_rules! I2C3_ER_IRQn {() => (73 as c_int);}
macro_rules! OTG_HS_EP1_OUT_IRQn {() => (74 as c_int);}
macro_rules! OTG_HS_EP1_IN_IRQn {() => (75 as c_int);}
macro_rules! OTG_HS_WKUP_IRQn {() => (76 as c_int);}
macro_rules! OTG_HS_IRQn {() => (77 as c_int);}
macro_rules! DCMI_IRQn {() => (78 as c_int);}
macro_rules! CRYP_IRQn {() => (79 as c_int);}
macro_rules! HASH_RNG_IRQn {() => (80 as c_int);}
macro_rules! FPU_IRQn {() => (81 as c_int);}
pub type IRQn_Type = Enum_IRQn;
pub type int32_t = c_int;
pub type int16_t = c_short;
pub type int8_t = c_schar;
pub type uint16_t = c_ushort;
pub type uint8_t = c_uchar;
pub type s32 = int32_t;
pub type s16 = int16_t;
pub type s8 = int8_t;
pub type sc32 = int32_t;
pub type sc16 = int16_t;
pub type sc8 = int8_t;
pub type vs32 = int32_t;
pub type vs16 = int16_t;
pub type vs8 = int8_t;
pub type vsc32 = int32_t;
pub type vsc16 = int16_t;
pub type vsc8 = int8_t;
pub type _u32 = uint32_t;
pub type _u16 = uint16_t;
pub type _u8 = uint8_t;
pub type uc32 = uint32_t;
pub type uc16 = uint16_t;
pub type uc8 = uint8_t;
pub type vu32 = uint32_t;
pub type vu16 = uint16_t;
pub type vu8 = uint8_t;
pub type vuc32 = uint32_t;
pub type vuc16 = uint16_t;
pub type vuc8 = uint8_t;
pub type FlagStatus = c_uint;
macro_rules! RESET {() => (0 as c_uint);}
macro_rules! SET {() => (1 as c_uint);}
pub type ITStatus = FlagStatus;
pub type FunctionalState = c_uint;
macro_rules! DISABLE {() => (0 as c_uint);}
macro_rules! ENABLE {() => (1 as c_uint);}
pub type ErrorStatus = c_uint;
macro_rules! ERROR {() => (0 as c_uint);}
macro_rules! SUCCESS {() => (1 as c_uint);}
pub struct ADCType {
pub SR: uint32_t,
pub CR1: uint32_t,
pub CR2: uint32_t,
pub SMPR1: uint32_t,
pub SMPR2: uint32_t,
pub JOFR1: uint32_t,
pub JOFR2: uint32_t,
pub JOFR3: uint32_t,
pub JOFR4: uint32_t,
pub HTR: uint32_t,
pub LTR: uint32_t,
pub SQR1: uint32_t,
pub SQR2: uint32_t,
pub SQR3: uint32_t,
pub JSQR: uint32_t,
pub JDR1: uint32_t,
pub JDR2: uint32_t,
pub JDR3: uint32_t,
pub JDR4: uint32_t,
pub DR: uint32_t,
}
pub struct ADC_CommonType {
pub CSR: uint32_t,
pub CCR: uint32_t,
pub CDR: uint32_t,
}
pub struct CAN_TxMailBoxType {
pub TIR: uint32_t,
pub TDTR: uint32_t,
pub TDLR: uint32_t,
pub TDHR: uint32_t,
}
pub struct CAN_FIFOMailBoxType {
pub RIR: uint32_t,
pub RDTR: uint32_t,
pub RDLR: uint32_t,
pub RDHR: uint32_t,
}
pub struct CAN_FilterRegisterType {
pub FR1: uint32_t,
pub FR2: uint32_t,
}
pub struct CANType {
pub MCR: uint32_t,
pub MSR: uint32_t,
pub TSR: uint32_t,
pub RF0R: uint32_t,
pub RF1R: uint32_t,
pub IER: uint32_t,
pub ESR: uint32_t,
pub BTR: uint32_t,
pub RESERVED0: [uint32_t; 88],
pub sTxMailBox: [CAN_TxMailBoxType; 3],
pub sFIFOMailBox: [CAN_FIFOMailBoxType; 2],
pub RESERVED1: [uint32_t; 12],
pub FMR: uint32_t,
pub FM1R: uint32_t,
pub RESERVED2: uint32_t,
pub FS1R: uint32_t,
pub RESERVED3: uint32_t,
pub FFA1R: uint32_t,
pub RESERVED4: uint32_t,
pub FA1R: uint32_t,
pub RESERVED5: [uint32_t; 8],
pub sFilterRegister: [CAN_FilterRegisterType; 28],
}
pub struct CRCType {
pub DR: uint32_t,
pub IDR: uint8_t,
pub RESERVED0: uint8_t,
pub RESERVED1: uint16_t,
pub CR: uint32_t,
}
pub struct DACType {
pub CR: uint32_t,
pub SWTRIGR: uint32_t,
pub DHR12R1: uint32_t,
pub DHR12L1: uint32_t,
pub DHR8R1: uint32_t,
pub DHR12R2: uint32_t,
pub DHR12L2: uint32_t,
pub DHR8R2: uint32_t,
pub DHR12RD: uint32_t,
pub DHR12LD: uint32_t,
pub DHR8RD: uint32_t,
pub DOR1: uint32_t,
pub DOR2: uint32_t,
pub SR: uint32_t,
}
pub struct DBGMCUType {
pub IDCODE: uint32_t,
pub CR: uint32_t,
pub APB1FZ: uint32_t,
pub APB2FZ: uint32_t,
}
pub struct DCMIType {
pub CR: uint32_t,
pub SR: uint32_t,
pub RISR: uint32_t,
pub IER: uint32_t,
pub MISR: uint32_t,
pub ICR: uint32_t,
pub ESCR: uint32_t,
pub ESUR: uint32_t,
pub CWSTRTR: uint32_t,
pub CWSIZER: uint32_t,
pub DR: uint32_t,
}
pub struct DMA_StreamType {
pub CR: uint32_t,
pub NDTR: uint32_t,
pub PAR: uint32_t,
pub M0AR: uint32_t,
pub M1AR: uint32_t,
pub FCR: uint32_t,
}
pub struct DMAType {
pub LISR: uint32_t,
pub HISR: uint32_t,
pub LIFCR: uint32_t,
pub HIFCR: uint32_t,
}
pub struct ETHType {
pub MACCR: uint32_t,
pub MACFFR: uint32_t,
pub MACHTHR: uint32_t,
pub MACHTLR: uint32_t,
pub MACMIIAR: uint32_t,
pub MACMIIDR: uint32_t,
pub MACFCR: uint32_t,
pub MACVLANTR: uint32_t,
pub RESERVED0: [uint32_t; 2],
pub MACRWUFFR: uint32_t,
pub MACPMTCSR: uint32_t,
pub RESERVED1: [uint32_t; 2],
pub MACSR: uint32_t,
pub MACIMR: uint32_t,
pub MACA0HR: uint32_t,
pub MACA0LR: uint32_t,
pub MACA1HR: uint32_t,
pub MACA1LR: uint32_t,
pub MACA2HR: uint32_t,
pub MACA2LR: uint32_t,
pub MACA3HR: uint32_t,
pub MACA3LR: uint32_t,
pub RESERVED2: [uint32_t; 40],
pub MMCCR: uint32_t,
pub MMCRIR: uint32_t,
pub MMCTIR: uint32_t,
pub MMCRIMR: uint32_t,
pub MMCTIMR: uint32_t,
pub RESERVED3: [uint32_t; 14],
pub MMCTGFSCCR: uint32_t,
pub MMCTGFMSCCR: uint32_t,
pub RESERVED4: [uint32_t; 5],
pub MMCTGFCR: uint32_t,
pub RESERVED5: [uint32_t; 10],
pub MMCRFCECR: uint32_t,
pub MMCRFAECR: uint32_t,
pub RESERVED6: [uint32_t; 10],
pub MMCRGUFCR: uint32_t,
pub RESERVED7: [uint32_t; 334],
pub PTPTSCR: uint32_t,
pub PTPSSIR: uint32_t,
pub PTPTSHR: uint32_t,
pub PTPTSLR: uint32_t,
pub PTPTSHUR: uint32_t,
pub PTPTSLUR: uint32_t,
pub PTPTSAR: uint32_t,
pub PTPTTHR: uint32_t,
pub PTPTTLR: uint32_t,
pub RESERVED8: uint32_t,
pub PTPTSSR: uint32_t,
pub RESERVED9: [uint32_t; 565],
pub DMABMR: uint32_t,
pub DMATPDR: uint32_t,
pub DMARPDR: uint32_t,
pub DMARDLAR: uint32_t,
pub DMATDLAR: uint32_t,
pub DMASR: uint32_t,
pub DMAOMR: uint32_t,
pub DMAIER: uint32_t,
pub DMAMFBOCR: uint32_t,
pub DMARSWTR: uint32_t,
pub RESERVED10: [uint32_t; 8],
pub DMACHTDR: uint32_t,
pub DMACHRDR: uint32_t,
pub DMACHTBAR: uint32_t,
pub DMACHRBAR: uint32_t,
}
pub struct EXTIType {
pub IMR: uint32_t,
pub EMR: uint32_t,
pub RTSR: uint32_t,
pub FTSR: uint32_t,
pub SWIER: uint32_t,
pub PR: uint32_t,
}
pub struct FLASHType {
pub ACR: uint32_t,
pub KEYR: uint32_t,
pub OPTKEYR: uint32_t,
pub SR: uint32_t,
pub CR: uint32_t,
pub OPTCR: uint32_t,
}
pub struct FSMC_Bank1Type {
pub BTCR: [uint32_t; 8],
}
pub struct FSMC_Bank1EType {
pub BWTR: [uint32_t; 7],
}
pub struct FSMC_Bank2Type {
pub PCR2: uint32_t,
pub SR2: uint32_t,
pub PMEM2: uint32_t,
pub PATT2: uint32_t,
pub RESERVED0: uint32_t,
pub ECCR2: uint32_t,
}
pub struct FSMC_Bank3Type {
pub PCR3: uint32_t,
pub SR3: uint32_t,
pub PMEM3: uint32_t,
pub PATT3: uint32_t,
pub RESERVED0: uint32_t,
pub ECCR3: uint32_t,
}
pub struct FSMC_Bank4Type {
pub PCR4: uint32_t,
pub SR4: uint32_t,
pub PMEM4: uint32_t,
pub PATT4: uint32_t,
pub PIO4: uint32_t,
}
pub struct GPIOType {
pub MODER: uint32_t,
pub OTYPER: uint32_t,
pub OSPEEDR: uint32_t,
pub PUPDR: uint32_t,
pub IDR: uint32_t,
pub ODR: uint32_t,
pub BSRRL: uint16_t,
pub BSRRH: uint16_t,
pub LCKR: uint32_t,
pub AFR: [uint32_t; 2],
}
pub struct SYSCFGType {
pub MEMRMP: uint32_t,
pub PMC: uint32_t,
pub EXTICR: [uint32_t; 4],
pub RESERVED: [uint32_t; 2],
pub CMPCR: uint32_t,
}
pub struct I2CType {
pub CR1: uint16_t,
pub RESERVED0: uint16_t,
pub CR2: uint16_t,
pub RESERVED1: uint16_t,
pub OAR1: uint16_t,
pub RESERVED2: uint16_t,
pub OAR2: uint16_t,
pub RESERVED3: uint16_t,
pub DR: uint16_t,
pub RESERVED4: uint16_t,
pub SR1: uint16_t,
pub RESERVED5: uint16_t,
pub SR2: uint16_t,
pub RESERVED6: uint16_t,
pub CCR: uint16_t,
pub RESERVED7: uint16_t,
pub TRISE: uint16_t,
pub RESERVED8: uint16_t,
}
pub struct IWDGType {
pub KR: uint32_t,
pub PR: uint32_t,
pub RLR: uint32_t,
pub SR: uint32_t,
}
pub struct PWRType {
pub CR: uint32_t,
pub CSR: uint32_t,
}
pub struct RCCType {
pub CR: uint32_t,
pub PLLCFGR: uint32_t,
pub CFGR: uint32_t,
pub CIR: uint32_t,
pub AHB1RSTR: uint32_t,
pub AHB2RSTR: uint32_t,
pub AHB3RSTR: uint32_t,
pub RESERVED0: uint32_t,
pub APB1RSTR: uint32_t,
pub APB2RSTR: uint32_t,
pub RESERVED1: [uint32_t; 2],
pub AHB1ENR: uint32_t,
pub AHB2ENR: uint32_t,
pub AHB3ENR: uint32_t,
pub RESERVED2: uint32_t,
pub APB1ENR: uint32_t,
pub APB2ENR: uint32_t,
pub RESERVED3: [uint32_t; 2],
pub AHB1LPENR: uint32_t,
pub AHB2LPENR: uint32_t,
pub AHB3LPENR: uint32_t,
pub RESERVED4: uint32_t,
pub APB1LPENR: uint32_t,
pub APB2LPENR: uint32_t,
pub RESERVED5: [uint32_t; 2],
pub BDCR: uint32_t,
pub CSR: uint32_t,
pub RESERVED6: [uint32_t; 2],
pub SSCGR: uint32_t,
pub PLLI2SCFGR: uint32_t,
}
pub struct RTCType {
pub TR: uint32_t,
pub DR: uint32_t,
pub CR: uint32_t,
pub ISR: uint32_t,
pub PRER: uint32_t,
pub WUTR: uint32_t,
pub CALIBR: uint32_t,
pub ALRMAR: uint32_t,
pub ALRMBR: uint32_t,
pub WPR: uint32_t,
pub SSR: uint32_t,
pub SHIFTR: uint32_t,
pub TSTR: uint32_t,
pub TSDR: uint32_t,
pub TSSSR: uint32_t,
pub CALR: uint32_t,
pub TAFCR: uint32_t,
pub ALRMASSR: uint32_t,
pub ALRMBSSR: uint32_t,
pub RESERVED7: uint32_t,
pub BKP0R: uint32_t,
pub BKP1R: uint32_t,
pub BKP2R: uint32_t,
pub BKP3R: uint32_t,
pub BKP4R: uint32_t,
pub BKP5R: uint32_t,
pub BKP6R: uint32_t,
pub BKP7R: uint32_t,
pub BKP8R: uint32_t,
pub BKP9R: uint32_t,
pub BKP10R: uint32_t,
pub BKP11R: uint32_t,
pub BKP12R: uint32_t,
pub BKP13R: uint32_t,
pub BKP14R: uint32_t,
pub BKP15R: uint32_t,
pub BKP16R: uint32_t,
pub BKP17R: uint32_t,
pub BKP18R: uint32_t,
pub BKP19R: uint32_t,
}
pub struct SDIOType {
pub POWER: uint32_t,
pub CLKCR: uint32_t,
pub ARG: uint32_t,
pub CMD: uint32_t,
pub RESPCMD: uint32_t,
pub RESP1: uint32_t,
pub RESP2: uint32_t,
pub RESP3: uint32_t,
pub RESP4: uint32_t,
pub DTIMER: uint32_t,
pub DLEN: uint32_t,
pub DCTRL: uint32_t,
pub DCOUNT: uint32_t,
pub STA: uint32_t,
pub ICR: uint32_t,
pub MASK: uint32_t,
pub RESERVED0: [uint32_t; 2],
pub FIFOCNT: uint32_t,
pub RESERVED1: [uint32_t; 13],
pub FIFO: uint32_t,
}
pub struct SPIType {
pub CR1: uint16_t,
pub RESERVED0: uint16_t,
pub CR2: uint16_t,
pub RESERVED1: uint16_t,
pub SR: uint16_t,
pub RESERVED2: uint16_t,
pub DR: uint16_t,
pub RESERVED3: uint16_t,
pub CRCPR: uint16_t,
pub RESERVED4: uint16_t,
pub RXCRCR: uint16_t,
pub RESERVED5: uint16_t,
pub TXCRCR: uint16_t,
pub RESERVED6: uint16_t,
pub I2SCFGR: uint16_t,
pub RESERVED7: uint16_t,
pub I2SPR: uint16_t,
pub RESERVED8: uint16_t,
}
pub struct TIMType {
pub CR1: uint16_t,
pub RESERVED0: uint16_t,
pub CR2: uint16_t,
pub RESERVED1: uint16_t,
pub SMCR: uint16_t,
pub RESERVED2: uint16_t,
pub DIER: uint16_t,
pub RESERVED3: uint16_t,
pub SR: uint16_t,
pub RESERVED4: uint16_t,
pub EGR: uint16_t,
pub RESERVED5: uint16_t,
pub CCMR1: uint16_t,
pub RESERVED6: uint16_t,
pub CCMR2: uint16_t,
pub RESERVED7: uint16_t,
pub CCER: uint16_t,
pub RESERVED8: uint16_t,
pub CNT: uint32_t,
pub PSC: uint16_t,
pub RESERVED9: uint16_t,
pub ARR: uint32_t,
pub RCR: uint16_t,
pub RESERVED10: uint16_t,
pub CCR1: uint32_t,
pub CCR2: uint32_t,
pub CCR3: uint32_t,
pub CCR4: uint32_t,
pub BDTR: uint16_t,
pub RESERVED11: uint16_t,
pub DCR: uint16_t,
pub RESERVED12: uint16_t,
pub DMAR: uint16_t,
pub RESERVED13: uint16_t,
pub OR: uint16_t,
pub RESERVED14: uint16_t,
}
pub struct USARTType {
pub SR: uint16_t,
pub RESERVED0: uint16_t,
pub DR: uint16_t,
pub RESERVED1: uint16_t,
pub BRR: uint16_t,
pub RESERVED2: uint16_t,
pub CR1: uint16_t,
pub RESERVED3: uint16_t,
pub CR2: uint16_t,
pub RESERVED4: uint16_t,
pub CR3: uint16_t,
pub RESERVED5: uint16_t,
pub GTPR: uint16_t,
pub RESERVED6: uint16_t,
}
pub struct WWDGType {
pub CR: uint32_t,
pub CFR: uint32_t,
pub SR: uint32_t,
}
pub struct CRYPType {
pub CR: uint32_t,
pub SR: uint32_t,
pub DR: uint32_t,
pub DOUT: uint32_t,
pub DMACR: uint32_t,
pub IMSCR: uint32_t,
pub RISR: uint32_t,
pub MISR: uint32_t,
pub K0LR: uint32_t,
pub K0RR: uint32_t,
pub K1LR: uint32_t,
pub K1RR: uint32_t,
pub K2LR: uint32_t,
pub K2RR: uint32_t,
pub K3LR: uint32_t,
pub K3RR: uint32_t,
pub IV0LR: uint32_t,
pub IV0RR: uint32_t,
pub IV1LR: uint32_t,
pub IV1RR: uint32_t,
}
pub struct HASHType {
pub CR: uint32_t,
pub DIN: uint32_t,
pub STR: uint32_t,
pub HR: [uint32_t; 5],
pub IMR: uint32_t,
pub SR: uint32_t,
pub RESERVED: [uint32_t; 52],
pub CSR: [uint32_t; 51],
}
pub struct RNGType {
pub CR: uint32_t,
pub SR: uint32_t,
pub DR: uint32_t,
}
/*Peripheral_memory_map */
macro_rules! FLASH_BASE {() => (0x08000000u32 as uint32_t);}
macro_rules! FLASH_BASE {() => (0x08000000u32 as uint32_t);} /*< FLASH(up to 1 MB) base address in the alias region */
macro_rules! CCMDATARAM_BASE {() => (0x10000000u32 as uint32_t);} /*< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
macro_rules! SRAM1_BASE {() => (0x20000000u32 as uint32_t);} /*< SRAM1(112 KB) base address in the alias region */
macro_rules! SRAM2_BASE {() => (0x2001C000u32 as uint32_t);} /*< SRAM2(16 KB) base address in the alias region */
macro_rules! PERIPH_BASE {() => (0x40000000u32 as uint32_t);} /*< Peripheral base address in the alias region */
macro_rules! BKPSRAM_BASE {() => (0x40024000u32 as uint32_t);} /*< Backup SRAM(4 KB) base address in the alias region */
macro_rules! FSMC_R_BASE {() => (0xA0000000u32 as uint32_t);} /*< FSMC registers base address */
macro_rules! CCMDATARAM_BB_BASE {() => (0x12000000u32 as uint32_t);} /*< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
macro_rules! SRAM1_BB_BASE {() => (0x22000000u32 as uint32_t);} /*< SRAM1(112 KB) base address in the bit-band region */
macro_rules! SRAM2_BB_BASE {() => (0x2201C000u32 as uint32_t);} /*< SRAM2(16 KB) base address in the bit-band region */
macro_rules! PERIPH_BB_BASE {() => (0x42000000u32 as uint32_t);} /*< Peripheral base address in the bit-band region */
macro_rules! BKPSRAM_BB_BASE {() => (0x42024000u32 as uint32_t);} /*< Backup SRAM(4 KB) base address in the bit-band region */
/* Legacy defines */
macro_rules! SRAM_BASE {() => (SRAM1_BASE!());}
macro_rules! SRAM_BB_BASE {() => (SRAM1_BB_BASE!());}
/*< Peripheral memory map */
macro_rules! APB1PERIPH_BASE {() => (PERIPH_BASE!());}
macro_rules! APB2PERIPH_BASE {() => (PERIPH_BASE!() + 0x00010000u32);}
macro_rules! AHB1PERIPH_BASE {() => (PERIPH_BASE!() + 0x00020000u32);}
macro_rules! AHB2PERIPH_BASE {() => (PERIPH_BASE!() + 0x10000000u32);}
/*< APB1 peripherals */
macro_rules! TIM2_BASE {() => (APB1PERIPH_BASE!() + 0x0000u32);}
macro_rules! TIM3_BASE {() => (APB1PERIPH_BASE!() + 0x0400u32);}
macro_rules! TIM4_BASE {() => (APB1PERIPH_BASE!() + 0x0800u32);}
macro_rules! TIM5_BASE {() => (APB1PERIPH_BASE!() + 0x0C00u32);}
macro_rules! TIM6_BASE {() => (APB1PERIPH_BASE!() + 0x1000u32);}
macro_rules! TIM7_BASE {() => (APB1PERIPH_BASE!() + 0x1400u32);}
macro_rules! TIM12_BASE {() => (APB1PERIPH_BASE!() + 0x1800u32);}
macro_rules! TIM13_BASE {() => (APB1PERIPH_BASE!() + 0x1C00u32);}
macro_rules! TIM14_BASE {() => (APB1PERIPH_BASE!() + 0x2000u32);}
macro_rules! RTC_BASE {() => (APB1PERIPH_BASE!() + 0x2800u32);}
macro_rules! WWDG_BASE {() => (APB1PERIPH_BASE!() + 0x2C00u32);}
macro_rules! IWDG_BASE {() => (APB1PERIPH_BASE!() + 0x3000u32);}
macro_rules! I2S2ext_BASE {() => (APB1PERIPH_BASE!() + 0x3400u32);}
macro_rules! SPI2_BASE {() => (APB1PERIPH_BASE!() + 0x3800u32);}
macro_rules! SPI3_BASE {() => (APB1PERIPH_BASE!() + 0x3C00u32);}
macro_rules! I2S3ext_BASE {() => (APB1PERIPH_BASE!() + 0x4000u32);}
macro_rules! USART2_BASE {() => (APB1PERIPH_BASE!() + 0x4400u32);}
macro_rules! USART3_BASE {() => (APB1PERIPH_BASE!() + 0x4800u32);}
macro_rules! UART4_BASE {() => (APB1PERIPH_BASE!() + 0x4C00u32);}
macro_rules! UART5_BASE {() => (APB1PERIPH_BASE!() + 0x5000u32);}
macro_rules! I2C1_BASE {() => (APB1PERIPH_BASE!() + 0x5400u32);}
macro_rules! I2C2_BASE {() => (APB1PERIPH_BASE!() + 0x5800u32);}
macro_rules! I2C3_BASE {() => (APB1PERIPH_BASE!() + 0x5C00u32);}
macro_rules! CAN1_BASE {() => (APB1PERIPH_BASE!() + 0x6400u32);}
macro_rules! CAN2_BASE {() => (APB1PERIPH_BASE!() + 0x6800u32);}
macro_rules! PWR_BASE {() => (APB1PERIPH_BASE!() + 0x7000u32);}
macro_rules! DAC_BASE {() => (APB1PERIPH_BASE!() + 0x7400u32);}
/*< APB2 peripherals */
macro_rules! TIM1_BASE {() => (APB2PERIPH_BASE!() + 0x0000u32);}
macro_rules! TIM8_BASE {() => (APB2PERIPH_BASE!() + 0x0400u32);}
macro_rules! USART1_BASE {() => (APB2PERIPH_BASE!() + 0x1000u32);}
macro_rules! USART6_BASE {() => (APB2PERIPH_BASE!() + 0x1400u32);}
macro_rules! ADC1_BASE {() => (APB2PERIPH_BASE!() + 0x2000u32);}
macro_rules! ADC2_BASE {() => (APB2PERIPH_BASE!() + 0x2100u32);}
macro_rules! ADC3_BASE {() => (APB2PERIPH_BASE!() + 0x2200u32);}
macro_rules! ADC_BASE {() => (APB2PERIPH_BASE!() + 0x2300u32);}
macro_rules! SDIO_BASE {() => (APB2PERIPH_BASE!() + 0x2C00u32);}
macro_rules! SPI1_BASE {() => (APB2PERIPH_BASE!() + 0x3000u32);}
macro_rules! SYSCFG_BASE {() => (APB2PERIPH_BASE!() + 0x3800u32);}
macro_rules! EXTI_BASE {() => (APB2PERIPH_BASE!() + 0x3C00u32);}
macro_rules! TIM9_BASE {() => (APB2PERIPH_BASE!() + 0x4000u32);}
macro_rules! TIM10_BASE {() => (APB2PERIPH_BASE!() + 0x4400u32);}
macro_rules! TIM11_BASE {() => (APB2PERIPH_BASE!() + 0x4800u32);}
/*< AHB1 peripherals */
macro_rules! GPIOA_BASE {() => (AHB1PERIPH_BASE!() + 0x0000u32);}
macro_rules! GPIOB_BASE {() => (AHB1PERIPH_BASE!() + 0x0400u32);}
macro_rules! GPIOC_BASE {() => (AHB1PERIPH_BASE!() + 0x0800u32);}
macro_rules! GPIOD_BASE {() => (AHB1PERIPH_BASE!() + 0x0C00u32);}
macro_rules! GPIOE_BASE {() => (AHB1PERIPH_BASE!() + 0x1000u32);}
macro_rules! GPIOF_BASE {() => (AHB1PERIPH_BASE!() + 0x1400u32);}
macro_rules! GPIOG_BASE {() => (AHB1PERIPH_BASE!() + 0x1800u32);}
macro_rules! GPIOH_BASE {() => (AHB1PERIPH_BASE!() + 0x1C00u32);}
macro_rules! GPIOI_BASE {() => (AHB1PERIPH_BASE!() + 0x2000u32);}
macro_rules! CRC_BASE {() => (AHB1PERIPH_BASE!() + 0x3000u32);}
macro_rules! RCC_BASE {() => (AHB1PERIPH_BASE!() + 0x3800u32);}
macro_rules! FLASH_R_BASE {() => (AHB1PERIPH_BASE!() + 0x3C00u32);}
macro_rules! DMA1_BASE {() => (AHB1PERIPH_BASE!() + 0x6000u32);}
macro_rules! DMA1_Stream0_BASE {() => (DMA1_BASE!() + 0x010u32);}
macro_rules! DMA1_Stream1_BASE {() => (DMA1_BASE!() + 0x028u32);}
macro_rules! DMA1_Stream2_BASE {() => (DMA1_BASE!() + 0x040u32);}
macro_rules! DMA1_Stream3_BASE {() => (DMA1_BASE!() + 0x058u32);}
macro_rules! DMA1_Stream4_BASE {() => (DMA1_BASE!() + 0x070u32);}
macro_rules! DMA1_Stream5_BASE {() => (DMA1_BASE!() + 0x088u32);}
macro_rules! DMA1_Stream6_BASE {() => (DMA1_BASE!() + 0x0A0u32);}
macro_rules! DMA1_Stream7_BASE {() => (DMA1_BASE!() + 0x0B8u32);}
macro_rules! DMA2_BASE {() => (AHB1PERIPH_BASE!() + 0x6400u32);}
macro_rules! DMA2_Stream0_BASE {() => (DMA2_BASE!() + 0x010u32);}
macro_rules! DMA2_Stream1_BASE {() => (DMA2_BASE!() + 0x028u32);}
macro_rules! DMA2_Stream2_BASE {() => (DMA2_BASE!() + 0x040u32);}
macro_rules! DMA2_Stream3_BASE {() => (DMA2_BASE!() + 0x058u32);}
macro_rules! DMA2_Stream4_BASE {() => (DMA2_BASE!() + 0x070u32);}
macro_rules! DMA2_Stream5_BASE {() => (DMA2_BASE!() + 0x088u32);}
macro_rules! DMA2_Stream6_BASE {() => (DMA2_BASE!() + 0x0A0u32);}
macro_rules! DMA2_Stream7_BASE {() => (DMA2_BASE!() + 0x0B8u32);}
macro_rules! ETH_BASE {() => (AHB1PERIPH_BASE!() + 0x8000u32);}
macro_rules! ETH_MAC_BASE {() => (ETH_BASE!());}
macro_rules! ETH_MMC_BASE {() => (ETH_BASE!() + 0x0100u32);}
macro_rules! ETH_PTP_BASE {() => (ETH_BASE!() + 0x0700u32);}
macro_rules! ETH_DMA_BASE {() => (ETH_BASE!() + 0x1000u32);}
/*< AHB2 peripherals */
macro_rules! DCMI_BASE {() => (AHB2PERIPH_BASE!() + 0x50000u32);}
macro_rules! CRYP_BASE {() => (AHB2PERIPH_BASE!() + 0x60000u32);}
macro_rules! HASH_BASE {() => (AHB2PERIPH_BASE!() + 0x60400u32);}
macro_rules! RNG_BASE {() => (AHB2PERIPH_BASE!() + 0x60800u32);}
/*< FSMC Bankx registers base address */
macro_rules! FSMC_Bank1_R_BASE {() => (FSMC_R_BASE!() + 0x0000u32);}
macro_rules! FSMC_Bank1E_R_BASE {() => (FSMC_R_BASE!() + 0x0104u32);}
macro_rules! FSMC_Bank2_R_BASE {() => (FSMC_R_BASE!() + 0x0060u32);}
macro_rules! FSMC_Bank3_R_BASE {() => (FSMC_R_BASE!() + 0x0080u32);}
macro_rules! FSMC_Bank4_R_BASE {() => (FSMC_R_BASE!() + 0x00A0u32);}
/* Debug MCU registers base address */
macro_rules! DBGMCU_BASE {() => (0xE0042000u32 as uint32_t);}
/* Exported_constants
*/
/* Peripheral_Registers_Bits_Definition
*/
/*
* Peripheral Registers_Bits_Definition
*/
/*
*Analog to Digital Converter
*/
/* Bit definition for ADC_SR register */
macro_rules! ADC_SR_AWD {() => (0x01u8 as uint8_t);} /*<Analog watchdog flag */
macro_rules! ADC_SR_EOC {() => (0x02u8 as uint8_t);} /*<End of conversion */
macro_rules! ADC_SR_JEOC {() => (0x04u8 as uint8_t);} /*<Injected channel end of conversion */
macro_rules! ADC_SR_JSTRT {() => (0x08u8 as uint8_t);} /*<Injected channel Start flag */
macro_rules! ADC_SR_STRT {() => (0x10u8 as uint8_t);} /*<Regular channel Start flag */
macro_rules! ADC_SR_OVR {() => (0x20u8 as uint8_t);} /*<Overrun flag */
/* Bit definition for ADC_CR1 register */
macro_rules! ADC_CR1_AWDCH {() => (0x0000001Fu32 as uint32_t);} /*<AWDCH[4:0] bits (Analog watchdog channel select bits) */
macro_rules! ADC_CR1_AWDCH_0 {() => (0x00000001u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_CR1_AWDCH_1 {() => (0x00000002u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_CR1_AWDCH_2 {() => (0x00000004u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_CR1_AWDCH_3 {() => (0x00000008u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_CR1_AWDCH_4 {() => (0x00000010u32 as uint32_t);} /*<Bit 4 */
macro_rules! ADC_CR1_EOCIE {() => (0x00000020u32 as uint32_t);} /*<Interrupt enable for EOC */
macro_rules! ADC_CR1_AWDIE {() => (0x00000040u32 as uint32_t);} /*<AAnalog Watchdog interrupt enable */
macro_rules! ADC_CR1_JEOCIE {() => (0x00000080u32 as uint32_t);} /*<Interrupt enable for injected channels */
macro_rules! ADC_CR1_SCAN {() => (0x00000100u32 as uint32_t);} /*<Scan mode */
macro_rules! ADC_CR1_AWDSGL {() => (0x00000200u32 as uint32_t);} /*<Enable the watchdog on a single channel in scan mode */
macro_rules! ADC_CR1_JAUTO {() => (0x00000400u32 as uint32_t);} /*<Automatic injected group conversion */
macro_rules! ADC_CR1_DISCEN {() => (0x00000800u32 as uint32_t);} /*<Discontinuous mode on regular channels */
macro_rules! ADC_CR1_JDISCEN {() => (0x00001000u32 as uint32_t);} /*<Discontinuous mode on injected channels */
macro_rules! ADC_CR1_DISCNUM {() => (0x0000E000u32 as uint32_t);} /*<DISCNUM[2:0] bits (Discontinuous mode channel count) */
macro_rules! ADC_CR1_DISCNUM_0 {() => (0x00002000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_CR1_DISCNUM_1 {() => (0x00004000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_CR1_DISCNUM_2 {() => (0x00008000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_CR1_JAWDEN {() => (0x00400000u32 as uint32_t);} /*<Analog watchdog enable on injected channels */
macro_rules! ADC_CR1_AWDEN {() => (0x00800000u32 as uint32_t);} /*<Analog watchdog enable on regular channels */
macro_rules! ADC_CR1_RES {() => (0x03000000u32 as uint32_t);} /*<RES[2:0] bits (Resolution) */
macro_rules! ADC_CR1_RES_0 {() => (0x01000000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_CR1_RES_1 {() => (0x02000000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_CR1_OVRIE {() => (0x04000000u32 as uint32_t);} /*<overrun interrupt enable */
/* Bit definition for ADC_CR2 register */
macro_rules! ADC_CR2_ADON {() => (0x00000001u32 as uint32_t);} /*<A/D Converter ON / OFF */
macro_rules! ADC_CR2_CONT {() => (0x00000002u32 as uint32_t);} /*<Continuous Conversion */
macro_rules! ADC_CR2_DMA {() => (0x00000100u32 as uint32_t);} /*<Direct Memory access mode */
macro_rules! ADC_CR2_DDS {() => (0x00000200u32 as uint32_t);} /*<DMA disable selection (Single ADC) */
macro_rules! ADC_CR2_EOCS {() => (0x00000400u32 as uint32_t);} /*<End of conversion selection */
macro_rules! ADC_CR2_ALIGN {() => (0x00000800u32 as uint32_t);} /*<Data Alignment */
macro_rules! ADC_CR2_JEXTSEL {() => (0x000F0000u32 as uint32_t);} /*<JEXTSEL[3:0] bits (External event select for injected group) */
macro_rules! ADC_CR2_JEXTSEL_0 {() => (0x00010000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_CR2_JEXTSEL_1 {() => (0x00020000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_CR2_JEXTSEL_2 {() => (0x00040000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_CR2_JEXTSEL_3 {() => (0x00080000u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_CR2_JEXTEN {() => (0x00300000u32 as uint32_t);} /*<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
macro_rules! ADC_CR2_JEXTEN_0 {() => (0x00100000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_CR2_JEXTEN_1 {() => (0x00200000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_CR2_JSWSTART {() => (0x00400000u32 as uint32_t);} /*<Start Conversion of injected channels */
macro_rules! ADC_CR2_EXTSEL {() => (0x0F000000u32 as uint32_t);} /*<EXTSEL[3:0] bits (External Event Select for regular group) */
macro_rules! ADC_CR2_EXTSEL_0 {() => (0x01000000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_CR2_EXTSEL_1 {() => (0x02000000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_CR2_EXTSEL_2 {() => (0x04000000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_CR2_EXTSEL_3 {() => (0x08000000u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_CR2_EXTEN {() => (0x30000000u32 as uint32_t);} /*<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
macro_rules! ADC_CR2_EXTEN_0 {() => (0x10000000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_CR2_EXTEN_1 {() => (0x20000000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_CR2_SWSTART {() => (0x40000000u32 as uint32_t);} /*<Start Conversion of regular channels */
/* Bit definition for ADC_SMPR1 register */
macro_rules! ADC_SMPR1_SMP10 {() => (0x00000007u32 as uint32_t);} /*<SMP10[2:0] bits (Channel 10 Sample time selection) */
macro_rules! ADC_SMPR1_SMP10_0 {() => (0x00000001u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SMPR1_SMP10_1 {() => (0x00000002u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SMPR1_SMP10_2 {() => (0x00000004u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SMPR1_SMP11 {() => (0x00000038u32 as uint32_t);} /*<SMP11[2:0] bits (Channel 11 Sample time selection) */
macro_rules! ADC_SMPR1_SMP11_0 {() => (0x00000008u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SMPR1_SMP11_1 {() => (0x00000010u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SMPR1_SMP11_2 {() => (0x00000020u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SMPR1_SMP12 {() => (0x000001C0u32 as uint32_t);} /*<SMP12[2:0] bits (Channel 12 Sample time selection) */
macro_rules! ADC_SMPR1_SMP12_0 {() => (0x00000040u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SMPR1_SMP12_1 {() => (0x00000080u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SMPR1_SMP12_2 {() => (0x00000100u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SMPR1_SMP13 {() => (0x00000E00u32 as uint32_t);} /*<SMP13[2:0] bits (Channel 13 Sample time selection) */
macro_rules! ADC_SMPR1_SMP13_0 {() => (0x00000200u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SMPR1_SMP13_1 {() => (0x00000400u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SMPR1_SMP13_2 {() => (0x00000800u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SMPR1_SMP14 {() => (0x00007000u32 as uint32_t);} /*<SMP14[2:0] bits (Channel 14 Sample time selection) */
macro_rules! ADC_SMPR1_SMP14_0 {() => (0x00001000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SMPR1_SMP14_1 {() => (0x00002000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SMPR1_SMP14_2 {() => (0x00004000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SMPR1_SMP15 {() => (0x00038000u32 as uint32_t);} /*<SMP15[2:0] bits (Channel 15 Sample time selection) */
macro_rules! ADC_SMPR1_SMP15_0 {() => (0x00008000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SMPR1_SMP15_1 {() => (0x00010000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SMPR1_SMP15_2 {() => (0x00020000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SMPR1_SMP16 {() => (0x001C0000u32 as uint32_t);} /*<SMP16[2:0] bits (Channel 16 Sample time selection) */
macro_rules! ADC_SMPR1_SMP16_0 {() => (0x00040000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SMPR1_SMP16_1 {() => (0x00080000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SMPR1_SMP16_2 {() => (0x00100000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SMPR1_SMP17 {() => (0x00E00000u32 as uint32_t);} /*<SMP17[2:0] bits (Channel 17 Sample time selection) */
macro_rules! ADC_SMPR1_SMP17_0 {() => (0x00200000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SMPR1_SMP17_1 {() => (0x00400000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SMPR1_SMP17_2 {() => (0x00800000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SMPR1_SMP18 {() => (0x07000000u32 as uint32_t);} /*<SMP18[2:0] bits (Channel 18 Sample time selection) */
macro_rules! ADC_SMPR1_SMP18_0 {() => (0x01000000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SMPR1_SMP18_1 {() => (0x02000000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SMPR1_SMP18_2 {() => (0x04000000u32 as uint32_t);} /*<Bit 2 */
/* Bit definition for ADC_SMPR2 register */
macro_rules! ADC_SMPR2_SMP0 {() => (0x00000007u32 as uint32_t);} /*<SMP0[2:0] bits (Channel 0 Sample time selection) */
macro_rules! ADC_SMPR2_SMP0_0 {() => (0x00000001u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SMPR2_SMP0_1 {() => (0x00000002u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SMPR2_SMP0_2 {() => (0x00000004u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SMPR2_SMP1 {() => (0x00000038u32 as uint32_t);} /*<SMP1[2:0] bits (Channel 1 Sample time selection) */
macro_rules! ADC_SMPR2_SMP1_0 {() => (0x00000008u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SMPR2_SMP1_1 {() => (0x00000010u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SMPR2_SMP1_2 {() => (0x00000020u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SMPR2_SMP2 {() => (0x000001C0u32 as uint32_t);} /*<SMP2[2:0] bits (Channel 2 Sample time selection) */
macro_rules! ADC_SMPR2_SMP2_0 {() => (0x00000040u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SMPR2_SMP2_1 {() => (0x00000080u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SMPR2_SMP2_2 {() => (0x00000100u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SMPR2_SMP3 {() => (0x00000E00u32 as uint32_t);} /*<SMP3[2:0] bits (Channel 3 Sample time selection) */
macro_rules! ADC_SMPR2_SMP3_0 {() => (0x00000200u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SMPR2_SMP3_1 {() => (0x00000400u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SMPR2_SMP3_2 {() => (0x00000800u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SMPR2_SMP4 {() => (0x00007000u32 as uint32_t);} /*<SMP4[2:0] bits (Channel 4 Sample time selection) */
macro_rules! ADC_SMPR2_SMP4_0 {() => (0x00001000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SMPR2_SMP4_1 {() => (0x00002000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SMPR2_SMP4_2 {() => (0x00004000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SMPR2_SMP5 {() => (0x00038000u32 as uint32_t);} /*<SMP5[2:0] bits (Channel 5 Sample time selection) */
macro_rules! ADC_SMPR2_SMP5_0 {() => (0x00008000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SMPR2_SMP5_1 {() => (0x00010000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SMPR2_SMP5_2 {() => (0x00020000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SMPR2_SMP6 {() => (0x001C0000u32 as uint32_t);} /*<SMP6[2:0] bits (Channel 6 Sample time selection) */
macro_rules! ADC_SMPR2_SMP6_0 {() => (0x00040000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SMPR2_SMP6_1 {() => (0x00080000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SMPR2_SMP6_2 {() => (0x00100000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SMPR2_SMP7 {() => (0x00E00000u32 as uint32_t);} /*<SMP7[2:0] bits (Channel 7 Sample time selection) */
macro_rules! ADC_SMPR2_SMP7_0 {() => (0x00200000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SMPR2_SMP7_1 {() => (0x00400000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SMPR2_SMP7_2 {() => (0x00800000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SMPR2_SMP8 {() => (0x07000000u32 as uint32_t);} /*<SMP8[2:0] bits (Channel 8 Sample time selection) */
macro_rules! ADC_SMPR2_SMP8_0 {() => (0x01000000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SMPR2_SMP8_1 {() => (0x02000000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SMPR2_SMP8_2 {() => (0x04000000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SMPR2_SMP9 {() => (0x38000000u32 as uint32_t);} /*<SMP9[2:0] bits (Channel 9 Sample time selection) */
macro_rules! ADC_SMPR2_SMP9_0 {() => (0x08000000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SMPR2_SMP9_1 {() => (0x10000000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SMPR2_SMP9_2 {() => (0x20000000u32 as uint32_t);} /*<Bit 2 */
/* Bit definition for ADC_JOFR1 register */
macro_rules! ADC_JOFR1_JOFFSET1 {() => (0x0FFFu16 as uint16_t);} /*<Data offset for injected channel 1 */
/* Bit definition for ADC_JOFR2 register */
macro_rules! ADC_JOFR2_JOFFSET2 {() => (0x0FFFu16 as uint16_t);} /*<Data offset for injected channel 2 */
/* Bit definition for ADC_JOFR3 register */
macro_rules! ADC_JOFR3_JOFFSET3 {() => (0x0FFFu16 as uint16_t);} /*<Data offset for injected channel 3 */
/* Bit definition for ADC_JOFR4 register */
macro_rules! ADC_JOFR4_JOFFSET4 {() => (0x0FFFu16 as uint16_t);} /*<Data offset for injected channel 4 */
/* Bit definition for ADC_HTR register */
macro_rules! ADC_HTR_HT {() => (0x0FFFu16 as uint16_t);} /*<Analog watchdog high threshold */
/* Bit definition for ADC_LTR register */
macro_rules! ADC_LTR_LT {() => (0x0FFFu16 as uint16_t);} /*<Analog watchdog low threshold */
/* Bit definition for ADC_SQR1 register */
macro_rules! ADC_SQR1_SQ13 {() => (0x0000001Fu32 as uint32_t);} /*<SQ13[4:0] bits (13th conversion in regular sequence) */
macro_rules! ADC_SQR1_SQ13_0 {() => (0x00000001u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SQR1_SQ13_1 {() => (0x00000002u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SQR1_SQ13_2 {() => (0x00000004u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SQR1_SQ13_3 {() => (0x00000008u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_SQR1_SQ13_4 {() => (0x00000010u32 as uint32_t);} /*<Bit 4 */
macro_rules! ADC_SQR1_SQ14 {() => (0x000003E0u32 as uint32_t);} /*<SQ14[4:0] bits (14th conversion in regular sequence) */
macro_rules! ADC_SQR1_SQ14_0 {() => (0x00000020u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SQR1_SQ14_1 {() => (0x00000040u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SQR1_SQ14_2 {() => (0x00000080u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SQR1_SQ14_3 {() => (0x00000100u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_SQR1_SQ14_4 {() => (0x00000200u32 as uint32_t);} /*<Bit 4 */
macro_rules! ADC_SQR1_SQ15 {() => (0x00007C00u32 as uint32_t);} /*<SQ15[4:0] bits (15th conversion in regular sequence) */
macro_rules! ADC_SQR1_SQ15_0 {() => (0x00000400u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SQR1_SQ15_1 {() => (0x00000800u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SQR1_SQ15_2 {() => (0x00001000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SQR1_SQ15_3 {() => (0x00002000u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_SQR1_SQ15_4 {() => (0x00004000u32 as uint32_t);} /*<Bit 4 */
macro_rules! ADC_SQR1_SQ16 {() => (0x000F8000u32 as uint32_t);} /*<SQ16[4:0] bits (16th conversion in regular sequence) */
macro_rules! ADC_SQR1_SQ16_0 {() => (0x00008000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SQR1_SQ16_1 {() => (0x00010000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SQR1_SQ16_2 {() => (0x00020000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SQR1_SQ16_3 {() => (0x00040000u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_SQR1_SQ16_4 {() => (0x00080000u32 as uint32_t);} /*<Bit 4 */
macro_rules! ADC_SQR1_L {() => (0x00F00000u32 as uint32_t);} /*<L[3:0] bits (Regular channel sequence length) */
macro_rules! ADC_SQR1_L_0 {() => (0x00100000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SQR1_L_1 {() => (0x00200000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SQR1_L_2 {() => (0x00400000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SQR1_L_3 {() => (0x00800000u32 as uint32_t);} /*<Bit 3 */
/* Bit definition for ADC_SQR2 register */
macro_rules! ADC_SQR2_SQ7 {() => (0x0000001Fu32 as uint32_t);} /*<SQ7[4:0] bits (7th conversion in regular sequence) */
macro_rules! ADC_SQR2_SQ7_0 {() => (0x00000001u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SQR2_SQ7_1 {() => (0x00000002u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SQR2_SQ7_2 {() => (0x00000004u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SQR2_SQ7_3 {() => (0x00000008u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_SQR2_SQ7_4 {() => (0x00000010u32 as uint32_t);} /*<Bit 4 */
macro_rules! ADC_SQR2_SQ8 {() => (0x000003E0u32 as uint32_t);} /*<SQ8[4:0] bits (8th conversion in regular sequence) */
macro_rules! ADC_SQR2_SQ8_0 {() => (0x00000020u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SQR2_SQ8_1 {() => (0x00000040u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SQR2_SQ8_2 {() => (0x00000080u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SQR2_SQ8_3 {() => (0x00000100u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_SQR2_SQ8_4 {() => (0x00000200u32 as uint32_t);} /*<Bit 4 */
macro_rules! ADC_SQR2_SQ9 {() => (0x00007C00u32 as uint32_t);} /*<SQ9[4:0] bits (9th conversion in regular sequence) */
macro_rules! ADC_SQR2_SQ9_0 {() => (0x00000400u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SQR2_SQ9_1 {() => (0x00000800u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SQR2_SQ9_2 {() => (0x00001000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SQR2_SQ9_3 {() => (0x00002000u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_SQR2_SQ9_4 {() => (0x00004000u32 as uint32_t);} /*<Bit 4 */
macro_rules! ADC_SQR2_SQ10 {() => (0x000F8000u32 as uint32_t);} /*<SQ10[4:0] bits (10th conversion in regular sequence) */
macro_rules! ADC_SQR2_SQ10_0 {() => (0x00008000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SQR2_SQ10_1 {() => (0x00010000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SQR2_SQ10_2 {() => (0x00020000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SQR2_SQ10_3 {() => (0x00040000u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_SQR2_SQ10_4 {() => (0x00080000u32 as uint32_t);} /*<Bit 4 */
macro_rules! ADC_SQR2_SQ11 {() => (0x01F00000u32 as uint32_t);} /*<SQ11[4:0] bits (11th conversion in regular sequence) */
macro_rules! ADC_SQR2_SQ11_0 {() => (0x00100000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SQR2_SQ11_1 {() => (0x00200000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SQR2_SQ11_2 {() => (0x00400000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SQR2_SQ11_3 {() => (0x00800000u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_SQR2_SQ11_4 {() => (0x01000000u32 as uint32_t);} /*<Bit 4 */
macro_rules! ADC_SQR2_SQ12 {() => (0x3E000000u32 as uint32_t);} /*<SQ12[4:0] bits (12th conversion in regular sequence) */
macro_rules! ADC_SQR2_SQ12_0 {() => (0x02000000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SQR2_SQ12_1 {() => (0x04000000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SQR2_SQ12_2 {() => (0x08000000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SQR2_SQ12_3 {() => (0x10000000u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_SQR2_SQ12_4 {() => (0x20000000u32 as uint32_t);} /*<Bit 4 */
/* Bit definition for ADC_SQR3 register */
macro_rules! ADC_SQR3_SQ1 {() => (0x0000001Fu32 as uint32_t);} /*<SQ1[4:0] bits (1st conversion in regular sequence) */
macro_rules! ADC_SQR3_SQ1_0 {() => (0x00000001u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SQR3_SQ1_1 {() => (0x00000002u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SQR3_SQ1_2 {() => (0x00000004u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SQR3_SQ1_3 {() => (0x00000008u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_SQR3_SQ1_4 {() => (0x00000010u32 as uint32_t);} /*<Bit 4 */
macro_rules! ADC_SQR3_SQ2 {() => (0x000003E0u32 as uint32_t);} /*<SQ2[4:0] bits (2nd conversion in regular sequence) */
macro_rules! ADC_SQR3_SQ2_0 {() => (0x00000020u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SQR3_SQ2_1 {() => (0x00000040u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SQR3_SQ2_2 {() => (0x00000080u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SQR3_SQ2_3 {() => (0x00000100u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_SQR3_SQ2_4 {() => (0x00000200u32 as uint32_t);} /*<Bit 4 */
macro_rules! ADC_SQR3_SQ3 {() => (0x00007C00u32 as uint32_t);} /*<SQ3[4:0] bits (3rd conversion in regular sequence) */
macro_rules! ADC_SQR3_SQ3_0 {() => (0x00000400u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SQR3_SQ3_1 {() => (0x00000800u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SQR3_SQ3_2 {() => (0x00001000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SQR3_SQ3_3 {() => (0x00002000u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_SQR3_SQ3_4 {() => (0x00004000u32 as uint32_t);} /*<Bit 4 */
macro_rules! ADC_SQR3_SQ4 {() => (0x000F8000u32 as uint32_t);} /*<SQ4[4:0] bits (4th conversion in regular sequence) */
macro_rules! ADC_SQR3_SQ4_0 {() => (0x00008000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SQR3_SQ4_1 {() => (0x00010000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SQR3_SQ4_2 {() => (0x00020000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SQR3_SQ4_3 {() => (0x00040000u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_SQR3_SQ4_4 {() => (0x00080000u32 as uint32_t);} /*<Bit 4 */
macro_rules! ADC_SQR3_SQ5 {() => (0x01F00000u32 as uint32_t);} /*<SQ5[4:0] bits (5th conversion in regular sequence) */
macro_rules! ADC_SQR3_SQ5_0 {() => (0x00100000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SQR3_SQ5_1 {() => (0x00200000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SQR3_SQ5_2 {() => (0x00400000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SQR3_SQ5_3 {() => (0x00800000u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_SQR3_SQ5_4 {() => (0x01000000u32 as uint32_t);} /*<Bit 4 */
macro_rules! ADC_SQR3_SQ6 {() => (0x3E000000u32 as uint32_t);} /*<SQ6[4:0] bits (6th conversion in regular sequence) */
macro_rules! ADC_SQR3_SQ6_0 {() => (0x02000000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_SQR3_SQ6_1 {() => (0x04000000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_SQR3_SQ6_2 {() => (0x08000000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_SQR3_SQ6_3 {() => (0x10000000u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_SQR3_SQ6_4 {() => (0x20000000u32 as uint32_t);} /*<Bit 4 */
/* Bit definition for ADC_JSQR register */
macro_rules! ADC_JSQR_JSQ1 {() => (0x0000001Fu32 as uint32_t);} /*<JSQ1[4:0] bits (1st conversion in injected sequence) */
macro_rules! ADC_JSQR_JSQ1_0 {() => (0x00000001u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_JSQR_JSQ1_1 {() => (0x00000002u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_JSQR_JSQ1_2 {() => (0x00000004u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_JSQR_JSQ1_3 {() => (0x00000008u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_JSQR_JSQ1_4 {() => (0x00000010u32 as uint32_t);} /*<Bit 4 */
macro_rules! ADC_JSQR_JSQ2 {() => (0x000003E0u32 as uint32_t);} /*<JSQ2[4:0] bits (2nd conversion in injected sequence) */
macro_rules! ADC_JSQR_JSQ2_0 {() => (0x00000020u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_JSQR_JSQ2_1 {() => (0x00000040u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_JSQR_JSQ2_2 {() => (0x00000080u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_JSQR_JSQ2_3 {() => (0x00000100u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_JSQR_JSQ2_4 {() => (0x00000200u32 as uint32_t);} /*<Bit 4 */
macro_rules! ADC_JSQR_JSQ3 {() => (0x00007C00u32 as uint32_t);} /*<JSQ3[4:0] bits (3rd conversion in injected sequence) */
macro_rules! ADC_JSQR_JSQ3_0 {() => (0x00000400u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_JSQR_JSQ3_1 {() => (0x00000800u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_JSQR_JSQ3_2 {() => (0x00001000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_JSQR_JSQ3_3 {() => (0x00002000u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_JSQR_JSQ3_4 {() => (0x00004000u32 as uint32_t);} /*<Bit 4 */
macro_rules! ADC_JSQR_JSQ4 {() => (0x000F8000u32 as uint32_t);} /*<JSQ4[4:0] bits (4th conversion in injected sequence) */
macro_rules! ADC_JSQR_JSQ4_0 {() => (0x00008000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_JSQR_JSQ4_1 {() => (0x00010000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_JSQR_JSQ4_2 {() => (0x00020000u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_JSQR_JSQ4_3 {() => (0x00040000u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_JSQR_JSQ4_4 {() => (0x00080000u32 as uint32_t);} /*<Bit 4 */
macro_rules! ADC_JSQR_JL {() => (0x00300000u32 as uint32_t);} /*<JL[1:0] bits (Injected Sequence length) */
macro_rules! ADC_JSQR_JL_0 {() => (0x00100000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_JSQR_JL_1 {() => (0x00200000u32 as uint32_t);} /*<Bit 1 */
/* Bit definition for ADC_JDR1 register */
macro_rules! ADC_JDR1_JDATA {() => (0xFFFFu16 as uint16_t);} /*<Injected data */
/* Bit definition for ADC_JDR2 register */
macro_rules! ADC_JDR2_JDATA {() => (0xFFFFu16 as uint16_t);} /*<Injected data */
/* Bit definition for ADC_JDR3 register */
macro_rules! ADC_JDR3_JDATA {() => (0xFFFFu16 as uint16_t);} /*<Injected data */
/* Bit definition for ADC_JDR4 register */
macro_rules! ADC_JDR4_JDATA {() => (0xFFFFu16 as uint16_t);} /*<Injected data */
/* Bit definition for ADC_DR register */
macro_rules! ADC_DR_DATA {() => (0x0000FFFFu32 as uint32_t);} /*<Regular data */
macro_rules! ADC_DR_ADC2DATA {() => (0xFFFF0000u32 as uint32_t);} /*<ADC2 data */
/* Bit definition for ADC_CSR register */
macro_rules! ADC_CSR_AWD1 {() => (0x00000001u32 as uint32_t);} /*<ADC1 Analog watchdog flag */
macro_rules! ADC_CSR_EOC1 {() => (0x00000002u32 as uint32_t);} /*<ADC1 End of conversion */
macro_rules! ADC_CSR_JEOC1 {() => (0x00000004u32 as uint32_t);} /*<ADC1 Injected channel end of conversion */
macro_rules! ADC_CSR_JSTRT1 {() => (0x00000008u32 as uint32_t);} /*<ADC1 Injected channel Start flag */
macro_rules! ADC_CSR_STRT1 {() => (0x00000010u32 as uint32_t);} /*<ADC1 Regular channel Start flag */
macro_rules! ADC_CSR_DOVR1 {() => (0x00000020u32 as uint32_t);} /*<ADC1 DMA overrun flag */
macro_rules! ADC_CSR_AWD2 {() => (0x00000100u32 as uint32_t);} /*<ADC2 Analog watchdog flag */
macro_rules! ADC_CSR_EOC2 {() => (0x00000200u32 as uint32_t);} /*<ADC2 End of conversion */
macro_rules! ADC_CSR_JEOC2 {() => (0x00000400u32 as uint32_t);} /*<ADC2 Injected channel end of conversion */
macro_rules! ADC_CSR_JSTRT2 {() => (0x00000800u32 as uint32_t);} /*<ADC2 Injected channel Start flag */
macro_rules! ADC_CSR_STRT2 {() => (0x00001000u32 as uint32_t);} /*<ADC2 Regular channel Start flag */
macro_rules! ADC_CSR_DOVR2 {() => (0x00002000u32 as uint32_t);} /*<ADC2 DMA overrun flag */
macro_rules! ADC_CSR_AWD3 {() => (0x00010000u32 as uint32_t);} /*<ADC3 Analog watchdog flag */
macro_rules! ADC_CSR_EOC3 {() => (0x00020000u32 as uint32_t);} /*<ADC3 End of conversion */
macro_rules! ADC_CSR_JEOC3 {() => (0x00040000u32 as uint32_t);} /*<ADC3 Injected channel end of conversion */
macro_rules! ADC_CSR_JSTRT3 {() => (0x00080000u32 as uint32_t);} /*<ADC3 Injected channel Start flag */
macro_rules! ADC_CSR_STRT3 {() => (0x00100000u32 as uint32_t);} /*<ADC3 Regular channel Start flag */
macro_rules! ADC_CSR_DOVR3 {() => (0x00200000u32 as uint32_t);} /*<ADC3 DMA overrun flag */
/* Bit definition for ADC_CCR register */
macro_rules! ADC_CCR_MULTI {() => (0x0000001Fu32 as uint32_t);} /*<MULTI[4:0] bits (Multi-ADC mode selection) */
macro_rules! ADC_CCR_MULTI_0 {() => (0x00000001u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_CCR_MULTI_1 {() => (0x00000002u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_CCR_MULTI_2 {() => (0x00000004u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_CCR_MULTI_3 {() => (0x00000008u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_CCR_MULTI_4 {() => (0x00000010u32 as uint32_t);} /*<Bit 4 */
macro_rules! ADC_CCR_DELAY {() => (0x00000F00u32 as uint32_t);} /*<DELAY[3:0] bits (Delay between 2 sampling phases) */
macro_rules! ADC_CCR_DELAY_0 {() => (0x00000100u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_CCR_DELAY_1 {() => (0x00000200u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_CCR_DELAY_2 {() => (0x00000400u32 as uint32_t);} /*<Bit 2 */
macro_rules! ADC_CCR_DELAY_3 {() => (0x00000800u32 as uint32_t);} /*<Bit 3 */
macro_rules! ADC_CCR_DDS {() => (0x00002000u32 as uint32_t);} /*<DMA disable selection (Multi-ADC mode) */
macro_rules! ADC_CCR_DMA {() => (0x0000C000u32 as uint32_t);} /*<DMA[1:0] bits (Direct Memory Access mode for multimode) */
macro_rules! ADC_CCR_DMA_0 {() => (0x00004000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_CCR_DMA_1 {() => (0x00008000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_CCR_ADCPRE {() => (0x00030000u32 as uint32_t);} /*<ADCPRE[1:0] bits (ADC prescaler) */
macro_rules! ADC_CCR_ADCPRE_0 {() => (0x00010000u32 as uint32_t);} /*<Bit 0 */
macro_rules! ADC_CCR_ADCPRE_1 {() => (0x00020000u32 as uint32_t);} /*<Bit 1 */
macro_rules! ADC_CCR_VBATE {() => (0x00400000u32 as uint32_t);} /*<VBAT Enable */
macro_rules! ADC_CCR_TSVREFE {() => (0x00800000u32 as uint32_t);} /*<Temperature Sensor and VREFINT Enable */
/* Bit definition for ADC_CDR register */
macro_rules! ADC_CDR_DATA1 {() => (0x0000FFFFu32 as uint32_t);} /*<1st data of a pair of regular conversions */
macro_rules! ADC_CDR_DATA2 {() => (0xFFFF0000u32 as uint32_t);} /*<2nd data of a pair of regular conversions */
/* */
/* Controller Area Network */
/* */
/*<CAN control and status registers */
/* Bit definition for CAN_MCR register */
macro_rules! CAN_MCR_INRQ {() => (0x0001u16 as uint16_t);} /*<Initialization Request */
macro_rules! CAN_MCR_SLEEP {() => (0x0002u16 as uint16_t);} /*<Sleep Mode Request */
macro_rules! CAN_MCR_TXFP {() => (0x0004u16 as uint16_t);} /*<Transmit FIFO Priority */
macro_rules! CAN_MCR_RFLM {() => (0x0008u16 as uint16_t);} /*<Receive FIFO Locked Mode */
macro_rules! CAN_MCR_NART {() => (0x0010u16 as uint16_t);} /*<No Automatic Retransmission */
macro_rules! CAN_MCR_AWUM {() => (0x0020u16 as uint16_t);} /*<Automatic Wakeup Mode */
macro_rules! CAN_MCR_ABOM {() => (0x0040u16 as uint16_t);} /*<Automatic Bus-Off Management */
macro_rules! CAN_MCR_TTCM {() => (0x0080u16 as uint16_t);} /*<Time Triggered Communication Mode */
macro_rules! CAN_MCR_RESET {() => (0x8000u16 as uint16_t);} /*<bxCAN software master reset */
/* Bit definition for CAN_MSR register */
macro_rules! CAN_MSR_INAK {() => (0x0001u16 as uint16_t);} /*<Initialization Acknowledge */
macro_rules! CAN_MSR_SLAK {() => (0x0002u16 as uint16_t);} /*<Sleep Acknowledge */
macro_rules! CAN_MSR_ERRI {() => (0x0004u16 as uint16_t);} /*<Error Interrupt */
macro_rules! CAN_MSR_WKUI {() => (0x0008u16 as uint16_t);} /*<Wakeup Interrupt */
macro_rules! CAN_MSR_SLAKI {() => (0x0010u16 as uint16_t);} /*<Sleep Acknowledge Interrupt */
macro_rules! CAN_MSR_TXM {() => (0x0100u16 as uint16_t);} /*<Transmit Mode */
macro_rules! CAN_MSR_RXM {() => (0x0200u16 as uint16_t);} /*<Receive Mode */
macro_rules! CAN_MSR_SAMP {() => (0x0400u16 as uint16_t);} /*<Last Sample Point */
macro_rules! CAN_MSR_RX {() => (0x0800u16 as uint16_t);} /*<CAN Rx Signal */
/* Bit definition for CAN_TSR register */
macro_rules! CAN_TSR_RQCP0 {() => (0x00000001u32 as uint32_t);} /*<Request Completed Mailbox0 */
macro_rules! CAN_TSR_TXOK0 {() => (0x00000002u32 as uint32_t);} /*<Transmission OK of Mailbox0 */
macro_rules! CAN_TSR_ALST0 {() => (0x00000004u32 as uint32_t);} /*<Arbitration Lost for Mailbox0 */
macro_rules! CAN_TSR_TERR0 {() => (0x00000008u32 as uint32_t);} /*<Transmission Error of Mailbox0 */
macro_rules! CAN_TSR_ABRQ0 {() => (0x00000080u32 as uint32_t);} /*<Abort Request for Mailbox0 */
macro_rules! CAN_TSR_RQCP1 {() => (0x00000100u32 as uint32_t);} /*<Request Completed Mailbox1 */
macro_rules! CAN_TSR_TXOK1 {() => (0x00000200u32 as uint32_t);} /*<Transmission OK of Mailbox1 */
macro_rules! CAN_TSR_ALST1 {() => (0x00000400u32 as uint32_t);} /*<Arbitration Lost for Mailbox1 */
macro_rules! CAN_TSR_TERR1 {() => (0x00000800u32 as uint32_t);} /*<Transmission Error of Mailbox1 */
macro_rules! CAN_TSR_ABRQ1 {() => (0x00008000u32 as uint32_t);} /*<Abort Request for Mailbox 1 */
macro_rules! CAN_TSR_RQCP2 {() => (0x00010000u32 as uint32_t);} /*<Request Completed Mailbox2 */
macro_rules! CAN_TSR_TXOK2 {() => (0x00020000u32 as uint32_t);} /*<Transmission OK of Mailbox 2 */
macro_rules! CAN_TSR_ALST2 {() => (0x00040000u32 as uint32_t);} /*<Arbitration Lost for mailbox 2 */
macro_rules! CAN_TSR_TERR2 {() => (0x00080000u32 as uint32_t);} /*<Transmission Error of Mailbox 2 */
macro_rules! CAN_TSR_ABRQ2 {() => (0x00800000u32 as uint32_t);} /*<Abort Request for Mailbox 2 */
macro_rules! CAN_TSR_CODE {() => (0x03000000u32 as uint32_t);} /*<Mailbox Code */
macro_rules! CAN_TSR_TME {() => (0x1C000000u32 as uint32_t);} /*<TME[2:0] bits */
macro_rules! CAN_TSR_TME0 {() => (0x04000000u32 as uint32_t);} /*<Transmit Mailbox 0 Empty */
macro_rules! CAN_TSR_TME1 {() => (0x08000000u32 as uint32_t);} /*<Transmit Mailbox 1 Empty */
macro_rules! CAN_TSR_TME2 {() => (0x10000000u32 as uint32_t);} /*<Transmit Mailbox 2 Empty */
macro_rules! CAN_TSR_LOW {() => (0xE0000000u32 as uint32_t);} /*<LOW[2:0] bits */
macro_rules! CAN_TSR_LOW0 {() => (0x20000000u32 as uint32_t);} /*<Lowest Priority Flag for Mailbox 0 */
macro_rules! CAN_TSR_LOW1 {() => (0x40000000u32 as uint32_t);} /*<Lowest Priority Flag for Mailbox 1 */
macro_rules! CAN_TSR_LOW2 {() => (0x80000000u32 as uint32_t);} /*<Lowest Priority Flag for Mailbox 2 */
/* Bit definition for CAN_RF0R register */
macro_rules! CAN_RF0R_FMP0 {() => (0x03u8 as uint8_t);} /*<FIFO 0 Message Pending */
macro_rules! CAN_RF0R_FULL0 {() => (0x08u8 as uint8_t);} /*<FIFO 0 Full */
macro_rules! CAN_RF0R_FOVR0 {() => (0x10u8 as uint8_t);} /*<FIFO 0 Overrun */
macro_rules! CAN_RF0R_RFOM0 {() => (0x20u8 as uint8_t);} /*<Release FIFO 0 Output Mailbox */
/* Bit definition for CAN_RF1R register */
macro_rules! CAN_RF1R_FMP1 {() => (0x03u8 as uint8_t);} /*<FIFO 1 Message Pending */
macro_rules! CAN_RF1R_FULL1 {() => (0x08u8 as uint8_t);} /*<FIFO 1 Full */
macro_rules! CAN_RF1R_FOVR1 {() => (0x10u8 as uint8_t);} /*<FIFO 1 Overrun */
macro_rules! CAN_RF1R_RFOM1 {() => (0x20u8 as uint8_t);} /*<Release FIFO 1 Output Mailbox */
/* Bit definition for CAN_IER register */
macro_rules! CAN_IER_TMEIE {() => (0x00000001u32 as uint32_t);} /*<Transmit Mailbox Empty Interrupt Enable */
macro_rules! CAN_IER_FMPIE0 {() => (0x00000002u32 as uint32_t);} /*<FIFO Message Pending Interrupt Enable */
macro_rules! CAN_IER_FFIE0 {() => (0x00000004u32 as uint32_t);} /*<FIFO Full Interrupt Enable */
macro_rules! CAN_IER_FOVIE0 {() => (0x00000008u32 as uint32_t);} /*<FIFO Overrun Interrupt Enable */
macro_rules! CAN_IER_FMPIE1 {() => (0x00000010u32 as uint32_t);} /*<FIFO Message Pending Interrupt Enable */
macro_rules! CAN_IER_FFIE1 {() => (0x00000020u32 as uint32_t);} /*<FIFO Full Interrupt Enable */
macro_rules! CAN_IER_FOVIE1 {() => (0x00000040u32 as uint32_t);} /*<FIFO Overrun Interrupt Enable */
macro_rules! CAN_IER_EWGIE {() => (0x00000100u32 as uint32_t);} /*<Error Warning Interrupt Enable */
macro_rules! CAN_IER_EPVIE {() => (0x00000200u32 as uint32_t);} /*<Error Passive Interrupt Enable */
macro_rules! CAN_IER_BOFIE {() => (0x00000400u32 as uint32_t);} /*<Bus-Off Interrupt Enable */
macro_rules! CAN_IER_LECIE {() => (0x00000800u32 as uint32_t);} /*<Last Error Code Interrupt Enable */
macro_rules! CAN_IER_ERRIE {() => (0x00008000u32 as uint32_t);} /*<Error Interrupt Enable */
macro_rules! CAN_IER_WKUIE {() => (0x00010000u32 as uint32_t);} /*<Wakeup Interrupt Enable */
macro_rules! CAN_IER_SLKIE {() => (0x00020000u32 as uint32_t);} /*<Sleep Interrupt Enable */
/* Bit definition for CAN_ESR register */
macro_rules! CAN_ESR_EWGF {() => (0x00000001u32 as uint32_t);} /*<Error Warning Flag */
macro_rules! CAN_ESR_EPVF {() => (0x00000002u32 as uint32_t);} /*<Error Passive Flag */
macro_rules! CAN_ESR_BOFF {() => (0x00000004u32 as uint32_t);} /*<Bus-Off Flag */
macro_rules! CAN_ESR_LEC {() => (0x00000070u32 as uint32_t);} /*<LEC[2:0] bits (Last Error Code) */
macro_rules! CAN_ESR_LEC_0 {() => (0x00000010u32 as uint32_t);} /*<Bit 0 */
macro_rules! CAN_ESR_LEC_1 {() => (0x00000020u32 as uint32_t);} /*<Bit 1 */
macro_rules! CAN_ESR_LEC_2 {() => (0x00000040u32 as uint32_t);} /*<Bit 2 */
macro_rules! CAN_ESR_TEC {() => (0x00FF0000u32 as uint32_t);} /*<Least significant byte of the 9-bit Transmit Error Counter */
macro_rules! CAN_ESR_REC {() => (0xFF000000u32 as uint32_t);} /*<Receive Error Counter */
/* Bit definition for CAN_BTR register */
macro_rules! CAN_BTR_BRP {() => (0x000003FFu32 as uint32_t);} /*<Baud Rate Prescaler */
macro_rules! CAN_BTR_TS1 {() => (0x000F0000u32 as uint32_t);} /*<Time Segment 1 */
macro_rules! CAN_BTR_TS2 {() => (0x00700000u32 as uint32_t);} /*<Time Segment 2 */
macro_rules! CAN_BTR_SJW {() => (0x03000000u32 as uint32_t);} /*<Resynchronization Jump Width */
macro_rules! CAN_BTR_LBKM {() => (0x40000000u32 as uint32_t);} /*<Loop Back Mode (Debug) */
macro_rules! CAN_BTR_SILM {() => (0x80000000u32 as uint32_t);} /*<Silent Mode */
/*<Mailbox registers */
/* Bit definition for CAN_TI0R register */
macro_rules! CAN_TI0R_TXRQ {() => (0x00000001u32 as uint32_t);} /*<Transmit Mailbox Request */
macro_rules! CAN_TI0R_RTR {() => (0x00000002u32 as uint32_t);} /*<Remote Transmission Request */
macro_rules! CAN_TI0R_IDE {() => (0x00000004u32 as uint32_t);} /*<Identifier Extension */
macro_rules! CAN_TI0R_EXID {() => (0x001FFFF8u32 as uint32_t);} /*<Extended Identifier */
macro_rules! CAN_TI0R_STID {() => (0xFFE00000u32 as uint32_t);} /*<Standard Identifier or Extended Identifier */
/* Bit definition for CAN_TDT0R register */
macro_rules! CAN_TDT0R_DLC {() => (0x0000000Fu32 as uint32_t);} /*<Data Length Code */
macro_rules! CAN_TDT0R_TGT {() => (0x00000100u32 as uint32_t);} /*<Transmit Global Time */
macro_rules! CAN_TDT0R_TIME {() => (0xFFFF0000u32 as uint32_t);} /*<Message Time Stamp */
/* Bit definition for CAN_TDL0R register */
macro_rules! CAN_TDL0R_DATA0 {() => (0x000000FFu32 as uint32_t);} /*<Data byte 0 */
macro_rules! CAN_TDL0R_DATA1 {() => (0x0000FF00u32 as uint32_t);} /*<Data byte 1 */
macro_rules! CAN_TDL0R_DATA2 {() => (0x00FF0000u32 as uint32_t);} /*<Data byte 2 */
macro_rules! CAN_TDL0R_DATA3 {() => (0xFF000000u32 as uint32_t);} /*<Data byte 3 */
/* Bit definition for CAN_TDH0R register */
macro_rules! CAN_TDH0R_DATA4 {() => (0x000000FFu32 as uint32_t);} /*<Data byte 4 */
macro_rules! CAN_TDH0R_DATA5 {() => (0x0000FF00u32 as uint32_t);} /*<Data byte 5 */
macro_rules! CAN_TDH0R_DATA6 {() => (0x00FF0000u32 as uint32_t);} /*<Data byte 6 */
macro_rules! CAN_TDH0R_DATA7 {() => (0xFF000000u32 as uint32_t);} /*<Data byte 7 */
/* Bit definition for CAN_TI1R register */
macro_rules! CAN_TI1R_TXRQ {() => (0x00000001u32 as uint32_t);} /*<Transmit Mailbox Request */
macro_rules! CAN_TI1R_RTR {() => (0x00000002u32 as uint32_t);} /*<Remote Transmission Request */
macro_rules! CAN_TI1R_IDE {() => (0x00000004u32 as uint32_t);} /*<Identifier Extension */
macro_rules! CAN_TI1R_EXID {() => (0x001FFFF8u32 as uint32_t);} /*<Extended Identifier */
macro_rules! CAN_TI1R_STID {() => (0xFFE00000u32 as uint32_t);} /*<Standard Identifier or Extended Identifier */
/* Bit definition for CAN_TDT1R register */
macro_rules! CAN_TDT1R_DLC {() => (0x0000000Fu32 as uint32_t);} /*<Data Length Code */
macro_rules! CAN_TDT1R_TGT {() => (0x00000100u32 as uint32_t);} /*<Transmit Global Time */
macro_rules! CAN_TDT1R_TIME {() => (0xFFFF0000u32 as uint32_t);} /*<Message Time Stamp */
/* Bit definition for CAN_TDL1R register */
macro_rules! CAN_TDL1R_DATA0 {() => (0x000000FFu32 as uint32_t);} /*<Data byte 0 */
macro_rules! CAN_TDL1R_DATA1 {() => (0x0000FF00u32 as uint32_t);} /*<Data byte 1 */
macro_rules! CAN_TDL1R_DATA2 {() => (0x00FF0000u32 as uint32_t);} /*<Data byte 2 */
macro_rules! CAN_TDL1R_DATA3 {() => (0xFF000000u32 as uint32_t);} /*<Data byte 3 */
/* Bit definition for CAN_TDH1R register */
macro_rules! CAN_TDH1R_DATA4 {() => (0x000000FFu32 as uint32_t);} /*<Data byte 4 */
macro_rules! CAN_TDH1R_DATA5 {() => (0x0000FF00u32 as uint32_t);} /*<Data byte 5 */
macro_rules! CAN_TDH1R_DATA6 {() => (0x00FF0000u32 as uint32_t);} /*<Data byte 6 */
macro_rules! CAN_TDH1R_DATA7 {() => (0xFF000000u32 as uint32_t);} /*<Data byte 7 */
/* Bit definition for CAN_TI2R register */
macro_rules! CAN_TI2R_TXRQ {() => (0x00000001u32 as uint32_t);} /*<Transmit Mailbox Request */
macro_rules! CAN_TI2R_RTR {() => (0x00000002u32 as uint32_t);} /*<Remote Transmission Request */
macro_rules! CAN_TI2R_IDE {() => (0x00000004u32 as uint32_t);} /*<Identifier Extension */
macro_rules! CAN_TI2R_EXID {() => (0x001FFFF8u32 as uint32_t);} /*<Extended identifier */
macro_rules! CAN_TI2R_STID {() => (0xFFE00000u32 as uint32_t);} /*<Standard Identifier or Extended Identifier */
/* Bit definition for CAN_TDT2R register */
macro_rules! CAN_TDT2R_DLC {() => (0x0000000Fu32 as uint32_t);} /*<Data Length Code */
macro_rules! CAN_TDT2R_TGT {() => (0x00000100u32 as uint32_t);} /*<Transmit Global Time */
macro_rules! CAN_TDT2R_TIME {() => (0xFFFF0000u32 as uint32_t);} /*<Message Time Stamp */
/* Bit definition for CAN_TDL2R register */
macro_rules! CAN_TDL2R_DATA0 {() => (0x000000FFu32 as uint32_t);} /*<Data byte 0 */
macro_rules! CAN_TDL2R_DATA1 {() => (0x0000FF00u32 as uint32_t);} /*<Data byte 1 */
macro_rules! CAN_TDL2R_DATA2 {() => (0x00FF0000u32 as uint32_t);} /*<Data byte 2 */
macro_rules! CAN_TDL2R_DATA3 {() => (0xFF000000u32 as uint32_t);} /*<Data byte 3 */
/* Bit definition for CAN_TDH2R register */
macro_rules! CAN_TDH2R_DATA4 {() => (0x000000FFu32 as uint32_t);} /*<Data byte 4 */
macro_rules! CAN_TDH2R_DATA5 {() => (0x0000FF00u32 as uint32_t);} /*<Data byte 5 */
macro_rules! CAN_TDH2R_DATA6 {() => (0x00FF0000u32 as uint32_t);} /*<Data byte 6 */
macro_rules! CAN_TDH2R_DATA7 {() => (0xFF000000u32 as uint32_t);} /*<Data byte 7 */
/* Bit definition for CAN_RI0R register */
macro_rules! CAN_RI0R_RTR {() => (0x00000002u32 as uint32_t);} /*<Remote Transmission Request */
macro_rules! CAN_RI0R_IDE {() => (0x00000004u32 as uint32_t);} /*<Identifier Extension */
macro_rules! CAN_RI0R_EXID {() => (0x001FFFF8u32 as uint32_t);} /*<Extended Identifier */
macro_rules! CAN_RI0R_STID {() => (0xFFE00000u32 as uint32_t);} /*<Standard Identifier or Extended Identifier */
/* Bit definition for CAN_RDT0R register */
macro_rules! CAN_RDT0R_DLC {() => (0x0000000Fu32 as uint32_t);} /*<Data Length Code */
macro_rules! CAN_RDT0R_FMI {() => (0x0000FF00u32 as uint32_t);} /*<Filter Match Index */
macro_rules! CAN_RDT0R_TIME {() => (0xFFFF0000u32 as uint32_t);} /*<Message Time Stamp */
/* Bit definition for CAN_RDL0R register */
macro_rules! CAN_RDL0R_DATA0 {() => (0x000000FFu32 as uint32_t);} /*<Data byte 0 */
macro_rules! CAN_RDL0R_DATA1 {() => (0x0000FF00u32 as uint32_t);} /*<Data byte 1 */
macro_rules! CAN_RDL0R_DATA2 {() => (0x00FF0000u32 as uint32_t);} /*<Data byte 2 */
macro_rules! CAN_RDL0R_DATA3 {() => (0xFF000000u32 as uint32_t);} /*<Data byte 3 */
/* Bit definition for CAN_RDH0R register */
macro_rules! CAN_RDH0R_DATA4 {() => (0x000000FFu32 as uint32_t);} /*<Data byte 4 */
macro_rules! CAN_RDH0R_DATA5 {() => (0x0000FF00u32 as uint32_t);} /*<Data byte 5 */
macro_rules! CAN_RDH0R_DATA6 {() => (0x00FF0000u32 as uint32_t);} /*<Data byte 6 */
macro_rules! CAN_RDH0R_DATA7 {() => (0xFF000000u32 as uint32_t);} /*<Data byte 7 */
/* Bit definition for CAN_RI1R register */
macro_rules! CAN_RI1R_RTR {() => (0x00000002u32 as uint32_t);} /*<Remote Transmission Request */
macro_rules! CAN_RI1R_IDE {() => (0x00000004u32 as uint32_t);} /*<Identifier Extension */
macro_rules! CAN_RI1R_EXID {() => (0x001FFFF8u32 as uint32_t);} /*<Extended identifier */
macro_rules! CAN_RI1R_STID {() => (0xFFE00000u32 as uint32_t);} /*<Standard Identifier or Extended Identifier */
/* Bit definition for CAN_RDT1R register */
macro_rules! CAN_RDT1R_DLC {() => (0x0000000Fu32 as uint32_t);} /*<Data Length Code */
macro_rules! CAN_RDT1R_FMI {() => (0x0000FF00u32 as uint32_t);} /*<Filter Match Index */
macro_rules! CAN_RDT1R_TIME {() => (0xFFFF0000u32 as uint32_t);} /*<Message Time Stamp */
/* Bit definition for CAN_RDL1R register */
macro_rules! CAN_RDL1R_DATA0 {() => (0x000000FFu32 as uint32_t);} /*<Data byte 0 */
macro_rules! CAN_RDL1R_DATA1 {() => (0x0000FF00u32 as uint32_t);} /*<Data byte 1 */
macro_rules! CAN_RDL1R_DATA2 {() => (0x00FF0000u32 as uint32_t);} /*<Data byte 2 */
macro_rules! CAN_RDL1R_DATA3 {() => (0xFF000000u32 as uint32_t);} /*<Data byte 3 */
/* Bit definition for CAN_RDH1R register */
macro_rules! CAN_RDH1R_DATA4 {() => (0x000000FFu32 as uint32_t);} /*<Data byte 4 */
macro_rules! CAN_RDH1R_DATA5 {() => (0x0000FF00u32 as uint32_t);} /*<Data byte 5 */
macro_rules! CAN_RDH1R_DATA6 {() => (0x00FF0000u32 as uint32_t);} /*<Data byte 6 */
macro_rules! CAN_RDH1R_DATA7 {() => (0xFF000000u32 as uint32_t);} /*<Data byte 7 */
/*<CAN filter registers */
/* Bit definition for CAN_FMR register */
macro_rules! CAN_FMR_FINIT {() => (0x01u8 as uint8_t);} /*<Filter Init Mode */
/* Bit definition for CAN_FM1R register */
macro_rules! CAN_FM1R_FBM {() => (0x3FFFu16 as uint16_t);} /*<Filter Mode */
macro_rules! CAN_FM1R_FBM0 {() => (0x0001u16 as uint16_t);} /*<Filter Init Mode bit 0 */
macro_rules! CAN_FM1R_FBM1 {() => (0x0002u16 as uint16_t);} /*<Filter Init Mode bit 1 */
macro_rules! CAN_FM1R_FBM2 {() => (0x0004u16 as uint16_t);} /*<Filter Init Mode bit 2 */
macro_rules! CAN_FM1R_FBM3 {() => (0x0008u16 as uint16_t);} /*<Filter Init Mode bit 3 */
macro_rules! CAN_FM1R_FBM4 {() => (0x0010u16 as uint16_t);} /*<Filter Init Mode bit 4 */
macro_rules! CAN_FM1R_FBM5 {() => (0x0020u16 as uint16_t);} /*<Filter Init Mode bit 5 */
macro_rules! CAN_FM1R_FBM6 {() => (0x0040u16 as uint16_t);} /*<Filter Init Mode bit 6 */
macro_rules! CAN_FM1R_FBM7 {() => (0x0080u16 as uint16_t);} /*<Filter Init Mode bit 7 */
macro_rules! CAN_FM1R_FBM8 {() => (0x0100u16 as uint16_t);} /*<Filter Init Mode bit 8 */
macro_rules! CAN_FM1R_FBM9 {() => (0x0200u16 as uint16_t);} /*<Filter Init Mode bit 9 */
macro_rules! CAN_FM1R_FBM10 {() => (0x0400u16 as uint16_t);} /*<Filter Init Mode bit 10 */
macro_rules! CAN_FM1R_FBM11 {() => (0x0800u16 as uint16_t);} /*<Filter Init Mode bit 11 */
macro_rules! CAN_FM1R_FBM12 {() => (0x1000u16 as uint16_t);} /*<Filter Init Mode bit 12 */
macro_rules! CAN_FM1R_FBM13 {() => (0x2000u16 as uint16_t);} /*<Filter Init Mode bit 13 */
/* Bit definition for CAN_FS1R register */
macro_rules! CAN_FS1R_FSC {() => (0x3FFFu16 as uint16_t);} /*<Filter Scale Configuration */
macro_rules! CAN_FS1R_FSC0 {() => (0x0001u16 as uint16_t);} /*<Filter Scale Configuration bit 0 */
macro_rules! CAN_FS1R_FSC1 {() => (0x0002u16 as uint16_t);} /*<Filter Scale Configuration bit 1 */
macro_rules! CAN_FS1R_FSC2 {() => (0x0004u16 as uint16_t);} /*<Filter Scale Configuration bit 2 */
macro_rules! CAN_FS1R_FSC3 {() => (0x0008u16 as uint16_t);} /*<Filter Scale Configuration bit 3 */
macro_rules! CAN_FS1R_FSC4 {() => (0x0010u16 as uint16_t);} /*<Filter Scale Configuration bit 4 */
macro_rules! CAN_FS1R_FSC5 {() => (0x0020u16 as uint16_t);} /*<Filter Scale Configuration bit 5 */
macro_rules! CAN_FS1R_FSC6 {() => (0x0040u16 as uint16_t);} /*<Filter Scale Configuration bit 6 */
macro_rules! CAN_FS1R_FSC7 {() => (0x0080u16 as uint16_t);} /*<Filter Scale Configuration bit 7 */
macro_rules! CAN_FS1R_FSC8 {() => (0x0100u16 as uint16_t);} /*<Filter Scale Configuration bit 8 */
macro_rules! CAN_FS1R_FSC9 {() => (0x0200u16 as uint16_t);} /*<Filter Scale Configuration bit 9 */
macro_rules! CAN_FS1R_FSC10 {() => (0x0400u16 as uint16_t);} /*<Filter Scale Configuration bit 10 */
macro_rules! CAN_FS1R_FSC11 {() => (0x0800u16 as uint16_t);} /*<Filter Scale Configuration bit 11 */
macro_rules! CAN_FS1R_FSC12 {() => (0x1000u16 as uint16_t);} /*<Filter Scale Configuration bit 12 */
macro_rules! CAN_FS1R_FSC13 {() => (0x2000u16 as uint16_t);} /*<Filter Scale Configuration bit 13 */
/* Bit definition for CAN_FFA1R register */
macro_rules! CAN_FFA1R_FFA {() => (0x3FFFu16 as uint16_t);} /*<Filter FIFO Assignment */
macro_rules! CAN_FFA1R_FFA0 {() => (0x0001u16 as uint16_t);} /*<Filter FIFO Assignment for Filter 0 */
macro_rules! CAN_FFA1R_FFA1 {() => (0x0002u16 as uint16_t);} /*<Filter FIFO Assignment for Filter 1 */
macro_rules! CAN_FFA1R_FFA2 {() => (0x0004u16 as uint16_t);} /*<Filter FIFO Assignment for Filter 2 */
macro_rules! CAN_FFA1R_FFA3 {() => (0x0008u16 as uint16_t);} /*<Filter FIFO Assignment for Filter 3 */
macro_rules! CAN_FFA1R_FFA4 {() => (0x0010u16 as uint16_t);} /*<Filter FIFO Assignment for Filter 4 */
macro_rules! CAN_FFA1R_FFA5 {() => (0x0020u16 as uint16_t);} /*<Filter FIFO Assignment for Filter 5 */
macro_rules! CAN_FFA1R_FFA6 {() => (0x0040u16 as uint16_t);} /*<Filter FIFO Assignment for Filter 6 */
macro_rules! CAN_FFA1R_FFA7 {() => (0x0080u16 as uint16_t);} /*<Filter FIFO Assignment for Filter 7 */
macro_rules! CAN_FFA1R_FFA8 {() => (0x0100u16 as uint16_t);} /*<Filter FIFO Assignment for Filter 8 */
macro_rules! CAN_FFA1R_FFA9 {() => (0x0200u16 as uint16_t);} /*<Filter FIFO Assignment for Filter 9 */
macro_rules! CAN_FFA1R_FFA10 {() => (0x0400u16 as uint16_t);} /*<Filter FIFO Assignment for Filter 10 */
macro_rules! CAN_FFA1R_FFA11 {() => (0x0800u16 as uint16_t);} /*<Filter FIFO Assignment for Filter 11 */
macro_rules! CAN_FFA1R_FFA12 {() => (0x1000u16 as uint16_t);} /*<Filter FIFO Assignment for Filter 12 */
macro_rules! CAN_FFA1R_FFA13 {() => (0x2000u16 as uint16_t);} /*<Filter FIFO Assignment for Filter 13 */
/* Bit definition for CAN_FA1R register */
macro_rules! CAN_FA1R_FACT {() => (0x3FFFu16 as uint16_t);} /*<Filter Active */
macro_rules! CAN_FA1R_FACT0 {() => (0x0001u16 as uint16_t);} /*<Filter 0 Active */
macro_rules! CAN_FA1R_FACT1 {() => (0x0002u16 as uint16_t);} /*<Filter 1 Active */
macro_rules! CAN_FA1R_FACT2 {() => (0x0004u16 as uint16_t);} /*<Filter 2 Active */
macro_rules! CAN_FA1R_FACT3 {() => (0x0008u16 as uint16_t);} /*<Filter 3 Active */
macro_rules! CAN_FA1R_FACT4 {() => (0x0010u16 as uint16_t);} /*<Filter 4 Active */
macro_rules! CAN_FA1R_FACT5 {() => (0x0020u16 as uint16_t);} /*<Filter 5 Active */
macro_rules! CAN_FA1R_FACT6 {() => (0x0040u16 as uint16_t);} /*<Filter 6 Active */
macro_rules! CAN_FA1R_FACT7 {() => (0x0080u16 as uint16_t);} /*<Filter 7 Active */
macro_rules! CAN_FA1R_FACT8 {() => (0x0100u16 as uint16_t);} /*<Filter 8 Active */
macro_rules! CAN_FA1R_FACT9 {() => (0x0200u16 as uint16_t);} /*<Filter 9 Active */
macro_rules! CAN_FA1R_FACT10 {() => (0x0400u16 as uint16_t);} /*<Filter 10 Active */
macro_rules! CAN_FA1R_FACT11 {() => (0x0800u16 as uint16_t);} /*<Filter 11 Active */
macro_rules! CAN_FA1R_FACT12 {() => (0x1000u16 as uint16_t);} /*<Filter 12 Active */
macro_rules! CAN_FA1R_FACT13 {() => (0x2000u16 as uint16_t);} /*<Filter 13 Active */
/* Bit definition for CAN_F0R1 register */
macro_rules! CAN_F0R1_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F0R1_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F0R1_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F0R1_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F0R1_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F0R1_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F0R1_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F0R1_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F0R1_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F0R1_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F0R1_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F0R1_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F0R1_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F0R1_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F0R1_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F0R1_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F0R1_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F0R1_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F0R1_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F0R1_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F0R1_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F0R1_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F0R1_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F0R1_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F0R1_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F0R1_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F0R1_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F0R1_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F0R1_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F0R1_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F0R1_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F0R1_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F1R1 register */
macro_rules! CAN_F1R1_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F1R1_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F1R1_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F1R1_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F1R1_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F1R1_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F1R1_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F1R1_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F1R1_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F1R1_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F1R1_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F1R1_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F1R1_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F1R1_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F1R1_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F1R1_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F1R1_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F1R1_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F1R1_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F1R1_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F1R1_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F1R1_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F1R1_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F1R1_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F1R1_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F1R1_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F1R1_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F1R1_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F1R1_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F1R1_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F1R1_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F1R1_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F2R1 register */
macro_rules! CAN_F2R1_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F2R1_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F2R1_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F2R1_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F2R1_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F2R1_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F2R1_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F2R1_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F2R1_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F2R1_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F2R1_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F2R1_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F2R1_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F2R1_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F2R1_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F2R1_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F2R1_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F2R1_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F2R1_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F2R1_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F2R1_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F2R1_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F2R1_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F2R1_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F2R1_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F2R1_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F2R1_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F2R1_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F2R1_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F2R1_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F2R1_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F2R1_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F3R1 register */
macro_rules! CAN_F3R1_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F3R1_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F3R1_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F3R1_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F3R1_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F3R1_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F3R1_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F3R1_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F3R1_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F3R1_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F3R1_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F3R1_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F3R1_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F3R1_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F3R1_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F3R1_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F3R1_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F3R1_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F3R1_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F3R1_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F3R1_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F3R1_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F3R1_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F3R1_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F3R1_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F3R1_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F3R1_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F3R1_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F3R1_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F3R1_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F3R1_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F3R1_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F4R1 register */
macro_rules! CAN_F4R1_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F4R1_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F4R1_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F4R1_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F4R1_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F4R1_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F4R1_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F4R1_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F4R1_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F4R1_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F4R1_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F4R1_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F4R1_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F4R1_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F4R1_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F4R1_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F4R1_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F4R1_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F4R1_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F4R1_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F4R1_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F4R1_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F4R1_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F4R1_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F4R1_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F4R1_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F4R1_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F4R1_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F4R1_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F4R1_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F4R1_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F4R1_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F5R1 register */
macro_rules! CAN_F5R1_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F5R1_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F5R1_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F5R1_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F5R1_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F5R1_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F5R1_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F5R1_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F5R1_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F5R1_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F5R1_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F5R1_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F5R1_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F5R1_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F5R1_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F5R1_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F5R1_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F5R1_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F5R1_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F5R1_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F5R1_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F5R1_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F5R1_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F5R1_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F5R1_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F5R1_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F5R1_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F5R1_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F5R1_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F5R1_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F5R1_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F5R1_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F6R1 register */
macro_rules! CAN_F6R1_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F6R1_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F6R1_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F6R1_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F6R1_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F6R1_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F6R1_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F6R1_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F6R1_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F6R1_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F6R1_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F6R1_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F6R1_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F6R1_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F6R1_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F6R1_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F6R1_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F6R1_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F6R1_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F6R1_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F6R1_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F6R1_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F6R1_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F6R1_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F6R1_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F6R1_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F6R1_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F6R1_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F6R1_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F6R1_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F6R1_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F6R1_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F7R1 register */
macro_rules! CAN_F7R1_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F7R1_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F7R1_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F7R1_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F7R1_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F7R1_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F7R1_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F7R1_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F7R1_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F7R1_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F7R1_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F7R1_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F7R1_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F7R1_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F7R1_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F7R1_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F7R1_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F7R1_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F7R1_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F7R1_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F7R1_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F7R1_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F7R1_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F7R1_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F7R1_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F7R1_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F7R1_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F7R1_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F7R1_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F7R1_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F7R1_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F7R1_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F8R1 register */
macro_rules! CAN_F8R1_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F8R1_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F8R1_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F8R1_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F8R1_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F8R1_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F8R1_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F8R1_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F8R1_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F8R1_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F8R1_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F8R1_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F8R1_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F8R1_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F8R1_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F8R1_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F8R1_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F8R1_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F8R1_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F8R1_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F8R1_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F8R1_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F8R1_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F8R1_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F8R1_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F8R1_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F8R1_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F8R1_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F8R1_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F8R1_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F8R1_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F8R1_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F9R1 register */
macro_rules! CAN_F9R1_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F9R1_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F9R1_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F9R1_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F9R1_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F9R1_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F9R1_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F9R1_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F9R1_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F9R1_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F9R1_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F9R1_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F9R1_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F9R1_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F9R1_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F9R1_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F9R1_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F9R1_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F9R1_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F9R1_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F9R1_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F9R1_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F9R1_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F9R1_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F9R1_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F9R1_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F9R1_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F9R1_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F9R1_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F9R1_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F9R1_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F9R1_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F10R1 register */
macro_rules! CAN_F10R1_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F10R1_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F10R1_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F10R1_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F10R1_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F10R1_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F10R1_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F10R1_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F10R1_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F10R1_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F10R1_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F10R1_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F10R1_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F10R1_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F10R1_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F10R1_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F10R1_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F10R1_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F10R1_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F10R1_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F10R1_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F10R1_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F10R1_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F10R1_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F10R1_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F10R1_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F10R1_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F10R1_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F10R1_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F10R1_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F10R1_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F10R1_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F11R1 register */
macro_rules! CAN_F11R1_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F11R1_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F11R1_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F11R1_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F11R1_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F11R1_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F11R1_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F11R1_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F11R1_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F11R1_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F11R1_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F11R1_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F11R1_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F11R1_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F11R1_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F11R1_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F11R1_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F11R1_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F11R1_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F11R1_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F11R1_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F11R1_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F11R1_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F11R1_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F11R1_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F11R1_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F11R1_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F11R1_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F11R1_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F11R1_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F11R1_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F11R1_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F12R1 register */
macro_rules! CAN_F12R1_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F12R1_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F12R1_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F12R1_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F12R1_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F12R1_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F12R1_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F12R1_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F12R1_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F12R1_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F12R1_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F12R1_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F12R1_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F12R1_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F12R1_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F12R1_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F12R1_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F12R1_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F12R1_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F12R1_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F12R1_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F12R1_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F12R1_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F12R1_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F12R1_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F12R1_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F12R1_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F12R1_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F12R1_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F12R1_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F12R1_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F12R1_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F13R1 register */
macro_rules! CAN_F13R1_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F13R1_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F13R1_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F13R1_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F13R1_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F13R1_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F13R1_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F13R1_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F13R1_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F13R1_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F13R1_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F13R1_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F13R1_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F13R1_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F13R1_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F13R1_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F13R1_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F13R1_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F13R1_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F13R1_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F13R1_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F13R1_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F13R1_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F13R1_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F13R1_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F13R1_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F13R1_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F13R1_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F13R1_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F13R1_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F13R1_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F13R1_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F0R2 register */
macro_rules! CAN_F0R2_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F0R2_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F0R2_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F0R2_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F0R2_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F0R2_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F0R2_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F0R2_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F0R2_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F0R2_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F0R2_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F0R2_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F0R2_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F0R2_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F0R2_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F0R2_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F0R2_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F0R2_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F0R2_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F0R2_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F0R2_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F0R2_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F0R2_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F0R2_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F0R2_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F0R2_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F0R2_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F0R2_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F0R2_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F0R2_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F0R2_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F0R2_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F1R2 register */
macro_rules! CAN_F1R2_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F1R2_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F1R2_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F1R2_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F1R2_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F1R2_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F1R2_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F1R2_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F1R2_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F1R2_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F1R2_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F1R2_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F1R2_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F1R2_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F1R2_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F1R2_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F1R2_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F1R2_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F1R2_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F1R2_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F1R2_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F1R2_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F1R2_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F1R2_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F1R2_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F1R2_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F1R2_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F1R2_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F1R2_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F1R2_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F1R2_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F1R2_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F2R2 register */
macro_rules! CAN_F2R2_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F2R2_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F2R2_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F2R2_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F2R2_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F2R2_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F2R2_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F2R2_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F2R2_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F2R2_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F2R2_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F2R2_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F2R2_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F2R2_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F2R2_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F2R2_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F2R2_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F2R2_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F2R2_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F2R2_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F2R2_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F2R2_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F2R2_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F2R2_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F2R2_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F2R2_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F2R2_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F2R2_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F2R2_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F2R2_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F2R2_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F2R2_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F3R2 register */
macro_rules! CAN_F3R2_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F3R2_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F3R2_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F3R2_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F3R2_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F3R2_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F3R2_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F3R2_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F3R2_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F3R2_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F3R2_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F3R2_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F3R2_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F3R2_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F3R2_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F3R2_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F3R2_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F3R2_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F3R2_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F3R2_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F3R2_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F3R2_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F3R2_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F3R2_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F3R2_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F3R2_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F3R2_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F3R2_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F3R2_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F3R2_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F3R2_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F3R2_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F4R2 register */
macro_rules! CAN_F4R2_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F4R2_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F4R2_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F4R2_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F4R2_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F4R2_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F4R2_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F4R2_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F4R2_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F4R2_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F4R2_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F4R2_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F4R2_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F4R2_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F4R2_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F4R2_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F4R2_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F4R2_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F4R2_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F4R2_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F4R2_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F4R2_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F4R2_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F4R2_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F4R2_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F4R2_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F4R2_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F4R2_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F4R2_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F4R2_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F4R2_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F4R2_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F5R2 register */
macro_rules! CAN_F5R2_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F5R2_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F5R2_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F5R2_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F5R2_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F5R2_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F5R2_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F5R2_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F5R2_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F5R2_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F5R2_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F5R2_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F5R2_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F5R2_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F5R2_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F5R2_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F5R2_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F5R2_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F5R2_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F5R2_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F5R2_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F5R2_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F5R2_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F5R2_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F5R2_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F5R2_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F5R2_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F5R2_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F5R2_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F5R2_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F5R2_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F5R2_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F6R2 register */
macro_rules! CAN_F6R2_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F6R2_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F6R2_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F6R2_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F6R2_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F6R2_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F6R2_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F6R2_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F6R2_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F6R2_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F6R2_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F6R2_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F6R2_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F6R2_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F6R2_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F6R2_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F6R2_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F6R2_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F6R2_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F6R2_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F6R2_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F6R2_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F6R2_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F6R2_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F6R2_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F6R2_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F6R2_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F6R2_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F6R2_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F6R2_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F6R2_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F6R2_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F7R2 register */
macro_rules! CAN_F7R2_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F7R2_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F7R2_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F7R2_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F7R2_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F7R2_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F7R2_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F7R2_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F7R2_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F7R2_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F7R2_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F7R2_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F7R2_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F7R2_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F7R2_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F7R2_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F7R2_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F7R2_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F7R2_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F7R2_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F7R2_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F7R2_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F7R2_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F7R2_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F7R2_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F7R2_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F7R2_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F7R2_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F7R2_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F7R2_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F7R2_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F7R2_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F8R2 register */
macro_rules! CAN_F8R2_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F8R2_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F8R2_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F8R2_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F8R2_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F8R2_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F8R2_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F8R2_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F8R2_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F8R2_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F8R2_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F8R2_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F8R2_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F8R2_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F8R2_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F8R2_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F8R2_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F8R2_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F8R2_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F8R2_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F8R2_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F8R2_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F8R2_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F8R2_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F8R2_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F8R2_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F8R2_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F8R2_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F8R2_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F8R2_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F8R2_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F8R2_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F9R2 register */
macro_rules! CAN_F9R2_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F9R2_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F9R2_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F9R2_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F9R2_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F9R2_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F9R2_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F9R2_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F9R2_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F9R2_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F9R2_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F9R2_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F9R2_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F9R2_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F9R2_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F9R2_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F9R2_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F9R2_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F9R2_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F9R2_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F9R2_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F9R2_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F9R2_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F9R2_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F9R2_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F9R2_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F9R2_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F9R2_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F9R2_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F9R2_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F9R2_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F9R2_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F10R2 register */
macro_rules! CAN_F10R2_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F10R2_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F10R2_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F10R2_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F10R2_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F10R2_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F10R2_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F10R2_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F10R2_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F10R2_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F10R2_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F10R2_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F10R2_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F10R2_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F10R2_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F10R2_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F10R2_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F10R2_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F10R2_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F10R2_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F10R2_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F10R2_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F10R2_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F10R2_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F10R2_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F10R2_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F10R2_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F10R2_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F10R2_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F10R2_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F10R2_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F10R2_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F11R2 register */
macro_rules! CAN_F11R2_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F11R2_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F11R2_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F11R2_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F11R2_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F11R2_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F11R2_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F11R2_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F11R2_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F11R2_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F11R2_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F11R2_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F11R2_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F11R2_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F11R2_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F11R2_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F11R2_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F11R2_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F11R2_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F11R2_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F11R2_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F11R2_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F11R2_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F11R2_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F11R2_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F11R2_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F11R2_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F11R2_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F11R2_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F11R2_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F11R2_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F11R2_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F12R2 register */
macro_rules! CAN_F12R2_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F12R2_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F12R2_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F12R2_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F12R2_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F12R2_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F12R2_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F12R2_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F12R2_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F12R2_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F12R2_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F12R2_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F12R2_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F12R2_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F12R2_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F12R2_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F12R2_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F12R2_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F12R2_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F12R2_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F12R2_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F12R2_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F12R2_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F12R2_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F12R2_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F12R2_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F12R2_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F12R2_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F12R2_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F12R2_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F12R2_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F12R2_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* Bit definition for CAN_F13R2 register */
macro_rules! CAN_F13R2_FB0 {() => (0x00000001u32 as uint32_t);} /*<Filter bit 0 */
macro_rules! CAN_F13R2_FB1 {() => (0x00000002u32 as uint32_t);} /*<Filter bit 1 */
macro_rules! CAN_F13R2_FB2 {() => (0x00000004u32 as uint32_t);} /*<Filter bit 2 */
macro_rules! CAN_F13R2_FB3 {() => (0x00000008u32 as uint32_t);} /*<Filter bit 3 */
macro_rules! CAN_F13R2_FB4 {() => (0x00000010u32 as uint32_t);} /*<Filter bit 4 */
macro_rules! CAN_F13R2_FB5 {() => (0x00000020u32 as uint32_t);} /*<Filter bit 5 */
macro_rules! CAN_F13R2_FB6 {() => (0x00000040u32 as uint32_t);} /*<Filter bit 6 */
macro_rules! CAN_F13R2_FB7 {() => (0x00000080u32 as uint32_t);} /*<Filter bit 7 */
macro_rules! CAN_F13R2_FB8 {() => (0x00000100u32 as uint32_t);} /*<Filter bit 8 */
macro_rules! CAN_F13R2_FB9 {() => (0x00000200u32 as uint32_t);} /*<Filter bit 9 */
macro_rules! CAN_F13R2_FB10 {() => (0x00000400u32 as uint32_t);} /*<Filter bit 10 */
macro_rules! CAN_F13R2_FB11 {() => (0x00000800u32 as uint32_t);} /*<Filter bit 11 */
macro_rules! CAN_F13R2_FB12 {() => (0x00001000u32 as uint32_t);} /*<Filter bit 12 */
macro_rules! CAN_F13R2_FB13 {() => (0x00002000u32 as uint32_t);} /*<Filter bit 13 */
macro_rules! CAN_F13R2_FB14 {() => (0x00004000u32 as uint32_t);} /*<Filter bit 14 */
macro_rules! CAN_F13R2_FB15 {() => (0x00008000u32 as uint32_t);} /*<Filter bit 15 */
macro_rules! CAN_F13R2_FB16 {() => (0x00010000u32 as uint32_t);} /*<Filter bit 16 */
macro_rules! CAN_F13R2_FB17 {() => (0x00020000u32 as uint32_t);} /*<Filter bit 17 */
macro_rules! CAN_F13R2_FB18 {() => (0x00040000u32 as uint32_t);} /*<Filter bit 18 */
macro_rules! CAN_F13R2_FB19 {() => (0x00080000u32 as uint32_t);} /*<Filter bit 19 */
macro_rules! CAN_F13R2_FB20 {() => (0x00100000u32 as uint32_t);} /*<Filter bit 20 */
macro_rules! CAN_F13R2_FB21 {() => (0x00200000u32 as uint32_t);} /*<Filter bit 21 */
macro_rules! CAN_F13R2_FB22 {() => (0x00400000u32 as uint32_t);} /*<Filter bit 22 */
macro_rules! CAN_F13R2_FB23 {() => (0x00800000u32 as uint32_t);} /*<Filter bit 23 */
macro_rules! CAN_F13R2_FB24 {() => (0x01000000u32 as uint32_t);} /*<Filter bit 24 */
macro_rules! CAN_F13R2_FB25 {() => (0x02000000u32 as uint32_t);} /*<Filter bit 25 */
macro_rules! CAN_F13R2_FB26 {() => (0x04000000u32 as uint32_t);} /*<Filter bit 26 */
macro_rules! CAN_F13R2_FB27 {() => (0x08000000u32 as uint32_t);} /*<Filter bit 27 */
macro_rules! CAN_F13R2_FB28 {() => (0x10000000u32 as uint32_t);} /*<Filter bit 28 */
macro_rules! CAN_F13R2_FB29 {() => (0x20000000u32 as uint32_t);} /*<Filter bit 29 */
macro_rules! CAN_F13R2_FB30 {() => (0x40000000u32 as uint32_t);} /*<Filter bit 30 */
macro_rules! CAN_F13R2_FB31 {() => (0x80000000u32 as uint32_t);} /*<Filter bit 31 */
/* */
/* CRC calculation unit */
/* */
/* Bit definition for CRC_DR register */
macro_rules! CRC_DR_DR {() => (0xFFFFFFFFu32 as uint32_t);} /*< Data register bits */
/* Bit definition for CRC_IDR register */
macro_rules! CRC_IDR_IDR {() => (0xFFu8 as uint8_t);} /*< General-purpose 8-bit data register bits */
/* Bit definition for CRC_CR register */
macro_rules! CRC_CR_RESET {() => (0x01u8 as uint8_t);} /*< RESET bit */
/* */
/* Crypto Processor */
/* */
/* Bits definition for CRYP_CR register */
macro_rules! CRYP_CR_ALGODIR {() => (0x00000004u32 as uint32_t);}
macro_rules! CRYP_CR_ALGOMODE {() => (0x00000038u32 as uint32_t);}
macro_rules! CRYP_CR_ALGOMODE_0 {() => (0x00000008u32 as uint32_t);}
macro_rules! CRYP_CR_ALGOMODE_1 {() => (0x00000010u32 as uint32_t);}
macro_rules! CRYP_CR_ALGOMODE_2 {() => (0x00000020u32 as uint32_t);}
macro_rules! CRYP_CR_ALGOMODE_TDES_ECB {() => (0x00000000u32 as uint32_t);}
macro_rules! CRYP_CR_ALGOMODE_TDES_CBC {() => (0x00000008u32 as uint32_t);}
macro_rules! CRYP_CR_ALGOMODE_DES_ECB {() => (0x00000010u32 as uint32_t);}
macro_rules! CRYP_CR_ALGOMODE_DES_CBC {() => (0x00000018u32 as uint32_t);}
macro_rules! CRYP_CR_ALGOMODE_AES_ECB {() => (0x00000020u32 as uint32_t);}
macro_rules! CRYP_CR_ALGOMODE_AES_CBC {() => (0x00000028u32 as uint32_t);}
macro_rules! CRYP_CR_ALGOMODE_AES_CTR {() => (0x00000030u32 as uint32_t);}
macro_rules! CRYP_CR_ALGOMODE_AES_KEY {() => (0x00000038u32 as uint32_t);}
macro_rules! CRYP_CR_DATATYPE {() => (0x000000C0u32 as uint32_t);}
macro_rules! CRYP_CR_DATATYPE_0 {() => (0x00000040u32 as uint32_t);}
macro_rules! CRYP_CR_DATATYPE_1 {() => (0x00000080u32 as uint32_t);}
macro_rules! CRYP_CR_KEYSIZE {() => (0x00000300u32 as uint32_t);}
macro_rules! CRYP_CR_KEYSIZE_0 {() => (0x00000100u32 as uint32_t);}
macro_rules! CRYP_CR_KEYSIZE_1 {() => (0x00000200u32 as uint32_t);}
macro_rules! CRYP_CR_FFLUSH {() => (0x00004000u32 as uint32_t);}
macro_rules! CRYP_CR_CRYPEN {() => (0x00008000u32 as uint32_t);}
/* Bits definition for CRYP_SR register */
macro_rules! CRYP_SR_IFEM {() => (0x00000001u32 as uint32_t);}
macro_rules! CRYP_SR_IFNF {() => (0x00000002u32 as uint32_t);}
macro_rules! CRYP_SR_OFNE {() => (0x00000004u32 as uint32_t);}
macro_rules! CRYP_SR_OFFU {() => (0x00000008u32 as uint32_t);}
macro_rules! CRYP_SR_BUSY {() => (0x00000010u32 as uint32_t);}
/* Bits definition for CRYP_DMACR register */
macro_rules! CRYP_DMACR_DIEN {() => (0x00000001u32 as uint32_t);}
macro_rules! CRYP_DMACR_DOEN {() => (0x00000002u32 as uint32_t);}
/* Bits definition for CRYP_IMSCR register */
macro_rules! CRYP_IMSCR_INIM {() => (0x00000001u32 as uint32_t);}
macro_rules! CRYP_IMSCR_OUTIM {() => (0x00000002u32 as uint32_t);}
/* Bits definition for CRYP_RISR register */
macro_rules! CRYP_RISR_OUTRIS {() => (0x00000001u32 as uint32_t);}
macro_rules! CRYP_RISR_INRIS {() => (0x00000002u32 as uint32_t);}
/* Bits definition for CRYP_MISR register */
macro_rules! CRYP_MISR_INMIS {() => (0x00000001u32 as uint32_t);}
macro_rules! CRYP_MISR_OUTMIS {() => (0x00000002u32 as uint32_t);}
/* */
/* Digital to Analog Converter */
/* */
/* Bit definition for DAC_CR register */
macro_rules! DAC_CR_EN1 {() => (0x00000001u32 as uint32_t);} /*<DAC channel1 enable */
macro_rules! DAC_CR_BOFF1 {() => (0x00000002u32 as uint32_t);} /*<DAC channel1 output buffer disable */
macro_rules! DAC_CR_TEN1 {() => (0x00000004u32 as uint32_t);} /*<DAC channel1 Trigger enable */
macro_rules! DAC_CR_TSEL1 {() => (0x00000038u32 as uint32_t);} /*<TSEL1[2:0] (DAC channel1 Trigger selection) */
macro_rules! DAC_CR_TSEL1_0 {() => (0x00000008u32 as uint32_t);} /*<Bit 0 */
macro_rules! DAC_CR_TSEL1_1 {() => (0x00000010u32 as uint32_t);} /*<Bit 1 */
macro_rules! DAC_CR_TSEL1_2 {() => (0x00000020u32 as uint32_t);} /*<Bit 2 */
macro_rules! DAC_CR_WAVE1 {() => (0x000000C0u32 as uint32_t);} /*<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
macro_rules! DAC_CR_WAVE1_0 {() => (0x00000040u32 as uint32_t);} /*<Bit 0 */
macro_rules! DAC_CR_WAVE1_1 {() => (0x00000080u32 as uint32_t);} /*<Bit 1 */
macro_rules! DAC_CR_MAMP1 {() => (0x00000F00u32 as uint32_t);} /*<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
macro_rules! DAC_CR_MAMP1_0 {() => (0x00000100u32 as uint32_t);} /*<Bit 0 */
macro_rules! DAC_CR_MAMP1_1 {() => (0x00000200u32 as uint32_t);} /*<Bit 1 */
macro_rules! DAC_CR_MAMP1_2 {() => (0x00000400u32 as uint32_t);} /*<Bit 2 */
macro_rules! DAC_CR_MAMP1_3 {() => (0x00000800u32 as uint32_t);} /*<Bit 3 */
macro_rules! DAC_CR_DMAEN1 {() => (0x00001000u32 as uint32_t);} /*<DAC channel1 DMA enable */
macro_rules! DAC_CR_EN2 {() => (0x00010000u32 as uint32_t);} /*<DAC channel2 enable */
macro_rules! DAC_CR_BOFF2 {() => (0x00020000u32 as uint32_t);} /*<DAC channel2 output buffer disable */
macro_rules! DAC_CR_TEN2 {() => (0x00040000u32 as uint32_t);} /*<DAC channel2 Trigger enable */
macro_rules! DAC_CR_TSEL2 {() => (0x00380000u32 as uint32_t);} /*<TSEL2[2:0] (DAC channel2 Trigger selection) */
macro_rules! DAC_CR_TSEL2_0 {() => (0x00080000u32 as uint32_t);} /*<Bit 0 */
macro_rules! DAC_CR_TSEL2_1 {() => (0x00100000u32 as uint32_t);} /*<Bit 1 */
macro_rules! DAC_CR_TSEL2_2 {() => (0x00200000u32 as uint32_t);} /*<Bit 2 */
macro_rules! DAC_CR_WAVE2 {() => (0x00C00000u32 as uint32_t);} /*<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
macro_rules! DAC_CR_WAVE2_0 {() => (0x00400000u32 as uint32_t);} /*<Bit 0 */
macro_rules! DAC_CR_WAVE2_1 {() => (0x00800000u32 as uint32_t);} /*<Bit 1 */
macro_rules! DAC_CR_MAMP2 {() => (0x0F000000u32 as uint32_t);} /*<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
macro_rules! DAC_CR_MAMP2_0 {() => (0x01000000u32 as uint32_t);} /*<Bit 0 */
macro_rules! DAC_CR_MAMP2_1 {() => (0x02000000u32 as uint32_t);} /*<Bit 1 */
macro_rules! DAC_CR_MAMP2_2 {() => (0x04000000u32 as uint32_t);} /*<Bit 2 */
macro_rules! DAC_CR_MAMP2_3 {() => (0x08000000u32 as uint32_t);} /*<Bit 3 */
macro_rules! DAC_CR_DMAEN2 {() => (0x10000000u32 as uint32_t);} /*<DAC channel2 DMA enabled */
/* Bit definition for DAC_SWTRIGR register */
macro_rules! DAC_SWTRIGR_SWTRIG1 {() => (0x01u8 as uint8_t);} /*<DAC channel1 software trigger */
macro_rules! DAC_SWTRIGR_SWTRIG2 {() => (0x02u8 as uint8_t);} /*<DAC channel2 software trigger */
/* Bit definition for DAC_DHR12R1 register */
macro_rules! DAC_DHR12R1_DACC1DHR {() => (0x0FFFu16 as uint16_t);} /*<DAC channel1 12-bit Right aligned data */
/* Bit definition for DAC_DHR12L1 register */
macro_rules! DAC_DHR12L1_DACC1DHR {() => (0xFFF0u16 as uint16_t);} /*<DAC channel1 12-bit Left aligned data */
/* Bit definition for DAC_DHR8R1 register */
macro_rules! DAC_DHR8R1_DACC1DHR {() => (0xFFu8 as uint8_t);} /*<DAC channel1 8-bit Right aligned data */
/* Bit definition for DAC_DHR12R2 register */
macro_rules! DAC_DHR12R2_DACC2DHR {() => (0x0FFFu16 as uint16_t);} /*<DAC channel2 12-bit Right aligned data */
/* Bit definition for DAC_DHR12L2 register */
macro_rules! DAC_DHR12L2_DACC2DHR {() => (0xFFF0u16 as uint16_t);} /*<DAC channel2 12-bit Left aligned data */
/* Bit definition for DAC_DHR8R2 register */
macro_rules! DAC_DHR8R2_DACC2DHR {() => (0xFFu8 as uint8_t);} /*<DAC channel2 8-bit Right aligned data */
/* Bit definition for DAC_DHR12RD register */
macro_rules! DAC_DHR12RD_DACC1DHR {() => (0x00000FFFu32 as uint32_t);} /*<DAC channel1 12-bit Right aligned data */
macro_rules! DAC_DHR12RD_DACC2DHR {() => (0x0FFF0000u32 as uint32_t);} /*<DAC channel2 12-bit Right aligned data */
/* Bit definition for DAC_DHR12LD register */
macro_rules! DAC_DHR12LD_DACC1DHR {() => (0x0000FFF0u32 as uint32_t);} /*<DAC channel1 12-bit Left aligned data */
macro_rules! DAC_DHR12LD_DACC2DHR {() => (0xFFF00000u32 as uint32_t);} /*<DAC channel2 12-bit Left aligned data */
/* Bit definition for DAC_DHR8RD register */
macro_rules! DAC_DHR8RD_DACC1DHR {() => (0x00FFu16 as uint16_t);} /*<DAC channel1 8-bit Right aligned data */
macro_rules! DAC_DHR8RD_DACC2DHR {() => (0xFF00u16 as uint16_t);} /*<DAC channel2 8-bit Right aligned data */
/* Bit definition for DAC_DOR1 register */
macro_rules! DAC_DOR1_DACC1DOR {() => (0x0FFFu16 as uint16_t);} /*<DAC channel1 data output */
/* Bit definition for DAC_DOR2 register */
macro_rules! DAC_DOR2_DACC2DOR {() => (0x0FFFu16 as uint16_t);} /*<DAC channel2 data output */
/* Bit definition for DAC_SR register */
macro_rules! DAC_SR_DMAUDR1 {() => (0x00002000u32 as uint32_t);} /*<DAC channel1 DMA underrun flag */
macro_rules! DAC_SR_DMAUDR2 {() => (0x20000000u32 as uint32_t);} /*<DAC channel2 DMA underrun flag */
/* */
/* Debug MCU */
/* */
/* */
/* DCMI */
/* */
/* Bits definition for DCMI_CR register */
macro_rules! DCMI_CR_CAPTURE {() => (0x00000001u32 as uint32_t);}
macro_rules! DCMI_CR_CM {() => (0x00000002u32 as uint32_t);}
macro_rules! DCMI_CR_CROP {() => (0x00000004u32 as uint32_t);}
macro_rules! DCMI_CR_JPEG {() => (0x00000008u32 as uint32_t);}
macro_rules! DCMI_CR_ESS {() => (0x00000010u32 as uint32_t);}
macro_rules! DCMI_CR_PCKPOL {() => (0x00000020u32 as uint32_t);}
macro_rules! DCMI_CR_HSPOL {() => (0x00000040u32 as uint32_t);}
macro_rules! DCMI_CR_VSPOL {() => (0x00000080u32 as uint32_t);}
macro_rules! DCMI_CR_FCRC_0 {() => (0x00000100u32 as uint32_t);}
macro_rules! DCMI_CR_FCRC_1 {() => (0x00000200u32 as uint32_t);}
macro_rules! DCMI_CR_EDM_0 {() => (0x00000400u32 as uint32_t);}
macro_rules! DCMI_CR_EDM_1 {() => (0x00000800u32 as uint32_t);}
macro_rules! DCMI_CR_CRE {() => (0x00001000u32 as uint32_t);}
macro_rules! DCMI_CR_ENABLE {() => (0x00004000u32 as uint32_t);}
/* Bits definition for DCMI_SR register */
macro_rules! DCMI_SR_HSYNC {() => (0x00000001u32 as uint32_t);}
macro_rules! DCMI_SR_VSYNC {() => (0x00000002u32 as uint32_t);}
macro_rules! DCMI_SR_FNE {() => (0x00000004u32 as uint32_t);}
/* Bits definition for DCMI_RISR register */
macro_rules! DCMI_RISR_FRAME_RIS {() => (0x00000001u32 as uint32_t);}
macro_rules! DCMI_RISR_OVF_RIS {() => (0x00000002u32 as uint32_t);}
macro_rules! DCMI_RISR_ERR_RIS {() => (0x00000004u32 as uint32_t);}
macro_rules! DCMI_RISR_VSYNC_RIS {() => (0x00000008u32 as uint32_t);}
macro_rules! DCMI_RISR_LINE_RIS {() => (0x00000010u32 as uint32_t);}
/* Bits definition for DCMI_IER register */
macro_rules! DCMI_IER_FRAME_IE {() => (0x00000001u32 as uint32_t);}
macro_rules! DCMI_IER_OVF_IE {() => (0x00000002u32 as uint32_t);}
macro_rules! DCMI_IER_ERR_IE {() => (0x00000004u32 as uint32_t);}
macro_rules! DCMI_IER_VSYNC_IE {() => (0x00000008u32 as uint32_t);}
macro_rules! DCMI_IER_LINE_IE {() => (0x00000010u32 as uint32_t);}
/* Bits definition for DCMI_MISR register */
macro_rules! DCMI_MISR_FRAME_MIS {() => (0x00000001u32 as uint32_t);}
macro_rules! DCMI_MISR_OVF_MIS {() => (0x00000002u32 as uint32_t);}
macro_rules! DCMI_MISR_ERR_MIS {() => (0x00000004u32 as uint32_t);}
macro_rules! DCMI_MISR_VSYNC_MIS {() => (0x00000008u32 as uint32_t);}
macro_rules! DCMI_MISR_LINE_MIS {() => (0x00000010u32 as uint32_t);}
/* Bits definition for DCMI_ICR register */
macro_rules! DCMI_ICR_FRAME_ISC {() => (0x00000001u32 as uint32_t);}
macro_rules! DCMI_ICR_OVF_ISC {() => (0x00000002u32 as uint32_t);}
macro_rules! DCMI_ICR_ERR_ISC {() => (0x00000004u32 as uint32_t);}
macro_rules! DCMI_ICR_VSYNC_ISC {() => (0x00000008u32 as uint32_t);}
macro_rules! DCMI_ICR_LINE_ISC {() => (0x00000010u32 as uint32_t);}
/* */
/* DMA Controller */
/* */
/* Bits definition for DMA_SxCR register */
macro_rules! DMA_SxCR_CHSEL {() => (0x0E000000u32 as uint32_t);}
macro_rules! DMA_SxCR_CHSEL_0 {() => (0x02000000u32 as uint32_t);}
macro_rules! DMA_SxCR_CHSEL_1 {() => (0x04000000u32 as uint32_t);}
macro_rules! DMA_SxCR_CHSEL_2 {() => (0x08000000u32 as uint32_t);}
macro_rules! DMA_SxCR_MBURST {() => (0x01800000u32 as uint32_t);}
macro_rules! DMA_SxCR_MBURST_0 {() => (0x00800000u32 as uint32_t);}
macro_rules! DMA_SxCR_MBURST_1 {() => (0x01000000u32 as uint32_t);}
macro_rules! DMA_SxCR_PBURST {() => (0x00600000u32 as uint32_t);}
macro_rules! DMA_SxCR_PBURST_0 {() => (0x00200000u32 as uint32_t);}
macro_rules! DMA_SxCR_PBURST_1 {() => (0x00400000u32 as uint32_t);}
macro_rules! DMA_SxCR_ACK {() => (0x00100000u32 as uint32_t);}
macro_rules! DMA_SxCR_CT {() => (0x00080000u32 as uint32_t);}
macro_rules! DMA_SxCR_DBM {() => (0x00040000u32 as uint32_t);}
macro_rules! DMA_SxCR_PL {() => (0x00030000u32 as uint32_t);}
macro_rules! DMA_SxCR_PL_0 {() => (0x00010000u32 as uint32_t);}
macro_rules! DMA_SxCR_PL_1 {() => (0x00020000u32 as uint32_t);}
macro_rules! DMA_SxCR_PINCOS {() => (0x00008000u32 as uint32_t);}
macro_rules! DMA_SxCR_MSIZE {() => (0x00006000u32 as uint32_t);}
macro_rules! DMA_SxCR_MSIZE_0 {() => (0x00002000u32 as uint32_t);}
macro_rules! DMA_SxCR_MSIZE_1 {() => (0x00004000u32 as uint32_t);}
macro_rules! DMA_SxCR_PSIZE {() => (0x00001800u32 as uint32_t);}
macro_rules! DMA_SxCR_PSIZE_0 {() => (0x00000800u32 as uint32_t);}
macro_rules! DMA_SxCR_PSIZE_1 {() => (0x00001000u32 as uint32_t);}
macro_rules! DMA_SxCR_MINC {() => (0x00000400u32 as uint32_t);}
macro_rules! DMA_SxCR_PINC {() => (0x00000200u32 as uint32_t);}
macro_rules! DMA_SxCR_CIRC {() => (0x00000100u32 as uint32_t);}
macro_rules! DMA_SxCR_DIR {() => (0x000000C0u32 as uint32_t);}
macro_rules! DMA_SxCR_DIR_0 {() => (0x00000040u32 as uint32_t);}
macro_rules! DMA_SxCR_DIR_1 {() => (0x00000080u32 as uint32_t);}
macro_rules! DMA_SxCR_PFCTRL {() => (0x00000020u32 as uint32_t);}
macro_rules! DMA_SxCR_TCIE {() => (0x00000010u32 as uint32_t);}
macro_rules! DMA_SxCR_HTIE {() => (0x00000008u32 as uint32_t);}
macro_rules! DMA_SxCR_TEIE {() => (0x00000004u32 as uint32_t);}
macro_rules! DMA_SxCR_DMEIE {() => (0x00000002u32 as uint32_t);}
macro_rules! DMA_SxCR_EN {() => (0x00000001u32 as uint32_t);}
/* Bits definition for DMA_SxCNDTR register */
macro_rules! DMA_SxNDT {() => (0x0000FFFFu32 as uint32_t);}
macro_rules! DMA_SxNDT_0 {() => (0x00000001u32 as uint32_t);}
macro_rules! DMA_SxNDT_1 {() => (0x00000002u32 as uint32_t);}
macro_rules! DMA_SxNDT_2 {() => (0x00000004u32 as uint32_t);}
macro_rules! DMA_SxNDT_3 {() => (0x00000008u32 as uint32_t);}
macro_rules! DMA_SxNDT_4 {() => (0x00000010u32 as uint32_t);}
macro_rules! DMA_SxNDT_5 {() => (0x00000020u32 as uint32_t);}
macro_rules! DMA_SxNDT_6 {() => (0x00000040u32 as uint32_t);}
macro_rules! DMA_SxNDT_7 {() => (0x00000080u32 as uint32_t);}
macro_rules! DMA_SxNDT_8 {() => (0x00000100u32 as uint32_t);}
macro_rules! DMA_SxNDT_9 {() => (0x00000200u32 as uint32_t);}
macro_rules! DMA_SxNDT_10 {() => (0x00000400u32 as uint32_t);}
macro_rules! DMA_SxNDT_11 {() => (0x00000800u32 as uint32_t);}
macro_rules! DMA_SxNDT_12 {() => (0x00001000u32 as uint32_t);}
macro_rules! DMA_SxNDT_13 {() => (0x00002000u32 as uint32_t);}
macro_rules! DMA_SxNDT_14 {() => (0x00004000u32 as uint32_t);}
macro_rules! DMA_SxNDT_15 {() => (0x00008000u32 as uint32_t);}
/* Bits definition for DMA_SxFCR register */
macro_rules! DMA_SxFCR_FEIE {() => (0x00000080u32 as uint32_t);}
macro_rules! DMA_SxFCR_FS {() => (0x00000038u32 as uint32_t);}
macro_rules! DMA_SxFCR_FS_0 {() => (0x00000008u32 as uint32_t);}
macro_rules! DMA_SxFCR_FS_1 {() => (0x00000010u32 as uint32_t);}
macro_rules! DMA_SxFCR_FS_2 {() => (0x00000020u32 as uint32_t);}
macro_rules! DMA_SxFCR_DMDIS {() => (0x00000004u32 as uint32_t);}
macro_rules! DMA_SxFCR_FTH {() => (0x00000003u32 as uint32_t);}
macro_rules! DMA_SxFCR_FTH_0 {() => (0x00000001u32 as uint32_t);}
macro_rules! DMA_SxFCR_FTH_1 {() => (0x00000002u32 as uint32_t);}
/* Bits definition for DMA_LISR register */
macro_rules! DMA_LISR_TCIF3 {() => (0x08000000u32 as uint32_t);}
macro_rules! DMA_LISR_HTIF3 {() => (0x04000000u32 as uint32_t);}
macro_rules! DMA_LISR_TEIF3 {() => (0x02000000u32 as uint32_t);}
macro_rules! DMA_LISR_DMEIF3 {() => (0x01000000u32 as uint32_t);}
macro_rules! DMA_LISR_FEIF3 {() => (0x00400000u32 as uint32_t);}
macro_rules! DMA_LISR_TCIF2 {() => (0x00200000u32 as uint32_t);}
macro_rules! DMA_LISR_HTIF2 {() => (0x00100000u32 as uint32_t);}
macro_rules! DMA_LISR_TEIF2 {() => (0x00080000u32 as uint32_t);}
macro_rules! DMA_LISR_DMEIF2 {() => (0x00040000u32 as uint32_t);}
macro_rules! DMA_LISR_FEIF2 {() => (0x00010000u32 as uint32_t);}
macro_rules! DMA_LISR_TCIF1 {() => (0x00000800u32 as uint32_t);}
macro_rules! DMA_LISR_HTIF1 {() => (0x00000400u32 as uint32_t);}
macro_rules! DMA_LISR_TEIF1 {() => (0x00000200u32 as uint32_t);}
macro_rules! DMA_LISR_DMEIF1 {() => (0x00000100u32 as uint32_t);}
macro_rules! DMA_LISR_FEIF1 {() => (0x00000040u32 as uint32_t);}
macro_rules! DMA_LISR_TCIF0 {() => (0x00000020u32 as uint32_t);}
macro_rules! DMA_LISR_HTIF0 {() => (0x00000010u32 as uint32_t);}
macro_rules! DMA_LISR_TEIF0 {() => (0x00000008u32 as uint32_t);}
macro_rules! DMA_LISR_DMEIF0 {() => (0x00000004u32 as uint32_t);}
macro_rules! DMA_LISR_FEIF0 {() => (0x00000001u32 as uint32_t);}
/* Bits definition for DMA_HISR register */
macro_rules! DMA_HISR_TCIF7 {() => (0x08000000u32 as uint32_t);}
macro_rules! DMA_HISR_HTIF7 {() => (0x04000000u32 as uint32_t);}
macro_rules! DMA_HISR_TEIF7 {() => (0x02000000u32 as uint32_t);}
macro_rules! DMA_HISR_DMEIF7 {() => (0x01000000u32 as uint32_t);}
macro_rules! DMA_HISR_FEIF7 {() => (0x00400000u32 as uint32_t);}
macro_rules! DMA_HISR_TCIF6 {() => (0x00200000u32 as uint32_t);}
macro_rules! DMA_HISR_HTIF6 {() => (0x00100000u32 as uint32_t);}
macro_rules! DMA_HISR_TEIF6 {() => (0x00080000u32 as uint32_t);}
macro_rules! DMA_HISR_DMEIF6 {() => (0x00040000u32 as uint32_t);}
macro_rules! DMA_HISR_FEIF6 {() => (0x00010000u32 as uint32_t);}
macro_rules! DMA_HISR_TCIF5 {() => (0x00000800u32 as uint32_t);}
macro_rules! DMA_HISR_HTIF5 {() => (0x00000400u32 as uint32_t);}
macro_rules! DMA_HISR_TEIF5 {() => (0x00000200u32 as uint32_t);}
macro_rules! DMA_HISR_DMEIF5 {() => (0x00000100u32 as uint32_t);}
macro_rules! DMA_HISR_FEIF5 {() => (0x00000040u32 as uint32_t);}
macro_rules! DMA_HISR_TCIF4 {() => (0x00000020u32 as uint32_t);}
macro_rules! DMA_HISR_HTIF4 {() => (0x00000010u32 as uint32_t);}
macro_rules! DMA_HISR_TEIF4 {() => (0x00000008u32 as uint32_t);}
macro_rules! DMA_HISR_DMEIF4 {() => (0x00000004u32 as uint32_t);}
macro_rules! DMA_HISR_FEIF4 {() => (0x00000001u32 as uint32_t);}
/* Bits definition for DMA_LIFCR register */
macro_rules! DMA_LIFCR_CTCIF3 {() => (0x08000000u32 as uint32_t);}
macro_rules! DMA_LIFCR_CHTIF3 {() => (0x04000000u32 as uint32_t);}
macro_rules! DMA_LIFCR_CTEIF3 {() => (0x02000000u32 as uint32_t);}
macro_rules! DMA_LIFCR_CDMEIF3 {() => (0x01000000u32 as uint32_t);}
macro_rules! DMA_LIFCR_CFEIF3 {() => (0x00400000u32 as uint32_t);}
macro_rules! DMA_LIFCR_CTCIF2 {() => (0x00200000u32 as uint32_t);}
macro_rules! DMA_LIFCR_CHTIF2 {() => (0x00100000u32 as uint32_t);}
macro_rules! DMA_LIFCR_CTEIF2 {() => (0x00080000u32 as uint32_t);}
macro_rules! DMA_LIFCR_CDMEIF2 {() => (0x00040000u32 as uint32_t);}
macro_rules! DMA_LIFCR_CFEIF2 {() => (0x00010000u32 as uint32_t);}
macro_rules! DMA_LIFCR_CTCIF1 {() => (0x00000800u32 as uint32_t);}
macro_rules! DMA_LIFCR_CHTIF1 {() => (0x00000400u32 as uint32_t);}
macro_rules! DMA_LIFCR_CTEIF1 {() => (0x00000200u32 as uint32_t);}
macro_rules! DMA_LIFCR_CDMEIF1 {() => (0x00000100u32 as uint32_t);}
macro_rules! DMA_LIFCR_CFEIF1 {() => (0x00000040u32 as uint32_t);}
macro_rules! DMA_LIFCR_CTCIF0 {() => (0x00000020u32 as uint32_t);}
macro_rules! DMA_LIFCR_CHTIF0 {() => (0x00000010u32 as uint32_t);}
macro_rules! DMA_LIFCR_CTEIF0 {() => (0x00000008u32 as uint32_t);}
macro_rules! DMA_LIFCR_CDMEIF0 {() => (0x00000004u32 as uint32_t);}
macro_rules! DMA_LIFCR_CFEIF0 {() => (0x00000001u32 as uint32_t);}