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b9c0b8a Add an extensions.txt file.
steve authored
2 Icarus Verilog Extensions
4 Icarus Verilog supports certain extensions to the baseline IEEE1364
5 standard. Some of these are picked from extended variants of the
6 language, such as SystemVerilog, and some are expressions of internal
7 behavior of Icarus Verilog, made available as a tool debugging aid.
9 * Builtin System Functions
11 ** Extended Verilog Data Types
13 This feature is turned off if the generation flag "-g" is set to other
14 then the default "2x". For example, "iverilog -g2x" enables extended
15 data types, and "iverilog -g2" disables them.
17 Icarus Verilog adds support for extended data types. This extended
18 type syntax is based on a proposal by Cadence Design Systems,
19 originally as an update to the IEEE1364. That original proposal has
20 apparently been absorbed by the IEEE1800 SystemVerilog
21 standard. Icarus Verilog currently only takes the new primitive types
22 from the proposal.
be73be8 Spelling patches from Larry.
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24 Extended data types separates the concept of net/variable from the
b9c0b8a Add an extensions.txt file.
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25 data type. Both nets and variables can declared with any data
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26 type. The primitive types available are:
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28 logic - The familiar 0, 1, x and z, optionally with strength.
29 bool - Limited to only 0 and 1
30 real - 64bit real values
32 Nets with logic type may have multiple drivers with strength, and the
33 value is resolved the usual way. Only logic values may be driven to
34 logic nets, so bool values driven onto logic nets are implicitly
35 converted to logic.
37 Nets with any other type may not have multiple drivers. The compiler
38 should detect the multiple drivers and report an error.
40 - Declarations
42 The declaration of a net is extended to include the type of the wire,
43 with the syntax:
45 wire <type> <wire-assignment-list>... ;
47 The <type>, if omitted, is taken to be logic. The "wire" can be any of
48 the net keywords. Wires can be logic, bool, real, or vectors of logic
49 or bool. Some valid examples:
51 wire real foo = 1.0;
52 tri logic bus[31:0];
53 wire bool addr[23:0];
54 ... and so on.
56 The declarations of variables is similar. The "reg" keyword is used to
57 specify that this is a variable. Variables can have the same data
58 types as nets.
60 - Ports
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62 Module and task ports in standard Verilog are restricted to logic
b9c0b8a Add an extensions.txt file.
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63 types. This extension removes that restriction, allowing any type to
64 pass through the port consistent with the continuous assignment
65 connectivity that is implied by the type.
67 - Expressions
69 Expressions in the face of real values is covered by the baseline
70 Verilog standard.
72 The bool type supports the same operators as the logic type, with the
293976b Spelling fixes.
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73 obvious differences imposed by the limited domain.
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75 Comparison operators (not case compare) return logic if either of
76 their operands is logic. If both are bool or real (including mix of
77 bool and real) then the result is bool. This is because comparison of
78 bools and reals always return exactly true or false.
80 Case comparison returns bool. This differs from baseline Verilog,
81 which strictly speaking returns a logic, but only 0 or 1 values.
83 All the arithmetic operators return bool if both of their operands are
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84 bool or real. Otherwise, they return logic.
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