Skip to content

HTTPS clone URL

Subversion checkout URL

You can clone with
or
.
Download ZIP
Newer
Older
100644 212 lines (189 sloc) 7.899 kB
3fb7a05 Introduce verilog to CVS.
steve authored
1 #ifndef __target_H
2 #define __target_H
3 /*
41f9a84 Handle much more complex event expressions.
steve authored
4 * Copyright (c) 1998-1999 Stephen Williams (steve@icarus.com)
3fb7a05 Introduce verilog to CVS.
steve authored
5 *
6 * This source code is free software; you can redistribute it
7 * and/or modify it in source code form under the terms of the GNU
8 * General Public License as published by the Free Software
9 * Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
20 */
b734ecf Macintosh compilers do not support ident.
steve authored
21 #if !defined(WINNT) && !defined(macintosh)
d58533f target methods need not take a file stream.
steve authored
22 #ident "$Id: target.h,v 1.41 2000/08/08 01:50:42 steve Exp $"
3fb7a05 Introduce verilog to CVS.
steve authored
23 #endif
24
25 # include "netlist.h"
26 class ostream;
27
28 /*
29 * This header file describes the types and constants used to describe
30 * the possible target output types of the compiler. The backends
31 * provide one of these in order to tell the previous steps what the
32 * backend is able to do.
33 */
34
35 /*
36 * The backend driver is hooked into the compiler, and given a name,
37 * by creating an instance of the target structure. The structure has
38 * the name that the compiler will use to locate the driver, and a
39 * pointer to a target_t object that is the actual driver.
40 */
41 struct target {
42 string name;
43 struct target_t* meth;
44 };
45
46 /*
47 * The emit process uses a target_t driver to send the completed
48 * design to a file. It is up to the driver object to follow along in
49 * the iteration through the design, generating output as it can.
50 */
51
52 struct target_t {
53 virtual ~target_t();
54
d58533f target methods need not take a file stream.
steve authored
55 /* Start the design. This sets the main output file stream
56 that the target should use. */
3fb7a05 Introduce verilog to CVS.
steve authored
57 virtual void start_design(ostream&os, const Design*);
58
4cfa3e4 Support the creation of scopes.
steve authored
59 /* This is called once for each scope in the design, before
60 anything else is called. */
d58533f target methods need not take a file stream.
steve authored
61 virtual void scope(const NetScope*);
4cfa3e4 Support the creation of scopes.
steve authored
62
30e8289 Simulate named event trigger and waits.
steve authored
63 /* Output an event object. Called for each named event in the scope. */
d58533f target methods need not take a file stream.
steve authored
64 virtual void event(const NetEvent*);
30e8289 Simulate named event trigger and waits.
steve authored
65
3fb7a05 Introduce verilog to CVS.
steve authored
66 /* Output a signal (called for each signal) */
d58533f target methods need not take a file stream.
steve authored
67 virtual void signal(const NetNet*);
3fb7a05 Introduce verilog to CVS.
steve authored
68
5895d3c Add memories to the parse and elaboration phases.
steve authored
69 /* Output a memory (called for each memory object) */
d58533f target methods need not take a file stream.
steve authored
70 virtual void memory(const NetMemory*);
5895d3c Add memories to the parse and elaboration phases.
steve authored
71
3ff6912 Elaborate user defined tasks.
steve authored
72 /* Output a defined task. */
d58533f target methods need not take a file stream.
steve authored
73 virtual void task_def(const NetTaskDef*);
74 virtual void func_def(const NetFuncDef*);
3ff6912 Elaborate user defined tasks.
steve authored
75
41a1c6b elaborate the binary plus operator.
steve authored
76 /* LPM style components are handled here. */
d58533f target methods need not take a file stream.
steve authored
77 virtual void lpm_add_sub(const NetAddSub*);
78 virtual void lpm_clshift(const NetCLShift*);
79 virtual void lpm_compare(const NetCompare*);
80 virtual void lpm_divide(const NetDivide*);
81 virtual void lpm_ff(const NetFF*);
82 virtual void lpm_mult(const NetMult*);
83 virtual void lpm_mux(const NetMux*);
84 virtual void lpm_ram_dq(const NetRamDq*);
41a1c6b elaborate the binary plus operator.
steve authored
85
3fb7a05 Introduce verilog to CVS.
steve authored
86 /* Output a gate (called for each gate) */
d58533f target methods need not take a file stream.
steve authored
87 virtual void logic(const NetLogic*);
88 virtual void bufz(const NetBUFZ*);
89 virtual void udp(const NetUDP*);
90 virtual void udp_comb(const NetUDP_COMB*);
91 virtual void net_assign(const NetAssign*);
92 virtual void net_assign_nb(const NetAssignNB*);
93 virtual void net_case_cmp(const NetCaseCmp*);
94 virtual bool net_cassign(const NetCAssign*);
95 virtual void net_const(const NetConst*);
96 virtual bool net_force(const NetForce*);
97 virtual void net_probe(const NetEvProbe*);
3fb7a05 Introduce verilog to CVS.
steve authored
98
7ba7b92 simplified process scan for targets.
steve authored
99 /* Output a process (called for each process). It is up to the
100 target to recurse if desired. */
d58533f target methods need not take a file stream.
steve authored
101 virtual bool process(const NetProcTop*);
3fb7a05 Introduce verilog to CVS.
steve authored
102
103 /* Various kinds of process nodes are dispatched through these. */
d58533f target methods need not take a file stream.
steve authored
104 virtual void proc_assign(const NetAssign*);
105 virtual void proc_assign_mem(const NetAssignMem*);
106 virtual void proc_assign_nb(const NetAssignNB*);
107 virtual void proc_assign_mem_nb(const NetAssignMemNB*);
108 virtual bool proc_block(const NetBlock*);
109 virtual void proc_case(const NetCase*);
110 virtual bool proc_cassign(const NetCAssign*);
111 virtual void proc_condit(const NetCondit*);
112 virtual bool proc_deassign(const NetDeassign*);
113 virtual bool proc_delay(const NetPDelay*);
114 virtual bool proc_disable(const NetDisable*);
115 virtual bool proc_force(const NetForce*);
116 virtual void proc_forever(const NetForever*);
117 virtual bool proc_release(const NetRelease*);
118 virtual void proc_repeat(const NetRepeat*);
119 virtual bool proc_trigger(const NetEvTrig*);
120 virtual void proc_stask(const NetSTask*);
121 virtual void proc_utask(const NetUTask*);
122 virtual bool proc_wait(const NetEvWait*);
123 virtual void proc_while(const NetWhile*);
3fb7a05 Introduce verilog to CVS.
steve authored
124
125 /* Done with the design. */
d58533f target methods need not take a file stream.
steve authored
126 virtual void end_design(const Design*);
3fb7a05 Introduce verilog to CVS.
steve authored
127 };
128
129 /* This class is used by the NetExpr class to help with the scanning
130 of expressions. */
131 struct expr_scan_t {
132 virtual ~expr_scan_t();
133 virtual void expr_const(const NetEConst*);
1464851 Add support for procedural concatenation expression.
steve authored
134 virtual void expr_concat(const NetEConcat*);
3fb7a05 Introduce verilog to CVS.
steve authored
135 virtual void expr_ident(const NetEIdent*);
5895d3c Add memories to the parse and elaboration phases.
steve authored
136 virtual void expr_memory(const NetEMemory*);
4cfa3e4 Support the creation of scopes.
steve authored
137 virtual void expr_scope(const NetEScope*);
fbe475e Add infrastructure for system functions, move
steve authored
138 virtual void expr_sfunc(const NetESFunc*);
b118634 Handle procedural conditional, and some
steve authored
139 virtual void expr_signal(const NetESignal*);
09cfbc6 Core handles subsignal expressions.
steve authored
140 virtual void expr_subsignal(const NetESubSignal*);
a5921ce netlist support for ternary operator.
steve authored
141 virtual void expr_ternary(const NetETernary*);
e69345b Elaborate and emit to vvm procedural functions.
steve authored
142 virtual void expr_ufunc(const NetEUFunc*);
3fb7a05 Introduce verilog to CVS.
steve authored
143 virtual void expr_unary(const NetEUnary*);
b118634 Handle procedural conditional, and some
steve authored
144 virtual void expr_binary(const NetEBinary*);
3fb7a05 Introduce verilog to CVS.
steve authored
145 };
146
147
148 /* The emit functions take a design and emit it to the output stream
149 using the specified target. If the target is given by name, it is
150 located in the target_table and used. */
0955058 Catch parallel blocks in vvm emit.
steve authored
151 extern bool emit(ostream&o, const Design*des, const char*type);
3fb7a05 Introduce verilog to CVS.
steve authored
152
153 /* This function takes a fully qualified verilog name (which may have,
154 for example, dots in it) and produces a mangled version that can be
155 used by most any language. */
156 extern string mangle(const string&str);
157
158 /* This is the table of supported output targets. It is a null
159 terminated array of pointers to targets. */
160 extern const struct target *target_table[];
161
162 /*
163 * $Log: target.h,v $
d58533f target methods need not take a file stream.
steve authored
164 * Revision 1.41 2000/08/08 01:50:42 steve
165 * target methods need not take a file stream.
166 *
3aa250b Report code generation errors through proc_delay.
steve authored
167 * Revision 1.40 2000/07/29 16:21:08 steve
168 * Report code generation errors through proc_delay.
169 *
4494a7a Support elaboration of disable statements.
steve authored
170 * Revision 1.39 2000/07/27 05:13:44 steve
171 * Support elaboration of disable statements.
172 *
367db72 Add support for procedural continuous assignment.
steve authored
173 * Revision 1.38 2000/05/11 23:37:27 steve
174 * Add support for procedural continuous assignment.
175 *
fbe475e Add infrastructure for system functions, move
steve authored
176 * Revision 1.37 2000/05/04 03:37:59 steve
177 * Add infrastructure for system functions, move
178 * $time to that structure and add $random.
179 *
a8114ae Add support for the procedural release statement.
steve authored
180 * Revision 1.36 2000/04/23 03:45:25 steve
181 * Add support for the procedural release statement.
182 *
44838f8 Add support for force assignment.
steve authored
183 * Revision 1.35 2000/04/22 04:20:20 steve
184 * Add support for force assignment.
185 *
b1fd927 Named events really should be expressed with PEIdent
steve authored
186 * Revision 1.34 2000/04/12 04:23:58 steve
187 * Named events really should be expressed with PEIdent
188 * objects in the pform,
189 *
190 * Handle named events within the mix of net events
191 * and edges. As a unified lot they get caught together.
192 * wait statements are broken into more complex statements
193 * that include a conditional.
194 *
195 * Do not generate NetPEvent or NetNEvent objects in
196 * elaboration. NetEvent, NetEvWait and NetEvProbe
197 * take over those functions in the netlist.
198 *
8dbd641 All events now use the NetEvent class.
steve authored
199 * Revision 1.33 2000/04/10 05:26:06 steve
200 * All events now use the NetEvent class.
201 *
30e8289 Simulate named event trigger and waits.
steve authored
202 * Revision 1.32 2000/04/04 03:20:15 steve
203 * Simulate named event trigger and waits.
204 *
694ff93 Add support for integer division.
steve authored
205 * Revision 1.31 2000/04/01 21:40:23 steve
206 * Add support for integer division.
207 *
d97ab9b New and improved combinational primitives.
steve authored
208 * Revision 1.30 2000/03/29 04:37:11 steve
209 * New and improved combinational primitives.
3fb7a05 Introduce verilog to CVS.
steve authored
210 */
211 #endif
Something went wrong with that request. Please try again.