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1 #ifndef __target_H
2 #define __target_H
3 /*
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4 * Copyright (c) 1998-1999 Stephen Williams (steve@icarus.com)
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5 *
6 * This source code is free software; you can redistribute it
7 * and/or modify it in source code form under the terms of the GNU
8 * General Public License as published by the Free Software
9 * Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
20 */
21 #if !defined(WINNT)
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22 #ident "$Id: target.h,v 1.16 1999/08/31 22:38:29 steve Exp $"
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23 #endif
24
25 # include "netlist.h"
26 class ostream;
27
28 /*
29 * This header file describes the types and constants used to describe
30 * the possible target output types of the compiler. The backends
31 * provide one of these in order to tell the previous steps what the
32 * backend is able to do.
33 */
34
35 /*
36 * The backend driver is hooked into the compiler, and given a name,
37 * by creating an instance of the target structure. The structure has
38 * the name that the compiler will use to locate the driver, and a
39 * pointer to a target_t object that is the actual driver.
40 */
41 struct target {
42 string name;
43 struct target_t* meth;
44 };
45
46 /*
47 * The emit process uses a target_t driver to send the completed
48 * design to a file. It is up to the driver object to follow along in
49 * the iteration through the design, generating output as it can.
50 */
51
52 struct target_t {
53 virtual ~target_t();
54
55 /* Start the design. */
56 virtual void start_design(ostream&os, const Design*);
57
58 /* Output a signal (called for each signal) */
59 virtual void signal(ostream&os, const NetNet*);
60
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61 /* Output a memory (called for each memory object) */
62 virtual void memory(ostream&os, const NetMemory*);
63
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64 /* Output a defined task. */
65 virtual void task_def(ostream&, const NetTaskDef*);
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66 virtual void func_def(ostream&, const NetFuncDef*);
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67
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68 /* Output a gate (called for each gate) */
69 virtual void logic(ostream&os, const NetLogic*);
70 virtual void bufz(ostream&os, const NetBUFZ*);
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71 virtual void udp(ostream&os, const NetUDP*);
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72 virtual void net_assign(ostream&os, const NetAssign*);
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73 virtual void net_assign_nb(ostream&os, const NetAssignNB*);
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74 virtual void net_const(ostream&os, const NetConst*);
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75 virtual void net_esignal(ostream&os, const NetESignal*);
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76 virtual void net_event(ostream&os, const NetNEvent*);
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77
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78 /* Output a process (called for each process). It is up to the
79 target to recurse if desired. */
80 virtual void process(ostream&os, const NetProcTop*);
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81
82 /* Various kinds of process nodes are dispatched through these. */
83 virtual void proc_assign(ostream&os, const NetAssign*);
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84 virtual void proc_assign_mem(ostream&os, const NetAssignMem*);
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85 virtual void proc_assign_nb(ostream&os, const NetAssignNB*);
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86 virtual void proc_block(ostream&os, const NetBlock*);
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87 virtual void proc_case(ostream&os, const NetCase*);
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88 virtual void proc_condit(ostream&os, const NetCondit*);
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89 virtual void proc_forever(ostream&os, const NetForever*);
90 virtual void proc_repeat(ostream&os, const NetRepeat*);
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91 virtual void proc_stask(ostream&os, const NetSTask*);
92 virtual void proc_utask(ostream&os, const NetUTask*);
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93 virtual void proc_while(ostream&os, const NetWhile*);
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94
95 virtual void proc_event(ostream&os, const NetPEvent*);
96 virtual void proc_delay(ostream&os, const NetPDelay*);
97
98 /* Done with the design. */
99 virtual void end_design(ostream&os, const Design*);
100 };
101
102 /* This class is used by the NetExpr class to help with the scanning
103 of expressions. */
104 struct expr_scan_t {
105 virtual ~expr_scan_t();
106 virtual void expr_const(const NetEConst*);
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107 virtual void expr_concat(const NetEConcat*);
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108 virtual void expr_ident(const NetEIdent*);
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109 virtual void expr_memory(const NetEMemory*);
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110 virtual void expr_signal(const NetESignal*);
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111 virtual void expr_subsignal(const NetESubSignal*);
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112 virtual void expr_ternary(const NetETernary*);
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113 virtual void expr_ufunc(const NetEUFunc*);
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114 virtual void expr_unary(const NetEUnary*);
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115 virtual void expr_binary(const NetEBinary*);
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116 };
117
118
119 /* The emit functions take a design and emit it to the output stream
120 using the specified target. If the target is given by name, it is
121 located in the target_table and used. */
122 extern void emit(ostream&o, const Design*des, const char*type);
123
124 /* This function takes a fully qualified verilog name (which may have,
125 for example, dots in it) and produces a mangled version that can be
126 used by most any language. */
127 extern string mangle(const string&str);
128
129 /* This is the table of supported output targets. It is a null
130 terminated array of pointers to targets. */
131 extern const struct target *target_table[];
132
133 /*
134 * $Log: target.h,v $
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135 * Revision 1.16 1999/08/31 22:38:29 steve
136 * Elaborate and emit to vvm procedural functions.
137 *
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138 * Revision 1.15 1999/07/17 19:51:00 steve
139 * netlist support for ternary operator.
140 *
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141 * Revision 1.14 1999/07/17 03:39:11 steve
142 * simplified process scan for targets.
143 *
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144 * Revision 1.13 1999/07/03 02:12:52 steve
145 * Elaborate user defined tasks.
146 *
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147 * Revision 1.12 1999/06/19 21:06:16 steve
148 * Elaborate and supprort to vvm the forever
149 * and repeat statements.
150 *
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151 * Revision 1.11 1999/06/09 03:00:06 steve
152 * Add support for procedural concatenation expression.
153 *
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154 * Revision 1.10 1999/06/06 20:45:39 steve
155 * Add parse and elaboration of non-blocking assignments,
156 * Replace list<PCase::Item*> with an svector version,
157 * Add integer support.
158 *
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159 * Revision 1.9 1999/05/12 04:03:20 steve
160 * emit NetAssignMem objects in vvm target.
161 *
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162 * Revision 1.8 1999/05/01 02:57:53 steve
163 * Handle much more complex event expressions.
164 *
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165 * Revision 1.7 1999/04/25 00:44:10 steve
166 * Core handles subsignal expressions.
167 *
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168 * Revision 1.6 1999/04/19 01:59:37 steve
169 * Add memories to the parse and elaboration phases.
170 *
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171 * Revision 1.5 1999/02/08 02:49:56 steve
172 * Turn the NetESignal into a NetNode so
173 * that it can connect to the netlist.
174 * Implement the case statement.
175 * Convince t-vvm to output code for
176 * the case statement.
177 *
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178 * Revision 1.4 1998/12/01 00:42:15 steve
179 * Elaborate UDP devices,
180 * Support UDP type attributes, and
181 * pass those attributes to nodes that
182 * are instantiated by elaboration,
183 * Put modules into a map instead of
184 * a simple list.
185 *
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186 * Revision 1.3 1998/11/09 18:55:35 steve
187 * Add procedural while loops,
188 * Parse procedural for loops,
189 * Add procedural wait statements,
190 * Add constant nodes,
191 * Add XNOR logic gate,
192 * Make vvm output look a bit prettier.
193 *
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194 * Revision 1.2 1998/11/07 17:05:06 steve
195 * Handle procedural conditional, and some
196 * of the conditional expressions.
197 *
198 * Elaborate signals and identifiers differently,
199 * allowing the netlist to hold signal information.
200 *
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201 * Revision 1.1 1998/11/03 23:29:06 steve
202 * Introduce verilog to CVS.
203 *
204 */
205 #endif
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