You can clone with
Cannot retrieve contributors at this time
THE VVP TARGETSYMBOL NAME CONVENTIONSThere are some naming conventions that the vp target uses forgenerating symbol names.* wires and regsNets and variables are named V_<full-name> where <full-name> is thefull hierarchical name of the signal.* Logic devicesLogic devices (and, or, buf, bufz, etc.) are named L_<full_name>. Inthis case the symbol is attached to a functor that is the output ofthe logic device.GENERAL FUNCTOR WEB STRUCTUREThe net of gates, signals and resolvers is formed from the inputdesign. The basic structure is wrapped around the nexus, which isrepresented by the ivl_nexus_t.Each nexus represents a resolved value. The input of the nexus is fedby a single driver. If the nexus in the design has multiple drivers,the drivers are first fed into a resolver (or a tree of resolvers) toform a single output that is the nexus.The nexus, then, feeds its output to the inputs of other gates, or tothe .net objects in the design.