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Update to v0.8.4 release.

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commit 1b551aaf94439e2512f442488bab7468495355e2 1 parent a3dda80
steve authored
Showing with 5 additions and 5 deletions.
  1. +2 −2 Makefile.in
  2. +3 −3 verilog.spec
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4 Makefile.in
@@ -16,7 +16,7 @@
# 59 Temple Place - Suite 330
# Boston, MA 02111-1307, USA
#
-#ident "$Id: Makefile.in,v 1.169.2.5 2006/10/04 17:08:59 steve Exp $"
+#ident "$Id: Makefile.in,v 1.169.2.6 2007/03/23 23:26:51 steve Exp $"
#
#
SHELL = /bin/sh
@@ -25,7 +25,7 @@ SHELL = /bin/sh
# by the compiler. It reflects the assigned version number for the
# product as a whole. Most components also print the CVS Name: token
# in order to get a more automatic version stamp as well.
-VERSION = 0.8.3
+VERSION = 0.8.4
prefix = @prefix@
exec_prefix = @exec_prefix@
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6 verilog.spec
@@ -1,10 +1,10 @@
Summary: Icarus Verilog
Name: verilog
-Version: 0.8.3
+Version: 0.8.4
Release: 0
License: GPL
Group: Applications/Engineering
-Source: ftp://icarus.com/pub/eda/verilog/v0.8/verilog-0.8.3.tar.gz
+Source: ftp://icarus.com/pub/eda/verilog/v0.8/verilog-0.8.4.tar.gz
URL: http://www.icarus.com/eda/verilog/index.html
Packager: Stephen Williams <steve@icarus.com>
@@ -29,7 +29,7 @@ engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard.
%prep
-%setup -n verilog-0.8.3
+%setup -n verilog-0.8.4
%build
%ifarch x86_64
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