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Prepare for v0.8.5 release.

Signed-off-by: Stephen Williams <steve@icarus.com>
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steveicarus committed Jul 24, 2007
1 parent d16a0bd commit 2fc5f4f7d8bde155a59d8628f042cffc2e00db39
Showing with 4 additions and 4 deletions.
  1. +1 −1 Makefile.in
  2. +3 −3 verilog.spec
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@@ -25,7 +25,7 @@ SHELL = /bin/sh
# by the compiler. It reflects the assigned version number for the
# product as a whole. Most components also print the CVS Name: token
# in order to get a more automatic version stamp as well.
-VERSION = 0.8.4
+VERSION = 0.8.5
prefix = @prefix@
exec_prefix = @exec_prefix@
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@@ -1,10 +1,10 @@
Summary: Icarus Verilog
Name: verilog
-Version: 0.8.4
+Version: 0.8.5
Release: 0
License: GPL
Group: Applications/Engineering
-Source: ftp://icarus.com/pub/eda/verilog/v0.8/verilog-0.8.4.tar.gz
+Source: ftp://icarus.com/pub/eda/verilog/v0.8/verilog-0.8.5.tar.gz
URL: http://www.icarus.com/eda/verilog/index.html
Packager: Stephen Williams <steve@icarus.com>
@@ -29,7 +29,7 @@ engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard.
%prep
-%setup -n verilog-0.8.4
+%setup -n verilog-0.8.5
%build
%ifarch x86_64

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