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Non-controversial whitespace cleanup

Nothing to do with tab width!  Eliminates useless
trailing spaces and tabs, and nearly all <space><tab>
pairings.  No change to derived files (e.g., .vvp),
non-master files (e.g., lxt2_write.c) or the new tgt-vhdl
directory.

Low priority, simple entropy reduction.  Please apply
unless it deletes some steganographic content you want
to keep.
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1 parent 6f00293 commit 66949122cf4cee30e72e693550989cef58240a61 @ldoolitt ldoolitt committed with steveicarus Sep 4, 2008
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@@ -3,7 +3,7 @@
`ifdef CONSTANTS_VAMS
`else
`define CONSTANTS_VAMS 1
-
+
// M_ is a mathematical constant
`define M_E 2.7182818284590452354
`define M_LOG2E 1.4426950408889634074
View
@@ -149,7 +149,7 @@ int cmdfile_stack_ptr = 0;
cflval.text = trim_trailing_white(yytext, 0);
BEGIN(0);
return TOK_STRING; }
-
+
/* Fallback match. */
. { return yytext[0]; }
View
@@ -221,7 +221,7 @@ implies the synthesis \fB-S\fP flag.
.TP 8
.B vhdl
This target produces a VHDL translation of the Verilog netlist. The
-output is a single file containing VHDL entities corresponding to
+output is a single file containing VHDL entities corresponding to
the modules in the Verilog source code. Note that only a subset of
the Verilog language is supported. See the wiki for more information.
View
@@ -341,7 +341,7 @@ static int t_default(char*cmd, unsigned ncmd)
} else {
fprintf(stderr, "Command signaled: %s\n", cmd);
rtn = -1;
- }
+ }
}
free(cmd);
@@ -523,7 +523,7 @@ int process_generation(const char*name)
void add_sft_file(const char *module)
{
char *file;
-
+
file = (char *) malloc(strlen(base)+1+strlen(module)+4+1);
sprintf(file, "%s%c%s.sft", base, sep, module);
if (access(file, R_OK) == 0)
@@ -654,7 +654,7 @@ int main(int argc, char **argv)
case 'c':
case 'f':
add_cmd_file(optarg);
- break;
+ break;
case 'D':
process_define(optarg);
break;
@@ -673,9 +673,9 @@ int main(int argc, char **argv)
if (rc != 0)
return -1;
break;
- case 'h':
- fprintf(stderr, "%s\n", HELP);
- return 1;
+ case 'h':
+ fprintf(stderr, "%s\n", HELP);
+ return 1;
case 'I':
process_include_dir(optarg);
View
@@ -504,7 +504,7 @@ NetExpr* PECallFunction::elaborate_sfunc_(Design*des, NetScope*scope, int expr_w
/* Elaborate the sub-expression to get its
self-determined width, and save that width. Then
delete the expression because we don't really want
- the expression itself. */
+ the expression itself. */
long sub_expr_width = 0;
if (NetExpr*tmp = expr->elaborate_expr(des, scope, -1, true)) {
sub_expr_width = tmp->expr_width();
View
@@ -394,15 +394,15 @@ static NetNet* compare_eq_constant(Design*des, NetScope*scope,
if (zeros > 0) {
type = op_code == 'e'? NetUReduce::NOR : NetUReduce::OR;
- if (debug_elaborate)
+ if (debug_elaborate)
cerr << lsig->get_fileline() << ": debug: "
<< "Replace net==" << val << " equality with "
<< zeros << "-input reduction [N]OR gate." << endl;
} else {
type = op_code == 'e'? NetUReduce::AND : NetUReduce::NAND;
- if (debug_elaborate)
+ if (debug_elaborate)
cerr << lsig->get_fileline() << ": debug: "
<< "Replace net==" << val << " equality with "
<< ones << "-input reduction AND gate." << endl;
@@ -1227,8 +1227,8 @@ NetNet* PEBinary::elaborate_net_shift_(Design*des, NetScope*scope,
}
/* If all data bits get shifted away, connect the zero or
- * padding bits directly to output, and stop before building the
- * concatenation. */
+ * padding bits directly to output, and stop before building the
+ * concatenation. */
if (dist >= lwidth) {
connect(osig->pin(0), zero->pin(0));
return osig;
@@ -1829,7 +1829,7 @@ NetNet* PEIdent::elaborate_net(Design*des, NetScope*scope,
if (id_msb || id_lsb) {
assert(id_msb && id_lsb);
const NetEConst*tmp = dynamic_cast<const NetEConst*>(id_msb);
- ivl_assert(*this, tmp);
+ ivl_assert(*this, tmp);
msb = tmp->value().as_long();
tmp = dynamic_cast<const NetEConst*>(id_lsb);
@@ -2997,7 +2997,7 @@ NetNet* PENumber::elaborate_net(Design*des, NetScope*scope,
if (value_->get(width-1) != verinum::V0)
break;
width -= 1;
-
+
}
} else if (value_->has_sign() == false) {
@@ -3406,7 +3406,7 @@ NetNet* PEUnary::elaborate_net(Design*des, NetScope*scope,
tmp->decay_time(decay);
connect(tmp->pin(1), sub_sig->pin(0));
- connect(tmp->pin(0), sig->pin(0));
+ connect(tmp->pin(0), sig->pin(0));
}
break;
@@ -3662,7 +3662,7 @@ NetNet* PEUnary::elab_net_unary_real_(Design*des, NetScope*scope,
" for real values." << endl;
des->errors += 1;
break;
-
+
case 'm': { // abs()
NetAbs*tmp = new NetAbs(scope, scope->local_symbol(), 1);
tmp->set_line(*this);
View
@@ -670,7 +670,7 @@ bool PGenerate::generate_scope_case_(Design*des, NetScope*container)
<< "Generate case matches item at "
<< item->get_fileline() << endl;
- // The name of the scope to generate, whatever that item is.
+ // The name of the scope to generate, whatever that item is.
hname_t use_name (item->scope_name);
NetScope*scope = new NetScope(container, use_name,
View
@@ -143,7 +143,7 @@ static void elaborate_sig_tasks(Design*des, NetScope*scope,
}
}
-
+
bool Module::elaborate_sig(Design*des, NetScope*scope) const
{
bool flag = true;
@@ -361,7 +361,7 @@ bool PGModule::elaborate_sig_mod_(Design*des, NetScope*scope,
continue;
flag = tmp->elaborate_sig(des, scope) && flag;
}
-
+
NetScope::scope_vec_t instance = scope->instance_arrays[get_name()];
View
@@ -1364,7 +1364,7 @@ NetExpr* NetETernary::eval_tree(int prune_to_width)
case C_0:
eval_expr(false_val_);
if (debug_eval_tree) {
-
+
cerr << get_fileline() << ": debug: Evaluate ternary with "
<< "constant condition value: ";
print_ternary_cond(cond_);
View
@@ -1103,7 +1103,7 @@ NetNet* NetEUFunc::synthesize(Design*des)
/* Connect the pins to the arguments. */
NetFuncDef*def = func_->func_def();
for (unsigned idx = 0; idx < eparms.count(); idx += 1) {
- NetNet*tmp = pad_to_width(des, eparms[idx],
+ NetNet*tmp = pad_to_width(des, eparms[idx],
def->port(idx)->vector_width());
connect(net->pin(idx+1), tmp->pin(0));
}
View
@@ -282,7 +282,7 @@ int main(int argc, char*argv[])
fclose(src);
break;
}
-
+
case 'v':
fprintf(stderr, "Icarus Verilog Preprocessor version %s\n",
VERSION);
@@ -35,7 +35,7 @@ int acc_object_of_type(handle object, PLI_INT32 type)
if (pli_trace) {
fprintf(pli_trace, "acc_object_of_type(%p \"%s\", %d)",
- object, vpi_get_str(vpiName, object), type);
+ object, vpi_get_str(vpiName, object), type);
fflush(pli_trace);
}
View
@@ -230,16 +230,16 @@ static void process_generation_flag(const char*gen)
} else if (strcmp(gen,"specify") == 0) {
gn_specify_blocks_flag = true;
-
+
} else if (strcmp(gen,"no-specify") == 0) {
gn_specify_blocks_flag = false;
-
+
} else if (strcmp(gen,"verilog-ams") == 0) {
gn_verilog_ams_flag = true;
-
+
} else if (strcmp(gen,"no-verilog-ams") == 0) {
gn_verilog_ams_flag = false;
-
+
} else if (strcmp(gen,"io-range-error") == 0) {
gn_io_range_error_flag = true;
View
@@ -731,7 +731,7 @@ class NetScope : public Attrib {
bool in_func();
/* Is the task or function automatic. */
void is_auto(bool is_auto) { is_auto_ = is_auto; };
- bool is_auto() const { return is_auto_; };
+ bool is_auto() const { return is_auto_; };
const NetTaskDef* task_def() const;
const NetFuncDef* func_def() const;
@@ -768,7 +768,7 @@ class NetScope : public Attrib {
void evaluate_parameters(class Design*);
- // Look for defparams that never matched, and print warnings.
+ // Look for defparams that never matched, and print warnings.
void residual_defparams(class Design*);
/* This method generates a non-hierarchical name that is
View
@@ -355,7 +355,7 @@ number : BASED_NUMBER
based_size = 0; }
;
- /* real and realtime are exactly the same so save some code
+ /* real and realtime are exactly the same so save some code
* with a common matching rule. */
real_or_realtime
: K_real
@@ -3974,7 +3974,7 @@ task_port_decl
}
/* Ports can be integer with a width of [31:0]. */
-
+
| K_input K_integer IDENTIFIER
{ svector<PExpr*>*range_stub = new svector<PExpr*>(2);
PExpr*re;
@@ -4040,7 +4040,7 @@ task_port_decl
}
/* Ports can be time with a width of [63:0] (unsigned). */
-
+
| K_input K_time IDENTIFIER
{ svector<PExpr*>*range_stub = new svector<PExpr*>(2);
PExpr*re;
View
@@ -1688,7 +1688,7 @@ extern "C" ivl_switch_t ivl_scope_switch(ivl_scope_t net, unsigned idx)
assert(idx < net->switches.size());
return net->switches[idx];
}
-
+
extern "C" int ivl_scope_time_precision(ivl_scope_t net)
{
assert(net);
View
@@ -857,7 +857,7 @@ bool dll_target::bufz(const NetBUFZ*net)
logic_attributes(obj, net);
make_logic_delays_(obj, net);
-
+
scope_add_logic(scope, obj);
return true;
View
@@ -1042,7 +1042,7 @@ static void signal_nexus_const(ivl_signal_t sig,
switch (ivl_const_type(con)) {
case IVL_VT_LOGIC:
bits = ivl_const_bits(con);
- for (idx = 0 ; idx < width ; idx += 1) {
+ for (idx = 0 ; idx < width ; idx += 1) {
fprintf(out, "%c", bits[width-idx-1]);
}
break;
View
@@ -362,10 +362,10 @@ static char* draw_net_input_drive(ivl_nexus_t nex, ivl_nexus_ptr_t nptr)
assert(number_is_immediate(d_rise, 64, 0));
assert(number_is_immediate(d_fall, 64, 0));
assert(number_is_immediate(d_decay, 64, 0));
-
+
fprintf(vvp_out, "L_%p/d .functor BUFZ 1, %s, "
"C4<0>, C4<0>, C4<0>;\n", cptr, result);
-
+
fprintf(vvp_out, "L_%p .delay (%lu,%lu,%lu) L_%p/d;\n",
cptr, get_number_immediate(d_rise),
get_number_immediate(d_rise),
View
@@ -2169,7 +2169,7 @@ static struct vector_info draw_select_signal(ivl_expr_t sube,
assert(res.base);
fprintf(vvp_out, " %%load/v %u, v%p_%u, %u; Only need %u of %u bits\n",
res.base, sig, use_word, bit_wid, bit_wid, ivl_expr_width(sube));
-
+
save_signal_lookaside(res.base, sig, use_word, bit_wid);
/* Pad the part select to the desired width. Note that
this *should* always turn into an unsigned pad
View
@@ -176,7 +176,7 @@ static int draw_number_real(ivl_expr_t exp)
/* If this is actually a negative number, then get the
positive equivalent, and set the sign bit in the exponent
- field.
+ field.
To get the positive equivalent of mant we need to take the
negative of the mantissa (0-mant) but also be aware that
View
@@ -539,7 +539,7 @@ static int show_stmt_assign_nb_real(ivl_statement_t net)
lval = ivl_stmt_lval(net, 0);
sig = ivl_lval_sig(lval);
assert(sig);
-
+
if (ivl_signal_dimensions(sig) > 0) {
word_ix = ivl_lval_idx(lval);
assert(word_ix);
View
@@ -77,7 +77,7 @@ V = va_math.o
LIBS = @LIBS@
SYSTEM_VPI_LDFLAGS = $(LIBS)
-VA_MATH_LDFLAGS =
+VA_MATH_LDFLAGS =
ifeq (@MINGW32@,yes)
SYSTEM_VPI_LDFLAGS += @EXTRALIBS@
VA_MATH_LDFLAGS += @EXTRALIBS@
View
@@ -252,8 +252,8 @@ static PLI_INT32 variable_cb_1(p_cb_data cause)
struct t_cb_data cb;
struct vcd_info*info = (struct vcd_info*)cause->user_data;
- if (dump_is_full) return 0;
- if (dump_is_off) return 0;
+ if (dump_is_full) return 0;
+ if (dump_is_off) return 0;
if (dump_header_pending()) return 0;
if (info->scheduled) return 0;
View
@@ -721,7 +721,7 @@ static PLI_INT32 sys_dumpvars_calltf(PLI_BYTE8*name)
for ( ; item; item = vpi_scan(argv)) {
const char *scname;
int add_var = 0;
-
+
vcd_names_sort(&vcd_tab);
/* If this is a signal make sure it has not already
Oops, something went wrong.

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