Skip to content
Browse files

Prepare for snapshot 20070608

  • Loading branch information...
1 parent 0a38499 commit 6f08f92ffcea2681d2e7e3569217c4a0ebd2d29a steve committed Jun 9, 2007
Showing with 4 additions and 4 deletions.
  1. +4 −4 verilog.spec
View
8 verilog.spec
@@ -1,14 +1,14 @@
Summary: Icarus Verilog
Name: verilog
-Version: 0.9.0.20070421
+Version: 0.9.0.20070608
Release: 0
License: GPL
Group: Productivity/Scientific/Electronics
-Source: verilog-20070421.tar.gz
+Source: verilog-20070608.tar.gz
URL: http://www.icarus.com/eda/verilog/index.html
Packager: Stephen Williams <steve@icarus.com>
-BuildRoot: %{_tmppath}/%{name}-%{version}-20070421-%{release}-root
+BuildRoot: %{_tmppath}/%{name}-%{version}-20070608-%{release}-root
BuildRequires: gcc-c++, zlib-devel, bison, flex, gperf, readline-devel
@@ -32,7 +32,7 @@ engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard.
%prep
-%setup -n verilog-20070421
+%setup -n verilog-20070608
%build
%ifarch x86_64

0 comments on commit 6f08f92

Please sign in to comment.
Something went wrong with that request. Please try again.