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Prepare for snapshot 20070608

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commit 6f08f92ffcea2681d2e7e3569217c4a0ebd2d29a 1 parent 0a38499
steve authored

Showing 1 changed file with 4 additions and 4 deletions. Show diff stats Hide diff stats

  1. +4 4 verilog.spec
8 verilog.spec
... ... @@ -1,14 +1,14 @@
1 1 Summary: Icarus Verilog
2 2 Name: verilog
3   -Version: 0.9.0.20070421
  3 +Version: 0.9.0.20070608
4 4 Release: 0
5 5 License: GPL
6 6 Group: Productivity/Scientific/Electronics
7   -Source: verilog-20070421.tar.gz
  7 +Source: verilog-20070608.tar.gz
8 8 URL: http://www.icarus.com/eda/verilog/index.html
9 9 Packager: Stephen Williams <steve@icarus.com>
10 10
11   -BuildRoot: %{_tmppath}/%{name}-%{version}-20070421-%{release}-root
  11 +BuildRoot: %{_tmppath}/%{name}-%{version}-20070608-%{release}-root
12 12
13 13 BuildRequires: gcc-c++, zlib-devel, bison, flex, gperf, readline-devel
14 14
@@ -32,7 +32,7 @@ engineering formats, including simulation. It strives to be true
32 32 to the IEEE-1364 standard.
33 33
34 34 %prep
35   -%setup -n verilog-20070421
  35 +%setup -n verilog-20070608
36 36
37 37 %build
38 38 %ifarch x86_64

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