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Allow SystemVerilog [size] dimension for unpacked arrays.
IEEE 1800-2005/9 says "each fixed-size dimension shall be represented by an address range, such as [1:1024], or a single positive number to specify the size of a fixed-size unpacked array, as in C. In other words, [size] becomes the same as [0:size-1]." This patch implements that translation in the parser. It issues a warning when doing so when the generation flag is less than 2005-sv.
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