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Spelling fixes

only comments and documentation
some punctuation and capitalization for good measure
Changelogs are purposefully untouched
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1 parent 31afec5 commit d9ac146b8f6deff1f2f1cf373fd28531ee8c01be @ldoolitt ldoolitt committed with steveicarus Jan 29, 2008
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@@ -76,7 +76,7 @@ In this case, if possible include not only the sample Verilog program,
but the generated netlist file(s) and a clear indication of what went
wrong. If it is not clear to me, I will ask for clarification.
-* The Output is Correct, But Less Then Ideal
+* The Output is Correct, But Less Than Ideal
If the output is strictly correct, but just not good enough for
practical use, I would like to know. These sorts of problems are
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@@ -31,10 +31,10 @@ extern const char*base;
extern char* iconfig_path;
extern char* iconfig_common_path;
- /* Ths is the optional -M<dependfile> value, if one was supplied. */
+ /* This is the optional -M<dependfile> value, if one was supplied. */
extern const char*depfile;
- /* Ths is the optional -N<path> value, if one was supplied. */
+ /* This is the optional -N<path> value, if one was supplied. */
extern const char*npath;
/* This is the name of the output file that the user selected. */
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@@ -156,7 +156,7 @@ typedef struct t_command_file {
p_command_file cmd_file_head = NULL; /* The FIFO head */
p_command_file cmd_file_tail = NULL; /* The FIFO tail */
-/* Function to add a comamnd file name to the FIFO. */
+/* Function to add a command file name to the FIFO. */
void add_cmd_file(const char* filename)
{
p_command_file new;
@@ -173,7 +173,7 @@ void add_cmd_file(const char* filename)
}
}
-/* Function to return the top comamnd file name from the FIFO. */
+/* Function to return the top command file name from the FIFO. */
char *get_cmd_file()
{
char *filename;
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@@ -30,7 +30,7 @@
# include "ivl_assert.h"
/*
- * The default behavor for the test_width method is to just return the
+ * The default behavior for the test_width method is to just return the
* minimum width that is passed in.
*/
unsigned PExpr::test_width(Design*des, NetScope*scope,
@@ -195,7 +195,7 @@ NetEBinary* PEBinary::elaborate_expr_base_(Design*des,
case '%':
/* The % operator does not support real arguments in
baseline Verilog. But we allow it in our extended
- form of verilog. */
+ form of Verilog. */
if (generation_flag < GN_VER2001X) {
if (lp->expr_type()==IVL_VT_REAL || rp->expr_type()==IVL_VT_REAL) {
cerr << get_fileline() << ": error: Modulus operator may not "
@@ -1379,7 +1379,7 @@ NetExpr* PEIdent::elaborate_expr_net_part_(Design*des, NetScope*scope,
return net;
}
- // If the part select convers exactly the entire
+ // If the part select covers exactly the entire
// vector, then do not bother with it. Return the
// signal itself.
if (net->sig()->sb_to_idx(lsv) == 0 && wid == net->vector_width())
@@ -1417,7 +1417,7 @@ NetExpr* PEIdent::elaborate_expr_net_idx_up_(Design*des, NetScope*scope,
if (NetEConst*base_c = dynamic_cast<NetEConst*> (base)) {
long lsv = base_c->value().as_long();
- // If the part select convers exactly the entire
+ // If the part select covers exactly the entire
// vector, then do not bother with it. Return the
// signal itself.
if (net->sig()->sb_to_idx(lsv) == 0 && wid == net->vector_width())
@@ -1476,7 +1476,7 @@ NetExpr* PEIdent::elaborate_expr_net_idx_do_(Design*des, NetScope*scope,
if (NetEConst*base_c = dynamic_cast<NetEConst*> (base)) {
long lsv = base_c->value().as_long();
- // If the part select convers exactly the entire
+ // If the part select covers exactly the entire
// vector, then do not bother with it. Return the
// signal itself.
if (net->sig()->sb_to_idx(lsv) == (wid-1) && wid == net->vector_width())
@@ -1544,7 +1544,7 @@ NetExpr* PEIdent::elaborate_expr_net_bit_(Design*des, NetScope*scope,
}
// If the vector is only one bit, we are done. The
- // bit select will return the scaler itself.
+ // bit select will return the scalar itself.
if (net->vector_width() == 1)
return net;
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@@ -33,7 +33,7 @@
* assignment. This is common code for the = and <= statements.
*
* What gets generated depends on the structure of the l-value. If the
- * l-value is a simple name (i.e., foo <= <value>) the the NetAssign_
+ * l-value is a simple name (i.e., foo <= <value>) then the NetAssign_
* is created the width of the foo reg and connected to all the
* bits.
*
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@@ -163,7 +163,7 @@ NetNet* PEBinary::elaborate_net_add_(Design*des, NetScope*scope,
/* The owidth is the output width of the lpm_add_sub
- device. If the desired width is greater then the width of
+ device. If the desired width is greater than the width of
the operands, then widen the adder and let code below pad
the operands. */
unsigned owidth = width;
@@ -1122,7 +1122,7 @@ NetNet* PEBinary::elaborate_net_shift_(Design*des, NetScope*scope,
/* Make the constant zero's that I'm going to pad to the
top or bottom of the left expression. Attach a signal
to its output so that I don't have to worry about it
- later. If the left expression is less then the
+ later. If the left expression is less than the
desired width (and we are doing right shifts) then we
can combine the expression padding with the distance
padding to reduce nodes. */
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@@ -350,7 +350,7 @@ bool PGenerate::generate_scope_loop_(Design*des, NetScope*container)
// The initial value for the genvar does not need (nor can it
// use) the genvar itself, so we can evaluate this expression
- // the same way any other paramter value is evaluated.
+ // the same way any other parameter value is evaluated.
NetExpr*init_ex = elab_and_eval(des, container, loop_init, -1);
NetEConst*init = dynamic_cast<NetEConst*> (init_ex);
if (init == 0) {
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@@ -159,7 +159,7 @@ bool Module::elaborate_sig(Design*des, NetScope*scope) const
}
- // Run through all the generate schemes to enaborate the
+ // Run through all the generate schemes to elaborate the
// signals that they hold. Note that the generate schemes hold
// the scopes that they instantiated, so we don't pass any
// scope in.
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@@ -2836,7 +2836,7 @@ NetProc* PForever::elaborate(Design*des, NetScope*scope) const
}
/*
- * Force is like a procedural assignment, most notably prodedural
+ * Force is like a procedural assignment, most notably procedural
* continuous assignment:
*
* force <lval> = <rval>
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@@ -766,7 +766,7 @@ NetEConst* NetEBComp::eval_tree(int prune_to_width)
case '<': // Less than
return eval_less_();
- case '>': // Greater then
+ case '>': // Greater than
return eval_gt_();
default:
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@@ -59,7 +59,7 @@ types as nets.
- Ports
-Module and task ports in standard verilog are restricted to logic
+Module and task ports in standard Verilog are restricted to logic
types. This extension removes that restriction, allowing any type to
pass through the port consistent with the continuous assignment
connectivity that is implied by the type.
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@@ -379,7 +379,7 @@ typedef const struct ivl_attribute_s*ivl_attribute_t;
/* DELAYPATH
* Delaypath objects represent delay paths called out by a specify
- * block in the verilog source file. The destination signal references
+ * block in the Verilog source file. The destination signal references
* the path object, which in turn points to the source for the path.
*
* ivl_path_scope
@@ -1174,7 +1174,7 @@ extern const char*ivl_lpm_string(ivl_lpm_t net);
* SEMANTIC NOTES
* The ivl_lval_width is not necessarily the same as the width of the
* signal or memory word it represents. It is the width of the vector
- * it receives and assigns. This may be less then the width of the
+ * it receives and assigns. This may be less than the width of the
* signal (or even 1) if only a part of the l-value signal is to be
* assigned.
*
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@@ -19,7 +19,7 @@
THE IVL PREPROCESSOR
-The ivlpp command is a verilog preprocessor that handles file
+The ivlpp command is a Verilog preprocessor that handles file
inclusion and macro substitution. The program runs separate from the
actual compiler so as to ease the task of the compiler proper, and
provides a means of preprocessing files off-line.
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@@ -59,7 +59,7 @@ static int yywrap();
struct include_stack_t {
char* path;
- /* If the current input is the the file, this member is set. */
+ /* If the current input is from a file, this member is set. */
FILE*file;
/* If we are reparsing a macro expansion, file is 0 and this
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@@ -52,7 +52,7 @@ handle acc_next(PLI_INT32 *type, handle scope, handle prev)
/*
* The acc_next_* functions need to be reentrant, so we need to
- * rescan all the items upto the previous one, then return
+ * rescan all the items up to the previous one, then return
* the next one.
*/
iter = vpi_iterate(vpiScope, scope); // ICARUS extension
@@ -24,7 +24,7 @@
#include <acc_user.h>
/*
- * tf_getinstance implemented using equvalent acc_ routing
+ * tf_getinstance implemented using equivalent acc_ routing
*/
char *tf_getcstringp(int n)
{
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@@ -32,7 +32,7 @@
extern char* __acc_newstring(const char*txt);
/*
- * Trace file for loggint ACC and TF calls.
+ * Trace file for logging ACC and TF calls.
*/
FILE* pli_trace;
@@ -23,7 +23,7 @@
/*
* Contains the routines required to implement veriusertfs routines
- * via VPI. This is extremly ugly, so don't look after eating dinner.
+ * via VPI. This is extremely ugly, so don't look after eating dinner.
*/
# include <string.h>
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@@ -85,7 +85,7 @@ const char*target = "null";
/*
* These are the language support control flags. These support which
* language features (the generation) to support. The generation_flag
- * is a major moce, and the gn_* flags control specifc sub-features.
+ * is a major mode, and the gn_* flags control specific sub-features.
*/
generation_t generation_flag = GN_DEFAULT;
bool gn_cadence_types_flag = true;
@@ -728,7 +728,7 @@ int main(int argc, char*argv[])
des->set_flags(flags);
- /* Done iwth all the pform data. Delete the modules. */
+ /* Done with all the pform data. Delete the modules. */
for (map<perm_string,Module*>::iterator idx = pform_modules.begin()
; idx != pform_modules.end() ; idx ++) {
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@@ -180,7 +180,7 @@ NexusSet* NetAssignBase::nex_input(bool rem_out)
{
NexusSet*result = rval_->nex_input(rem_out);
- /* It is possible that the lval_ can hav nex_input values. In
+ /* It is possible that the lval_ can have nex_input values. In
particular, index expressions are statement inputs as well,
so should be addressed here. */
for (NetAssign_*cur = lval_ ; cur ; cur = cur->more) {
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