Permalink
Browse files

Revert bad merge from vhdl branch

  • Loading branch information...
1 parent 7f2cb6a commit ec49f10e2d00aa8acacf96667547ddac6916e49b @steveicarus steveicarus committed Oct 2, 2010
Showing with 1,253 additions and 1,139 deletions.
  1. +2 −2 Makefile.in
  2. +3 −3 discipline.h
  3. +1 −1 driver/Makefile.in
  4. +2 −2 driver/globals.h
  5. +1 −1 driver/iverilog.man.in
  6. +6 −6 driver/main.c
  7. +19 −49 elab_expr.cc
  8. +9 −20 elab_lval.cc
  9. +4 −4 elab_net.cc
  10. +1 −1 elaborate.cc
  11. +17 −11 eval_tree.cc
  12. +63 −63 examples/des.v
  13. +4 −4 examples/pal_reg.v
  14. +2 −2 examples/sqrt-virtex.v
  15. +2 −2 expr_synth.cc
  16. +2 −2 ivl_target.h
  17. +5 −5 ivlpp/lexor.lex
  18. +1 −1 lexor.lex
  19. +1 −1 main.cc
  20. +1 −1 mingw.txt
  21. +32 −17 net_design.cc
  22. +15 −1 net_expr.cc
  23. +1 −1 net_link.cc
  24. +2 −2 net_scope.cc
  25. +1 −1 netlist.cc
  26. +4 −1 netlist.h
  27. +159 −4 netmisc.cc
  28. +9 −17 netmisc.h
  29. +7 −9 nodangle.cc
  30. +1 −1 parse.y
  31. +1 −1 parse_misc.h
  32. +11 −11 pform.cc
  33. +1 −1 pform.h
  34. +1 −1 symbol_search.cc
  35. +2 −2 tgt-vhdl/Makefile.in
  36. +19 −40 tgt-vhdl/cast.cc
  37. +200 −0 tgt-vhdl/display.cc
  38. +26 −26 tgt-vhdl/expr.cc
  39. +15 −15 tgt-vhdl/logic.cc
  40. +28 −28 tgt-vhdl/lpm.cc
  41. +16 −13 tgt-vhdl/process.cc
  42. +119 −139 tgt-vhdl/scope.cc
  43. +17 −70 tgt-vhdl/state.cc
  44. +119 −270 tgt-vhdl/stmt.cc
  45. +3 −3 tgt-vhdl/support.cc
  46. +1 −1 tgt-vhdl/support.hh
  47. +3 −3 tgt-vhdl/vhdl.cc
  48. +6 −17 tgt-vhdl/vhdl_element.cc
  49. +1 −1 tgt-vhdl/vhdl_element.hh
  50. +2 −2 tgt-vhdl/vhdl_helper.hh
  51. +71 −120 tgt-vhdl/vhdl_syntax.cc
  52. +34 −64 tgt-vhdl/vhdl_syntax.hh
  53. +4 −3 tgt-vhdl/vhdl_target.h
  54. +1 −1 tgt-vhdl/vhdl_type.cc
  55. +2 −2 tgt-vhdl/vhdl_type.hh
  56. +3 −2 tgt-vvp/draw_mux.c
  57. +13 −7 tgt-vvp/draw_net_input.c
  58. +1 −1 tgt-vvp/draw_ufunc.c
  59. +2 −1 tgt-vvp/draw_vpi.c
  60. +11 −11 tgt-vvp/eval_expr.c
  61. +1 −1 tgt-vvp/eval_real.c
  62. +1 −1 tgt-vvp/modpath.c
  63. +48 −5 tgt-vvp/vvp_scope.c
  64. +57 −9 vpi/fstapi.c
  65. +2 −1 vpi/sys_display.c
  66. +3 −2 vpi/sys_fileio.c
  67. +2 −1 vpi/sys_sdf.c
  68. +6 −3 vvp/Makefile.in
  69. +1 −2 vvp/array.cc
  70. +1 −1 vvp/concat.cc
  71. +1 −1 vvp/dff.h
  72. +1 −1 vvp/event.cc
  73. +1 −1 vvp/examples/vector.vvp
  74. +1 −1 vvp/opcodes.txt
  75. +2 −2 vvp/schedule.h
  76. +1 −1 vvp/vpi_mcd.cc
  77. +1 −1 vvp/vpi_vthr_vector.cc
  78. +2 −2 vvp/vthread.cc
  79. +1 −1 vvp/vvp_island.cc
  80. +3 −3 vvp/vvp_net.cc
  81. +4 −5 vvp/vvp_net.h
  82. +2 −2 vvp/vvp_net_sig.h
  83. +1 −1 vvp/words.cc
View
@@ -30,7 +30,7 @@ SHELL = /bin/sh
# The "suffix" is used as an installation suffix. It modifies certain
# key install paths/files such that a build and install of Icarus Verilog
# with the same $(prefix) but a different $(suffix) will not interfere.
-# The normal configuratin leaves suffix empty
+# The normal configuration leaves suffix empty
suffix = @install_suffix@
prefix = @prefix@
@@ -240,7 +240,7 @@ iverilog-vpi.man: $(srcdir)/iverilog-vpi.man.in version.exe
tail -n +2 $(srcdir)/iverilog-vpi.man.in >> $@
iverilog-vpi.ps: iverilog-vpi.man
- $(MAN) -t iverilog-vpi.man > iverilog-vpi.ps
+ $(MAN) -t ./iverilog-vpi.man > iverilog-vpi.ps
iverilog-vpi.pdf: iverilog-vpi.ps
$(PS2PDF) iverilog-vpi.ps iverilog-vpi.pdf
View
@@ -1,7 +1,7 @@
#ifndef __discipline_H
#define __discipline_H
/*
- * Copyright (c) 2008 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2008-2010 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -55,8 +55,8 @@ class ivl_discipline_s : public LineInfo {
perm_string name() const { return name_; }
ivl_dis_domain_t domain() const { return domain_; }
- const ivl_nature_t potential() const { return potential_; }
- const ivl_nature_t flow() const { return flow_; }
+ ivl_nature_t potential() const { return potential_; }
+ ivl_nature_t flow() const { return flow_; }
private:
perm_string name_;
View
@@ -89,7 +89,7 @@ iverilog.man: $(srcdir)/iverilog.man.in ../version.exe
tail -n +2 $(srcdir)/iverilog.man.in >> $@
iverilog.ps: iverilog.man
- $(MAN) -t iverilog.man > iverilog.ps
+ $(MAN) -t ./iverilog.man > iverilog.ps
iverilog.pdf: iverilog.ps
$(PS2PDF) iverilog.ps iverilog.pdf
View
@@ -40,10 +40,10 @@ extern void process_include_dir(const char*name);
/* Add a new -D define. */
extern void process_define(const char*name);
-
+
/* Add a new parameter definition */
extern void process_parameter(const char*name);
-
+
/* Set the default timescale for the simulator. */
extern void process_timescale(const char*ts_string);
@@ -64,7 +64,7 @@ Verilog source for use by other compilers.
.B -g1995\fI|\fP-g2001\fI|\fP-g2001-noconfig\fI|\fP-g2005\fI|\fP-g2009
Select the Verilog language \fIgeneration\fP to support in the
compiler. This selects between \fIIEEE1364\-1995\fP,
-\fIIEEE1364\-2001\fP, \fIIEEE1364\-2005\fP, or \fIIEEE1800-2009\fP.
+\fIIEEE1364\-2001\fP, \fIIEEE1364\-2005\fP, or \fIIEEE1800-2009\fP.
Normally, Icarus Verilog defaults to the latest known generation of the
language. This flag is most useful to restrict the language to a set
supported by tools of specific generations, for compatibility with
View
@@ -169,8 +169,8 @@ typedef struct t_command_file {
p_command_file cmd_file_head = NULL; /* The FIFO head */
p_command_file cmd_file_tail = NULL; /* The FIFO tail */
-/* Temprarily store parameter definition from command line and
- * parse it after we have delt with command file
+/* Temporarily store parameter definition from command line and
+ * parse it after we have dealt with command file
*/
static const char** defparm_base = 0;
static int defparm_size = 0;
@@ -777,10 +777,10 @@ int main(int argc, char **argv)
turning the last two \ characters to null. Then we append
the lib\ivl$(suffix) to finish. */
{ char *s;
- char basepath[4096], tmp[4096];
- GetModuleFileName(NULL, tmp, sizeof tmp);
+ char basepath[4096], tmppath[4096];
+ GetModuleFileName(NULL, tmppath, sizeof tmppath);
/* Convert to a short name to remove any embedded spaces. */
- GetShortPathName(tmp, basepath, sizeof basepath);
+ GetShortPathName(tmppath, basepath, sizeof basepath);
strncpy(ivl_root, basepath, MAXSIZE);
ivl_root[MAXSIZE-1] = 0;
s = strrchr(ivl_root, sep);
@@ -1105,7 +1105,7 @@ int main(int argc, char **argv)
/* If we are planning on opening a dependencies file, then
open and truncate it here. The other phases of compilation
- will append to the file, so this is necessray to make sure
+ will append to the file, so this is necessary to make sure
it starts out empty. */
if (depfile) {
FILE*fd = fopen(depfile, "w");
View
@@ -729,7 +729,7 @@ NetExpr* PEBinary::elaborate_expr_base_rshift_(Design*des,
return tmp;
}
- // Falback, handle the general case.
+ // Fallback, handle the general case.
if (expr_wid > 0)
lp = pad_to_width(lp, expr_wid, *this);
tmp = new NetEBShift(op_, lp, rp);
@@ -1011,7 +1011,7 @@ unsigned PEBLeftWidth::test_width(Design*des, NetScope*scope,
&& wid_left > 0
&& wid_left < integer_width) {
wid_left = integer_width;
-
+
if (debug_elaborate)
cerr << get_fileline() << ": debug: "
<< "Test width of unsized " << human_readable_op(op_)
@@ -1273,7 +1273,7 @@ NetExpr*PECallFunction::cast_to_width_(NetExpr*expr, int wid, bool signed_flag)
if (wid < 0)
wid = expr->expr_width();
-
+
if (debug_elaborate)
cerr << get_fileline() << ": debug: cast to " << wid
<< " bits" << endl;
@@ -2494,11 +2494,7 @@ NetExpr* PEIdent::elaborate_expr_param_idx_up_(Design*des, NetScope*scope,
return result_ex;
}
- if (par_msv >= par_lsv) {
- if (par_lsv != 0) base = make_add_expr(base, -par_lsv);
- } else {
- base = make_sub_expr(par_lsv-wid+1, base);
- }
+ base = normalize_variable_base(base, par_msv, par_lsv, wid, true);
NetExpr*tmp = par->dup_expr();
tmp = new NetESelect(tmp, base, wid);
@@ -2578,13 +2574,7 @@ NetExpr* PEIdent::elaborate_expr_param_idx_do_(Design*des, NetScope*scope,
return result_ex;
}
- if (par_msv >= par_lsv) {
- if (long offset = par_lsv+wid-1) {
- base = make_add_expr(base, -offset);
- }
- } else {
- base = make_sub_expr(par_lsv, base);
- }
+ base = normalize_variable_base(base, par_msv, par_lsv, wid, false);
NetExpr*tmp = par->dup_expr();
tmp = new NetESelect(tmp, base, wid);
@@ -2610,7 +2600,7 @@ NetExpr* PEIdent::elaborate_expr_param_(Design*des,
if (!name_tail.index.empty())
use_sel = name_tail.index.back().sel;
- if (par->expr_type() == IVL_VT_REAL &&
+ if (par->expr_type() == IVL_VT_REAL &&
use_sel != index_component_t::SEL_NONE) {
perm_string name = peek_tail_name(path_);
cerr << get_fileline() << ": error: "
@@ -2742,17 +2732,10 @@ NetExpr* PEIdent::elaborate_expr_param_(Design*des,
} else {
if (par_me) {
- long par_mv = par_me->value().as_long();
- long par_lv = par_le->value().as_long();
- if (par_mv >= par_lv) {
- mtmp = par_lv
- ? make_add_expr(mtmp, 0-par_lv)
- : mtmp;
- } else {
- if (par_lv != 0)
- mtmp = make_add_expr(mtmp, 0-par_mv);
- mtmp = make_sub_expr(par_lv-par_mv, mtmp);
- }
+ mtmp = normalize_variable_base(mtmp,
+ par_me->value().as_long(),
+ par_le->value().as_long(),
+ 1, true);
}
/* The value is constant, but the bit select
@@ -2869,7 +2852,8 @@ NetExpr* PEIdent::elaborate_expr_net_word_(Design*des, NetScope*scope,
// expression to calculate the canonical address.
if (long base = net->array_first()) {
- word_index = make_add_expr(word_index, 0-base);
+ word_index = normalize_variable_array_base(
+ word_index, base, net->array_count());
eval_expr(word_index);
}
}
@@ -2945,7 +2929,7 @@ NetExpr* PEIdent::elaborate_expr_net_part_(Design*des, NetScope*scope,
cerr << get_fileline() << ": : "
"Replacing select with a constant 'bx." << endl;
}
-
+
NetEConst*tmp = new NetEConst(verinum(verinum::Vx, 1, false));
tmp->set_line(*this);
return tmp;
@@ -3053,7 +3037,7 @@ NetExpr* PEIdent::elaborate_expr_net_idx_up_(Design*des, NetScope*scope,
}
// Otherwise, make a part select that covers the right
// range.
- ex = new NetEConst(verinum(net->sig()->sb_to_idx(lsv) +
+ ex = new NetEConst(verinum(net->sig()->sb_to_idx(lsv) +
offset));
if (warn_ob_select) {
long rel_base = net->sig()->sb_to_idx(lsv) + offset;
@@ -3092,12 +3076,7 @@ NetExpr* PEIdent::elaborate_expr_net_idx_up_(Design*des, NetScope*scope,
return ss;
}
- if (net->msi() > net->lsi()) {
- if (long offset = net->lsi())
- base = make_add_expr(base, -offset);
- } else {
- base = make_sub_expr(net->lsi()-wid+1, base);
- }
+ base = normalize_variable_base(base, net->msi(), net->lsi(), wid, true);
NetESelect*ss = new NetESelect(net, base, wid);
ss->set_line(*this);
@@ -3184,12 +3163,7 @@ NetExpr* PEIdent::elaborate_expr_net_idx_do_(Design*des, NetScope*scope,
return ss;
}
- if (net->msi() > net->lsi()) {
- if (long offset = net->lsi()+wid-1)
- base = make_add_expr(base, -offset);
- } else {
- base = make_sub_expr(net->lsi(), base);
- }
+ base = normalize_variable_base(base, net->msi(), net->lsi(), wid, false);
NetESelect*ss = new NetESelect(net, base, wid);
ss->set_line(*this);
@@ -3294,12 +3268,8 @@ NetExpr* PEIdent::elaborate_expr_net_bit_(Design*des, NetScope*scope,
// complicated task because we need to generate
// expressions to convert calculated bit select
// values to canonical values that are used internally.
-
- if (net->sig()->msb() < net->sig()->lsb()) {
- ex = make_sub_expr(net->sig()->lsb(), ex);
- } else {
- ex = make_add_expr(ex, - net->sig()->lsb());
- }
+ ex = normalize_variable_base(ex, net->sig()->msb(), net->sig()->lsb(),
+ 1, true);
NetESelect*ss = new NetESelect(net, ex, 1);
ss->set_line(*this);
@@ -3537,7 +3507,7 @@ NetExpr*PETernary::elaborate_expr(Design*des, NetScope*scope,
// evaluation of ternary expressions, but it doesn't disallow
// it. The disadvantage of doing this is that semantic errors
// in the unused clause will be missed, but people don't seem
- // to mind, and do apreciate the optimization available here.
+ // to mind, and do appreciate the optimization available here.
if (NetEConst*tmp = dynamic_cast<NetEConst*> (con)) {
verinum cval = tmp->value();
ivl_assert(*this, cval.len()==1);
View
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2000-2009 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2000-2010 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -198,7 +198,7 @@ NetAssign_* PEIdent::elaborate_lval(Design*des,
if (reg->array_dimensions() > 0)
return elaborate_lval_net_word_(des, scope, reg);
- // This must be after the array word elaboration above!
+ // This must be after the array word elaboration above!
if (reg->get_scalar() &&
use_sel != index_component_t::SEL_NONE) {
cerr << get_fileline() << ": error: can not select part of ";
@@ -269,7 +269,8 @@ NetAssign_* PEIdent::elaborate_lval_net_word_(Design*des,
// expression to calculate the canonical address.
if (long base = reg->array_first()) {
- word = make_add_expr(word, 0-base);
+ word = normalize_variable_array_base(word, base,
+ reg->array_count());
eval_expr(word);
}
@@ -342,7 +343,6 @@ bool PEIdent::elaborate_lval_net_bit_(Design*des,
index_tail.msb->test_width(des, scope, integer_width, integer_width,
expr_type_tmp, unsized_flag_tmp);
-
// Bit selects have a single select expression. Evaluate the
// constant value and treat it as a part select with a bit
// width of 1.
@@ -357,10 +357,7 @@ bool PEIdent::elaborate_lval_net_bit_(Design*des,
if (mux) {
// Non-constant bit mux. Correct the mux for the range
// of the vector, then set the l-value part select expression.
- if (reg->msb() < reg->lsb())
- mux = make_sub_expr(reg->lsb(), mux);
- else if (reg->lsb() != 0)
- mux = make_add_expr(mux, - reg->lsb());
+ mux = normalize_variable_base(mux, reg->msb(), reg->lsb(), 1, true);
lv->set_part(mux, 1);
@@ -535,20 +532,12 @@ bool PEIdent::elaborate_lval_net_idx_(Design*des,
} else {
/* Correct the mux for the range of the vector. */
if (use_sel == index_component_t::SEL_IDX_UP) {
- if (reg->msb() > reg->lsb()) {
- if (long offset = reg->lsb())
- base = make_add_expr(base, -offset);
- } else {
- base = make_sub_expr(reg->lsb()-wid+1, base);
- }
+ base = normalize_variable_base(base, reg->msb(), reg->lsb(),
+ wid, true);
} else {
// This is assumed to be a SEL_IDX_DO.
- if (reg->msb() > reg->lsb()) {
- if (long offset = reg->lsb()+wid-1)
- base = make_add_expr(base, -offset);
- } else {
- base = make_sub_expr(reg->lsb(), base);
- }
+ base = normalize_variable_base(base, reg->msb(), reg->lsb(),
+ wid, false);
}
}
View
@@ -497,7 +497,7 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope,
/* The array has a part/bit select at the end. */
if (name_tail.index.size() > sig->array_dimensions()) {
if (sig->get_scalar()) {
- cerr << get_fileline() << ": error: "
+ cerr << get_fileline() << ": error: "
<< "can not select part of ";
if (sig->data_type() == IVL_VT_REAL) cerr << "real";
else cerr << "scalar";
@@ -512,7 +512,7 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope,
return 0;
if (lidx_tmp < 0) {
- cerr << get_fileline() << ": sorry: part selects "
+ cerr << get_fileline() << ": sorry: part selects "
"straddling the start of signal (" << path_
<< ") are not currently supported." << endl;
des->errors += 1;
@@ -523,7 +523,7 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope,
}
} else if (!name_tail.index.empty()) {
if (sig->get_scalar()) {
- cerr << get_fileline() << ": error: "
+ cerr << get_fileline() << ": error: "
<< "can not select part of ";
if (sig->data_type() == IVL_VT_REAL) cerr << "real: ";
else cerr << "scalar: ";
@@ -537,7 +537,7 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope,
return 0;
if (lidx_tmp < 0) {
- cerr << get_fileline() << ": sorry: part selects "
+ cerr << get_fileline() << ": sorry: part selects "
"straddling the start of signal (" << path_
<< ") are not currently supported." << endl;
des->errors += 1;
View
@@ -1422,7 +1422,7 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
des->errors += 1;
continue;
}
-
+
// We do not support real inout ports at all.
if (!prts.empty() && (prts[0]->data_type() == IVL_VT_REAL )) {
cerr << pins[idx]->get_fileline() << ": error: "
Oops, something went wrong.

0 comments on commit ec49f10

Please sign in to comment.