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Commits on Apr 7, 2011
  1. @steveicarus

    tgt-vhdl: Fix expression generation corner case and bug in xnor reduc…

    authored steveicarus committed
    …tion operator
    
    Certain types of expressions involving only constants would produce
    ambiguous VHDL output. Fixed by qualifying one of the arguments. E.g.
    
       ('0' or '1') = '1'
    
    Which is ambiguous becomes
    
       (std_logic'('0') or '1') = '1'
    
    This fixes the xnor_test test.
    
    Reduce XNOR was implemented incorrectly because of trivial typo
  2. @steveicarus

    tgt-vhdl: Improve temporary signal name generation to avoid collisions

    authored steveicarus committed
    Fixes regression of simple_gen test.
    
    Also extended ivl_lpm_size API call to support all LPM types. This
    simplifies some of the VHDL LPM generation code a little.
Commits on Mar 29, 2011
  1. @ldoolitt @steveicarus

    Spelling fixes

    ldoolitt authored steveicarus committed
    All are in comments and .txt files except for one in the Architecture::Statement dump message.
Commits on Mar 14, 2011
  1. @ldoolitt @steveicarus

    Spelling fixes

    ldoolitt authored steveicarus committed
    Mostly then/than confusion.  All comments or README files,
    except for one user-visible change in a tgt-vlog95 error message.
  2. @caryr @steveicarus

    Fix remaining space issues.

    caryr authored steveicarus committed
Commits on Mar 9, 2011
  1. @steveicarus

    tgt-vhdl: Fix shift2 test regression

    authored steveicarus committed
    Caused by translate_select emitting a logical instead of arithmetic
    shift for signed arguments.
Commits on Mar 3, 2011
  1. @caryr @steveicarus

    Fix spacing problems.

    caryr authored steveicarus committed
    This patch fixes spacing problems in the source code, space/tab at
    the end of line and space before tab.
Commits on Oct 22, 2010
  1. @steveicarus

    Fix for pr2661101

    authored steveicarus committed
    Fixes VHDL compilation errors when signal or instance names collide
    after renaming.
Commits on Oct 15, 2010
  1. @caryr @steveicarus

    Add cppcheck target to the Makefile

    caryr authored steveicarus committed
    This patch adds support for running cppcheck from the Makefile. It also
    standardizes the order of some of the targets. It renames vpip_format.c
    to vpip_format.cc and fixes the size of the array tables to make room
    for the trailing NULL. Found when using a C++ compiler.
Commits on Oct 5, 2010
  1. Basic parameter support in VHDL target

    authored
    This is a fix for pr2555831. A separate entity/architecture pair is
    generated for each module that is instantiated with a unique
    parameter combination.
  2. List parameters/values in VHDL entity comment

    authored
    For example:
    
      -- Generated from Verilog module child (vhdl_tests/generics.v:30)
      --   MY_VALUE = 3
      entity child is
    
    To make it clear which values were used for this entity.
    
    Conflicts:
    
    	tgt-vhdl/scope.cc
  3. Change VHDL $finish to use report not assert

    authored
    Changes:
    
       assert false report "SIMULATION FINISHED" severity failure;
    
    To just:
    
       report "SIMULATION FINISHED" severity failure;
  4. Generate VHDL report statements for $display

    authored
    This changes the implementation of $display/$write to use VHDL
    report statements rather the the std.textio functions. The code
    produced is simpler and more like what a real VHDL designed would
    write. However it no longer exactly matches the Verilog output as
    most VHDL simulators prepend the text with simulation time, entity
    name, severity level, etc. There is a corresponding change in
    ivtest to support this.
    
    Conflicts:
    
    	tgt-vhdl/cast.cc
    	tgt-vhdl/display.cc
    	tgt-vhdl/vhdl_syntax.cc
    	tgt-vhdl/vhdl_target.h
  5. Add VHDL report statement

    authored
    Not output yet, but will be used to replace std.textio
    implementation of $display.
    
    Conflicts:
    
    	tgt-vhdl/vhdl_syntax.cc
  6. Reduce number of 0 ns waits in generated VHDL

    authored
    Previous we generated a "wait for 0 ns" statement after
    every blocking assignment that wasn't the last statement
    in the process. While this implements the Verilog semantics,
    it generates excessive waits, and cannot usually be synthesised.
    This patch only generates "wait for 0 ns" statements when it
    cannot be avoid (e.g. when the target of a blocking assignment
    is read in the same process).
    
    An example:
    
      begin
        x = 5;
        if (x == 2)
          y = 7;
      end
    
    Becomes:
    
      x <= 5;
      wait for 0 ns;    -- Required to implement assignment semantics
      if x = 2 then
        y <= 7;         -- No need for wait here, not read
        -- wait for 0 ns  (previously)
      end if;
    
    Conflicts:
    
    	tgt-vhdl/process.cc
    	tgt-vhdl/stmt.cc
    	tgt-vhdl/vhdl_target.h
Commits on Oct 2, 2010
  1. @steveicarus
Commits on Sep 30, 2010
  1. Add uwire support to VHDL backend

    authored
    Implemented as std_ulogic which behaves almost identically.
Commits on Sep 11, 2010
  1. Basic parameter support in VHDL target

    authored
    This is a fix for pr2555831. A separate entity/architecture pair is
    generated for each module that is instantiated with a unique
    parameter combination.
Commits on Sep 8, 2010
Commits on Aug 28, 2010
  1. List parameters/values in VHDL entity comment

    authored
    For example:
    
      -- Generated from Verilog module child (vhdl_tests/generics.v:30)
      --   MY_VALUE = 3
      entity child is
    
    To make it clear which values were used for this entity.
Commits on Aug 24, 2010
  1. Change VHDL $finish to use report not assert

    authored
    Changes:
    
       assert false report "SIMULATION FINISHED" severity failure;
    
    To just:
    
       report "SIMULATION FINISHED" severity failure;
  2. Generate VHDL report statements for $display

    authored
    This changes the implementation of $display/$write to use VHDL
    report statements rather the the std.textio functions. The code
    produced is simpler and more like what a real VHDL designed would
    write. However it no longer exactly matches the Verilog output as
    most VHDL simulators prepend the text with simulation time, entity
    name, severity level, etc. There is a corresponding change in
    ivtest to support this.
Commits on Aug 18, 2010
  1. Add VHDL report statement

    authored
    Not output yet, but will be used to replace std.textio
    implementation of $display.
Commits on Aug 17, 2010
  1. Reduce number of 0 ns waits in generated VHDL

    authored
    Previous we generated a "wait for 0 ns" statement after
    every blocking assignment that wasn't the last statement
    in the process. While this implements the Verilog semantics,
    it generates excessive waits, and cannot usually be synthesised.
    This patch only generates "wait for 0 ns" statements when it
    cannot be avoid (e.g. when the target of a blocking assignment
    is read in the same process).
    
    An example:
    
      begin
        x = 5;
        if (x == 2)
          y = 7;
      end
    
    Becomes:
    
      x <= 5;
      wait for 0 ns;    -- Required to implement assignment semantics
      if x = 2 then
        y <= 7;         -- No need for wait here, not read
        -- wait for 0 ns  (previously)
      end if;
  2. Add find_vars method to VHDL syntax objects

    authored
    Finds set of read and written variables. For use in
    post-processing the syntax tree for cleanup.
  3. Reduce superflous parens in generated VHDL

    authored
    Purely cosmetic, replaces output like:
    
      if (x + foo(x + (2 * y))) then ...
    
    With:
    
      if x + foo(x + (2 * y)) then ...
Commits on Aug 12, 2010
  1. @steveicarus

    Resize VHDL vector before cast in signed comparison

    authored steveicarus committed
    E.g. $signed(x) > y with x, y different sizes should be
    
      resize(signed(x), N) > y
    
    Not
    
      signed(resize(x, N)) > y
    
    As this does not treat the sign bit correctly. Was causing
    the signed5 test to fail.
  2. @steveicarus

    Rename modules which are VHDL reserved words

    authored steveicarus committed
Commits on Aug 8, 2010
  1. @steveicarus

    Avoid emitting VHDL Bool_To_Logic calls for common cases

    authored steveicarus committed
    No functional change, just improves the output a bit. E.g.
    
      x <= Bool_To_Logic(y = z);
    
    Becomes:
    
      x <= '1' when y = z else '0';
  2. @steveicarus

    Avoid VHDL type error in concurrent assignment

    authored steveicarus committed
    When translating a relational LPM to concurrent VHDL assignment, the
    generated code would be incorrect if the input types differed in
    signedness.
  3. @steveicarus

    Rename VHDL instances which are reserved words

    authored steveicarus committed
    Fixes compiler errors with some real-world examples
Commits on Jul 31, 2010
  1. @caryr @steveicarus

    Remove some cppcheck warnings.

    caryr authored steveicarus committed
    This patch modifies the code to remove some more cppcheck warnings.
Commits on Jun 1, 2010
  1. @caryr @steveicarus

    Remove malloc.h support and for C++ files use <c...> include files.

    caryr authored steveicarus committed
    The functions (malloc, free, etc.) that used to be provided in
    malloc.h are now provided in cstdlib for C++ files and stdlib.h for
    C files. Since we require a C99 compliant compiler it makes sense
    that malloc.h is no longer needed.
    
    This patch also modifies all the C++ files to use the <c...>
    version of the standard C header files (e.g. <cstdlib> vs
    <stdlib.h>). Some of the files used the C++ version and others did
    not. There are still a few other header changes that could be done,
    but this takes care of much of it.
Commits on May 14, 2010
  1. @caryr @steveicarus

    C++ functions passed to C should be declared extern "C" (second patch)

    caryr authored steveicarus committed
    The SunPro compiler was complaining about C++ routines that
    were being passed to the ivl C routines if the C++ routines
    were not declared extern "C".
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