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Commits on Apr 7, 2011
  1. @steveicarus

    tgt-vhdl: Fix expression generation corner case and bug in xnor reduc…

    committed with steveicarus
    …tion operator
    Certain types of expressions involving only constants would produce
    ambiguous VHDL output. Fixed by qualifying one of the arguments. E.g.
       ('0' or '1') = '1'
    Which is ambiguous becomes
       (std_logic'('0') or '1') = '1'
    This fixes the xnor_test test.
    Reduce XNOR was implemented incorrectly because of trivial typo
  2. @steveicarus

    tgt-vhdl: Improve temporary signal name generation to avoid collisions

    committed with steveicarus
    Fixes regression of simple_gen test.
    Also extended ivl_lpm_size API call to support all LPM types. This
    simplifies some of the VHDL LPM generation code a little.
  3. @ldoolitt @steveicarus

    Add HAVE_LROUND to

    ldoolitt committed with steveicarus
    Needed by
  4. @caryr @steveicarus

    Add vpiBitVar to the memory cleanup code.

    caryr committed with steveicarus
    Support for vpiBitVar also needed to be added to the memory (valgrind)
    cleanup code.
  5. @martinwhitaker @steveicarus

    Fix for compiler crash when function arguments are unknown.

    martinwhitaker committed with steveicarus
    When a user or system function is called on the RHS of a continuous
    assignment, and one of the function arguments is an undeclared
    identifier, the compiler reports the error correctly but then
    crashes. This patch fixes the crash.
  6. @martinwhitaker @steveicarus

    Rework of constant expression error reporting.

    martinwhitaker committed with steveicarus
    This patch changes the method used to signal that a constant expression
    is being elaborated from flags stored in global variables to flags
    passed down the call chain. It also generates more informative error
    messages when variable references are found in a constant expression.
  7. @pszostek @steveicarus

    Change indentation mechanism in debug dump for VHDL

    pszostek committed with steveicarus
    There has been added additional default attribute to
    all 'dump' function calls which is in all cases equal
    to 0. Now one can specify how much this debug dumping should
    be intended. This should allow people to dump smoothly whole
    designs (as it was now) as far as separate units.
    This is now the parent who specifies the base indentation
    for all components (children). For example, architecture
    "decides" how much their signals should be indented.
Commits on Apr 4, 2011
  1. @steveicarus
  2. @steveicarus
  3. @steveicarus

    Support collapse of PartSelect::PV to concatenation

    steveicarus committed
    During elaboration, it is sometimes efficient to collapse a
    collections of PV drivers to a net to a single concatenation.
    This removes a bunch of resolutions and other nodes, and also
    is the only way that 2-value logic should work.
Commits on Apr 2, 2011
  1. @steveicarus
  2. @pszostek @steveicarus
  3. @pszostek @steveicarus

    Add component specification parsing

    pszostek committed with steveicarus
    A class for component specification has been added
  4. @pszostek @steveicarus

    Add basic instantiation list handling in VHDL

    pszostek committed with steveicarus
    A class for representing instantiation list has
    been added.
  5. @pszostek @steveicarus
  6. @pszostek @steveicarus

    Add entity aspects to VHDL parsing

    pszostek committed with steveicarus
    Entity aspects are now recognized and parsed
    into corresponding objects. A new class (entity_aspect)
    has been added.
Commits on Apr 1, 2011
  1. @steveicarus

    Basic elaboration of vhdl component instantiations.

    steveicarus committed
    This gets us as far as emiting a component instantiation. Very little
    error checking/elaboration is done, so there is room for improvement,
    but this is a working stub.
  2. @pszostek @steveicarus

    Add use clause parsing

    pszostek committed with steveicarus
    Up till now only "global" use clauses were parsed
    and as a result libraries were loaded.
    Since use clauses can appear not only in global context,
    parsing of non-global clauses has been introduced and
    selected names are now handled (like name1.name2.name3).
Commits on Mar 29, 2011
  1. @ldoolitt @steveicarus

    Spelling fixes

    ldoolitt committed with steveicarus
    All are in comments and .txt files except for one in the Architecture::Statement dump message.
Commits on Mar 28, 2011
  1. @steveicarus

    Add more complete support for vhdl local signals.

    steveicarus committed
    These signals are declared in the architecture and are local to
    the module. The Architecture already parsed and stored these signal
    declarations, but this patch adds the ability to actually emit these
    signals in the generated code.
    In the process of doing this, I had to regularize the elaboration
    and emit of VTypes, so that it can be used in multiple places, not
    just in entity headers (for ports).
    I also added support for bit selects of signals. This effected a couple
    places in the parser, and expressions in general.
  2. @pszostek @steveicarus

    Basic VHDL configuration parsing

    pszostek committed with steveicarus
    The bison grammar has been extended in order
    to parse configuration statements. Parsing
    remains very primitive but principal constructs
    can be now recognized.
  3. @martinwhitaker @steveicarus

    Fix for over-enthusiastic pruning of expressions.

    martinwhitaker committed with steveicarus
    The minimum width for expressions containing a literal number was
    being incorrectly calculated, leading to loss of information in
    some circumstances.
  4. @jaredcasper @steveicarus

    SystemVerilog 'N bit vectors.

    jaredcasper committed with steveicarus
    Adds a is_single_ flag to the verinum class to indicate it came from a
    'N bit vector and needs to be handled accordingly.
  5. @jaredcasper @steveicarus

    Allow SystemVerilog [size] dimension for unpacked arrays.

    jaredcasper committed with steveicarus
    IEEE 1800-2005/9 says "each fixed-size dimension shall be represented by
    an address range, such as [1:1024], or a single positive number to
    specify the size of a fixed-size unpacked array, as in C. In other
    words, [size] becomes the same as [0:size-1]."
    This patch implements that translation in the parser.  It issues a
    warning when doing so when the generation flag is less than 2005-sv.
Commits on Mar 23, 2011
  1. @pszostek @steveicarus
  2. @caryr @steveicarus

    vlog95: Print double values correctly and clean up string emitting.

    caryr committed with steveicarus
    This patch adds code to make sure a double (Verilog real) constant
    is printed correctly. It also adds code to trim any leading escaped
    NULLs from an expression string.
  3. @caryr @steveicarus

    Update the FST dumper to include the vpiDefName if it's unique.

    caryr committed with steveicarus
    This patch adds the vpiDefName for a module if it is different than
    the vpiName. This will be used in a future version of GTKWave.
  4. @pszostek @steveicarus

    Soft treating of multiple architectures in VHDL

    pszostek committed with steveicarus
    In VHDL it is allowed to have multiple architectures
    per one entity. The proper architecture should be then
    chosen in a configuration block. Now, if many architectures
    will be found, then there will be a warning message printed.
    FIXME notes are added in order not to forget about changes to
    be done
  5. @caryr @steveicarus

    vlog95: Add code to emit logicals that are the base of a CA as a CA.

    caryr committed with steveicarus
    This patch uses the new function (ivl_logic_is_cassign) to determine
    if a logical was really the base of a continuous assignment. This
    allows creating code that more closely matches the original.
  6. @caryr @steveicarus

    Add a routine to say if a logical came from a CA and some other fixes.

    caryr committed with steveicarus
    This patch adds code that allows the targets to determine if a logical
    gate came from a continuous assignment. This helps some of the targets
    generate code that more closely matches the input.
    It also reworks/simplifies the synthesis of && and || since the
    compiler has already converted the two operands to single bit form
    and fixes a mismatched delete from a previous patch.
  7. @caryr @steveicarus

    vlog95: Add support for most unconnected ports and more signed support.

    caryr committed with steveicarus
    This patch adds support for correctly handling most unconnected ports.
    Most important is top level ports that are the root of the conversion.
    This patch also adds support for emitting more signed constructs when
    they are requested. $signed() and $unsigned() are still not supported
    or recognized as an error when not emitting signed constructs.
  8. @caryr @steveicarus

    Change elaboration to better support top level and unconnected ports.

    caryr committed with steveicarus
    This patch changes the module elaboration slightly to allow passing
    the appropriate information for unconnected and top level ports. This
    allows the vlog95 generator to get the basic structure correct.
  9. @jaredcasper @steveicarus

    Wildcard named port connections.

    jaredcasper committed with steveicarus
    Implements Section of IEEE 1800-2009.
  10. @caryr @steveicarus

    Make the >>> error message depend on the allow signed flag.

    caryr committed with steveicarus
    The >>> operator is also part of the allow signed extensions.
Commits on Mar 22, 2011
  1. @steveicarus

    Parse component declarations / parse signal declarations.

    steveicarus committed
    These go into the architecture/block of their scope and will be
    used by component instantiations to make sure the bindings are
    correct and complete.
    Also handle signal declarations. The elaborator will use these
    to generate module local variables that are used by the architecture.
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