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Prototype generation for signal array arguments

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1 parent 2d11ad4 commit bb9cfa5dd9305aefb9df62a71e6e66127d033494 @nickg committed Dec 28, 2012
Showing with 24 additions and 14 deletions.
  1. +20 −10 src/cgen.c
  2. +1 −1 src/type.c
  3. +3 −3 test/regress/proc4.vhd
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@@ -710,18 +710,23 @@ static void cgen_prototype(tree_t t, LLVMTypeRef *args, bool procedure)
const int nports = tree_ports(t);
for (int i = 0; i < nports; i++) {
tree_t p = tree_port(t, i);
+ type_t type = tree_type(p);
+
+ port_mode_t mode = tree_port_mode(p);
+ const bool array = type_is_array(type);
+
switch (tree_class(p)) {
case C_SIGNAL:
- args[i] = LLVMPointerType(cgen_signal_type(tree_type(t)), 0);
+ {
+ LLVMTypeRef base_type = cgen_signal_type(type);
+ args[i] = array ? base_type : LLVMPointerType(base_type, 0);
+ }
break;
case C_VARIABLE:
case C_DEFAULT:
case C_CONSTANT:
{
- type_t type = tree_type(p);
- port_mode_t mode = tree_port_mode(p);
- bool array = type_is_array(type);
bool need_ptr = ((mode == PORT_OUT || mode == PORT_INOUT)
&& !array);
if (need_ptr)
@@ -2934,14 +2939,19 @@ static void cgen_array_signal_load_fn(type_t elem_type)
static LLVMTypeRef cgen_signal_type(type_t type)
{
if (type_is_array(type)) {
- range_t r = type_dim(type, 0);
- int64_t low, high;
- range_bounds(r, &low, &high);
+ LLVMTypeRef base_type = cgen_signal_type(type_elem(type));
- const unsigned n_elems = high - low + 1;
+ if (type_kind(type) == T_UARRAY)
+ return llvm_uarray_type(base_type);
+ else {
+ range_t r = type_dim(type, 0);
+ int64_t low, high;
+ range_bounds(r, &low, &high);
- LLVMTypeRef base_type = cgen_signal_type(type_elem(type));
- return LLVMArrayType(base_type, n_elems);
+ const unsigned n_elems = high - low + 1;
+
+ return LLVMArrayType(base_type, n_elems);
+ }
}
else {
LLVMTypeRef ty = LLVMGetTypeByName(module, "signal_s");
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@@ -196,7 +196,7 @@ static item_t *lookup_item(type_t t, imask_t mask)
;
assert(item < ARRAY_LEN(item_text_map));
- fatal("tree kind %s does not have item %s",
+ fatal("type kind %s does not have item %s",
kind_text_map[t->kind], item_text_map[item]);
}
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@@ -27,12 +27,12 @@ architecture rtl of proc4 is
x <= x + 1;
end procedure;
- --procedure test5(signal x : inout bit_vector) is
- --begin
+ procedure test5(signal x : inout bit_vector) is
+ begin
--for i in x'range loop
--x(i) <= not x(i);
--end loop;
- --end procedure;
+ end procedure;
signal s : integer;
signal k : bit_vector(1 downto 0);

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