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Panda: Sync ES2.1 changes

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1 parent e4b7fb6 commit 85fefd1b2c6b080b0ac8b3b77edfaa9e7997f6db @sakoman sakoman committed
Showing with 71 additions and 17 deletions.
  1. +33 −6 board/omap4430panda/clock.c
  2. +32 −10 board/omap4430panda/omap4430panda.c
  3. +5 −1 cpu/omap4/cpu.c
  4. +1 −0 include/asm/arch-omap4/cpu.h
View
39 board/omap4430panda/clock.c
@@ -116,6 +116,24 @@ struct dpll_param core_dpll_param[7] = {
{0x7d, 0x05, 0x02, 0x05, 0x08, 0x04, 0x06, 0x05},
};
+/* CORE parameters - ES2.1 */
+struct dpll_param core_dpll_param_ddr400[7] = {
+ /* 12M values */
+ {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
+ /* 13M values */
+ {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
+ /* 16.8M values */
+ {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
+ /* 19.2M values */
+ {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
+ /* 26M values */
+ {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
+ /* 27M values */
+ {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
+ /* 38.4M values - DDR@400MHz*/
+ {0x7d, 0x05, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05},
+};
+
/* CORE parameters for L3 at 190 MHz - For ES1 only*/
struct dpll_param core_dpll_param_l3_190[7] = {
/* 12M values */
@@ -142,7 +160,6 @@ struct dpll_param core_dpll_param_l3_190[7] = {
#endif
};
-
/* PER parameters */
struct dpll_param per_dpll_param[7] = {
/* 12M values */
@@ -162,7 +179,7 @@ struct dpll_param per_dpll_param[7] = {
/* SDC settings */
{0x0a, 0x00, 0x04, 0x03, 0x06, 0x05, 0x02, 0x03},
#endif
- {0x14, 0x00, 0x08, 0x04, 0x0c, 0x02, 0x04, 0x05},
+ {0x14, 0x00, 0x08, 0x06, 0x0c, 0x09, 0x04, 0x05},
};
/* ABE parameters */
@@ -404,9 +421,11 @@ static void configure_core_dpll(clk_index)
/* Program Core DPLL */
if(omap_revision() == OMAP4430_ES1_0)
dpll_param_p = &core_dpll_param_l3_190[clk_index];
- else
+ else if(omap_revision() == OMAP4430_ES2_0)
dpll_param_p = &core_dpll_param[clk_index];
-
+ else if(omap_revision() == OMAP4430_ES2_1)
+ dpll_param_p = &core_dpll_param_ddr400[clk_index];
+
/* Disable autoidle */
sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0);
@@ -461,8 +480,10 @@ void configure_core_dpll_no_lock(void)
/* Program Core DPLL */
if(omap_revision() == OMAP4430_ES1_0)
dpll_param_p = &core_dpll_param_l3_190[clk_index];
- else
+ else if(omap_revision() == OMAP4430_ES2_0)
dpll_param_p = &core_dpll_param[clk_index];
+ else if(omap_revision() == OMAP4430_ES2_1)
+ dpll_param_p = &core_dpll_param_ddr400[clk_index];
/* Disable autoidle */
sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0);
@@ -505,7 +526,13 @@ void lock_core_dpll_shadow(void)
/* Lock the core dpll using freq update method */
*(volatile int*)0x4A004120 = 10; //(CM_CLKMODE_DPLL_CORE)
- dpll_param_p = &core_dpll_param[6];
+ if(omap_revision() == OMAP4430_ES1_0)
+ dpll_param_p = &core_dpll_param_l3_190[6];
+ else if(omap_revision() == OMAP4430_ES2_0)
+ dpll_param_p = &core_dpll_param[6];
+ else if(omap_revision() == OMAP4430_ES2_1)
+ dpll_param_p = &core_dpll_param_ddr400[6];
+
/* CM_SHADOW_FREQ_CONFIG1: DLL_OVERRIDE = 1(hack), DLL_RESET = 1,
* DPLL_CORE_M2_DIV =1, DPLL_CORE_DPLL_EN = 0x7, FREQ_UPDATE = 1
*/
View
42 board/omap4430panda/omap4430panda.c
@@ -206,6 +206,20 @@ const struct ddr_regs ddr_regs_200_mhz_2cs = {
.mr2 = 0x1
};
+const struct ddr_regs ddr_regs_400_mhz_2cs = {
+ /* tRRD changed from 10ns to 12.5ns because of the tFAW requirement*/
+ .tim1 = 0x10eb0662,
+ .tim2 = 0x20370dd2,
+ .tim3 = 0x00b1c33f,
+ .phy_ctrl_1 = 0x849FF408,
+ .ref_ctrl = 0x00000618,
+ .config_init = 0x80000eb9,
+ .config_final = 0x80001ab9,
+ .zq_config = 0xD00b3215,
+ .mr1 = 0x83,
+ .mr2 = 0x4
+};
+
/*******************************************************
* Routine: delay
* Description: spinning delay to use before udelay works
@@ -238,6 +252,8 @@ static int emif_config(unsigned int base)
ddr_regs = &ddr_regs_380_mhz;
else if (rev == OMAP4430_ES2_0)
ddr_regs = &ddr_regs_200_mhz_2cs;
+ else if (rev == OMAP4430_ES2_1)
+ ddr_regs = &ddr_regs_400_mhz_2cs;
/*
* set SDRAM CONFIG register
* EMIF_SDRAM_CONFIG[31:29] REG_SDRAM_TYPE = 4 for LPDDR2-S4
@@ -366,6 +382,8 @@ static void ddr_init(void)
__raw_writel(0x1c1c1c1c, 0x4A100648);
__raw_writel(0x1c1c1c1c, 0x4A10064c);
__raw_writel(0x1c1c1c1c, 0x4A100650);
+ /* LPDDR2IO set to NMOS PTV */
+ __raw_writel(0x00ffc000, 0x4A100704);
} else if (rev == OMAP4430_ES2_0) {
__raw_writel(0x9e9e9e9e, 0x4A100638);
__raw_writel(0x9e9e9e9e, 0x4A10063c);
@@ -373,10 +391,9 @@ static void ddr_init(void)
__raw_writel(0x9e9e9e9e, 0x4A100648);
__raw_writel(0x9e9e9e9e, 0x4A10064c);
__raw_writel(0x9e9e9e9e, 0x4A100650);
+ /* LPDDR2IO set to NMOS PTV */
+ __raw_writel(0x00ffc000, 0x4A100704);
}
- /* LPDDR2IO set to NMOS PTV */
- __raw_writel(0x00ffc000, 0x4A100704);
-
/*
* DMM Configuration
@@ -385,7 +402,7 @@ static void ddr_init(void)
/* Both EMIFs 128 byte interleaved*/
if (rev == OMAP4430_ES1_0)
*(volatile int*)(DMM_BASE + DMM_LISA_MAP_0) = 0x80540300;
- else if (rev == OMAP4430_ES2_0)
+ else
*(volatile int*)(DMM_BASE + DMM_LISA_MAP_0) = 0x80640300;
/* EMIF2 only at 0x90000000 */
@@ -451,8 +468,10 @@ static void ddr_init(void)
* be kept higher than default 0x7. As per recommondation 0x0A will
* be used for better performance with REG_LL_THRESH_MAX = 0x00
*/
- *(volatile int*)(EMIF1_BASE + EMIF_L3_CONFIG) = 0x0A0000FF;
- *(volatile int*)(EMIF2_BASE + EMIF_L3_CONFIG) = 0x0A0000FF;
+ if (rev == OMAP4430_ES1_0) {
+ *(volatile int*)(EMIF1_BASE + EMIF_L3_CONFIG) = 0x0A0000FF;
+ *(volatile int*)(EMIF2_BASE + EMIF_L3_CONFIG) = 0x0A0000FF;
+ }
/*
* DMM : DMM_LISA_MAP_0(Section_0)
@@ -553,10 +572,11 @@ static scale_vcores(void)
/* set VCORE1 force VSEL */
/* PRM_VC_VAL_BYPASS) */
- if(rev == OMAP4430_ES1_0)
+ if(rev == OMAP4430_ES1_0)
*(volatile int*)(0x4A307BA0) = 0x3B5512;
else
*(volatile int*)(0x4A307BA0) = 0x3A5512;
+
*(volatile int*)(0x4A307BA0) |= 0x1000000;
while((*(volatile int*)(0x4A307BA0)) & 0x1000000);
@@ -578,10 +598,12 @@ static scale_vcores(void)
/*/set VCORE3 force VSEL */
/* PRM_VC_VAL_BYPASS */
- if(rev == OMAP4430_ES1_0)
+ if(rev == OMAP4430_ES1_0)
*(volatile int*)(0x4A307BA0) = 0x316112;
- else
+ else if (rev == OMAP4430_ES2_0)
*(volatile int*)(0x4A307BA0) = 0x296112;
+ else if (rev == OMAP4430_ES2_1)
+ *(volatile int*)(0x4A307BA0) = 0x2A6112;
*(volatile int*)(0x4A307BA0) |= 0x1000000;
while((*(volatile int*)(0x4A307BA0)) & 0x1000000);
@@ -618,7 +640,7 @@ void s_init(void)
#endif
prcm_init();
- if(rev == OMAP4430_ES2_0) {
+ if(rev != OMAP4430_ES1_0) {
if (__raw_readl(0x4805D138) & (1<<22)) {
sr32(0x4A30a31C, 8, 1, 0x1); /* enable software ioreq */
sr32(0x4A30a31C, 1, 2, 0x0); /* set for sys_clk (38.4MHz) */
View
6 cpu/omap4/cpu.c
@@ -31,6 +31,7 @@
*/
#include <common.h>
+#include <asm/io.h>
/* See also ARM Ref. Man. */
#define C1_MMU (1<<0) /* mmu off/on */
@@ -68,7 +69,10 @@ unsigned int omap_revision(void)
case 0x410FC091:
return OMAP4430_ES1_0;
case 0x411FC092:
- return OMAP4430_ES2_0;
+ if (__raw_readl(0x4a002204) == 0x3b95c02f)
+ return OMAP4430_ES2_1;
+ else
+ return OMAP4430_ES2_0;
default:
return OMAP4430_SILICON_ID_INVALID;
}
View
1 include/asm/arch-omap4/cpu.h
@@ -451,6 +451,7 @@
#define OMAP4430_SILICON_ID_INVALID 0
#define OMAP4430_ES1_0 1
#define OMAP4430_ES2_0 2
+#define OMAP4430_ES2_1 3
#ifndef __ASSEMBLY__
/*Functions for silicon revision */

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