WARNING - Create a new implementation in an existing sub-directory 'actual_top_impl'.
synpwrap -msg -prj "actual_top_impl_synplify.tcl" -log "actual_top_impl.srf"
Copyright (C) 1992-2019 Lattice Semiconductor Corporation. All rights reserved.
Lattice Diamond Version 3.11.0.396.4
==contents of actual_top_impl.srf
#Build: Synplify Pro (R) N-2018.03L-SP1-1, Build 443R, Apr 1 2019
#install: C:\lscc\diamond\3.11_x64\synpbase
#OS: Windows 8 6.2
#Hostname: DESKTOP-H0PMN4M
# Sun Apr 4 05:17:05 2021
#Implementation: actual_top_impl
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: DESKTOP-H0PMN4M
Implementation : actual_top_impl
Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: DESKTOP-H0PMN4M
Implementation : actual_top_impl
Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\msys64\home\William\Projects\FPGA\nmigen\efbutils\diamond-test\build\add.v" (library work)
@I::"C:\msys64\home\William\Projects\FPGA\nmigen\efbutils\diamond-test\build\sub.v" (library work)
@I::"C:\msys64\home\William\Projects\FPGA\nmigen\efbutils\diamond-test\build\top.v" (library work)
@I::"C:\msys64\home\William\Projects\FPGA\nmigen\efbutils\diamond-test\build\actual_top.v" (library work)
Verilog syntax check successful!
Compiler output is up to date. No re-compile necessary
Selecting top level module actual_top
@N: CG364 :"C:\msys64\home\William\Projects\FPGA\nmigen\efbutils\diamond-test\build\add.v":1:7:1:9|Synthesizing module add in library work.
Running optimization stage 1 on add .......
@N: CG364 :"C:\msys64\home\William\Projects\FPGA\nmigen\efbutils\diamond-test\build\sub.v":1:7:1:9|Synthesizing module sub in library work.
Running optimization stage 1 on sub .......
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1793:7:1793:10|Synthesizing module OSCH in library work.
Running optimization stage 1 on OSCH .......
@N: CG364 :"C:\msys64\home\William\Projects\FPGA\nmigen\efbutils\diamond-test\build\top.v":1:7:1:9|Synthesizing module top in library work.
Running optimization stage 1 on top .......
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":498:7:498:8|Synthesizing module IB in library work.
Running optimization stage 1 on IB .......
@N: CG364 :"C:\msys64\home\William\Projects\FPGA\nmigen\efbutils\diamond-test\build\actual_top.v":37:7:37:13|Synthesizing module pin_a_0 in library work.
Running optimization stage 1 on pin_a_0 .......
@N: CG364 :"C:\msys64\home\William\Projects\FPGA\nmigen\efbutils\diamond-test\build\actual_top.v":46:7:46:13|Synthesizing module pin_b_0 in library work.
Running optimization stage 1 on pin_b_0 .......
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":857:7:857:8|Synthesizing module OB in library work.
Running optimization stage 1 on OB .......
@N: CG364 :"C:\msys64\home\William\Projects\FPGA\nmigen\efbutils\diamond-test\build\actual_top.v":55:7:55:15|Synthesizing module pin_led_0 in library work.
Running optimization stage 1 on pin_led_0 .......
@N: CG364 :"C:\msys64\home\William\Projects\FPGA\nmigen\efbutils\diamond-test\build\actual_top.v":64:7:64:15|Synthesizing module pin_sel_0 in library work.
Running optimization stage 1 on pin_sel_0 .......
@N: CG364 :"C:\msys64\home\William\Projects\FPGA\nmigen\efbutils\diamond-test\build\actual_top.v":4:7:4:16|Synthesizing module actual_top in library work.
Running optimization stage 1 on actual_top .......
Running optimization stage 2 on actual_top .......
Running optimization stage 2 on pin_sel_0 .......
Running optimization stage 2 on pin_led_0 .......
Running optimization stage 2 on OB .......
Running optimization stage 2 on pin_b_0 .......
Running optimization stage 2 on pin_a_0 .......
Running optimization stage 2 on IB .......
Running optimization stage 2 on top .......
Running optimization stage 2 on OSCH .......
Running optimization stage 2 on sub .......
Running optimization stage 2 on add .......
For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: C:\msys64\home\William\Projects\FPGA\nmigen\efbutils\diamond-test\build\actual_top_impl\synwork\layer0.rt.csv
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 71MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Sun Apr 4 05:17:06 2021
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: DESKTOP-H0PMN4M
Implementation : actual_top_impl
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
Linker output is up to date. No re-linking necessary
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Sun Apr 4 05:17:06 2021
###########################################################]
For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: C:\msys64\home\William\Projects\FPGA\nmigen\efbutils\diamond-test\build\actual_top_impl\synwork\actual_top_impl_comp.rt.csv
@END
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Sun Apr 4 05:17:06 2021
###########################################################]
@A: multi_srs_gen output is up to date. No run necessary.
To force a re-synthesis, select [Resynthesize All] in menu [Run].
Click link to view previous log file.
Multi-srs Generator Report
@R:"C:\msys64\home\William\Projects\FPGA\nmigen\efbutils\diamond-test\build\actual_top_impl\synlog\actual_top_impl_multi_srs_gen.srr"
Synthesis exit by 0.
edif2ngd -l "MachXO2" -d LCMXO2-1200HC -path "C:/msys64/home/William/Projects/FPGA/nmigen/efbutils/diamond-test/build/actual_top_impl" -path "C:/msys64/home/William/Projects/FPGA/nmigen/efbutils/diamond-test/build" "C:/msys64/home/William/Projects/FPGA/nmigen/efbutils/diamond-test/build/actual_top_impl/actual_top_impl.edi" "actual_top_impl.ngo"
edif2ngd: version Diamond (64-bit) 3.11.0.396.4
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved.
Writing the design to actual_top_impl.ngo...
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 10 MB
ngdbuild -a "MachXO2" -d LCMXO2-1200HC -p "C:/lscc/diamond/3.11_x64/ispfpga/xo2c00/data" -p "C:/msys64/home/William/Projects/FPGA/nmigen/efbutils/diamond-test/build/actual_top_impl" -p "C:/msys64/home/William/Projects/FPGA/nmigen/efbutils/diamond-test/build" "actual_top_impl.ngo" "actual_top_impl.ngd"
ngdbuild: version Diamond (64-bit) 3.11.0.396.4
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved.
Reading 'actual_top_impl.ngo' ...
Loading NGL library 'C:/lscc/diamond/3.11_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.11_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.11_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.11_x64/ispfpga/or5g00/data/orc5glib.ngl'...
Running DRC...
WARNING - ngdbuild: logical net 'U$$0/internal_oscillator_inst_SEDSTDBY' has no load.
WARNING - ngdbuild: logical net 'sel_0__io' has no load.
WARNING - ngdbuild: DRC complete with 2 warnings.
Design Results:
11 blocks expanded
Complete the first expansion.
Writing 'actual_top_impl.ngd' ...
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 18 MB
map -a "MachXO2" -p LCMXO2-1200HC -t QFN32 -s 4 -oc Commercial "actual_top_impl.ngd" -o "actual_top_impl_map.ncd" -pr "actual_top_impl.prf" -mp "actual_top_impl.mrp" -lpf "C:/msys64/home/William/Projects/FPGA/nmigen/efbutils/diamond-test/build/actual_top_impl/actual_top_impl_synplify.lpf" -lpf "C:/msys64/home/William/Projects/FPGA/nmigen/efbutils/diamond-test/build/actual_top.lpf" -c 0
map: version Diamond (64-bit) 3.11.0.396.4
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved.
Process the file: actual_top_impl.ngd
Picdevice="LCMXO2-1200HC"
Pictype="QFN32"
Picspeed=4
Remove unused logic
Do not produce over sized NCDs.
Part used: LCMXO2-1200HCQFN32, Performance used: 4.
Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status: Preliminary Version 1.42.
Running general design DRC...
Removing unused logic...
Optimizing...
WARNING - map: IO buffer missing for top level port sel_0__io...logic will be discarded.
Design Summary:
Number of registers: 1 out of 1346 (0%)
PFU registers: 0 out of 1280 (0%)
PIO registers: 1 out of 66 (2%)
Number of SLICEs: 1 out of 640 (0%)
SLICEs as Logic/ROM: 1 out of 640 (0%)
SLICEs as RAM: 0 out of 480 (0%)
SLICEs as Carry: 0 out of 640 (0%)
Number of LUT4s: 1 out of 1280 (0%)
Number used as logic LUTs: 1
Number used as distributed RAM: 0
Number used as ripple logic: 0
Number used as shift registers: 0
Number of PIO sites used: 3 + 4(JTAG) out of 22 (32%)
Number of block RAMs: 0 out of 7 (0%)
Number of GSRs: 0 out of 1 (0%)
EFB used : No
JTAG used : No
Readback used : No
Oscillator used : Yes
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Number of PLLs: 0 out of 1 (0%)
Number of DQSDLLs: 0 out of 2 (0%)
Number of CLKDIVC: 0 out of 4 (0%)
Number of ECLKSYNCA: 0 out of 4 (0%)
Number of ECLKBRIDGECS: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.
Number of clocks: 1
Net U$$0.clk: 1 loads, 1 rising, 0 falling (Driver: U$$0/internal_oscillator_inst )
Number of Clock Enables: 0
Number of LSRs: 0
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net a_0__i: 1 loads
Net b_0__i: 1 loads
Net led_0__o: 1 loads
Net U$$0.adder.o_2: 1 loads
Number of warnings: 1
Number of errors: 0
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 39 MB
Dumping design to file actual_top_impl_map.ncd.
mpartrce -p "actual_top_impl.p2t" -f "actual_top_impl.p3t" -tf "actual_top_impl.pt" "actual_top_impl_map.ncd" "actual_top_impl.ncd"
---- MParTrce Tool ----
Removing old design directory at request of -rem command line option to this program.
Running par. Please wait . . .
Lattice Place and Route Report for Design "actual_top_impl_map.ncd"
Sun Apr 04 05:17:11 2021
PAR: Place And Route Diamond (64-bit) 3.11.0.396.4.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF actual_top_impl_map.ncd actual_top_impl.dir/5_1.ncd actual_top_impl.prf
Preference file: actual_top_impl.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file actual_top_impl_map.ncd.
Design name: actual_top
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: QFN32
Performance: 4
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status: Preliminary Version 1.42.
Performance Hardware Data Status: Final Version 34.4.
License checked out.
Ignore Preference Error(s): True
Device utilization summary:
PIO (prelim) 3+4(JTAG)/108 6% used
3+4(JTAG)/22 32% bonded
IOLOGIC 1/108 <1% used
SLICE 1/640 <1% used
OSC 1/1 100% used
Number of Signals: 5
Number of Connections: 5
Pin Constraint Summary:
3 out of 3 pins locked (100% locked).
No signal is selected as primary clock.
No signal is selected as secondary clock.
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
Finished Placer Phase 0. REAL time: 0 secs
Starting Placer Phase 1.
..................
Placer score = 1401.
Finished Placer Phase 1. REAL time: 3 secs
Starting Placer Phase 2.
.
Placer score = 1401
Finished Placer Phase 2. REAL time: 3 secs
------------------ Clock Report ------------------
Global Clock Resources:
CLK_PIN : 0 out of 8 (0%)
PLL : 0 out of 1 (0%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Global Clocks:
PRIMARY : 0 out of 8 (0%)
SECONDARY: 0 out of 8 (0%)
Edge Clocks:
No edge clock selected.
--------------- End of Clock Report ---------------
I/O Usage Summary (final):
3 + 4(JTAG) out of 108 (6.5%) PIO sites used.
3 + 4(JTAG) out of 22 (31.8%) bonded PIO sites used.
Number of PIO comps: 3; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+--------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+--------------+------------+-----------+
| 0 | 0 / 9 ( 0%) | - | - |
| 1 | 0 / 2 ( 0%) | - | - |
| 2 | 3 / 9 ( 33%) | 2.5V | - |
| 3 | 0 / 2 ( 0%) | - | - |
+----------+--------------+------------+-----------+
Total placer CPU time: 2 secs
Dumping design to file actual_top_impl.dir/5_1.ncd.
0 connections routed; 5 unrouted.
Starting router resource preassignment
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=U$$0.clk loads=1 clock_loads=1
Completed router resource preassignment. Real time: 3 secs
Start NBR router at 05:17:14 04/04/21
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
Start NBR special constraint process at 05:17:14 04/04/21
Start NBR section for initial routing at 05:17:14 04/04/21
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 0 (nbr) score; real time: 3 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 05:17:14 04/04/21
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 0 (nbr) score; real time: 3 secs
Start NBR section for re-routing at 05:17:14 04/04/21
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 0 (nbr) score; real time: 3 secs
Start NBR section for post-routing at 05:17:14 04/04/21
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack :
Timing score : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=U$$0.clk loads=1 clock_loads=1
Total CPU time 3 secs
Total REAL time: 4 secs
Completely routed.
End of route. 5 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
Timing score: 0
Dumping design to file actual_top_impl.dir/5_1.ncd.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack> = 1073741.823
PAR_SUMMARY::Timing score> = 0.000
PAR_SUMMARY::Worst slack> = 1073741.823
PAR_SUMMARY::Timing score> = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 3 secs
Total REAL time to completion: 4 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved.
Exiting par with exit code 0
Exiting mpartrce with exit code 0
trce -f "actual_top_impl.pt" -o "actual_top_impl.twr" "actual_top_impl.ncd" "actual_top_impl.prf"
trce: version Diamond (64-bit) 3.11.0.396.4
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved.
Loading design for application trce from file actual_top_impl.ncd.
Design name: actual_top
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: QFN32
Performance: 4
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status: Preliminary Version 1.42.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.11.0.396.4
Sun Apr 04 05:17:15 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o actual_top_impl.twr actual_top_impl.ncd actual_top_impl.prf
Design file: actual_top_impl.ncd
Preference file: actual_top_impl.prf
Device,speed: LCMXO2-1200HC,4
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 0 paths, 1 nets, and 2 connections (40.00% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.11.0.396.4
Sun Apr 04 05:17:16 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o actual_top_impl.twr actual_top_impl.ncd actual_top_impl.prf
Design file: actual_top_impl.ncd
Preference file: actual_top_impl.prf
Device,speed: LCMXO2-1200HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 0 paths, 1 nets, and 2 connections (40.00% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 45 MB
tmcheck -par "actual_top_impl.par"
bitgen -f "actual_top_impl.t2b" -w "actual_top_impl.ncd" "actual_top_impl.prf"
BITGEN: Bitstream Generator Diamond (64-bit) 3.11.0.396.4
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved.
Loading design for application Bitgen from file actual_top_impl.ncd.
Design name: actual_top
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: QFN32
Performance: 4
Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status: Preliminary Version 1.42.
Performance Hardware Data Status: Final Version 34.4.
Running DRC.
DRC detected 0 errors and 0 warnings.
Reading Preference File from actual_top_impl.prf.
Preference Summary:
+---------------------------------+---------------------------------+
| Preference | Current Setting |
+---------------------------------+---------------------------------+
| RamCfg | Reset** |
+---------------------------------+---------------------------------+
| MCCLK_FREQ | 2.08** |
+---------------------------------+---------------------------------+
| CONFIG_SECURE | OFF** |
+---------------------------------+---------------------------------+
| INBUF | ON** |
+---------------------------------+---------------------------------+
| JTAG_PORT | ENABLE** |
+---------------------------------+---------------------------------+
| SDM_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| SLAVE_SPI_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| MASTER_SPI_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| I2C_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| MUX_CONFIGURATION_PORTS | DISABLE** |
+---------------------------------+---------------------------------+
| CONFIGURATION | CFG** |
+---------------------------------+---------------------------------+
| COMPRESS_CONFIG | ON** |
+---------------------------------+---------------------------------+
| MY_ASSP | OFF** |
+---------------------------------+---------------------------------+
| ONE_TIME_PROGRAM | OFF** |
+---------------------------------+---------------------------------+
| ENABLE_TRANSFR | DISABLE** |
+---------------------------------+---------------------------------+
| SHAREDEBRINIT | DISABLE** |
+---------------------------------+---------------------------------+
| BACKGROUND_RECONFIG | OFF** |
+---------------------------------+---------------------------------+
* Default setting.
** The specified setting matches the default setting.
Creating bit map...
Bitstream Status: Final Version 1.95.
Saving bit stream in "actual_top_impl.bit".
Total CPU Time: 3 secs
Total REAL Time: 4 secs
Peak Memory Usage: 253 MB
tmcheck -par "actual_top_impl.par"
bitgen -f "actual_top_impl.t2b" -w "actual_top_impl.ncd" -jedec "actual_top_impl.prf"
BITGEN: Bitstream Generator Diamond (64-bit) 3.11.0.396.4
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved.
Loading design for application Bitgen from file actual_top_impl.ncd.
Design name: actual_top
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: QFN32
Performance: 4
Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status: Preliminary Version 1.42.
Performance Hardware Data Status: Final Version 34.4.
Running DRC.
DRC detected 0 errors and 0 warnings.
Reading Preference File from actual_top_impl.prf.
Preference Summary:
+---------------------------------+---------------------------------+
| Preference | Current Setting |
+---------------------------------+---------------------------------+
| RamCfg | Reset** |
+---------------------------------+---------------------------------+
| MCCLK_FREQ | 2.08** |
+---------------------------------+---------------------------------+
| CONFIG_SECURE | OFF** |
+---------------------------------+---------------------------------+
| INBUF | ON** |
+---------------------------------+---------------------------------+
| JTAG_PORT | ENABLE** |
+---------------------------------+---------------------------------+
| SDM_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| SLAVE_SPI_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| MASTER_SPI_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| I2C_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| MUX_CONFIGURATION_PORTS | DISABLE** |
+---------------------------------+---------------------------------+
| CONFIGURATION | CFG** |
+---------------------------------+---------------------------------+
| COMPRESS_CONFIG | ON** |
+---------------------------------+---------------------------------+
| MY_ASSP | OFF** |
+---------------------------------+---------------------------------+
| ONE_TIME_PROGRAM | OFF** |
+---------------------------------+---------------------------------+
| ENABLE_TRANSFR | DISABLE** |
+---------------------------------+---------------------------------+
| SHAREDEBRINIT | DISABLE** |
+---------------------------------+---------------------------------+
| BACKGROUND_RECONFIG | OFF** |
+---------------------------------+---------------------------------+
* Default setting.
** The specified setting matches the default setting.
Creating bit map...
Bitstream Status: Final Version 1.95.
Saving bit stream in "actual_top_impl.jed".
===========
UFM Summary.
===========
UFM Size: 511 Pages (128*511 Bits).
UFM Utilization: General Purpose Flash Memory.
Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
Initialized UFM Pages: 0 Page.
Total CPU Time: 4 secs
Total REAL Time: 4 secs
Peak Memory Usage: 253 MB
Lattice Diamond Deployment Tool 3.11 Command Line
Loading Programmer Device Database...
Generating Bitstream.....
Reading Input File: actual_top_impl/actual_top_impl.bit
Output File: actual_top.bit
Start generation.
Generating Binary Bitstream.....
Processing file actual_top_impl\actual_top_impl.bit ......
File actual_top_impl\actual_top_impl.bit processed successfully.
The file actual_top.bit was generated successfully.
Lattice Diamond Deployment Tool has exited successfully.
Lattice Diamond Deployment Tool 3.11 Command Line
Loading Programmer Device Database...
Generating JED.....
Device Name: LCMXO2-1200HC-4SG32C
Reading Input File: actual_top_impl/actual_top_impl.jed
Output File: actual_top.jed
Generating JEDEC.....
File actual_top.jed generated successfully.
Lattice Diamond Deployment Tool has exited successfully.
Lattice Diamond Deployment Tool 3.11 Command Line
Loading Programmer Device Database...
Generating SVF.....
Reading Input File: actual_top_impl/actual_top_impl.jed
Output File: actual_top_flash.svf
Revision D: ON
Generate Single SVF file: Start
Device 1 LCMXO2-1200HC:FLASH Erase,Program,Verify
Build SVF File Operation: Successful.
Lattice Diamond Deployment Tool has exited successfully.
1 file(s) copied.
Lattice Diamond Deployment Tool 3.11 Command Line
Loading Programmer Device Database...
Generating SVF.....
Reading Input File: actual_top_impl/actual_top_impl.bit
Output File: actual_top_sram.svf
Revision D: ON
Generate Single SVF file: Start
Device 1 LCMXO2-1200HC:SRAM Fast Program
Build SVF File Operation: Successful.
Lattice Diamond Deployment Tool has exited successfully.