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ALU VHDL implemented in a structural and behavioral.
VHDL
branch: master
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simulation add operation
src Alpha version
testbench Alpha version
Makefile sinulation bug fix
README.md Edited README.md via GitHub

README.md

Copyright

Copyright Johalf Farina, Pontifícia Universidade Católica do Rio Grande do Sul 2011. This work is the intellectual property of the author(s). Permission is granted for this material to be shared for non-commercial, educational purposes, provided that this copyright statement appears on the reproduced materials and notice is given that the copying is by permission of the author(s). To disseminate otherwise or to republish requires written permission from the author(s).

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