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[nrf fromtree] soc: nordic: Gate FLASH_0 MPU region on CONFIG_XIP #3508

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Merged
merged 1 commit into from
Nov 18, 2025
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[nrf fromtree] soc: nordic: Gate FLASH_0 MPU region on CONFIG_XIP #3508

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2 changes: 2 additions & 0 deletions soc/nordic/common/nrf54hx_nrf92x_mpu_regions.c
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Original file line number Diff line number Diff line change
Expand Up @@ -22,10 +22,12 @@
#define SOFTPERIPH_SIZE DT_REG_SIZE(DT_NODELABEL(softperiph_ram))

static struct arm_mpu_region mpu_regions[] = {
#ifdef CONFIG_XIP
MPU_REGION_ENTRY("FLASH_0",
CONFIG_FLASH_BASE_ADDRESS,
REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS,
CONFIG_FLASH_SIZE * 1024)),
#endif
MPU_REGION_ENTRY("SRAM_0",
CONFIG_SRAM_BASE_ADDRESS,
REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS,
Expand All @@ -34,7 +36,7 @@
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usbhs))
MPU_REGION_ENTRY("USBHS_CORE", USBHS_BASE,
REGION_RAM_NOCACHE_ATTR(USBHS_BASE, USBHS_SIZE)),
#endif

Check notice on line 39 in soc/nordic/common/nrf54hx_nrf92x_mpu_regions.c

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soc/nordic/common/nrf54hx_nrf92x_mpu_regions.c:39 
-	MPU_REGION_ENTRY("FLASH_0",
-			 CONFIG_FLASH_BASE_ADDRESS,
-			 REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS,
-				CONFIG_FLASH_SIZE * 1024)),
+	MPU_REGION_ENTRY("FLASH_0", CONFIG_FLASH_BASE_ADDRESS,
+			 REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS, CONFIG_FLASH_SIZE * 1024)),
 #endif
-	MPU_REGION_ENTRY("SRAM_0",
-			 CONFIG_SRAM_BASE_ADDRESS,
-			 REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS,
-				CONFIG_SRAM_SIZE * 1024)),
+	MPU_REGION_ENTRY("SRAM_0", CONFIG_SRAM_BASE_ADDRESS,
+			 REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, CONFIG_SRAM_SIZE * 1024)),
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usbhs))
-	MPU_REGION_ENTRY("USBHS_CORE", USBHS_BASE,
-			 REGION_RAM_NOCACHE_ATTR(USBHS_BASE, USBHS_SIZE)),
+	MPU_REGION_ENTRY("USBHS_CORE", USBHS_BASE, REGION_RAM_NOCACHE_ATTR(USBHS_BASE, USBHS_SIZE)),
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(can120))
MPU_REGION_ENTRY("CAN120_MCAN", CAN120_BASE,
REGION_RAM_NOCACHE_ATTR(CAN120_BASE, CAN120_SIZE)),
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