digital mixer on FPGA
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avr
controller
dspsw
filterpy
ise
lpc
nkmd
testdata/gen
.gitignore
LICENSE.txt
Makefile.async_fifo
Makefile.csr
Makefile.csr_spi
Makefile.dac_drv
Makefile.dcm
Makefile.decimator
Makefile.dmix
Makefile.genpulse
Makefile.hw_test
Makefile.mixer
Makefile.mpemu
Makefile.mpemu_scale
Makefile.nkmdhpa
Makefile.pipeline
Makefile.pop_latch
Makefile.posedge_latch
Makefile.resampler
Makefile.ringbuf
Makefile.spdif
Makefile.spdif_tx
Makefile.spi
Makefile.uart
README.md
async_fifo.v
async_fifo_t.v
csr.v
csr_spi.v
csr_spi_t.v
csr_t.v
dac_drv.v
dac_drv_t.v
dcm.v
dcm_t.v
decimator.v
decimator_t.v
dmix.v
dmix_t.v
dmix_top.ucf
fa1242.v
gen_random_mul.rb
gen_random_mul_scale.rb
genpulse.v
genpulse_t.v
hw_test.v
hw_test_t.v
labtoolcsv2memb.rb
mixer.v
mixer_t.v
mp_settings.png
mpemu.v
mpemu_scale_t.v
mpemu_t.v
nkmdhpa.v
nkmdhpa_t.v
pop_latch.v
pop_latch_t.v
posedge_latch.v
posedge_latch_t.v
progcmd.memh
resample_pipeline.v
resample_pipeline_t.v
resampler.v
resampler_t.v
ringbuf.v
ringbuf_t.v
rom_firbank_32_48.v
rom_firbank_441_480.v
rom_firbank_48_96.v
rom_firbank_96_192.v
spdif_capture.tgz
spdif_dai.v
spdif_dai_t.v
spdif_dai_varclk.v
spdif_tx.v
spdif_tx_t.v
spi_trx.v
spi_trx_t.v
synth.v
top_spdif.v
top_uarttest.ucf
top_uarttest.v
uart.v
uart_t.v

README.md

dmix

dmix is a FPGA-based digital mixer.

License

MIT License

Block diagram

https://docs.google.com/presentation/d/1eTRmQODLgxqnv2yuBNbpwJNigMHqBfnhtFLWPbKyl60/edit?usp=sharing

List of modules

  • dac_drv.v
    • output I2S-like but 24bit MSB first format accepted by FA1242
  • fa1242.v
    • reset FA1242 chip
  • mixer.v
    • mix multiple 2ch audio streams w/ attenuators
  • mpemu.v
    • multiplier IP core emulator
  • posedge_latch.v
    • latch wb signal on posedge
    • used to interface modules w/ different clocks
  • resampler.v
    • resample audio stream using polyphase FIR filters
  • ringbuf.v
    • ringbuf for buffering audio data avoiding jitters
    • also serves as a delay line for FIR filters
  • rom_firbank_441_480.v
    • polyphase FIR bank for 44.1kHz -> 48.0kHz resampling
  • rom_firbank_half.v
    • polyphase FIR bank for halfband filter
  • spdif_dai.v
    • decode S/PDIF signal
  • synth.v
    • sawwave synth for test

Protocol

Pull-based

  • The downstream requests new sample to be output by the upstream by setting pop_i to 1.
  • The upstream responds to request by setting ack_o to 1, with the new sample on data_o[].
    • For modules w/o ack_o, simply assume the data_o[] returns the valid sample in the immediate next cycle.