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Newer
100644
145 lines (123 sloc)
3.95 KB
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#include "audio.h"
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#include "pi.h"
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/**
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* Audio wrapper for PWM on baremetal Pi.
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*/
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static void configure_pwm_clock() {
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// disable pwm
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PWM_CONTROL = 0;
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// disable clock
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PWMCLK_CNTL = 0x5a000000 | (PWMCLK_CNTL & ~(1 << 4));
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// wait for busy flag to clear
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while (PWMCLK_CNTL & (1 << 7));
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// divide clock by 5.08626302083 to get to 2048*48KHz
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PWMCLK_DIV = 0x5a005058;
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// use PLLD @ 500MHz
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PWMCLK_CNTL = 0x5a000006;
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// enable clock (bit 4)
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PWMCLK_CNTL = 0x5a000016;
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// wait for busy flag to set
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while (!(PWMCLK_CNTL & (1 << 7)));
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}
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static void configure_pwm() {
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// map gpio40 to pwm0 out (4 = alt function 0)
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GPFSEL4 = (GPFSEL4 & ~(7)) | 4;
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// map gpio45 to pwm1 out (4 = alt function 0)
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GPFSEL4 = (GPFSEL4 & ~(7 << 15)) | (4 << 15);
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PWM0_RANGE = PULSES_PER_SAMPLE;
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PWM1_RANGE = PULSES_PER_SAMPLE;
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// enable pwm0, use fifo for pwm0, enable pwm1, use fifo for pwm1
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PWM_CONTROL = 1 + (1 << 5) + (1 << 8) + (1 << 13);
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// enable dma, and raise dreq as soon as only 7 words left in the fifo
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PWM_DMAC = 0x80000707;
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unsigned int transfer_info;
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unsigned int source_ad;
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unsigned int dest_ad;
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unsigned int txfr_len;
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unsigned int stride;
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unsigned int nextconblk;
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unsigned int reserved1;
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unsigned int reserved2;
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} dma_cb_t;
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// Defined in start.s so I can guarantee 8-byte alignment
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extern dma_cb_t dma_control_blocks[];
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unsigned int pwm_buffer0[BLOCK_SIZE];
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unsigned int pwm_buffer1[BLOCK_SIZE];
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unsigned int dma_cb0_addr;
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unsigned int dma_cb1_addr;
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unsigned int dma_last_filled;
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static void configure_dma()
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{
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dma_cb0_addr = ((unsigned int) &dma_control_blocks[0]) + RAM_PHYS_OFFSET;
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dma_cb1_addr = ((unsigned int) &dma_control_blocks[1]) + RAM_PHYS_OFFSET;
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// 5 = pwm channel, 1 = src_inc, 4 = dest_dreq, 8 = wait_resp
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dma_control_blocks[0].transfer_info = 0x00050148;
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dma_control_blocks[0].source_ad = ((unsigned int) pwm_buffer0) + RAM_PHYS_OFFSET;
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dma_control_blocks[0].dest_ad = 0x7E20C018; // PWM_FIFO physical address
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dma_control_blocks[0].txfr_len = BLOCK_SIZE * sizeof(int);
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dma_control_blocks[0].stride = 0;
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dma_control_blocks[0].nextconblk = dma_cb1_addr;
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dma_control_blocks[0].reserved1 = 0;
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dma_control_blocks[0].reserved2 = 0;
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dma_control_blocks[1].transfer_info = 0x00050148;
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dma_control_blocks[1].source_ad = ((unsigned int) pwm_buffer1) + RAM_PHYS_OFFSET;
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dma_control_blocks[1].dest_ad = 0x7E20C018;
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dma_control_blocks[1].txfr_len = BLOCK_SIZE * sizeof(int);
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dma_control_blocks[1].stride = 0;
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dma_control_blocks[1].nextconblk = dma_cb0_addr;
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dma_control_blocks[1].reserved1 = 0;
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dma_control_blocks[1].reserved2 = 0;
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dma_last_filled = 0;
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// reset dma controller
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DMA0_CS = 0x80000000;
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}
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void audio_init()
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{
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}
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void audio_write(float* block)
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// Wait for the buffers to flip
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while (DMA0_CONBLK_AD != dma_last_filled);
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unsigned int* pwm_buffer;
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if (DMA0_CONBLK_AD == dma_cb0_addr) {
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pwm_buffer = pwm_buffer1;
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dma_last_filled = dma_cb1_addr;
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} else {
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pwm_buffer = pwm_buffer0;
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dma_last_filled = dma_cb0_addr;
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}
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int i;
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for (i = 0; i < BLOCK_SIZE; i++) {
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pwm_buffer[i] = PULSES_PER_SAMPLE * ((1 + block[i]) / 2);
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}
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// Start DMA if not already active
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if (!(DMA0_CS & 1)) {
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// clear end flag
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DMA0_CS |= 2;
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// set control block
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DMA0_CONBLK_AD = dma_last_filled;
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// enable dma
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DMA0_CS |= 1;
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}
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}
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// Write PWM data via the FIFO register. Slow and no longer used.
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void audio_write_fifo(float* block)
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{
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int i;
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for (i = 0; i < BLOCK_SIZE; i++) {
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int data = PULSES_PER_SAMPLE * ((1 + block[i]) / 2);
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// wait for space in fifo
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while (PWM_STATUS & 1);
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// write data
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PWM_FIFO = data;
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}
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}