From 2bbf21ba7d356da6768ee2ada0c216e8a3d8bd7a Mon Sep 17 00:00:00 2001 From: Jan Vermaete Date: Wed, 26 Apr 2023 20:27:14 +0200 Subject: [PATCH 01/11] Lint the generated reStructuredText files. * Added the Python package to lint the generated files. * Add the 'test_rst' target in the Makefile (as the test_c) * Added to the ci pipeline Signed-off-by: Jan Vermaete --- .circleci/config.yml | 1 + Makefile | 2 ++ requirements.txt | 1 + 3 files changed, 4 insertions(+) diff --git a/.circleci/config.yml b/.circleci/config.yml index 7d044f0..585707e 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -24,4 +24,5 @@ jobs: - run: make compile_ghdl - run: make compile_verilator - run: make test_c + - run: make test_rst diff --git a/Makefile b/Makefile index 2c26eee..699b6e5 100644 --- a/Makefile +++ b/Makefile @@ -87,6 +87,8 @@ clean: validate: xmllint --noout --schema ipxact2systemverilog/xml/component.xsd example/input/test.xml +test_rst: + rst-lint example/output/*.rst venv: requirements.txt python3 -m venv ./venv diff --git a/requirements.txt b/requirements.txt index 9dca3fe..5ab727f 100644 --- a/requirements.txt +++ b/requirements.txt @@ -2,3 +2,4 @@ docutils lxml tabulate mdutils +restructuredtext-lint From 43a7422b1883735da3c86824b0cd13a43c037c56 Mon Sep 17 00:00:00 2001 From: Jan Vermaete Date: Thu, 18 May 2023 17:17:57 +0200 Subject: [PATCH 02/11] rst: using the RstCloth Python module to generate the RestucturedText code. RstCloth: A simple Python API for generating RestructuredText. https://pypi.org/project/rstcloth/ It reduced a bit the own Python code. The output stays the same. * Except some white spacing alignent. What's nice to have, but not needed because the generated RST files are just an input to generated the real document. * underline symbols of the sections is now more in line with the kind-of-standard https://www.sphinx-doc.org/en/master/usage/restructuredtext/basics.html#sections Linting at RST is done and ok. Signed-off-by: Jan Vermaete --- README.md | 2 +- ipxact2systemverilog/ipxact2hdlCommon.py | 76 ++++++++---------------- requirements.txt | 2 +- 3 files changed, 27 insertions(+), 53 deletions(-) diff --git a/README.md b/README.md index d1991d0..c3b141c 100644 --- a/README.md +++ b/README.md @@ -56,7 +56,7 @@ xmllint --noout --schema ipxact2systemverilog/xml/component.xsd example/input/t ## Dependencies ```bash -pip install docutils lxml tabulate mdutils +pip install docutils lxml mdutils ``` ## Dependencies used by makefile diff --git a/ipxact2systemverilog/ipxact2hdlCommon.py b/ipxact2systemverilog/ipxact2hdlCommon.py index 02e4495..cb7e640 100644 --- a/ipxact2systemverilog/ipxact2hdlCommon.py +++ b/ipxact2systemverilog/ipxact2hdlCommon.py @@ -19,12 +19,13 @@ # # andreas.lindh (a) hiced.com +import io import math import os import sys import xml.etree.ElementTree as ETree -import tabulate from mdutils.mdutils import MdUtils +from rstcloth import RstCloth DEFAULT_INI = {'global': {'unusedholes': 'yes', 'onebitenum': 'no'}, @@ -189,25 +190,33 @@ def returnEnumValueString(self, enumTypeObj): return s def returnAsString(self): - r = "" + r = RstCloth(io.StringIO()) # with default parameter, sys.stdout is used regNameList = [reg.name for reg in self.registerList] regAddressList = [reg.address for reg in self.registerList] regDescrList = [reg.desc for reg in self.registerList] - r += self.returnRstTitle() - r += self.returnRstSubTitle() + r.title("Register description") + r.newline() + r.h2("Registers") summary_table = [] for i in range(len(regNameList)): summary_table.append(["%#04x" % regAddressList[i], str(regNameList[i]) + "_", str(regDescrList[i])]) - r += tabulate.tabulate(summary_table, - headers=['Address', 'Register Name', 'Description'], - tablefmt="grid") - r += "\n" - r += "\n" + r.table(header=['Address', 'Register Name', 'Description'], + data=summary_table) for reg in self.registerList: - r += self.returnRstRegDesc(reg.name, reg.address, reg.size, reg.resetValue, reg.desc, reg.access) + r.h2(reg.name) + r.newline() + r.field("Name", reg.name) + r.field("Address", hex(reg.address)) + if reg.resetValue: + # display the resetvalue in hex notation in the full length of the register + r.field("Reset Value", + "{value:#0{size:d}x}".format(value=int(reg.resetValue, 0), size=reg.size // 4 + 2)) + r.field("Access", reg.access) + r.field("Description", reg.desc) + reg_table = [] for fieldIndex in reversed(list(range(len(reg.fieldNameList)))): bits = "[" + str(reg.bitOffsetList[fieldIndex] + reg.bitWidthList[fieldIndex] - 1) + \ @@ -229,19 +238,14 @@ def returnAsString(self): if reg.resetValue: _headers.append('Reset') _headers.append('Description') - r += tabulate.tabulate(reg_table, - headers=_headers, - tablefmt="grid") - r += "\n" - r += "\n" + r.table(header=_headers, + data=reg_table) # enumerations for enum in reg.enumTypeList: if enum: # header - r += enum.name + "\n" - r += ',' * len(enum.name) + "\n" - r += "\n" + r.h3(enum.name) # table enum_table = [] for i in range(len(enum.keyList)): @@ -252,40 +256,10 @@ def returnAsString(self): _value, enum.descrList[i]] enum_table.append(_line) - r += tabulate.tabulate(enum_table, - headers=['Name', 'Value', 'Description'], - tablefmt="grid") - r += "\n\n" - - return r + r.table(header=['Name', 'Value', 'Description'], + data=enum_table) - def returnRstTitle(self): - r = '' - r += "====================\n" - r += "Register description\n" - r += "====================\n\n" - return r - - def returnRstSubTitle(self): - r = '' - r += "Registers\n" - r += "---------\n\n" - return r - - def returnRstRegDesc(self, name, address, size, resetValue, desc, access): - r = "" - r += name + "\n" - r += len(name) * '-' + "\n" - r += "\n" - r += ":Name: " + str(name) + "\n" - r += ":Address: " + hex(address) + "\n" - if resetValue: - # display the resetvalue in hex notation in the full length of the register - r += ":Reset Value: {value:#0{size:d}x}\n".format(value=int(resetValue, 0), size=size // 4 + 2) - r += ":Access: " + access + "\n" - r += ":Description: " + desc + "\n" - r += "\n" - return r + return r.data class mdAddressBlock(addressBlockClass): diff --git a/requirements.txt b/requirements.txt index 5ab727f..063dc3c 100644 --- a/requirements.txt +++ b/requirements.txt @@ -1,5 +1,5 @@ docutils lxml -tabulate mdutils restructuredtext-lint +rstcloth From 407bb3e2b67e5906f779d4065aa47b932df9c53e Mon Sep 17 00:00:00 2001 From: Jan Vermaete Date: Thu, 18 May 2023 17:43:39 +0200 Subject: [PATCH 03/11] Update of the goldenreference output. Signed-off-by: Jan Vermaete --- example/output/example.docx | Bin 11620 -> 11656 bytes example/output/example.html | 13 +++-- example/output/example.rst | 66 ++++++++++++------------ example/output_default/example.rst | 66 ++++++++++++------------ example/output_no_default/example.rst | 70 +++++++++++++------------- 5 files changed, 112 insertions(+), 103 deletions(-) diff --git a/example/output/example.docx b/example/output/example.docx index 0427aeced2c2b03fdc3d2e2988f5d11245e0f2b0..c42af61ee6cfb986c622a350c155ce6f8b48b0c8 100644 GIT binary patch delta 6400 zcmZvg1x%bxx5pP2D^e(4T#GG>TXA! zHiwhdwhI~nFajGxB!$8}B3L*G76(FTaDBYR)-FXL<;z~oIFbM2ALwQlf?(yYR5^QB4oI?IYGI>ez~?zAY;WS2OEgu=l=bjVCHzJL|} zi@O|kftLe)Dnlr3Xbz@3Q*#)(P|sjw$bdmKq7mCtATgT5zOQR#N-Lz<-T^Vf0s2Kb zoPBSf>ZFP@n}donh{okGCTI^WORxFg|HO;y>`2H4ikEhhO#IlbP$tW`-P#+sprrYY z7p#iy+Zz&3OW6z9)ZzEO#WX$)5Fu9v>%;-#k<2$y$f83$^NwGFl}SqANN28>4p8hk%#oSvrH1DkXt&Whfx-vV>DIm zo`?EF#Z++TB(!Hd(VH!$jcSkWqx;XPjzJ1Zg@Ld}rFYqSeIptqQE9_#hn-jWEsgvz zPCBGkJ!qg5|AeU?+V$;3opC$JmY%jqtrt#*)=%{eHRNq z+F!iRh8&*(rp`%WHGn%P;PGk^385V`_I&{F9f%^+x*R<%vb;hW*7C%dQ7j(;~Sn z6(WPPdo>ZS-&^S2?o}=;H5BMa6Awz>H|>oyxpcR`2WE~on3765eJz4A$9}r!vbW?` zNhzw7Wc~ip_VCWSr(!hSEuoaSxIoP79qf*{;EwnVaeZ|ZV0d5Of}tot5p`cY@|p9Y zgqAW7#85#VXc&2@RTvcPklapT{un4IaG#mKe;z|b_ns$=4?yS4w+vUF|AovZwr{88 z4-jK!D$fbvUZ6K}>XU>be@BZeFWFJ*aWCR1qKX~9EUcsXmOhilNo5-|_qoPQvt&ls zTKked_Pq|o0~CA4!{aM3DOE+ws*uigqPoqcpIrEiRl!F6%A|TK-!u21d<@mN#w;%z z7vAvBS$t&<5i&V1sdc)T|E;_5Xg|P4P;s@@Z~1$=R!|dmT9XI#b^dr5$T}x@1dh{~ zKGM#noF1)KVz(cNHYx7;9LT5R`CQ2JdB#LPaZ_~riPPZlA}wkw8edZ@f_#}%_)9IF z>uyZcmoE~^LSiaMg~SGAsr&L%%UF~G%Fp+oDdSSw=@`5w+X@yY9%M*kuH$}YuV^@; zew?PUz@7RzsiQ6oy4b%fmF}|8NagWqJ&`$j&$p7ySKnD>a-vSe)mYthMGv<>hHu_?qF$L3CP zmc$H*zC$!=kJ3oyUZPnr@hG`8enk9AA~2&5JILgu@d9h7LZ8WSdnzK++C{#&{9Q~i zYtc2k)mTfy9;|;6Y!!MVzJ%khH=znoH+KnoSce04Q0wMj81)yc{6u|k^&yRNmWKGm z+aHItK5HBsmj$ExasvM%ILx*>jj}Irg7i7XS+QUk!8o=_`(1yex^;9SMv7|_SnTK8~=pKF2AQy2dmYE{minh;0uo(KqKOQcpssMYT( zPp|^1%@HpK3p=b8w+1ZWSWG}zHTLu3Oz07GzD}NG0~Jp}*6YBl2QhB-8|3=TH-T!K z910s~4*E4K(kda)Q#e4E^kBAb#Tv4zH^*uptpXwi+uFPFX0EFSiDGrBb$>*HmS1Tf zXNgKn(xTook>-{Sd7lkQ5kfVtzN`YS@eV?UR(`5x>&-3Xw(^@C!->r<3iRJ@M6jwf zLk`|RTg$lLQqVCI7nsBZ^XOozUUbE7(=%8HdcmXMi$ayjKh5!?l2Xkq)h|Qol~Y?6 z%ibMK&oB#a?@!bwC!<0=6L0v1!M3W1;7@H76qE5k%-${)=AEg9`%*=Ijg#G$#8x7~ z!@lf8)n~rTo=7Dsa}j46mq{Fni3lR7AAX|%z33ag@WxQs+uU^X)K(B|P+%;QV1i67 zZ#rLiR?`MltGZJyFOExgjkw}IT~9=W{q~$o^lJkOANLGwp%;tA=7(meJb8ua^jeH% zUjzvx##_cJ__L3x`hqh{TO3D%+uXr@!6_Lx7LyV{n-#*}oZrBI z!%BlXhR9!9fhA#xss4pYfO5dr|9jspPT0ssJycPV5g2Q z7r%`$TO0Zd3A(Oq>UFh5LOpQYv+G4jj(M$-FzY0S`UO%eaUPCK5=QL|&#+N>RN;Qr&P1<6CcTM> zY?a)Q(AT9fcE1j^qL&klPPy`D8D;k$c$1Gr6qloy8M&ra21trsTPbj-<|=Q(D*U@U ztYXUBJY}J5%~`J4orQi0(~@j#Yb;!he%FqN(%#s)HKP(4hOs2y-?y?W6{{fL6TjSu zj4=0ESh>;qt{r}KEGqs@U5rL3VsrneeRq(osk0xH*eVWU(yne&OZvQLeX2R|Y%nnL zhdA*h2E-&t-Q<^ExG~h?@^^Sa*Y$TN;FNW9V5E#y;Ik&VQW8m11f8$xXXau*B|9J~-TJYM`+#e{(W=qxmDS zg6&^as?C<2V}khvp|vWohv!7l758O+e7_SN&$I7lm>WrRjnN79Njwl3Q=uPW6M&~_ zD{G7tzWg(bm3-Ld`ub+tHP%NCD0Qk=aM|rZjI+`w?&&<= zk{!2pMfy?n%iXmTNi72r3JTv~HlRz{+kuO}B6I0Z1 z#kwW%Xfy4pV z?056r!K+`I)2=bXH@*gxYPGpt#;-mSCEsMdP)*z*IJs-voqrr?6Gp36Q) zzNGuX1M}z9WWq^Fhg_L#Laj;cbtWJCpm39yDewZe!bYUq&+XBhZv6S;jckvt%c#*qhAq1 zKRx|^8dBCO&u?zGWLc{3Wk2GpwIQuhVd&YKm6nl}mXtNyu#Y9#ME54A0LdpC(*bYF zFQo^gV=%D|N=gk4Y543ri74~I5-hotzFeE(v%a(EtOpSxOobs&(iAVoa6tmRc2Hhu;_8E#oI!av5j?Qr7 zlhx$Krlk8$hy+NvyJ0`WBk~sXg|{ko)=HP3t#k1=wEvrYW0j~o^O1cq5AF#x z3V{X}pefQEQcCN7M4L1;TeAhHp?QAAg86~fgi>+n`LxjY?b7M}s1Kdoz>d*qRUID| zwu@+o6rtJNuR=_Fa`gqu`i~c2=QB((n$5ny;#L%?I->B6!4{eA-^xhfMzMLA zkIseC(bkWvW7JnbNXe$ZTA93ZWMyPhrG*-daD>g4MV(&yLX-_S0++^El|a9J36w{| zxAu(=(=O1WMt0n3cR#O*oej{?{tlazu>xl`ELK~>Kc#T>5T7;e!SefETuW%6mdEmM zv)3A3`>A94Am5k@b2L6g#=dxYB&e+Oz@5x;Ve~fSlW?HFa*o#9?@duV#d40MeSXlC z)fcC8_!>^Bbo0&xjcP_!5Y5mWR;_8yqS!YUrVeqbeG)Z$%Qd40UM6{0^!1BNsh^KG zz!K$*ubyc?T1*+{#rlQB#pzmEI25)xs%hS0_+Z3JhB7g&<(BYu#hy2^-q5U;JLo=Z zQkZD!xDRndAwHk&C?w1@P-lJf`JolsA`uJR45C``{F#aGvnSkP&K6=0>AVL{P=_vR zD`&WUZLhB&3G?pwv=P? zlMUiyX2p&S-6gALp0z$0$Zl;p){$mIt6<`{r?mKAi9=!>ycxI_>-Rg)iN>M!e4F*X zjbu#U1rKs!P+5zs5GXRW#p?H34>#=Q~U zgpS?y+ZLr*h{R(ian}efx3S+Nf9#{ubZOpEd!BSlo2P8P96FY6H5tQKJp7VcSsv?< z4FJ^q{p{s~kap-}Ktuf6+c|kC*|KOLOHnqpmYj!DSFaJ*o~z1sTZ}6T8QFH7A^@g7 z5fEGef=gqXFdaNi^Xz;#Ut`Nroa{DZ#5yBPaggy$)z^l0z1%Z(y|-YJaZO$>-Fm1y zQDsmYX57rr&wy)bgR90{y4m9}e+0kdX>;1X2~k)`Bd7=Ng&1rXO+xWRt*MM}I7<~k zZ3dVPZd^fj)qBG=98#h^RIEpq!3yO7?NK}7cm~O_$!-O{C>zL9ns78rq@zExf+m8n zlTP)`3)y{Xl-Wk*8s|F#v$ymGLfVm@3;S0ltCr|$bl)`58_5Sevd{RG8kGLfo=lWE%y$UM&ZNuei>Ru_6tinAH%b_#Ju0Q;pt0ceZpc+&aJ3n)da}3=$AQM>{a69v(PSN)jK}1ldaIAn9dgd zYNvZHE%fb_bzsd}C!jy-LgM*rCx$R^G9@WzZWQps3vQGTXUI4Y)wn^2A%u?z`8$IO zIwasZ8GFXvC69oAVM7BCk?en}Sx{nB1hhYZ_>*(?2Q2O-74%&XJ5Jcu@2DZ4O}b=s zJ!;IVH2pHWGX3`rhqStVl=U@O_jeh9Ksg6;wiDO*lfyUB*^V&dQ*k{m2I&+SQcSHz zx|NEE_Nbc-;iVxx8Qy$vMe}nZW;FRjuE1w}45U(nj96yCjBpU{t1$Zmo-LPLp9*yd&7BUZ|(`>shZTESN?Nv(gVJsQN5=}mJDT`eK%E#6R$#twDFiY?u~!FnioU>Px7`WoV8A^ytwwfnd2EMI;VijUfg8mV3a@)x%HW7_@6 ztErV){*-YqFO5T9cU+l&9Da92w=w(A>`w$&W8!JVaveBgBUmvH&s*I~ zc3+chu^9+qmrwrG>Ca{t;8^hDp7Bn8>U}&zpTEd>1%D31N31uCs2*+nKA7(juSed06zb32m|89{D&1hjU zKd)UCiK@1I{?euFO%SnAx#b;Iy5i>-3F+>G7eP&kDwtssT%y! zX~Frrp^<_;6wUEu5yVM0C0G%mV=>ieF^a{B)F^7@uIs*{FOq@XyHQSM5jav>5p%W; zKTef6bq|3C?2cl24=EmW4@E>lXTZ&W02&AS+XOvi8S*|2wucc=@i zwNw-0vg1W(M(2~tuP{n3Ap&`?F8vB9V9>%BoWwST`obX*z!SDvsAn6Sm_5;ZdSOqFgDdx6L37B4k5@Mb%O%Tpmj{{;K2-gWD>Pqphh993d;HEMn^ zoa8{a(sbdIZu5XQ;lZ5ln%M&h28b|u(JtJcT<1cRq!SNb*QYt$3Zn8Vy-`&&{{pb& zN1s;dyNqh7_L^vnq#BGhv-mUyJ-l&AIx-Hsfd4DvYsdcV;ePjY@cf>P{K@|LQejTaAj<#msr-*d z9M;B6P4!3f&$9~v!2U<@_z`YlQ?DH;Cr%3_TDjq9Qp=jGPD-3&Q*x v$^wxhq{3Q2)PIxw_kHtE9y8cA=s(MnvXUaEF~SlU31KR%I4D+3e?}&?ghO|S99kOb?(Pn0X%Ga2mlja+a7d4YfOLa&cO4LN- z|IGdGci)*kdq1<+UTe>++3S6t6>Gj__DDw^6^#T0#=-)!U@B|6KF(Uw$t9- z9Gy?t{k%W^7*M;%5PZ-V1`3jeWc@gDmRE7sVoT`=?<7so#X`LWmZ@yNGX1pvEgDDY zFZb4sLQzoqYmRd~f6jF}_1iPI-@=P|7fX%nAy(l`#C1^qp6UrSc_h>9sqm(YuJ09z|6TlIh(^WODP8egr}%GsFt-8V8(XmaI_IC!H{j^d2I{r zvYA)Kr{BAJyyalZZNQEE=wtR}7X6^T)`W}TjHiyplv0#)41X?Kv4Uf}G!}8keg8`( zTs=qNxx8F5U@fQ;u}PE;k3!N*Ts>hYa?F5Z``W)#7{1g<%E3Es+o0)fp83-W)V>@(s+?aXY%W#3Du;k1u+&HlSm4EKS zvM;8liTM*FUa>3B#0zsEMYbcdAd~oW4i*p=s^Z^`Ljz&(Vu)4-RqFfK`RDJ>4kwBk zq*iPA?0m>5C+%q0$)`Rn8)eaew{x|3R$YyB%xao#Q1{2EAcx?yYr|R(!i2-)_#_#+lJXEP?&e z1$Joxo@r4-!+7k*pisveWUfjzuhXb(KEH-?_}Mh;JmH65?@qxG3-vIb4pWQhBJgXb zu7k2t&4;~V<&yFdS7jSxreNYyNFJ5Yr=eK@qJ{rZwO9O<7+uwJ;1nZ_Wxc@tt6`r- zEV!`B?hF;Ar>TE|R@hP+8^KKY6gZXhnr#(4y#FzqL0|mKaLjJPScu*E(05WD;T*-%$y;S~K5NcOq>2iRjL*UP+rNJj;=R)); zy|sb7@tKm!#VbpRaer2GC`3u?1jfwcRm$#O7Rjrh_)r?_FdMn~o zRKjUH%}zu@9o>KIFyY`eczn-pibP$<=vQpbL0~$Fdo~f}5Yxo^5t)aPoM1W@oy=Kg zIVnS3cr$l7R-+?PN@xw3WZOPTUCLpwtiP!fEp&dR*e9~;y) zqvpzQSUx$z0!C2s$b&I_`jFG*dEb9+Db7X z!!OPb#;$1o$t!^DNq^rr5QtCPfrfa~mX9QZlOIx^^WQyqOQ!F3*m#zWL1O(R3lF?W z)79oTzr3v!8HyZ`w=&u}l1F=kGcB@2c(=bsrcuyE0hx9>()77e=n^kyA=trIN;Gfw zT5nr=B}I=MLl$VPF|NWJj6N@M<~ODucHCC2N_LqUT?2-Ml5QnIFCMeAbuD>1N`gWM zmPQWFZVUsAUW`?zT6V{%S5GdTXq-JB$;GfK+0ssxZfxTWn9NOO7(@X$%l$x8&lpDmy zy25LwOcb63jOE^{@eJZVrRXQ2N zw=|(Rkl9CqgF>WOo%#DA0kN5u!H4LI-NA)z^O3?-4!A*S;pMS`iqPf@tAQUrm{2+k zg`pQSbiE0_P&zNF9hf9;LY`*lH;I8iztx}JvX^tOQCfZx{EL|wrSUFh)jQ*g{pBaH zLcEVe|IiZ;rfPT$3JB!>hoTUHVBa`MfPwUh#0Wmf(8({7!mCF5SFuVz9XA~77bAax zNXt?iq8rdxKYdL{x0FnNlwrk=xIs2Zt2nhTS)db`75kZv;C-V6qrd_U)6UYutM4v_ z&~q-v_UqCTMEM*h!V{8%0!O+RGlQ`6Cy^RDlI5;!l_w@p*#txxal1iTi6LA7sB|y< zmdubQBdd-*C;V8_`Gd2E6cwSwxW6I>8SZRcArJ0>I}`~TdE!9W%MdonO64&cFvs8d zP_@XgU$J5uOzGKj0rwx4$*m_ew~Yyt?-LUU`0?J-v-6ur=olum(~ztcz#&4>b`wgY z;Qz?x>w#LEA%be{MUkHdk2XdDKq9uDHL8F0rR}D=eGI?tORj7Ud9oO#V$bD+mJOqo zi5E#iAJ;HR<`gbo&j>r7Y5|llg+5b|HX6In9!KL4een3j@9Ph$yV5_v#L=7R-Nzv~ z<14rtZwGN@XtX&%rSzFMFHuy6rEx*8zV}P2O-Wjs4`Su-?sT*XInOuzVl4cO-X~4| z`r`lP50GjSA^Vdhq$Z4qfE+OQT@ob;{c63w-Z4PY%R18_uaf21f}eym`Z|^hoCDjx@lzsB@6+A0$-nLGhM3ppO#bVBcx*2HXs;y<~G0v>L}evT>?4o zRyXHizZ9PHGXF$qjtqg0ut9^I?d)h!@IuiiOpTRf8%!m_&7EKuKuSjT;LbXxhoW_% zB?1=`EV#j~N`0eL*VF*@9MAo{3&nS~mv|RBEbBbU-u)&$39KQN5Q)`D0hU!5A_U8M z4FC`(Ed}+7jA4h$BVcr48W=yMdr8h+{wYqANo+sdChG&=OJ8x$b1tDpx7jyj44#gg zdgLcdMWXfuaFtp@Io;D^Ifpw zt@XuRrF7_49CIs5_%#0&s~2s0=*2SL?RR1yONz9^2vVPQBtVMi!Th~y`5}w#c9e>S z2J_JA`4sZ|Zh;d;2;O2dBZG~qO!KG|5?U|TmrK<5eD2D4t!SRZjsir#V>((RA&Pe= z;*gv$KY0ta88{sX%UB3`*Z0*xf<-w2jVHksl`JMlMr%yI$Fc=;t;Zf+WwE$0G9Jfm z*pd6$G9{bt1fY;2(a6cMz=*XE5%pH6%`GW>9}Q(9yfdP}m4_`*JZBCJi-%-rfG;b0 zbGu8iFHO@}<0gCV+DmFypp~nk(DKzz_R`>&=GVf?vypa4J!krxV>osAd;lcII*|Uz zY}1LP2EDWrPp7&dxZKzjkA4ym6BBsN?VYURgkGux5M{8Rs_PbrUO#!hT%rfpt|}+- ztTKeso$k*RQh_mpGq#qb?Fz0-(Z-{3rNeR1;kfsPo-{M0Y#THV3uE>+8DVsF zBv!S6Wa7dq+70tN!|mln_LTG%aEQ=F-t+X24)bXzk@mz$Jq-zU!5{dktE_dBQLszp z5vw{kZ?E612rOTnAf}rc#?Fw4FnVWkyDt9O@6M!#Z_oNvJ%obtB~>(~M2p=30_m^8 zVzrj6H)g_&9eXvtfvl@hDor%$1?{G-j;6(ckb0%Uff$^^SZfH`Wd7tT)p?gim#jX& z0D>o^-cX+Ie8n=ItxyS5cwP-XAUbkMch=^fUQ;a)iu1RQRG7|XnHFeNKxz?Hsy1A4 zu-vvPE*ih71Be_n)10bh)2cP1P#du@9}~_gu>Y>wX6aR8qA61pm58fh>+MmET2cf= z_1<{-5!q@+^}(<%;!Z#JO(HhH*snjWGKg(O^y_2mdJz{DR3)0ukmFdy@Lan?s=gcw zCu5Q~yiC!W@_|dcbDSiXXg?`NDb}I8Ua@;v7T+E=9-O8PY22K|IrZGX4v7A|thd-v zy+MSZTa$Vsr9XBNLd#sst@|cE$J!jA(VZ#o-m%_Sha!nBhMz=lm8zXiygJgbC;(i8 z;gsF)tBEzG?aj1keSyfb)2vmrpfz%xjwxmD=I#18%3Ow0%OM&LZg&mnWx$?5mXo>o z_D#7ja>*~0aDwDDxSzLtlJQ4T*|^)={_j&Rt;Zi(Ef?_1YN%NaEuS3KE#3o)4j-L8 z-fUILO4u(V!gRD4F|Sk$5_3}F`}RlK96#+#)zYC3g+#c|g4@x^Ts5C}Y5E*R7Af`Yy>n}v#B^e8Fg zJV*7CNnTIQgH6eU;i{^+`^)#R#gH;$NB@gC^~9vPMRwqt?%V~>F8&kH@tNYt&*1_i6_D|9I|o%T7#-uTdLR$P3GR9 zpg8jubh`TIOxE@d)f9*Xjf&^Pec>rG!^AO`?1G zrG2EsFi>a#B_{HJCD(;unP$|o^}m+a?<&5@l>2NNT(3f4QXxeAK6*;F8}_5BXGl4h zs0jw)=S}{=j7Z{s+~wl!r)58?!;eDzv>g2&<)BU>*ZY9<=**? z=dU-$onTj@F)89mgr`#SPWJn|+K4Sr5-j!L)w~prurIYwwKqpZZFX%+sSORxg%2Nl zv(8KqsJfKpDIbqM65qh;UKgf zI`Mh^JfVa3&@Hb4QYym94%a5g7b1)-VRp4k>Lwp3bAHc+D8#2IS4Ri&$|9{yr06g4= zD{;8$w1B_21?HZ$cPjfQ4En&kdu$a3G2XO1<^a1x*&nq}@t?aLT9L=wjH{NR0RR1)Ilo1Ms1gK% z&?t=sl@sx~36XNO&D8bye5W}5y*l|fR#5^Jp?U-d~KBUKI9vXgfmC&{Xrx zC)?OXmtYM&J^P@-I?dk4v5OA3lwsY5v>yGoe+* z_`4`%9{x`Q@RWqr0tXcYii8ESG5}w#drsSp`aPAFO&gmCj!2K9q4`n<-sxIkUjj<9L={ReXFfRwv}+Sp{gE$wWTE za>Yb1#owA;Efbvbdld0K-Nrzbn|P)`4~<`yBKmBIo78o`Dq$qTzm3Fl1P{>LA}U3D z^3tIEQnxPIkCQ>j{p&e~JNi2cJniZ~Qd;DPrKd_&C2X~Y#XrKlt$oun*@MT>0?LD3 z4Y60#o1)_6Y<`qnG?%cGaV@4tz@?{fM6Fc?h~oPnYpShp$zsIYkrp3Q1h4RjK?wWT zt*9aDSyYyU6d4+F@_2a$PC)mKEfYIt#PoKL8X;qB8Kiv15xE{$SR;YfY`+pF_lvg2 zKmvL2r8q8)4UX~N0Hr-rr+cGxc|UC~H^q?b=)p4IoeNMuFTh%r7^R(c8Awj%7U5;V zNf>vtknhq>HA$iI?a=4y%!u!>HN_$jkRxn}IR56_L$4Dv%{!ho35YJvcak^WlX-4* zmd#-%ya2)@s<0iC8hPcjHp|nt=FW6-TS&5c*Pr_(9oEFuJWG~-;@X76fg_?&QEo-@ z(TOW)b@6_|{AHhG7fz1St~lbx*+2Va^>)+rO7H>xuwL@%dy>}qhXETw(M>>@YCPsn z;CH)-*}L`K)o^K=Twuqu4RK%X@yxM2LQ6r1t7xB!CTZY>U%&2MO%WH{B!bBW?}AeS zQabUrXpRfKf|Gl?E?mb}X#|^#@apUrtM!v>4&BY8Xh&yx9C)uXTb9`U+-DyzgELjK z{>zdeUwSqsTSd#7(z@_-SG^UFk9cfHj)b+>7{*K_La!JuB!Q@g3o7AbEMwc+r|T*9 zi$7YG$|q;H6>Si9W0VpD3hwx?owqaI0pETz2Z%z<4viXk=v~J@neG1 z?Hsrj60TXu>z)g?IB3omxkl6^p}$v|bin@+G69599iX%K>0(_ml^ORNPWTpUVo`dK zFqb>rpLYWX`lPyVyY8gD@BUqyU`6Z`|2!Jl3#ioJxd|%#|C;AFQ2xI=JRH<03NSSe zPWpceSi)|vpeG0f3i&f=|BU~B(XccQuD>?_R=EGQ0D*X6UpW{V{_*o)Z3O}m{9hB$ zHa?7jllE_D8BS^xc9;bx<6ji^2l>F>aWec3@=qn@`Xi$)z#tIezZ|@REpsybJ#qi% z#5|0Oi~cW?;G#xxftheI{Y4>v5DP4ei{&rs{)4<=D_o3!egAI(`6K@R?OPm1!~GxM T(%jT2elT + - Register description -
-

Register description

+
+

example

Registers

diff --git a/example/output/example.md b/example/output/example.md index c4ec3a7..557b8b6 100644 --- a/example/output/example.md +++ b/example/output/example.md @@ -1,5 +1,5 @@ -# Register description +# example ## Registers diff --git a/example/output/example.rst b/example/output/example.rst index 5ecc964..c993e4c 100644 --- a/example/output/example.rst +++ b/example/output/example.rst @@ -1,6 +1,6 @@ -==================== -Register description -==================== +======= +example +======= Registers --------- diff --git a/example/output/example.rtf b/example/output/example.rtf index 485086f..5230f4d 100644 --- a/example/output/example.rtf +++ b/example/output/example.rtf @@ -2,7 +2,7 @@ {\colortbl;\red255\green0\blue0;\red0\green0\blue255;} \widowctrl\hyphauto -{\pard \qc \f0 \sa180 \li0 \fi0 \b \fs36 Register description\par} +{\pard \qc \f0 \sa180 \li0 \fi0 \b \fs36 example\par} {\pard \ql \f0 \sa180 \li0 \fi0 \par} {\pard \ql \f0 \sa180 \li0 \fi0 \b \fs36 Registers\par} { diff --git a/example/output_default/example.md b/example/output_default/example.md index c4ec3a7..557b8b6 100644 --- a/example/output_default/example.md +++ b/example/output_default/example.md @@ -1,5 +1,5 @@ -# Register description +# example ## Registers diff --git a/example/output_default/example.rst b/example/output_default/example.rst index 5ecc964..c993e4c 100644 --- a/example/output_default/example.rst +++ b/example/output_default/example.rst @@ -1,6 +1,6 @@ -==================== -Register description -==================== +======= +example +======= Registers --------- diff --git a/example/output_no_default/example.md b/example/output_no_default/example.md index 36a2c2f..a01a13b 100644 --- a/example/output_no_default/example.md +++ b/example/output_no_default/example.md @@ -1,5 +1,5 @@ -# Register description +# example ## Registers diff --git a/example/output_no_default/example.rst b/example/output_no_default/example.rst index cc60707..da75e53 100644 --- a/example/output_no_default/example.rst +++ b/example/output_no_default/example.rst @@ -1,6 +1,6 @@ -==================== -Register description -==================== +======= +example +======= Registers --------- From 6568cfc5a3d4dd9f5cca709acbb668b7496dd449 Mon Sep 17 00:00:00 2001 From: Jan Vermaete Date: Thu, 18 May 2023 20:29:35 +0200 Subject: [PATCH 06/11] Add the base address of the registers in the generated documentation Signed-off-by: Jan Vermaete --- ipxact2systemverilog/ipxact2hdlCommon.py | 28 ++++++++++++++++++------ 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/ipxact2systemverilog/ipxact2hdlCommon.py b/ipxact2systemverilog/ipxact2hdlCommon.py index ae340ea..8563386 100644 --- a/ipxact2systemverilog/ipxact2hdlCommon.py +++ b/ipxact2systemverilog/ipxact2hdlCommon.py @@ -91,8 +91,9 @@ def addAddressBlock(self, addressBlock): class addressBlockClass(): - def __init__(self, name, addrWidth, dataWidth): + def __init__(self, name, baseAddress, addrWidth, dataWidth): self.name = name + self.baseAddress = baseAddress self.addrWidth = addrWidth self.dataWidth = dataWidth self.registerList = [] @@ -171,8 +172,9 @@ def compareLists(self, list1, list2): class rstAddressBlock(addressBlockClass): """Generates a ReStructuredText file from a IP-XACT register description""" - def __init__(self, name, addrWidth, dataWidth, config): + def __init__(self, name, baseAddress, addrWidth, dataWidth, config): self.name = name + self.baseAddress = baseAddress self.addrWidth = addrWidth self.dataWidth = dataWidth self.registerList = [] @@ -197,6 +199,8 @@ def returnAsString(self): r.title(self.name) # Use the name of the addressBlock as title r.newline() + r.field("Base Address", hex(self.baseAddress)) + r.newline() r.h2("Registers") summary_table = [] @@ -265,8 +269,9 @@ def returnAsString(self): class mdAddressBlock(addressBlockClass): """Generates a Markdown file from a IP-XACT register description""" - def __init__(self, name, addrWidth, dataWidth, config): + def __init__(self, name, baseAddress, addrWidth, dataWidth, config): self.name = name + self.baseAddress = baseAddress self.addrWidth = addrWidth self.dataWidth = dataWidth self.registerList = [] @@ -290,6 +295,8 @@ def returnAsString(self): regDescrList = [reg.desc for reg in self.registerList] self.mdFile.new_header(level=1, title=self.name) # Use the name of the addressBlock as title + self.mdFile.new_paragraph(f"Base Address: {self.baseAddress:#x}") + self.mdFile.new_paragraph() self.mdFile.new_header(level=2, title="Registers") # summary @@ -367,8 +374,9 @@ def returnMdRegDesc(self, name, address, size, resetValue, desc, access): class vhdlAddressBlock(addressBlockClass): """Generates a vhdl file from a IP-XACT register description""" - def __init__(self, name, addrWidth, dataWidth, config): + def __init__(self, name, baseAddress, addrWidth, dataWidth, config): self.name = name + self.baseAddress = baseAddress self.addrWidth = addrWidth self.dataWidth = dataWidth self.registerList = [] @@ -742,8 +750,9 @@ def returnPkgBodyString(self): class systemVerilogAddressBlock(addressBlockClass): - def __init__(self, name, addrWidth, dataWidth, config): + def __init__(self, name, baseAddress, addrWidth, dataWidth, config): self.name = name + self.baseAddress = baseAddress self.addrWidth = addrWidth self.dataWidth = dataWidth self.registerList = [] @@ -900,8 +909,9 @@ def returnAsString(self): class cAddressBlock(addressBlockClass): - def __init__(self, name, addrWidth, dataWidth, config): + def __init__(self, name, baseAddress, addrWidth, dataWidth, config): self.name = name + self.baseAddress = baseAddress self.addrWidth = addrWidth self.dataWidth = dataWidth self.registerList = [] @@ -1036,7 +1046,10 @@ def returnDocument(self): nbrOfAddresses = int(addressBlock.find(spiritString + "range").text, 0) # TODO, this is wrong addrWidth = int(math.ceil((math.log(baseAddress + nbrOfAddresses, 2)))) dataWidth = int(addressBlock.find(spiritString + "width").text, 0) - a = addressBlockClass(addressBlockName, addrWidth, dataWidth) + a = addressBlockClass(addressBlockName, + baseAddress, + addrWidth, + dataWidth) for registerElem in registerList: regName = registerElem.find(spiritString + "name").text reset = registerElem.find(spiritString + "reset") @@ -1145,6 +1158,7 @@ def generate(self, generatorClass, document): blockName = addressBlock.name block = generatorClass(addressBlock.name, + addressBlock.baseAddress, addressBlock.addrWidth, addressBlock.dataWidth, self.config, From 97eca86372174f90e3757582fa55c0cc0343e468 Mon Sep 17 00:00:00 2001 From: Jan Vermaete Date: Thu, 18 May 2023 20:30:20 +0200 Subject: [PATCH 07/11] Update of the golden reference Signed-off-by: Jan Vermaete --- example/output/example.docx | Bin 11644 -> 11644 bytes example/output/example.html | 6 +++++- example/output/example.md | 4 ++++ example/output/example.rst | 2 ++ example/output_default/example.md | 4 ++++ example/output_default/example.rst | 2 ++ example/output_no_default/example.md | 4 ++++ example/output_no_default/example.rst | 2 ++ 8 files changed, 23 insertions(+), 1 deletion(-) diff --git a/example/output/example.docx b/example/output/example.docx index 916ab4cd19d00c181a48b3224d55bb86b07ceace..4f580a0d1d2a1dbf47b1f51654ba8e7284a7248d 100644 GIT binary patch delta 563 zcmewp^(Traz?+#xgn@~JgTZ>jMxF(XOx6=NuVWMh(+8PmbAb49-1Z>;%{jXhMJ*^}=({Trs{!QGQ``~T15QpodYmeX6SkK!UtN(4;**XQ6w{PZbSfnBu@p8(x z*_M^@x}PN@P0F`^iP^=l{$M4?3dOX{b8dQn=i~_5E;l))DCd(Crq|6DZ4mMZ);<}S%+33z^`q{Uk~cD@ zk`4>FeecV4m#nn5DA8LnW6J7RTW%a^Iu)c~cf?*>{_5k)S)Q{z4J=oFDw?(VX4lz@ zlRv)vdtGtn>Yt+*mMo8bU2idux9!OF`HOzCB1gdHe^L{`Aw5B6Cn%)7Wxd!y^mOHu z;1EtyHDLxt#0-sdASy%C9z?CwGzU?SG;KkYqLv4U%GUA(QQNfaK-4!aYY=6u4dxYV l+als=hc;OEM{OIB3Vj{0kp()AAl_yju=>wBV3Un>y#OF{>FEFf delta 563 zcmewp^(Traz?+#xgn@~JgF&QoBhLaxCXvp~>lg*W^g*WC93Xxiw>^kIc|Oky5Z9CU zGFV!U-yAF*F75&5FO=Y5%{LPelM6K6?LLE zW-awvnss$9kA=eI9AU8msk_D#uO&% zffr83TaGKmzG5re%dMsMbdi-_S%PD#rhxqsdrkSt$Cp2CG7&Xct!BCV^y!zIY98dA z%D;L2-;C~`n-_Ze@4ocEz(!I=D88=inK*I;Z2l)T0UXj3WOjl=+FRC(4Ma~@J_!!t zBvlh;P(;koI0vFKH0?puN=KD jo_1)1b$`^h0jbc}0UKGM;|Sty)&Z;ktOGXLNY@Jhp+Men diff --git a/example/output/example.html b/example/output/example.html index 44fc01d..91a42e1 100644 --- a/example/output/example.html +++ b/example/output/example.html @@ -606,7 +606,11 @@

example

- +
+
Base Address:
+

0x0

+
+

Registers

diff --git a/example/output/example.md b/example/output/example.md index 557b8b6..3765692 100644 --- a/example/output/example.md +++ b/example/output/example.md @@ -1,6 +1,10 @@ # example + +Base Address: 0x0 + + ## Registers |Address|Register Name|Description| diff --git a/example/output/example.rst b/example/output/example.rst index c993e4c..3a458f0 100644 --- a/example/output/example.rst +++ b/example/output/example.rst @@ -2,6 +2,8 @@ example ======= +:Base Address: 0x0 + Registers --------- diff --git a/example/output_default/example.md b/example/output_default/example.md index 557b8b6..3765692 100644 --- a/example/output_default/example.md +++ b/example/output_default/example.md @@ -1,6 +1,10 @@ # example + +Base Address: 0x0 + + ## Registers |Address|Register Name|Description| diff --git a/example/output_default/example.rst b/example/output_default/example.rst index c993e4c..3a458f0 100644 --- a/example/output_default/example.rst +++ b/example/output_default/example.rst @@ -2,6 +2,8 @@ example ======= +:Base Address: 0x0 + Registers --------- diff --git a/example/output_no_default/example.md b/example/output_no_default/example.md index a01a13b..72e3ba9 100644 --- a/example/output_no_default/example.md +++ b/example/output_no_default/example.md @@ -1,6 +1,10 @@ # example + +Base Address: 0x0 + + ## Registers |Address|Register Name|Description| diff --git a/example/output_no_default/example.rst b/example/output_no_default/example.rst index da75e53..528787b 100644 --- a/example/output_no_default/example.rst +++ b/example/output_no_default/example.rst @@ -2,6 +2,8 @@ example ======= +:Base Address: 0x0 + Registers --------- From 2f2536bc93a87c7b6a96b6eefc2389f5bf5e3a45 Mon Sep 17 00:00:00 2001 From: Jan Vermaete Date: Thu, 18 May 2023 21:46:20 +0200 Subject: [PATCH 08/11] Adding description of an addressBlock. Added the description into the test xml file. Added it to the generated MarkDown and restructuredText files. Signed-off-by: Jan Vermaete --- example/input/test.xml | 1 + ipxact2systemverilog/ipxact2hdlCommon.py | 24 ++++++++++++++++++------ 2 files changed, 19 insertions(+), 6 deletions(-) diff --git a/example/input/test.xml b/example/input/test.xml index 91168ba..a8bd687 100644 --- a/example/input/test.xml +++ b/example/input/test.xml @@ -12,6 +12,7 @@ unusedMemoryMapName example + Demo example used for the testing of the ipxact2systemverilog tool. 0 6 32 diff --git a/ipxact2systemverilog/ipxact2hdlCommon.py b/ipxact2systemverilog/ipxact2hdlCommon.py index 8563386..a4431ef 100644 --- a/ipxact2systemverilog/ipxact2hdlCommon.py +++ b/ipxact2systemverilog/ipxact2hdlCommon.py @@ -91,8 +91,9 @@ def addAddressBlock(self, addressBlock): class addressBlockClass(): - def __init__(self, name, baseAddress, addrWidth, dataWidth): + def __init__(self, name, description, baseAddress, addrWidth, dataWidth): self.name = name + self.description = description self.baseAddress = baseAddress self.addrWidth = addrWidth self.dataWidth = dataWidth @@ -172,8 +173,9 @@ def compareLists(self, list1, list2): class rstAddressBlock(addressBlockClass): """Generates a ReStructuredText file from a IP-XACT register description""" - def __init__(self, name, baseAddress, addrWidth, dataWidth, config): + def __init__(self, name, description, baseAddress, addrWidth, dataWidth, config): self.name = name + self.description = description self.baseAddress = baseAddress self.addrWidth = addrWidth self.dataWidth = dataWidth @@ -199,6 +201,8 @@ def returnAsString(self): r.title(self.name) # Use the name of the addressBlock as title r.newline() + r.content(self.description) + r.newline() r.field("Base Address", hex(self.baseAddress)) r.newline() r.h2("Registers") @@ -269,8 +273,9 @@ def returnAsString(self): class mdAddressBlock(addressBlockClass): """Generates a Markdown file from a IP-XACT register description""" - def __init__(self, name, baseAddress, addrWidth, dataWidth, config): + def __init__(self, name, description, baseAddress, addrWidth, dataWidth, config): self.name = name + self.description = description self.baseAddress = baseAddress self.addrWidth = addrWidth self.dataWidth = dataWidth @@ -295,6 +300,7 @@ def returnAsString(self): regDescrList = [reg.desc for reg in self.registerList] self.mdFile.new_header(level=1, title=self.name) # Use the name of the addressBlock as title + self.mdFile.new_paragraph(self.description) self.mdFile.new_paragraph(f"Base Address: {self.baseAddress:#x}") self.mdFile.new_paragraph() self.mdFile.new_header(level=2, title="Registers") @@ -374,8 +380,9 @@ def returnMdRegDesc(self, name, address, size, resetValue, desc, access): class vhdlAddressBlock(addressBlockClass): """Generates a vhdl file from a IP-XACT register description""" - def __init__(self, name, baseAddress, addrWidth, dataWidth, config): + def __init__(self, name, description, baseAddress, addrWidth, dataWidth, config): self.name = name + self.description = description self.baseAddress = baseAddress self.addrWidth = addrWidth self.dataWidth = dataWidth @@ -750,8 +757,9 @@ def returnPkgBodyString(self): class systemVerilogAddressBlock(addressBlockClass): - def __init__(self, name, baseAddress, addrWidth, dataWidth, config): + def __init__(self, name, description, baseAddress, addrWidth, dataWidth, config): self.name = name + self.description = description self.baseAddress = baseAddress self.addrWidth = addrWidth self.dataWidth = dataWidth @@ -909,8 +917,9 @@ def returnAsString(self): class cAddressBlock(addressBlockClass): - def __init__(self, name, baseAddress, addrWidth, dataWidth, config): + def __init__(self, name, description, baseAddress, addrWidth, dataWidth, config): self.name = name + self.description = description self.baseAddress = baseAddress self.addrWidth = addrWidth self.dataWidth = dataWidth @@ -1040,6 +1049,7 @@ def returnDocument(self): addressBlockList = memoryMap.findall(spiritString + "addressBlock") m = memoryMapClass(memoryMapName) for addressBlock in addressBlockList: + description = addressBlock.find(spiritString + "description").text addressBlockName = addressBlock.find(spiritString + "name").text registerList = addressBlock.findall(spiritString + "register") baseAddress = int(addressBlock.find(spiritString + "baseAddress").text, 0) @@ -1047,6 +1057,7 @@ def returnDocument(self): addrWidth = int(math.ceil((math.log(baseAddress + nbrOfAddresses, 2)))) dataWidth = int(addressBlock.find(spiritString + "width").text, 0) a = addressBlockClass(addressBlockName, + description, baseAddress, addrWidth, dataWidth) @@ -1158,6 +1169,7 @@ def generate(self, generatorClass, document): blockName = addressBlock.name block = generatorClass(addressBlock.name, + addressBlock.description, addressBlock.baseAddress, addressBlock.addrWidth, addressBlock.dataWidth, From 8d1635017a65debe22aae42e747a350acc630979 Mon Sep 17 00:00:00 2001 From: Jan Vermaete Date: Thu, 18 May 2023 21:48:05 +0200 Subject: [PATCH 09/11] Update of the golden reference Signed-off-by: Jan Vermaete --- example/output/example.docx | Bin 11644 -> 11715 bytes example/output/example.html | 8 +++++--- example/output/example.md | 2 ++ example/output/example.rst | 2 ++ example/output/example.rtf | 3 +++ example/output_default/example.md | 2 ++ example/output_default/example.rst | 2 ++ example/output_no_default/example.md | 2 ++ example/output_no_default/example.rst | 2 ++ 9 files changed, 20 insertions(+), 3 deletions(-) diff --git a/example/output/example.docx b/example/output/example.docx index 4f580a0d1d2a1dbf47b1f51654ba8e7284a7248d..2a48affd0ae6f352daf98e26e640d3e6bf5bbeb0 100644 GIT binary patch delta 3135 zcmZWr2{e@Z8=j>sVTQ6Bj3wKUB~eTpY zj3Q)&Y@vy)S<=Oo{-%5W=iKi9JLfy^dEW2+-uHQ*-*>+A>|Mt`jv+==!-)h!^?k}EyY zP_P)Hh91A*u@{Td2mz|cw9egr*};}Sl?yovB_N`V zkLe7GI%rVy{^y-Xf4wXEsPj?D@T+)Cq`)G-+B30l>?DDmVzH@oKRr;i8v7NINW-&+ zz;BC$0N=#(34??U+;IuNqk_3AoY!IswJoHtX>4%P#63UYL#e3cM)wX{H7G)+v;TB^ zHZH!{m)i&Lt&PfAxV?7CVPzR(8(!${##?fx>Gb{b@+Oa@{kscQh{E%lW&*D*Q(t^C z?5$H-vd6hfX}x<9=kA;VZoTWbG5tdBIXpdxFsf6glO`sYVcRp_MT75d9hFTA@L15} zUL3f6Q)h3DJ3H$_1YYw)xzU024E@zhmDwM1FI5tEgwn)jQf7~yx@SdX2IUyD2=9_I`1H&Q7Re%tes}S2~%p9t)7Tp7F+f|8Z3twtby*^fck9^O{ z{o$wh&e1ibk3>Wy zbn3SXHjxtt#2vjpEwIyj?U_d@I;?O)9@HYslM$ z=4btB6PfRl<&~Wt{S+0Lmc+7Z5@WJerNHN!q{}S{J+9rxMZdWfxhxazWgC4CaBEUo zjxmA?^ccjLuXrVkwV)QCi4Y!)w9NLv`)N1>)^9Aw8ePmQY7*uS6DW&!z}7goab>wO zW`Z=0;;}n+Rzk%M z2=JybmoooK>RCu+$bd)!8KNpt96NWWb-ycE=dglCAR#r!KBy)bM;V=52>TY)RGPh@ z@J*=YjT*bvNrLjRy4vL~*OU{Po~_ipPH8@RRX47&Tsk+8?s$*wkA_-qi{7BKY3u@$PRDr=5}8oNVYcTqw9|G zxi+8mSEM#uW0ixS|>P=_uN%Yn>%ldacA?$K#62I;gbPZ4(TzG_cw}QrdKCBVI~OYu)%p zNX)fAo>s{;8{d2nX8{o}u`_$^rrFZWfol~UH4S8tP5+p=yeFEmwz zk__a7=Lx%&QFcs}^N=y8Gd{|y+h||N}ndJq0@AAYS3@69Iu*QoMTMNbg>toc( z_R`g*SZ{5Usiv6m>0F!mr_h|I;ll55`dOz3P@Xs0#xHvoW|#FPnV0*_$FU8d@DQ-3 z9Ug+jL-P6!I4ATEPD}}# zj9PxArKf5^`a`=S+k86Fx7sY<&Kgrqu9ZbX1~BKyV_XB4X;W(Suotlj=L(>CZa3Z# zd^Fj#YkhAF>TL_YjEUWTe>JXku7rYL2h7nNxx{%y=9<^9KN7x{G+bc{&ma%0ynYwM ze%Y5{2-C^o<*B;3=4>7_T zI1`pE%h5?Znu<({cpaQGvITpiY=(=3Yyl%6)!8mCe=H2<+C)b{%GP1E{lU+7PJUrM zZD}J!LX8{N*#>kaTX>}m`To@qasS}wS@m9A-Rh$%$tRL9;n~5-L~=)QQw}TP`+WbC zvA3?C(-+pC$TdN+=l?8z;m$&jw&(1LzPgGJ`mv@TZp$7vB_k+uopa0ZMYCH=uC0B8 zTG0S)Ypz}{Gu)`;D2Cr-*RY35$`A;STfePNQ~aKn*1Vhci`QW%9H;~Ij}ngWS57-M1t0Jx89Hy2BXxtzmOd+;!0e-^ z2ExEIX4RsSbwxU%I2#vKFr|HRTeWlEq48-4kAvg&iILhMt7}iAY$~qai&uq=IPw(E z$BFcsn0^Os74Q{MBJh@l>DlJile_~OHZJxX4A#)bHgJ61lr@qccTvq*-=|Z|dWe{5a?PDVw z!_L>n?>!XA2D9%&TUp2q{HiB3s#2gK1p>(my z)L;p*2K7GKoBYCh#He=6T|R2qYXOd22k0JSR_C97r{0-EhiQ0-MVu8(--G6&|MEX# zP)#-_wi7V=g^LB*fNV@Z#CDN*lSmOl5ZLAU8uiXL%nchqG=5*D+3Or{urGCU;^oAs zG`H^D$fva^?ZQSUrLg8JG3~6LZ}WLErpHw}j6L(t?b<8Rg)qb64{uzyhXzb*tyjRM z1N)E2Oy>J>i#}Gr!{seTHOi5ztr>;6FN!QZAKPU4B0V5p!NSOtDrbE)oSMe)mM3(1 zFUCYoh!~-Yk8-hqm8kKBm?L$s-o`mM!5ceT6CQm*!xo*)rN%;?MjoCQ-V*q>y#2Y= z<&2FCToYvEgl;!?#* zsha_7VybB(YRtln*;226sp@u89ejw1Idc8X;4QDi43+Yl|F)iM@~X@y5(+S2F7bi_ zf(d*TV4!hMVjZVAu|k1UoOw8Q^5vssAOK*&4FDVm{PRjA(iJ2enKjAW5&-59h6e<3u9Ri7cf0k;dg=s hL~fk zjy*OD>!KUgDs*zVw=@^M`|C@YTE()6ufV$$P}HTIYpW;SqGC-FKqtxFPtud?eG2Ax zlfHTb!wIjhrES6-pD4WqL;nS4iTsj2i6@&TPlHrF@HdA7mbHG~4b;nHAoW=MY{_%y zn@Z3uycbiD)AHna_`J!4YGvC{go4>n>a2!TL#j)Y+cNi{rK5K8r963i98aV#&H?4| zFH+x!@TlS_&jk%p`Y3LvrN@8yM;i-b_DV5wF)$q)VMJCN@y!x>P_h7nhT}o;V^K}m z<6*}lnucBCdpuFz=(i+&5w5d|`iBWJiJ^1w&MpWu}IrBjIMN<;l4#UOPqKwFC|19D|ZZ#atY*k zw3=3Q$%2rLjhBjJW6;IM(dVTDPAd-%qe&t^6wPgO;?n90{OqGT75(w4>K_)i+xNNb z8#L22#b^?}6TO5h6|R~eV94@6i%Jwd?mFS_q@`n}4rBFao_npYv|B}9jFk5@~ha^zz z_9Q{Ig0&NNhHasnH)nqZxCkZp_V#S_ycrCa>LoQAv}IpdMFCf&e_!uKzp%G3--p~lc&W~4>)vGu@kqI{ATeUgYb@H9|P)LI>y&-Hs5D2 z)vjcIF81?_o!3Kd@^W3>DxL}{kFfDF2J3>uB~oshS>%8h_{hewo+hzV3-CKv%>LGf z=qE^>?7GvyxT?sK=P~MSyXQQ=XSyr#oV#q?ZmQTU>OTl)&-D6gYG%eY{1k@jRRLF6 zYa6x)WxDEt5FVE7w2m<}uI%he>%2&%t(55yQ<~1c)LMFjPqb2us^i_F!eV_faF5{R z&O(FN1|@k;#}`D1TlU>*bs(rOxpLTuozw`I!67!uHL`BL|>sEPUjez?Ox- z1%IY;*V-H}sp6{t3#IC#?5@_pCjN(AozCaqD41Va$MF#I`gX4F#qtpNY}2xx#}Li3 zjZ*C2TVJMjO#WRvWW{jY(boKIGwMN8?x2Cdm)fuv?B!2;;NkFxtsy53ua&CBf`k-; zeuNt1Sujo=BJ__1;CxDtBT;#ZLi&%_K0yqPSrvo%n%fkE&%uKg>k31jKb;2eKhi&)RSan5`$Yu@@u^4=Wt!f&dNj0>CJwjhJ@sl zt4GBHud>&%>hYw~N%~s2?9`F)p;rfCD=!#5q%enD$I?LBz5=w{#CSl2zMeB=r?<}EUc&~Cb=>VHW0&bRLNdZ!F)%520&E}h^Gwu?#u)p zGuNB_!BFLY@UPy)uLa*QqEl8ZZeg(Y)(cT(+dvd})Z!<*Tw)eIP)tJU;a?2UADMj) z6ohOJ-p-J|9=%WAdX>GAFUe;;%lA$HRjWrER9?rBWSSQwtQPY1Y zo~Vsy3LTu`QJHWU2o*%WeiO(IG;XTS3xWbYH#NggUQ}sSw|WOnXL!FC50c#MmpBBz zT2tS#+m<92&CKDnR;;JTx|x34Sq;HXFMErm>8`d7-vW{EHyV81+bJ7(wH7$ya!Vls z%}m;@a&Ea}n9&;)xhbP&?~{h%O*HG0f-bqw;YLSA?s$g5yHW00?axG;Al5x;B#zW1 z{NnKQH74^U0wbyPO_*U|rGIWE|9jgjLW^IFxIOoqOLQ+cHwZ=<&gxpFO!n{ySSF}) zQD2T{)o$gBav#n!^pivm1&7YAl1U=2RnmlIIa`3!sV+ayg3uuIY8o>UXk)hGn=4vp zJCo;VD~&T-Wq6G!QX8Dqq@w&#b-ZmxkY=1XgI*=MqlBDi5#GOZZ^Snsfb1st*BY!X z8k=utOURbNjm={jD|`xg?Kdt&WG;5tE4!%e!CiE77r|w>E>71D(P)0#L`x@R$-&-gEPKmvA zRiL^GRUKn$;p8s{>Y|J3Y^37i1zAFLHM0Q%Ci^Mj4{OlvVzERX=4nd>@6y^tlTbF!%9koLbZu-=G2^Q^m*uog-;vjxoPD1Kg)c-GYl zab@aL4J=3vP+YaNF2((nR{MWuRFOeacKl>uU|S$jMplUO6c1M3Dc=TxKQtBmxw3GIXgw7;U{Y52pLhNv z%L6U~c;tjB`|5Hqs_pZDgPh=5cH&B6QR->R@l)gcC-vzp0RZGg&d%uI7#pB;Akfii zdEEbVMi&^96Qe{ul7oTM0A9pd37QBP*a2`voaKu|z^KxtfFDvkKo#N~owGD0z`p^` C_be9x diff --git a/example/output/example.html b/example/output/example.html index 91a42e1..fffc8b7 100644 --- a/example/output/example.html +++ b/example/output/example.html @@ -606,9 +606,11 @@

example

-
-
Base Address:
-

0x0

+ +

Demo example used for the testing of the ipxact2systemverilog tool.

+
+
Base Address:
+

0x0

diff --git a/example/output/example.md b/example/output/example.md index 3765692..c060b9c 100644 --- a/example/output/example.md +++ b/example/output/example.md @@ -2,6 +2,8 @@ # example +Demo example used for the testing of the ipxact2systemverilog tool. + Base Address: 0x0 diff --git a/example/output/example.rst b/example/output/example.rst index 3a458f0..86f6269 100644 --- a/example/output/example.rst +++ b/example/output/example.rst @@ -2,6 +2,8 @@ example ======= +Demo example used for the testing of the ipxact2systemverilog tool. + :Base Address: 0x0 Registers diff --git a/example/output/example.rtf b/example/output/example.rtf index 5230f4d..c9980da 100644 --- a/example/output/example.rtf +++ b/example/output/example.rtf @@ -4,6 +4,9 @@ {\pard \qc \f0 \sa180 \li0 \fi0 \b \fs36 example\par} {\pard \ql \f0 \sa180 \li0 \fi0 \par} +{\pard \ql \f0 \sa180 \li0 \fi0 Demo example used for the testing of the ipxact2systemverilog tool.\par} +{\pard \ql \f0 \sa0 \li0 \fi0 Base Address\par} +{\pard \ql \f0 \sa180 \li360 \fi0 0x0\sa180\par} {\pard \ql \f0 \sa180 \li0 \fi0 \b \fs36 Registers\par} { \trowd \trgaph120 diff --git a/example/output_default/example.md b/example/output_default/example.md index 3765692..c060b9c 100644 --- a/example/output_default/example.md +++ b/example/output_default/example.md @@ -2,6 +2,8 @@ # example +Demo example used for the testing of the ipxact2systemverilog tool. + Base Address: 0x0 diff --git a/example/output_default/example.rst b/example/output_default/example.rst index 3a458f0..86f6269 100644 --- a/example/output_default/example.rst +++ b/example/output_default/example.rst @@ -2,6 +2,8 @@ example ======= +Demo example used for the testing of the ipxact2systemverilog tool. + :Base Address: 0x0 Registers diff --git a/example/output_no_default/example.md b/example/output_no_default/example.md index 72e3ba9..a0fc172 100644 --- a/example/output_no_default/example.md +++ b/example/output_no_default/example.md @@ -2,6 +2,8 @@ # example +Demo example used for the testing of the ipxact2systemverilog tool. + Base Address: 0x0 diff --git a/example/output_no_default/example.rst b/example/output_no_default/example.rst index 528787b..3d13a9d 100644 --- a/example/output_no_default/example.rst +++ b/example/output_no_default/example.rst @@ -2,6 +2,8 @@ example ======= +Demo example used for the testing of the ipxact2systemverilog tool. + :Base Address: 0x0 Registers From 6ac8e012e31aa7447a556a24a6fb41603399c29c Mon Sep 17 00:00:00 2001 From: Jan Vermaete Date: Fri, 19 May 2023 19:47:09 +0200 Subject: [PATCH 10/11] If a entry is not in the ini config file -> use the default. Python was trowing an error if a entry was not in the ini file and the ini file was used. Signed-off-by: Jan Vermaete --- bin/ipxact2c | 1 + bin/ipxact2md | 1 + bin/ipxact2rst | 1 + bin/ipxact2systemverilog | 1 + bin/ipxact2vhdl | 1 + 5 files changed, 5 insertions(+) diff --git a/bin/ipxact2c b/bin/ipxact2c index 8853a19..b30c68f 100755 --- a/bin/ipxact2c +++ b/bin/ipxact2c @@ -25,6 +25,7 @@ if __name__ == '__main__': config = configparser.ConfigParser() if args.config: + config.read_dict(DEFAULT_INI) config.read(args.config) else: config.read_dict(DEFAULT_INI) diff --git a/bin/ipxact2md b/bin/ipxact2md index 6c13f97..86f90a7 100755 --- a/bin/ipxact2md +++ b/bin/ipxact2md @@ -23,6 +23,7 @@ if __name__ == '__main__': config = configparser.ConfigParser() if args.config: + config.read_dict(DEFAULT_INI) config.read(args.config) else: config.read_dict(DEFAULT_INI) diff --git a/bin/ipxact2rst b/bin/ipxact2rst index e5bfa7b..a1c1c47 100755 --- a/bin/ipxact2rst +++ b/bin/ipxact2rst @@ -24,6 +24,7 @@ if __name__ == '__main__': config = configparser.ConfigParser() if args.config: + config.read_dict(DEFAULT_INI) config.read(args.config) else: config.read_dict(DEFAULT_INI) diff --git a/bin/ipxact2systemverilog b/bin/ipxact2systemverilog index e6b4c06..d9a09eb 100755 --- a/bin/ipxact2systemverilog +++ b/bin/ipxact2systemverilog @@ -25,6 +25,7 @@ if __name__ == '__main__': config = configparser.ConfigParser() if args.config: + config.read_dict(DEFAULT_INI) config.read(args.config) else: config.read_dict(DEFAULT_INI) diff --git a/bin/ipxact2vhdl b/bin/ipxact2vhdl index 8b48dff..95c9f09 100755 --- a/bin/ipxact2vhdl +++ b/bin/ipxact2vhdl @@ -25,6 +25,7 @@ if __name__ == '__main__': config = configparser.ConfigParser() if args.config: + config.read_dict(DEFAULT_INI) config.read(args.config) else: config.read_dict(DEFAULT_INI) From fe3d9dc142209f2d243962843ca08928fb6d6687 Mon Sep 17 00:00:00 2001 From: wolfgang-blaszczyk <131867480+wolfgang-blaszczyk@users.noreply.github.com> Date: Mon, 22 May 2023 11:30:17 +0200 Subject: [PATCH 11/11] Update ipxact2hdlCommon.py check first whether there is a description for the addressBlock --- ipxact2systemverilog/ipxact2hdlCommon.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/ipxact2systemverilog/ipxact2hdlCommon.py b/ipxact2systemverilog/ipxact2hdlCommon.py index a4431ef..a831073 100644 --- a/ipxact2systemverilog/ipxact2hdlCommon.py +++ b/ipxact2systemverilog/ipxact2hdlCommon.py @@ -1049,6 +1049,11 @@ def returnDocument(self): addressBlockList = memoryMap.findall(spiritString + "addressBlock") m = memoryMapClass(memoryMapName) for addressBlock in addressBlockList: + # check first whether there is a description field + if addressBlock.find(spiritString + "description") != None: + description = addressBlock.find(spiritString + "description").text + else: + description = "" description = addressBlock.find(spiritString + "description").text addressBlockName = addressBlock.find(spiritString + "name").text registerList = addressBlock.findall(spiritString + "register")