From 8fe1d41fd4e4bb0c6855bfeba384225c083cf4d0 Mon Sep 17 00:00:00 2001 From: MiLo Date: Sat, 6 Oct 2012 12:16:34 +0200 Subject: [PATCH 01/17] Add a "local" meta layer with a "my-image" example If you build your own image, this demonstrates how to do that by creating a "scratch" area for your recipes. To help getting started, there's a my-image recipe that demonstrates how to create an image packed with your favorite features. --- .gitignore | 2 ++ Makefile | 3 ++- meta-local/conf/layer.conf | 7 +++++++ meta-local/recipes-local/images/my-image.bb | 19 +++++++++++++++++++ 4 files changed, 30 insertions(+), 1 deletion(-) create mode 100644 meta-local/conf/layer.conf create mode 100644 meta-local/recipes-local/images/my-image.bb diff --git a/.gitignore b/.gitignore index 41e8bfb015..197185e897 100644 --- a/.gitignore +++ b/.gitignore @@ -2,7 +2,9 @@ /.deps/ /meta-*/ !/meta-openpli/ +!/meta-local/ /openembedded-core/ /sources/ *.swp site.conf +bblayers.conf diff --git a/Makefile b/Makefile index b3ff488998..01a478a162 100644 --- a/Makefile +++ b/Makefile @@ -1,6 +1,6 @@ #!/usr/bin/make -f -# MACHINE examples: et5x00 et6x00 et9x00 dm500hd dm800se dm7020hd dm8000 +# MACHINE examples: et4x00 et5x00 et6x00 et9x00 dm500hd dm800se dm7020hd dm8000 xp1000 MACHINE ?= ${subst /,,${subst build-,,${firstword ${dir ${wildcard build-*/}}}}} ifeq "$(MACHINE)" "" @@ -26,6 +26,7 @@ BBLAYERS ?= \ $(CURDIR)/meta-openembedded/meta-oe \ $(CURDIR)/openembedded-core/meta \ $(CURDIR)/meta-openpli \ + $(CURDUR)/meta-local CONFFILES = \ $(TOPDIR)/env.source \ diff --git a/meta-local/conf/layer.conf b/meta-local/conf/layer.conf new file mode 100644 index 0000000000..85f8ded9ac --- /dev/null +++ b/meta-local/conf/layer.conf @@ -0,0 +1,7 @@ +# We have a recipes directory, add to BBFILES +BBFILES += "${LAYERDIR}/recipes-*/*/*.bb ${LAYERDIR}/recipes-*/*/*.bbappend" + +BBFILE_COLLECTIONS += "local-layer" +BBFILE_PATTERN_local-layer := "^${LAYERDIR}/" +BBFILE_PRIORITY_local-layer = "100" + diff --git a/meta-local/recipes-local/images/my-image.bb b/meta-local/recipes-local/images/my-image.bb new file mode 100644 index 0000000000..8638929003 --- /dev/null +++ b/meta-local/recipes-local/images/my-image.bb @@ -0,0 +1,19 @@ +# This recipe bakes an image close to the old MiLo-image +# It also serves as an example of how you can arrange +# for extra components to be preinstalled while remaining +# compatible with the central repository. + +require ../../../meta-openpli/recipes-openpli/images/openpli-enigma2-image.bb + +IMAGE_INSTALL += "enigma2-plugin-softcams-cccam \ + enigma2-plugin-extensions-xmltvimport \ + enigma2-plugin-extensions-autotimer \ + enigma2-plugin-extensions-foreca \ + enigma2-src \ + " + +# To get things in the local feed, like settings +DEPENDS += "\ + enigma2-plugin-settings-henksat-19e-23e-28e \ + " + From cd88c00261b626de95a1dcc334d65a4f691aa930 Mon Sep 17 00:00:00 2001 From: radxnl Date: Sat, 6 Oct 2012 22:48:08 +0200 Subject: [PATCH 02/17] Makefile: fix typo --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 01a478a162..2c9ae28779 100644 --- a/Makefile +++ b/Makefile @@ -26,7 +26,7 @@ BBLAYERS ?= \ $(CURDIR)/meta-openembedded/meta-oe \ $(CURDIR)/openembedded-core/meta \ $(CURDIR)/meta-openpli \ - $(CURDUR)/meta-local + $(CURDIR)/meta-local CONFFILES = \ $(TOPDIR)/env.source \ From ec449e1d57057f9dbe44a9a867d486ef4d62d911 Mon Sep 17 00:00:00 2001 From: pieterg Date: Sun, 7 Oct 2012 16:26:04 +0200 Subject: [PATCH 03/17] opkg: intercept modprobe modprobe is called from the postinst hook, for autoload modules. As a result, modprobe would run before depmod (which is intercepted). Unfortunately, there is no easy way to determine the running order of the interceptors. So simply intercepting modprobe would still cause it to run before depmod, after the installation has completed. Therefore, prepend a 'depmod -a' command to the modprobe interceptor file. This will cause depmod to be run twice (once by the modprobe interceptor, and again by its own interceptor), but this avoids having to rewrite interceptor handling, to force a certain calling order. This will fix the 'FATAL' error messages during installation of autoload modules, and ensures the modules will be loaded right away, no more reboot required. --- meta-openpli/recipes-devtools/opkg/opkg/modprobe | 7 +++++++ meta-openpli/recipes-devtools/opkg/opkg_svn.bbappend | 8 +++++++- 2 files changed, 14 insertions(+), 1 deletion(-) create mode 100644 meta-openpli/recipes-devtools/opkg/opkg/modprobe diff --git a/meta-openpli/recipes-devtools/opkg/opkg/modprobe b/meta-openpli/recipes-devtools/opkg/opkg/modprobe new file mode 100644 index 0000000000..3bc065767b --- /dev/null +++ b/meta-openpli/recipes-devtools/opkg/opkg/modprobe @@ -0,0 +1,7 @@ +#!/bin/sh + +if [ ! -f $OPKG_INTERCEPT_DIR/modprobe ]; then + echo "depmod -a" > $OPKG_INTERCEPT_DIR/modprobe + chmod +x $OPKG_INTERCEPT_DIR/modprobe +fi +echo "modprobe $@" >> $OPKG_INTERCEPT_DIR/modprobe diff --git a/meta-openpli/recipes-devtools/opkg/opkg_svn.bbappend b/meta-openpli/recipes-devtools/opkg/opkg_svn.bbappend index 4f1deb60d4..798c7603b7 100644 --- a/meta-openpli/recipes-devtools/opkg/opkg_svn.bbappend +++ b/meta-openpli/recipes-devtools/opkg/opkg_svn.bbappend @@ -1,7 +1,13 @@ -PRINC = "2" +PRINC = "3" SRC_URI += "file://sanity-check-provides.patch \ file://fix_uname_cache.patch \ + file://modprobe \ " FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" + +do_install_prepend() { + install -d ${D}${datadir}/opkg/intercept + install -m 755 ${WORKDIR}/modprobe ${D}${datadir}/opkg/intercept/ +} From 702913ef03fea56b244b56484a6ed6df7cd766ed Mon Sep 17 00:00:00 2001 From: MiLo Date: Wed, 10 Oct 2012 19:34:56 +0200 Subject: [PATCH 04/17] Linux: Build XFS filesystem as module for all boxes. Some built it internally, some as module, some not at all. This makes them all build the XFS filesystem as a kernel module. --- .../linux/linux-dreambox-3.2/dm500hd/defconfig | 4 ++-- .../linux/linux-dreambox-3.2/dm7020hd/defconfig | 4 ++-- .../linux/linux-dreambox-3.2/dm8000/defconfig | 2 +- .../linux/linux-dreambox-3.2/dm800se/defconfig | 4 ++-- .../recipes-linux/linux/linux-dreambox_3.2.bb | 2 +- .../linux/linux-etxx00/et4x00/defconfig | 6 +++++- .../linux/linux-etxx00/et5x00/defconfig | 6 +++++- .../linux/linux-etxx00/et6x00/defconfig | 6 +++++- .../linux/linux-etxx00/et9x00/defconfig | 13 +++++++++++-- .../recipes-linux/linux/linux-etxx00_3.4.3.bb | 2 +- .../linux/linux-vuduo-3.1.1/vuduo_defconfig | 6 +++++- .../recipes-linux/linux/linux-vuduo_3.1.1.bb | 2 +- .../linux/linux-vusolo-3.1.1/vusolo_defconfig | 6 +++++- .../recipes-linux/linux/linux-vusolo_3.1.1.bb | 2 +- .../linux/linux-vuultimo-3.1.1/vuultimo_defconfig | 6 +++++- .../recipes-linux/linux/linux-vuultimo_3.1.1.bb | 2 +- .../linux/linux-vuuno-3.1.1/vuuno_defconfig | 6 +++++- .../recipes-linux/linux/linux-vuuno_3.1.1.bb | 2 +- .../recipes-linux/linux/linux-xp/xp1000/defconfig | 6 +++++- meta-openpli/recipes-linux/linux/linux-xp_3.5.1.bb | 2 +- 20 files changed, 65 insertions(+), 24 deletions(-) diff --git a/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/dm500hd/defconfig b/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/dm500hd/defconfig index e733843304..ee8e85c386 100644 --- a/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/dm500hd/defconfig +++ b/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/dm500hd/defconfig @@ -2461,10 +2461,10 @@ CONFIG_JFS_FS=m # CONFIG_JFS_SECURITY is not set # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set -CONFIG_XFS_FS=y +CONFIG_XFS_FS=m # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set -# CONFIG_XFS_RT is not set +CONFIG_XFS_RT=y # CONFIG_XFS_DEBUG is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set diff --git a/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/dm7020hd/defconfig b/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/dm7020hd/defconfig index 220aab1b06..31a56fb062 100644 --- a/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/dm7020hd/defconfig +++ b/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/dm7020hd/defconfig @@ -2465,10 +2465,10 @@ CONFIG_JFS_FS=m # CONFIG_JFS_SECURITY is not set # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set -CONFIG_XFS_FS=y +CONFIG_XFS_FS=m # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set -# CONFIG_XFS_RT is not set +CONFIG_XFS_RT=y # CONFIG_XFS_DEBUG is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set diff --git a/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/dm8000/defconfig b/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/dm8000/defconfig index aad96fa153..5606319fd4 100644 --- a/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/dm8000/defconfig +++ b/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/dm8000/defconfig @@ -2478,7 +2478,7 @@ CONFIG_JFS_FS=m CONFIG_XFS_FS=m # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set -# CONFIG_XFS_RT is not set +CONFIG_XFS_RT=m # CONFIG_XFS_DEBUG is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set diff --git a/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/dm800se/defconfig b/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/dm800se/defconfig index 17658bee1a..ad9f42ab00 100644 --- a/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/dm800se/defconfig +++ b/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/dm800se/defconfig @@ -2462,10 +2462,10 @@ CONFIG_JFS_FS=m # CONFIG_JFS_SECURITY is not set # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set -CONFIG_XFS_FS=y +CONFIG_XFS_FS=m # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set -# CONFIG_XFS_RT is not set +CONFIG_XFS_RT=y # CONFIG_XFS_DEBUG is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set diff --git a/meta-openpli/recipes-linux/linux/linux-dreambox_3.2.bb b/meta-openpli/recipes-linux/linux/linux-dreambox_3.2.bb index 4b267b6d0b..6da3896a69 100644 --- a/meta-openpli/recipes-linux/linux/linux-dreambox_3.2.bb +++ b/meta-openpli/recipes-linux/linux/linux-dreambox_3.2.bb @@ -1,4 +1,4 @@ -MACHINE_KERNEL_PR_append = ".${INC_PR}.28" +MACHINE_KERNEL_PR_append = ".${INC_PR}.29" PATCHREV = "b299a6a132d842b074b289b2568eece452d0663c" PATCHLEVEL = "30" diff --git a/meta-openpli/recipes-linux/linux/linux-etxx00/et4x00/defconfig b/meta-openpli/recipes-linux/linux/linux-etxx00/et4x00/defconfig index 2859ba8fff..3f54251dc2 100644 --- a/meta-openpli/recipes-linux/linux/linux-etxx00/et4x00/defconfig +++ b/meta-openpli/recipes-linux/linux/linux-etxx00/et4x00/defconfig @@ -2227,7 +2227,11 @@ CONFIG_JBD=m CONFIG_JBD2=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +CONFIG_XFS_RT=y +# CONFIG_XFS_DEBUG is not set # CONFIG_GFS2_FS is not set # CONFIG_BTRFS_FS is not set # CONFIG_NILFS2_FS is not set diff --git a/meta-openpli/recipes-linux/linux/linux-etxx00/et5x00/defconfig b/meta-openpli/recipes-linux/linux/linux-etxx00/et5x00/defconfig index 93e7a4ed32..12a0ef9dde 100644 --- a/meta-openpli/recipes-linux/linux/linux-etxx00/et5x00/defconfig +++ b/meta-openpli/recipes-linux/linux/linux-etxx00/et5x00/defconfig @@ -2510,7 +2510,11 @@ CONFIG_JBD=m CONFIG_JBD2=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +CONFIG_XFS_RT=y +# CONFIG_XFS_DEBUG is not set # CONFIG_GFS2_FS is not set # CONFIG_BTRFS_FS is not set # CONFIG_NILFS2_FS is not set diff --git a/meta-openpli/recipes-linux/linux/linux-etxx00/et6x00/defconfig b/meta-openpli/recipes-linux/linux/linux-etxx00/et6x00/defconfig index 45b30a7713..c753e41cc0 100644 --- a/meta-openpli/recipes-linux/linux/linux-etxx00/et6x00/defconfig +++ b/meta-openpli/recipes-linux/linux/linux-etxx00/et6x00/defconfig @@ -2510,7 +2510,11 @@ CONFIG_JBD=m CONFIG_JBD2=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +CONFIG_XFS_RT=y +# CONFIG_XFS_DEBUG is not set # CONFIG_GFS2_FS is not set # CONFIG_BTRFS_FS is not set # CONFIG_NILFS2_FS is not set diff --git a/meta-openpli/recipes-linux/linux/linux-etxx00/et9x00/defconfig b/meta-openpli/recipes-linux/linux/linux-etxx00/et9x00/defconfig index 45b30a7713..34001dc049 100644 --- a/meta-openpli/recipes-linux/linux/linux-etxx00/et9x00/defconfig +++ b/meta-openpli/recipes-linux/linux/linux-etxx00/et9x00/defconfig @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/mips 3.4.0 Kernel Configuration +# Linux/mips 3.4.3 Kernel Configuration # CONFIG_MIPS=y @@ -1594,6 +1594,7 @@ CONFIG_MEDIA_TUNER_MXL5007T=m CONFIG_MEDIA_TUNER_MC44S803=m CONFIG_MEDIA_TUNER_MAX2165=m CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_TUA9001=m CONFIG_MEDIA_TUNER_TDA18212=m CONFIG_VIDEO_V4L2=m CONFIG_VIDEOBUF_GEN=m @@ -1823,6 +1824,8 @@ CONFIG_DVB_USB_CINERGY_T2=m CONFIG_DVB_USB_ANYSEE=m CONFIG_DVB_USB_DTV5100=m CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_RTL2832=m CONFIG_DVB_USB_CE6230=m CONFIG_DVB_USB_FRIIO=m CONFIG_DVB_USB_EC168=m @@ -1833,6 +1836,7 @@ CONFIG_DVB_USB_TECHNISAT_USB2=m CONFIG_DVB_USB_IT913X=m CONFIG_DVB_USB_MXL111SF=m CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_A867=m # CONFIG_DVB_TTUSB_BUDGET is not set # CONFIG_DVB_TTUSB_DEC is not set CONFIG_SMS_SIANO_MDTV=m @@ -1953,6 +1957,7 @@ CONFIG_DVB_DIB7000P=m CONFIG_DVB_DIB9000=m CONFIG_DVB_TDA10048=m CONFIG_DVB_AF9013=m +CONFIG_DVB_AF9033=m CONFIG_DVB_EC100=m CONFIG_DVB_HD29L2=m CONFIG_DVB_STV0367=m @@ -2510,7 +2515,11 @@ CONFIG_JBD=m CONFIG_JBD2=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +CONFIG_XFS_RT=y +# CONFIG_XFS_DEBUG is not set # CONFIG_GFS2_FS is not set # CONFIG_BTRFS_FS is not set # CONFIG_NILFS2_FS is not set diff --git a/meta-openpli/recipes-linux/linux/linux-etxx00_3.4.3.bb b/meta-openpli/recipes-linux/linux/linux-etxx00_3.4.3.bb index ba150449d1..e41f4bbfaf 100644 --- a/meta-openpli/recipes-linux/linux/linux-etxx00_3.4.3.bb +++ b/meta-openpli/recipes-linux/linux/linux-etxx00_3.4.3.bb @@ -9,7 +9,7 @@ SRC_URI[sha256sum] = "d81d051e6f702fc4bda0cb6b18db7319ed3b36401a924b682b0b0b94e0 LIC_FILES_CHKSUM = "file://${WORKDIR}/linux-${PV}/COPYING;md5=d7810fab7487fb0aad327b76f1be7cd7" -MACHINE_KERNEL_PR_append = ".8" +MACHINE_KERNEL_PR_append = ".9" # By default, kernel.bbclass modifies package names to allow multiple kernels # to be installed in parallel. We revert this change and rprovide the versioned diff --git a/meta-openpli/recipes-linux/linux/linux-vuduo-3.1.1/vuduo_defconfig b/meta-openpli/recipes-linux/linux/linux-vuduo-3.1.1/vuduo_defconfig index 5de4c04a98..73602bcbc7 100644 --- a/meta-openpli/recipes-linux/linux/linux-vuduo-3.1.1/vuduo_defconfig +++ b/meta-openpli/recipes-linux/linux/linux-vuduo-3.1.1/vuduo_defconfig @@ -2279,7 +2279,11 @@ CONFIG_JBD=y CONFIG_JBD2=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +CONFIG_XFS_RT=y +# CONFIG_XFS_DEBUG is not set # CONFIG_GFS2_FS is not set # CONFIG_BTRFS_FS is not set # CONFIG_NILFS2_FS is not set diff --git a/meta-openpli/recipes-linux/linux/linux-vuduo_3.1.1.bb b/meta-openpli/recipes-linux/linux/linux-vuduo_3.1.1.bb index 960cc1ee0a..b2dafaff1c 100644 --- a/meta-openpli/recipes-linux/linux/linux-vuduo_3.1.1.bb +++ b/meta-openpli/recipes-linux/linux/linux-vuduo_3.1.1.bb @@ -1,6 +1,6 @@ require linux-vuplus-3.1.1.inc -MACHINE_KERNEL_PR_append = "${PR_INC}.9" +MACHINE_KERNEL_PR_append = "${PR_INC}.10" SRC_URI += "\ file://linux_3.1.1_vuduo.patch;striplevel=1 \ diff --git a/meta-openpli/recipes-linux/linux/linux-vusolo-3.1.1/vusolo_defconfig b/meta-openpli/recipes-linux/linux/linux-vusolo-3.1.1/vusolo_defconfig index 7e683fda5d..db0348e2b3 100644 --- a/meta-openpli/recipes-linux/linux/linux-vusolo-3.1.1/vusolo_defconfig +++ b/meta-openpli/recipes-linux/linux/linux-vusolo-3.1.1/vusolo_defconfig @@ -2265,7 +2265,11 @@ CONFIG_JBD=y CONFIG_JBD2=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +CONFIG_XFS_RT=y +# CONFIG_XFS_DEBUG is not set # CONFIG_GFS2_FS is not set # CONFIG_BTRFS_FS is not set # CONFIG_NILFS2_FS is not set diff --git a/meta-openpli/recipes-linux/linux/linux-vusolo_3.1.1.bb b/meta-openpli/recipes-linux/linux/linux-vusolo_3.1.1.bb index ad7c3109e8..a74b14025d 100644 --- a/meta-openpli/recipes-linux/linux/linux-vusolo_3.1.1.bb +++ b/meta-openpli/recipes-linux/linux/linux-vusolo_3.1.1.bb @@ -1,6 +1,6 @@ require linux-vuplus-3.1.1.inc -MACHINE_KERNEL_PR_append = "${PR_INC}.8" +MACHINE_KERNEL_PR_append = "${PR_INC}.9" SRC_URI += "\ file://linux_3.1.1_vusolo.patch;striplevel=1 \ diff --git a/meta-openpli/recipes-linux/linux/linux-vuultimo-3.1.1/vuultimo_defconfig b/meta-openpli/recipes-linux/linux/linux-vuultimo-3.1.1/vuultimo_defconfig index ff7d8cc105..6b4b477c40 100644 --- a/meta-openpli/recipes-linux/linux/linux-vuultimo-3.1.1/vuultimo_defconfig +++ b/meta-openpli/recipes-linux/linux/linux-vuultimo-3.1.1/vuultimo_defconfig @@ -2288,7 +2288,11 @@ CONFIG_JBD=m CONFIG_JBD2=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +CONFIG_XFS_RT=y +# CONFIG_XFS_DEBUG is not set # CONFIG_GFS2_FS is not set # CONFIG_BTRFS_FS is not set # CONFIG_NILFS2_FS is not set diff --git a/meta-openpli/recipes-linux/linux/linux-vuultimo_3.1.1.bb b/meta-openpli/recipes-linux/linux/linux-vuultimo_3.1.1.bb index 414396a0e4..ccd9401b6d 100644 --- a/meta-openpli/recipes-linux/linux/linux-vuultimo_3.1.1.bb +++ b/meta-openpli/recipes-linux/linux/linux-vuultimo_3.1.1.bb @@ -1,6 +1,6 @@ require linux-vuplus-3.1.1.inc -MACHINE_KERNEL_PR_append = "${PR_INC}.10" +MACHINE_KERNEL_PR_append = "${PR_INC}.11" SRC_URI += "\ file://linux-sata_brcm.patch;striplevel=1 \ diff --git a/meta-openpli/recipes-linux/linux/linux-vuuno-3.1.1/vuuno_defconfig b/meta-openpli/recipes-linux/linux/linux-vuuno-3.1.1/vuuno_defconfig index a18f4e18dc..d997d1c955 100644 --- a/meta-openpli/recipes-linux/linux/linux-vuuno-3.1.1/vuuno_defconfig +++ b/meta-openpli/recipes-linux/linux/linux-vuuno-3.1.1/vuuno_defconfig @@ -2288,7 +2288,11 @@ CONFIG_JBD=m CONFIG_JBD2=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +CONFIG_XFS_RT=y +# CONFIG_XFS_DEBUG is not set # CONFIG_GFS2_FS is not set # CONFIG_BTRFS_FS is not set # CONFIG_NILFS2_FS is not set diff --git a/meta-openpli/recipes-linux/linux/linux-vuuno_3.1.1.bb b/meta-openpli/recipes-linux/linux/linux-vuuno_3.1.1.bb index 471c544486..6d124a8991 100644 --- a/meta-openpli/recipes-linux/linux/linux-vuuno_3.1.1.bb +++ b/meta-openpli/recipes-linux/linux/linux-vuuno_3.1.1.bb @@ -1,6 +1,6 @@ require linux-vuplus-3.1.1.inc -MACHINE_KERNEL_PR_append = "${PR_INC}.10" +MACHINE_KERNEL_PR_append = "${PR_INC}.11" SRC_URI += "\ file://linux_3.1.1_vuuno.patch;striplevel=1 \ diff --git a/meta-openpli/recipes-linux/linux/linux-xp/xp1000/defconfig b/meta-openpli/recipes-linux/linux/linux-xp/xp1000/defconfig index 8d77fc1b20..8542913b4e 100644 --- a/meta-openpli/recipes-linux/linux/linux-xp/xp1000/defconfig +++ b/meta-openpli/recipes-linux/linux/linux-xp/xp1000/defconfig @@ -2286,7 +2286,11 @@ CONFIG_JBD=m CONFIG_JBD2=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +CONFIG_XFS_RT=y +# CONFIG_XFS_DEBUG is not set # CONFIG_GFS2_FS is not set # CONFIG_BTRFS_FS is not set # CONFIG_NILFS2_FS is not set diff --git a/meta-openpli/recipes-linux/linux/linux-xp_3.5.1.bb b/meta-openpli/recipes-linux/linux/linux-xp_3.5.1.bb index 50c8214b8b..10c7e55912 100644 --- a/meta-openpli/recipes-linux/linux/linux-xp_3.5.1.bb +++ b/meta-openpli/recipes-linux/linux/linux-xp_3.5.1.bb @@ -9,7 +9,7 @@ SRC_URI[sha256sum] = "3abe16a21183d72db7f8d07bf78bb704fb72ecaed35043e5d938368878 LIC_FILES_CHKSUM = "file://${WORKDIR}/linux-${PV}/COPYING;md5=d7810fab7487fb0aad327b76f1be7cd7" -MACHINE_KERNEL_PR_append = ".0" +MACHINE_KERNEL_PR_append = ".1" # By default, kernel.bbclass modifies package names to allow multiple kernels # to be installed in parallel. We revert this change and rprovide the versioned From 82a1f0917aa9c9b2daa01707b814ed73bb2d60ba Mon Sep 17 00:00:00 2001 From: MiLo Date: Wed, 10 Oct 2012 19:55:22 +0200 Subject: [PATCH 05/17] Add xfsprogs 3.1.8 recipe (3.1.7 is no longer available) --- .../remove-install-as-user.patch | 368 ++++++++++++++++++ .../recipes-core/xfsprogs/xfsprogs_3.1.8.bb | 48 +++ 2 files changed, 416 insertions(+) create mode 100644 meta-openpli/recipes-core/xfsprogs/xfsprogs-3.1.8/remove-install-as-user.patch create mode 100644 meta-openpli/recipes-core/xfsprogs/xfsprogs_3.1.8.bb diff --git a/meta-openpli/recipes-core/xfsprogs/xfsprogs-3.1.8/remove-install-as-user.patch b/meta-openpli/recipes-core/xfsprogs/xfsprogs-3.1.8/remove-install-as-user.patch new file mode 100644 index 0000000000..1263aafa22 --- /dev/null +++ b/meta-openpli/recipes-core/xfsprogs/xfsprogs-3.1.8/remove-install-as-user.patch @@ -0,0 +1,368 @@ +diff -urN a/include/buildmacros b/include/buildmacros +--- a/include/buildmacros 2011-12-27 23:32:31.554197934 -0600 ++++ b/include/buildmacros 2011-12-27 23:33:17.895485348 -0600 +@@ -30,7 +30,7 @@ + $(LFILES:.l=.o) \ + $(YFILES:%.y=%.tab.o) + +-INSTALL = $(TOPDIR)/install-sh -o $(PKG_USER) -g $(PKG_GROUP) ++INSTALL = $(TOPDIR)/install-sh + + IMAGES_DIR = $(TOPDIR)/all-images + DIST_DIR = $(TOPDIR)/dist +diff -urN a/include/install-sh b/include/install-sh +--- a/include/install-sh 2011-12-27 23:32:31.556198121 -0600 ++++ b/include/install-sh 2011-12-27 23:32:57.012201738 -0600 +@@ -24,11 +24,11 @@ + # set set | yes yes + # + _usage() { +- echo "Usage: $prog [-o owner] [-g group] [-m mode] -d directory" +- echo "or $prog [-D] [-o owner] [-g group] [-m mode] file directory/file" +- echo "or $prog [-o owner] [-g group] [-m mode] file [file ...] directory" ++ echo "Usage: $prog [-m mode] -d directory" ++ echo "or $prog [-m mode] file directory/file" ++ echo "or $prog [-m mode] file [file ...] directory" + echo "or $prog -S file target (creates \"target\" symlink)" +- echo "or $prog -T lt_arg [-o owner] [-g group] [-m mode] libtool.lai directory" ++ echo "or $prog -T lt_arg [-m mode] libtool.lai directory" + echo "" + echo "The \$DIST_MANIFEST and \$DIST_ROOT environment variables affect the" + echo "behaviour of this command - see comments in the script." +@@ -38,32 +38,6 @@ + exit 1 + } + +-_chown () +-{ +- _st=255 +- if [ $# -eq 3 ] ; then +- chown $1:$2 $3 +- _st=$? +- if [ $_st -ne 0 ] ; then +- if [ $REAL_UID != '0' ] ; then +- if [ ! -f $DIST_ROOT/.chown.quiet ] ; then +- echo '===============================================' +- echo Ownership of files under ${DIST_ROOT:-/} +- echo cannot be changed +- echo '===============================================' +- if [ -n "$DIST_ROOT" ] ; then +- touch $DIST_ROOT/.chown.quiet +- fi +- fi +- _st=0 +- fi +- fi +- fi +- +- return $_st +-} +- +- + _manifest () + { + echo $* | sed -e 's/\/\//\//g' >>${DIST_MANIFEST:-/dev/null} +@@ -77,9 +51,6 @@ + Tflag=false + DIRMODE=755 + FILEMODE=644 +-OWNER=`id -u` +-GROUP=`id -g` +-REAL_UID=$OWNER + + # default is to install and don't append manifest + INSTALL=true +@@ -92,24 +63,16 @@ + + if $INSTALL + then +- CP=cp; LN=ln; MKDIR=mkdir; CHMOD=chmod; CHOWN=_chown ++ CP=cp; LN=ln; MKDIR=mkdir; CHMOD=chmod; + else +- CP=true; LN=true; MKDIR=true; CHMOD=true; CHOWN=true ++ CP=true; LN=true; MKDIR=true; CHMOD=true; + fi + +-[ -n "$DIST_ROOT" -a $REAL_UID -ne 0 ] && CHOWN=true +- +-while getopts "Dcm:d:S:o:g:T:" c $* ++while getopts "Dcm:d:S:T:" c $* + do + case $c in + c) + ;; +- g) +- GROUP=$OPTARG +- ;; +- o) +- OWNER=$OPTARG +- ;; + m) + DIRMODE=`expr $OPTARG` + FILEMODE=$DIRMODE +@@ -144,18 +107,7 @@ + # first usage + # + $MKDIR -p $dir +- status=$? +- if [ $status -eq 0 ] +- then +- $CHMOD $DIRMODE $dir +- status=$? +- fi +- if [ $status -eq 0 ] +- then +- $CHOWN $OWNER $GROUP $dir +- status=$? +- fi +- $MANIFEST d $DIRMODE $OWNER $GROUP ${dir#$DIST_ROOT} ++ $MANIFEST d $DIRMODE ${dir#$DIST_ROOT} + elif $Sflag + then + # +@@ -201,7 +153,7 @@ + install_name=$target/$solib + $CP $solib $install_name + status=$? +- $MANIFEST f $FILEMODE $OWNER $GROUP $HERE/$solib ${install_name#$DIST_ROOT} ++ $MANIFEST f $FILEMODE $HERE/$solib ${install_name#$DIST_ROOT} + break + fi + done +@@ -252,7 +204,7 @@ + install_name=$target/$old_library + $CP $old_library $install_name + status=$? +- $MANIFEST f $FILEMODE $OWNER $GROUP $HERE/$old_library ${install_name#$DIST_ROOT} ++ $MANIFEST f $FILEMODE $HERE/$old_library ${install_name#$DIST_ROOT} + ;; + *) + echo "$prog: -T $lt_install invalid" +@@ -265,7 +217,6 @@ + if [ $status -eq 0 ] + then + $CHMOD $FILEMODE $install_name +- $CHOWN $OWNER $GROUP $install_name + fi + ;; + esac +@@ -290,23 +241,10 @@ + then + if [ -f $dir/$f ] + then +- $CHMOD $FILEMODE $dir/$f +- status=$? +- if [ $status -eq 0 ] +- then +- $CHOWN $OWNER $GROUP $dir/$f +- status=$? +- fi +- $MANIFEST f $FILEMODE $OWNER $GROUP $HERE/$f ${dir#$DIST_ROOT}/$f ++ $MANIFEST f $FILEMODE $HERE/$f ${dir#$DIST_ROOT}/$f + else + $CHMOD $FILEMODE $dir +- status=$? +- if [ $status -eq 0 ] +- then +- $CHOWN $OWNER $GROUP $dir +- status=$? +- fi +- $MANIFEST f $FILEMODE $OWNER $GROUP $HERE/$dir ${dir#$DIST_ROOT} ++ $MANIFEST f $FILEMODE $HERE/$dir ${dir#$DIST_ROOT} + fi + fi + else +@@ -332,14 +270,7 @@ + status=$? + if [ $status -eq 0 ] + then +- $CHMOD $FILEMODE $dir/$f +- status=$? +- if [ $status -eq 0 ] +- then +- $CHOWN $OWNER $GROUP $dir/$f +- status=$? +- fi +- $MANIFEST f $FILEMODE $OWNER $GROUP $HERE/$f ${dir#$DIST_ROOT}/$f ++ $MANIFEST f $FILEMODE $HERE/$f ${dir#$DIST_ROOT}/$f + fi + [ $status -ne 0 ] && break + done +diff -urN a/install-sh b/install-sh +--- a/install-sh 2011-12-27 23:32:31.565200349 -0600 ++++ b/install-sh 2011-12-27 23:32:51.854178224 -0600 +@@ -24,11 +24,11 @@ + # set set | yes yes + # + _usage() { +- echo "Usage: $prog [-o owner] [-g group] [-m mode] -d directory" +- echo "or $prog [-D] [-o owner] [-g group] [-m mode] file directory/file" +- echo "or $prog [-o owner] [-g group] [-m mode] file [file ...] directory" ++ echo "Usage: $prog [-m mode] -d directory" ++ echo "or $prog [-m mode] file directory/file" ++ echo "or $prog [-m mode] file [file ...] directory" + echo "or $prog -S file target (creates \"target\" symlink)" +- echo "or $prog -T lt_arg [-o owner] [-g group] [-m mode] libtool.lai directory" ++ echo "or $prog -T lt_arg [-m mode] libtool.lai directory" + echo "" + echo "The \$DIST_MANIFEST and \$DIST_ROOT environment variables affect the" + echo "behaviour of this command - see comments in the script." +@@ -38,32 +38,6 @@ + exit 1 + } + +-_chown () +-{ +- _st=255 +- if [ $# -eq 3 ] ; then +- chown $1:$2 $3 +- _st=$? +- if [ $_st -ne 0 ] ; then +- if [ $REAL_UID != '0' ] ; then +- if [ ! -f $DIST_ROOT/.chown.quiet ] ; then +- echo '===============================================' +- echo Ownership of files under ${DIST_ROOT:-/} +- echo cannot be changed +- echo '===============================================' +- if [ -n "$DIST_ROOT" ] ; then +- touch $DIST_ROOT/.chown.quiet +- fi +- fi +- _st=0 +- fi +- fi +- fi +- +- return $_st +-} +- +- + _manifest () + { + echo $* | sed -e 's/\/\//\//g' >>${DIST_MANIFEST:-/dev/null} +@@ -77,9 +51,6 @@ + Tflag=false + DIRMODE=755 + FILEMODE=644 +-OWNER=`id -u` +-GROUP=`id -g` +-REAL_UID=$OWNER + + # default is to install and don't append manifest + INSTALL=true +@@ -92,24 +63,16 @@ + + if $INSTALL + then +- CP=cp; LN=ln; MKDIR=mkdir; CHMOD=chmod; CHOWN=_chown ++ CP=cp; LN=ln; MKDIR=mkdir; CHMOD=chmod; + else +- CP=true; LN=true; MKDIR=true; CHMOD=true; CHOWN=true ++ CP=true; LN=true; MKDIR=true; CHMOD=true; + fi + +-[ -n "$DIST_ROOT" -a $REAL_UID -ne 0 ] && CHOWN=true +- +-while getopts "Dcm:d:S:o:g:T:" c $* ++while getopts "Dcm:d:S:T:" c $* + do + case $c in + c) + ;; +- g) +- GROUP=$OPTARG +- ;; +- o) +- OWNER=$OPTARG +- ;; + m) + DIRMODE=`expr $OPTARG` + FILEMODE=$DIRMODE +@@ -144,18 +107,7 @@ + # first usage + # + $MKDIR -p $dir +- status=$? +- if [ $status -eq 0 ] +- then +- $CHMOD $DIRMODE $dir +- status=$? +- fi +- if [ $status -eq 0 ] +- then +- $CHOWN $OWNER $GROUP $dir +- status=$? +- fi +- $MANIFEST d $DIRMODE $OWNER $GROUP ${dir#$DIST_ROOT} ++ $MANIFEST d $DIRMODE ${dir#$DIST_ROOT} + elif $Sflag + then + # +@@ -201,7 +153,7 @@ + install_name=$target/$solib + $CP $solib $install_name + status=$? +- $MANIFEST f $FILEMODE $OWNER $GROUP $HERE/$solib ${install_name#$DIST_ROOT} ++ $MANIFEST f $FILEMODE $HERE/$solib ${install_name#$DIST_ROOT} + break + fi + done +@@ -252,7 +204,7 @@ + install_name=$target/$old_library + $CP $old_library $install_name + status=$? +- $MANIFEST f $FILEMODE $OWNER $GROUP $HERE/$old_library ${install_name#$DIST_ROOT} ++ $MANIFEST f $FILEMODE $HERE/$old_library ${install_name#$DIST_ROOT} + ;; + *) + echo "$prog: -T $lt_install invalid" +@@ -265,7 +217,6 @@ + if [ $status -eq 0 ] + then + $CHMOD $FILEMODE $install_name +- $CHOWN $OWNER $GROUP $install_name + fi + ;; + esac +@@ -290,23 +241,10 @@ + then + if [ -f $dir/$f ] + then +- $CHMOD $FILEMODE $dir/$f +- status=$? +- if [ $status -eq 0 ] +- then +- $CHOWN $OWNER $GROUP $dir/$f +- status=$? +- fi +- $MANIFEST f $FILEMODE $OWNER $GROUP $HERE/$f ${dir#$DIST_ROOT}/$f ++ $MANIFEST f $FILEMODE $HERE/$f ${dir#$DIST_ROOT}/$f + else + $CHMOD $FILEMODE $dir +- status=$? +- if [ $status -eq 0 ] +- then +- $CHOWN $OWNER $GROUP $dir +- status=$? +- fi +- $MANIFEST f $FILEMODE $OWNER $GROUP $HERE/$dir ${dir#$DIST_ROOT} ++ $MANIFEST f $FILEMODE $HERE/$dir ${dir#$DIST_ROOT} + fi + fi + else +@@ -332,14 +270,7 @@ + status=$? + if [ $status -eq 0 ] + then +- $CHMOD $FILEMODE $dir/$f +- status=$? +- if [ $status -eq 0 ] +- then +- $CHOWN $OWNER $GROUP $dir/$f +- status=$? +- fi +- $MANIFEST f $FILEMODE $OWNER $GROUP $HERE/$f ${dir#$DIST_ROOT}/$f ++ $MANIFEST f $FILEMODE $HERE/$f ${dir#$DIST_ROOT}/$f + fi + [ $status -ne 0 ] && break + done diff --git a/meta-openpli/recipes-core/xfsprogs/xfsprogs_3.1.8.bb b/meta-openpli/recipes-core/xfsprogs/xfsprogs_3.1.8.bb new file mode 100644 index 0000000000..9a46264fff --- /dev/null +++ b/meta-openpli/recipes-core/xfsprogs/xfsprogs_3.1.8.bb @@ -0,0 +1,48 @@ +DESCRIPTION = "XFS Filesystem Utilities" +HOMEPAGE = "http://oss.sgi.com/projects/xfs" +SECTION = "base" +LICENSE = "GPLv2" +LICENSE_libhandle = "LGPLv2.1" +LIC_FILES_CHKSUM = "file://doc/COPYING;md5=dbdb5f4329b7e7145de650e9ecd4ac2a" +DEPENDS = "util-linux" +PR = "r1" + +SRC_URI = "ftp://oss.sgi.com/projects/xfs/cmd_tars/${P}.tar.gz \ + file://remove-install-as-user.patch \ +" +SRC_URI[md5sum] = "f70b2e7200d4c29f0af1cf70e7be1db6" +SRC_URI[sha256sum] = "74409e2e3748074999df25c00f722621659a0bd3607e677f0bcc4373b8c93eab" + + +inherit autotools + +PACKAGES =+ "${PN}-fsck ${PN}-mkfs libhandle" + +RDEPENDS_${PN} = "${PN}-fsck ${PN}-mkfs" + +FILES_${PN}-fsck = "${base_sbindir}/fsck.xfs" +FILES_${PN}-mkfs = "${base_sbindir}/mkfs.xfs" +FILES_libhandle = "${base_libdir}/libhandle${SOLIBS}" + +EXTRA_OECONF = "--enable-gettext=no" +do_configure () { + export DEBUG="-DNDEBUG" + oe_runconf +} + +LIBTOOL = "${HOST_SYS}-libtool" +EXTRA_OEMAKE = "'LIBTOOL=${LIBTOOL}'" +TARGET_CC_ARCH += "${LDFLAGS}" +PARALLEL_MAKE = "" + +do_install () { + export DIST_ROOT=${D} + oe_runmake install + # needed for xfsdump + oe_runmake install-dev + rm ${D}${base_libdir}/libhandle.a + rm ${D}${base_libdir}/libhandle.la + rm ${D}${base_libdir}/libhandle.so + rm ${D}${libdir}/libhandle.so + ln -s ../..${base_libdir}/libhandle.so.1 ${D}${libdir}/libhandle.so +} From 346f0b59b362b0ba38965a6a3146d2f05eeb09b3 Mon Sep 17 00:00:00 2001 From: MiLo Date: Wed, 10 Oct 2012 19:56:09 +0200 Subject: [PATCH 06/17] Add xfsprogs to feed --- meta-openpli/recipes-openpli/images/openpli-image.bb | 1 + 1 file changed, 1 insertion(+) diff --git a/meta-openpli/recipes-openpli/images/openpli-image.bb b/meta-openpli/recipes-openpli/images/openpli-image.bb index f7c29c63a7..36743d1ce7 100644 --- a/meta-openpli/recipes-openpli/images/openpli-image.bb +++ b/meta-openpli/recipes-openpli/images/openpli-image.bb @@ -66,6 +66,7 @@ OPTIONAL_PACKAGES += " \ transmission \ vim \ wakelan \ + xfsprogs \ zeroconf \ " From 7fcd4683fd136c3aeabe90c39be68ed45f68dcbc Mon Sep 17 00:00:00 2001 From: pieterg Date: Wed, 10 Oct 2012 20:21:41 +0200 Subject: [PATCH 07/17] autoload xfs module --- meta-openpli/conf/machine/include/autoload-filesystems.inc | 1 + meta-openpli/conf/machine/include/dreambox.inc | 1 + meta-openpli/conf/machine/include/etxx00.inc | 1 + meta-openpli/conf/machine/include/vuxxo.inc | 1 + meta-openpli/conf/machine/include/xp.inc | 1 + 5 files changed, 5 insertions(+) create mode 100644 meta-openpli/conf/machine/include/autoload-filesystems.inc diff --git a/meta-openpli/conf/machine/include/autoload-filesystems.inc b/meta-openpli/conf/machine/include/autoload-filesystems.inc new file mode 100644 index 0000000000..b3ef351c8d --- /dev/null +++ b/meta-openpli/conf/machine/include/autoload-filesystems.inc @@ -0,0 +1 @@ +module_autoload_xfs = "xfs" diff --git a/meta-openpli/conf/machine/include/dreambox.inc b/meta-openpli/conf/machine/include/dreambox.inc index 1b48d88e19..54692f2628 100644 --- a/meta-openpli/conf/machine/include/dreambox.inc +++ b/meta-openpli/conf/machine/include/dreambox.inc @@ -9,6 +9,7 @@ MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "dreambox-dvb-modules-${MACHINE}" include conf/machine/include/autoload-wifi.inc include conf/machine/include/autoload-dvb-usb.inc include conf/machine/include/autoload-usbserial.inc +include conf/machine/include/autoload-filesystems.inc MACHINE_EXTRA_RRECOMMENDS = " \ gst-plugin-dreambox-dvbmediasink \ diff --git a/meta-openpli/conf/machine/include/etxx00.inc b/meta-openpli/conf/machine/include/etxx00.inc index 5776072a98..7d4c186bd0 100644 --- a/meta-openpli/conf/machine/include/etxx00.inc +++ b/meta-openpli/conf/machine/include/etxx00.inc @@ -9,6 +9,7 @@ MACHINE_ESSENTIAL_EXTRA_RRECOMMENDS = "\ include conf/machine/include/autoload-wifi.inc include conf/machine/include/autoload-dvb-usb.inc include conf/machine/include/autoload-usbserial.inc +include conf/machine/include/autoload-filesystems.inc MACHINE_EXTRA_RRECOMMENDS = " \ gst-plugin-dvbmediasink \ diff --git a/meta-openpli/conf/machine/include/vuxxo.inc b/meta-openpli/conf/machine/include/vuxxo.inc index 73282c86c5..43b33a3ffc 100644 --- a/meta-openpli/conf/machine/include/vuxxo.inc +++ b/meta-openpli/conf/machine/include/vuxxo.inc @@ -5,6 +5,7 @@ MACHINE_ESSENTIAL_EXTRA_RDEPENDS = " \ include conf/machine/include/autoload-wifi.inc include conf/machine/include/autoload-dvb-usb.inc include conf/machine/include/autoload-usbserial.inc +include conf/machine/include/autoload-filesystems.inc MACHINE_EXTRA_RRECOMMENDS = " \ vuplus-shutdown \ diff --git a/meta-openpli/conf/machine/include/xp.inc b/meta-openpli/conf/machine/include/xp.inc index 93e84a6c19..a46a46dada 100644 --- a/meta-openpli/conf/machine/include/xp.inc +++ b/meta-openpli/conf/machine/include/xp.inc @@ -9,6 +9,7 @@ MACHINE_ESSENTIAL_EXTRA_RRECOMMENDS = "\ include conf/machine/include/autoload-wifi.inc include conf/machine/include/autoload-dvb-usb.inc include conf/machine/include/autoload-usbserial.inc +include conf/machine/include/autoload-filesystems.inc MACHINE_EXTRA_RRECOMMENDS = " \ gst-plugin-dvbmediasink \ From 1efcf186cf958859ab92b509772a59f9f4f97f16 Mon Sep 17 00:00:00 2001 From: pieterg Date: Sat, 13 Oct 2012 01:18:51 +0200 Subject: [PATCH 08/17] linux-dreambox: "fixes stability problems since previous update" --- .../jffs2-compression-fixes.patch | 4 +- .../revert-mips-module-loader-stuff.patch | 114 ++++++++++++++++++ .../recipes-linux/linux/linux-dreambox_3.2.bb | 3 +- 3 files changed, 119 insertions(+), 2 deletions(-) create mode 100644 meta-openpli/recipes-linux/linux/linux-dreambox-3.2/revert-mips-module-loader-stuff.patch diff --git a/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/jffs2-compression-fixes.patch b/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/jffs2-compression-fixes.patch index 1fab82acbd..6f5d5421f8 100644 --- a/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/jffs2-compression-fixes.patch +++ b/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/jffs2-compression-fixes.patch @@ -57,7 +57,7 @@ index 5b6c9d1..99e4c05 100644 if (c->mount_opts.override_compr) mode = c->mount_opts.compr; -@@ -168,63 +171,58 @@ uint16_t jffs2_compress(struct jffs2_sb_info *c, struct jffs2_inode_info *f, +@@ -168,63 +171,60 @@ uint16_t jffs2_compress(struct jffs2_sb_info *c, struct jffs2_inode_info *f, break; case JFFS2_COMPR_MODE_SIZE: case JFFS2_COMPR_MODE_FAVOURLZO: @@ -149,6 +149,8 @@ index 5b6c9d1..99e4c05 100644 ret = best->compr; *cpage_out = output_buf; } ++ else ++ kfree(best_buf); - spin_unlock(&jffs2_compressor_list_lock); break; case JFFS2_COMPR_MODE_FORCELZO: diff --git a/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/revert-mips-module-loader-stuff.patch b/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/revert-mips-module-loader-stuff.patch new file mode 100644 index 0000000000..b81655e392 --- /dev/null +++ b/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/revert-mips-module-loader-stuff.patch @@ -0,0 +1,114 @@ +diff -Naur linux-3.2-broken/arch/mips/include/asm/module.h linux-3.2/arch/mips/include/asm/module.h +--- linux-3.2-broken/arch/mips/include/asm/module.h 2012-10-04 14:40:09.713467966 +0200 ++++ linux-3.2/arch/mips/include/asm/module.h 2012-01-05 00:55:44.000000000 +0100 +@@ -9,7 +9,6 @@ + struct list_head dbe_list; + const struct exception_table_entry *dbe_start; + const struct exception_table_entry *dbe_end; +- struct mips_hi16 *r_mips_hi16_list; + }; + + typedef uint8_t Elf64_Byte; /* Type for a 8-bit quantity. */ +diff -Naur linux-3.2-broken/arch/mips/kernel/module.c linux-3.2/arch/mips/kernel/module.c +--- linux-3.2-broken/arch/mips/kernel/module.c 2012-10-04 14:40:09.713467966 +0200 ++++ linux-3.2/arch/mips/kernel/module.c 2012-01-05 00:55:44.000000000 +0100 +@@ -39,6 +39,8 @@ + Elf_Addr value; + }; + ++static struct mips_hi16 *mips_hi16_list; ++ + static LIST_HEAD(dbe_list); + static DEFINE_SPINLOCK(dbe_lock); + +@@ -126,8 +128,8 @@ + + n->addr = (Elf_Addr *)location; + n->value = v; +- n->next = me->arch.r_mips_hi16_list; +- me->arch.r_mips_hi16_list = n; ++ n->next = mips_hi16_list; ++ mips_hi16_list = n; + + return 0; + } +@@ -140,28 +142,18 @@ + return 0; + } + +-static void free_relocation_chain(struct mips_hi16 *l) +-{ +- struct mips_hi16 *next; +- +- while (l) { +- next = l->next; +- kfree(l); +- l = next; +- } +-} +- + static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v) + { + unsigned long insnlo = *location; +- struct mips_hi16 *l; + Elf_Addr val, vallo; + + /* Sign extend the addend we extract from the lo insn. */ + vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000; + +- if (me->arch.r_mips_hi16_list != NULL) { +- l = me->arch.r_mips_hi16_list; ++ if (mips_hi16_list != NULL) { ++ struct mips_hi16 *l; ++ ++ l = mips_hi16_list; + while (l != NULL) { + struct mips_hi16 *next; + unsigned long insn; +@@ -196,7 +188,7 @@ + l = next; + } + +- me->arch.r_mips_hi16_list = NULL; ++ mips_hi16_list = NULL; + } + + /* +@@ -209,9 +201,6 @@ + return 0; + + out_danger: +- free_relocation_chain(l); +- me->arch.r_mips_hi16_list = NULL; +- + pr_err("module %s: dangerous R_MIPS_LO16 REL relocation\n", me->name); + + return -ENOEXEC; +@@ -284,7 +273,6 @@ + pr_debug("Applying relocate section %u to %u\n", relsec, + sechdrs[relsec].sh_info); + +- me->arch.r_mips_hi16_list = NULL; + for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { + /* This is where to make the change */ + location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr +@@ -308,19 +296,6 @@ + return res; + } + +- /* +- * Normally the hi16 list should be deallocated at this point. A +- * malformed binary however could contain a series of R_MIPS_HI16 +- * relocations not followed by a R_MIPS_LO16 relocation. In that +- * case, free up the list and return an error. +- */ +- if (me->arch.r_mips_hi16_list) { +- free_relocation_chain(me->arch.r_mips_hi16_list); +- me->arch.r_mips_hi16_list = NULL; +- +- return -ENOEXEC; +- } +- + return 0; + } + diff --git a/meta-openpli/recipes-linux/linux/linux-dreambox_3.2.bb b/meta-openpli/recipes-linux/linux/linux-dreambox_3.2.bb index 6da3896a69..d6ffa3df28 100644 --- a/meta-openpli/recipes-linux/linux/linux-dreambox_3.2.bb +++ b/meta-openpli/recipes-linux/linux/linux-dreambox_3.2.bb @@ -1,4 +1,4 @@ -MACHINE_KERNEL_PR_append = ".${INC_PR}.29" +MACHINE_KERNEL_PR_append = ".${INC_PR}.30" PATCHREV = "b299a6a132d842b074b289b2568eece452d0663c" PATCHLEVEL = "30" @@ -24,6 +24,7 @@ SRC_URI = " \ file://brcmnand-fixed-possible-race-condition.patch \ file://0001-nand_base.c-2ms-for-nand_wait_ready-is-not-enough.patch \ file://0002-MTD-dreambox_nand-cleanup-speedup-implement-select_c.patch \ + file://revert-mips-module-loader-stuff.patch \ file://em28xx_fix_terratec_entries.patch \ file://em28xx_add_terratec_h5_rev3.patch \ file://defconfig \ From e1d3c69b2dc51e68bb43ef89bada05e79d6e45bf Mon Sep 17 00:00:00 2001 From: pieterg Date: Sat, 13 Oct 2012 01:24:24 +0200 Subject: [PATCH 09/17] dreambox: bump MACHINE_KERNEL_PR recent kernel changes break external modules --- meta-openpli/conf/machine/include/dreambox-mips32el.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-openpli/conf/machine/include/dreambox-mips32el.inc b/meta-openpli/conf/machine/include/dreambox-mips32el.inc index 132695db0b..35e186aac3 100644 --- a/meta-openpli/conf/machine/include/dreambox-mips32el.inc +++ b/meta-openpli/conf/machine/include/dreambox-mips32el.inc @@ -6,4 +6,4 @@ DEFAULTTUNE = "mips32el" require conf/machine/include/dreambox.inc require conf/machine/include/tune-mips32.inc -MACHINE_KERNEL_PR = "r1" +MACHINE_KERNEL_PR = "r2" From b831b2caae9dde49a5c4f0c7d142c219506be522 Mon Sep 17 00:00:00 2001 From: pieterg Date: Sat, 13 Oct 2012 09:32:47 +0200 Subject: [PATCH 10/17] openpli-bootlogo: handle when /boot is already mounted Some people might have a /boot entry in their fstab, so /boot will be mounted already, causing bootlogo updates to fail. --- .../bootlogo/openpli-bootlogo.bb | 34 ++++++++++++++----- 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/meta-openpli/recipes-openpli/bootlogo/openpli-bootlogo.bb b/meta-openpli/recipes-openpli/bootlogo/openpli-bootlogo.bb index 9e27327db5..2a1d2f7d7f 100644 --- a/meta-openpli/recipes-openpli/bootlogo/openpli-bootlogo.bb +++ b/meta-openpli/recipes-openpli/bootlogo/openpli-bootlogo.bb @@ -63,23 +63,41 @@ do_install() { } pkg_preinst() { - [ -d /proc/stb ] && mount -t jffs2 -o rw,compr=none mtd:'boot partition' /boot - true + if [ -z "$D" ] + then + if mountpoint -q /boot + then + mount -o remount,rw,compr=none /boot + else + mount -t jffs2 -o rw,compr=none mtd:'boot partition' /boot + fi + fi } pkg_postinst() { - [ -d /proc/stb ] && umount /boot - true + if [ -z "$D" ] + then + umount /boot + fi } pkg_prerm() { - [ -d /proc/stb ] && mount -t jffs2 -o rw,compr=none mtd:'boot partition' /boot - true + if [ -z "$D" ] + then + if mountpoint -q /boot + then + mount -o remount,rw,compr=none /boot + else + mount -t jffs2 -o rw,compr=none mtd:'boot partition' /boot + fi + fi } pkg_postrm() { - [ -d /proc/stb ] && umount /boot - true + if [ -z "$D" ] + then + umount /boot + fi } PACKAGE_ARCH := "${MACHINE_ARCH}" From 18b4a533ac5c6dffa502770a8c092535330db373 Mon Sep 17 00:00:00 2001 From: MiLo Date: Sat, 13 Oct 2012 11:38:59 +0200 Subject: [PATCH 11/17] mdev-mount.sh: Tell enigma about non-mountable devices If a disk doesn't contain a filesystem, it's still a good thing to tell the UI about it. If you attach an unpartitioned or otherwise unrecognized disk, you still want to be able to format it. (*) This may fix some reports about "missing" USB drives, since they wouldn't show up in Enigma2 if they weren't yet there at startup. (*) Note: E2 could just listen on a netlink socket for this. --- .../recipes-core/busybox/busybox-1.19.4/mdev-mount.sh | 11 ++++++----- .../recipes-core/busybox/busybox_1.19.4.bbappend | 2 +- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/meta-openpli/recipes-core/busybox/busybox-1.19.4/mdev-mount.sh b/meta-openpli/recipes-core/busybox/busybox-1.19.4/mdev-mount.sh index 087fff4cbc..f8148b6911 100644 --- a/meta-openpli/recipes-core/busybox/busybox-1.19.4/mdev-mount.sh +++ b/meta-openpli/recipes-core/busybox/busybox-1.19.4/mdev-mount.sh @@ -10,11 +10,6 @@ notify() { case "$ACTION" in add|"") ACTION="add" - # Run the result of blkid as a shell command - eval `blkid /dev/${MDEV} | grep ${MDEV} | cut -d ':' -f 2` - if [ -z "$TYPE" ] ; then - exit 0 - fi # check if already mounted if grep -q "^/dev/${MDEV} " /proc/mounts ; then # Already mounted @@ -26,6 +21,12 @@ case "$ACTION" in # blocked exit 0 fi + # Run the result of blkid as a shell command + eval `blkid /dev/${MDEV} | grep ${MDEV} | cut -d ':' -f 2` + if [ -z "$TYPE" ] ; then + notify + exit 0 + fi if [ $TYPE == swap ] ; then if ! grep -q "^/dev/${MDEV} " /proc/swaps ; then swapon /dev/${MDEV} diff --git a/meta-openpli/recipes-core/busybox/busybox_1.19.4.bbappend b/meta-openpli/recipes-core/busybox/busybox_1.19.4.bbappend index 60e86c0870..018b3c8903 100644 --- a/meta-openpli/recipes-core/busybox/busybox_1.19.4.bbappend +++ b/meta-openpli/recipes-core/busybox/busybox_1.19.4.bbappend @@ -1,4 +1,4 @@ -PRINC = "21" +PRINC = "22" SRC_URI += " \ file://0001-ifupdown-support-post-up-pre-down-hooks.patch \ From fcd71266b203bd811a4042b600d60559b1c86af3 Mon Sep 17 00:00:00 2001 From: pieterg Date: Sat, 13 Oct 2012 18:53:06 +0200 Subject: [PATCH 12/17] linux-dreambox: 3.2.31 update --- .../linux-dreambox-3.2/clear_sublevel.patch | 4 ++-- .../nand-driver-smp-fixes.patch | 20 +++++++++++++++++++ .../recipes-linux/linux/linux-dreambox_3.2.bb | 7 ++++--- 3 files changed, 26 insertions(+), 5 deletions(-) create mode 100644 meta-openpli/recipes-linux/linux/linux-dreambox-3.2/nand-driver-smp-fixes.patch diff --git a/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/clear_sublevel.patch b/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/clear_sublevel.patch index 36f55bece1..17d711dbd1 100644 --- a/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/clear_sublevel.patch +++ b/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/clear_sublevel.patch @@ -5,8 +5,8 @@ Index: linux-3.2/Makefile @@ -1,6 +1,6 @@ VERSION = 3 PATCHLEVEL = 2 --SUBLEVEL = 30 -+#SUBLEVEL = 30 +-SUBLEVEL = 31 ++#SUBLEVEL = 31 EXTRAVERSION = NAME = Saber-toothed Squirrel diff --git a/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/nand-driver-smp-fixes.patch b/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/nand-driver-smp-fixes.patch new file mode 100644 index 0000000000..b6397a9330 --- /dev/null +++ b/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/nand-driver-smp-fixes.patch @@ -0,0 +1,20 @@ +diff --git a/drivers/mtd/nand/dreambox_nand.c b/drivers/mtd/nand/dreambox_nand.c +index 3aff2a9..f0adbdc 100644 +--- a/drivers/mtd/nand/dreambox_nand.c ++++ b/drivers/mtd/nand/dreambox_nand.c +@@ -89,6 +89,7 @@ static void dreambox_nand_select_chip(struct mtd_info *mtd, int chipnr) + PRINTK(KERN_DEBUG "select chip\n"); + writeb(0xEE, (void __iomem *)0xBF030003); + } ++ readb((void __iomem *)0xBF030003); + } + + /* +@@ -118,6 +119,7 @@ static void dreambox_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, + ctrl & 0x80 ? "CHANGE" : ""); + + writeb(cmd, (void __iomem *)addr); ++ readb((void __iomem *)addr); + } + + static uint8_t dreambox_nand_read_byte(struct mtd_info *mtd) diff --git a/meta-openpli/recipes-linux/linux/linux-dreambox_3.2.bb b/meta-openpli/recipes-linux/linux/linux-dreambox_3.2.bb index d6ffa3df28..ea95d7d3d0 100644 --- a/meta-openpli/recipes-linux/linux/linux-dreambox_3.2.bb +++ b/meta-openpli/recipes-linux/linux/linux-dreambox_3.2.bb @@ -1,7 +1,7 @@ MACHINE_KERNEL_PR_append = ".${INC_PR}.30" PATCHREV = "b299a6a132d842b074b289b2568eece452d0663c" -PATCHLEVEL = "30" +PATCHLEVEL = "31" SRC_URI = " \ ${KERNELORG_MIRROR}/linux/kernel/v3.x/linux-3.2.tar.bz2;name=kernel \ @@ -25,6 +25,7 @@ SRC_URI = " \ file://0001-nand_base.c-2ms-for-nand_wait_ready-is-not-enough.patch \ file://0002-MTD-dreambox_nand-cleanup-speedup-implement-select_c.patch \ file://revert-mips-module-loader-stuff.patch \ + file://nand-driver-smp-fixes.patch \ file://em28xx_fix_terratec_entries.patch \ file://em28xx_add_terratec_h5_rev3.patch \ file://defconfig \ @@ -32,8 +33,8 @@ SRC_URI = " \ SRC_URI[kernel.md5sum] = "7ceb61f87c097fc17509844b71268935" SRC_URI[kernel.sha256sum] = "c881fc2b53cf0da7ca4538aa44623a7de043a41f76fd5d0f51a31f6ed699d463" -SRC_URI[kernel-patch.md5sum] = "008626f6c88d0d3660f088c56be73bc0" -SRC_URI[kernel-patch.sha256sum] = "036178afd870667b022de02cb21a07d11205df6f6972205e989784cc9fc747f7" +SRC_URI[kernel-patch.md5sum] = "d6b622b1c842c53a3ce0c24045a4e816" +SRC_URI[kernel-patch.sha256sum] = "dc564ad8eab78ee7c77df2c543bdc5f86d3cb33f505329295e84a67679a9ad38" SRC_URI[dmm-patch.md5sum] = "c364975ed4c2d066634729827f8552b9" SRC_URI[dmm-patch.sha256sum] = "e56c75ad2c8e1d9328d55a7abf7c7ce805acb96354eb26449d5f91c65ad340a4" SRC_URI[unionfs.md5sum] = "06e7c9f6cafd49b72184be851116c511" From 3991fe0b0c49b9e821714e1ece5a570587fbc966 Mon Sep 17 00:00:00 2001 From: pieterg Date: Sun, 14 Oct 2012 18:54:11 +0200 Subject: [PATCH 13/17] dreambox: bump MACHINE_KERNEL_PR to 12 Before we used MACHINE_KERNEL_PR, the kernel had a PR of 11. So we need MACHINE_KERNEL_PR to be higher than that. --- meta-openpli/conf/machine/include/dreambox-mips32el.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-openpli/conf/machine/include/dreambox-mips32el.inc b/meta-openpli/conf/machine/include/dreambox-mips32el.inc index 35e186aac3..5adb021b9d 100644 --- a/meta-openpli/conf/machine/include/dreambox-mips32el.inc +++ b/meta-openpli/conf/machine/include/dreambox-mips32el.inc @@ -6,4 +6,4 @@ DEFAULTTUNE = "mips32el" require conf/machine/include/dreambox.inc require conf/machine/include/tune-mips32.inc -MACHINE_KERNEL_PR = "r2" +MACHINE_KERNEL_PR = "r12" From d9ce510d2e28760911b295d49e3fc8cc7542da57 Mon Sep 17 00:00:00 2001 From: pieterg Date: Mon, 15 Oct 2012 21:50:15 +0200 Subject: [PATCH 14/17] dm7020hd: build XFS into the kernel again, and disable XFS_RT just to find out whether this avoids the booting problem, introduced after 20121010 (coinciding with the XFS defconfig changes in 702913ef03fea56b244b56484a6ed6df7cd766ed) --- meta-openpli/conf/machine/include/dreambox-mips32el.inc | 2 +- .../recipes-linux/linux/linux-dreambox-3.2/dm7020hd/defconfig | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/meta-openpli/conf/machine/include/dreambox-mips32el.inc b/meta-openpli/conf/machine/include/dreambox-mips32el.inc index 5adb021b9d..8d5666a253 100644 --- a/meta-openpli/conf/machine/include/dreambox-mips32el.inc +++ b/meta-openpli/conf/machine/include/dreambox-mips32el.inc @@ -6,4 +6,4 @@ DEFAULTTUNE = "mips32el" require conf/machine/include/dreambox.inc require conf/machine/include/tune-mips32.inc -MACHINE_KERNEL_PR = "r12" +MACHINE_KERNEL_PR = "r13" diff --git a/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/dm7020hd/defconfig b/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/dm7020hd/defconfig index 31a56fb062..220aab1b06 100644 --- a/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/dm7020hd/defconfig +++ b/meta-openpli/recipes-linux/linux/linux-dreambox-3.2/dm7020hd/defconfig @@ -2465,10 +2465,10 @@ CONFIG_JFS_FS=m # CONFIG_JFS_SECURITY is not set # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set -CONFIG_XFS_FS=m +CONFIG_XFS_FS=y # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set -CONFIG_XFS_RT=y +# CONFIG_XFS_RT is not set # CONFIG_XFS_DEBUG is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set From ebd973f2c553e183443e661d1315078b978317ce Mon Sep 17 00:00:00 2001 From: blzr Date: Thu, 18 Oct 2012 18:43:37 +0200 Subject: [PATCH 15/17] libpng: update to 1.5.13 Signed-off-by: MiLo --- .../libpng/{libpng_1.5.12.bb => libpng_1.5.13.bb} | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) rename meta-openpli/recipes-multimedia/libpng/{libpng_1.5.12.bb => libpng_1.5.13.bb} (70%) diff --git a/meta-openpli/recipes-multimedia/libpng/libpng_1.5.12.bb b/meta-openpli/recipes-multimedia/libpng/libpng_1.5.13.bb similarity index 70% rename from meta-openpli/recipes-multimedia/libpng/libpng_1.5.12.bb rename to meta-openpli/recipes-multimedia/libpng/libpng_1.5.13.bb index 281a7568e1..3169b90800 100644 --- a/meta-openpli/recipes-multimedia/libpng/libpng_1.5.12.bb +++ b/meta-openpli/recipes-multimedia/libpng/libpng_1.5.13.bb @@ -4,7 +4,7 @@ LICENSE = "libpng" SECTION = "libs" PRIORITY = "required" LICENSE = "Libpng" -LIC_FILES_CHKSUM = "file://LICENSE;md5=efd93d73f344c56580c7f0ea3815fdbf" +LIC_FILES_CHKSUM = "file://LICENSE;md5=00b5b35853278d508806c2e5860e82cb" DEPENDS = "zlib" @@ -15,8 +15,8 @@ S = "${WORKDIR}/libpng-${PV}" inherit autotools pkgconfig binconfig -SRC_URI[libpng.md5sum] = "d87f9c34ccab8242c00e41925839f6c9" -SRC_URI[libpng.sha256sum] = "e83c4897bb92a7c67e6610a56676f2fdc213fe2995e9c1fef6f0cf7d70b30976" +SRC_URI[libpng.md5sum] = "186b3098d1ef844f76681bc69968efe2" +SRC_URI[libpng.sha256sum] = "16e761e584e5d72d72fc80923e7851a468bf86538456e304aea401b99038ca92" PACKAGES =+ "${PN}15" From 540779f1bcb41117b8b9a18d64d1541604b3e9e5 Mon Sep 17 00:00:00 2001 From: slashdev Date: Fri, 12 Oct 2012 19:23:14 +0200 Subject: [PATCH 16/17] linux-etxx00: 3.6.0 update Signed-off-by: MiLo --- meta-openpli/conf/machine/include/etxx00.inc | 3 +- .../etxx00/et-dvb-modules-et4x00.bb | 8 +- .../etxx00/et-dvb-modules-et5x00.bb | 8 +- .../etxx00/et-dvb-modules-et6x00.bb | 8 +- .../etxx00/et-dvb-modules-et9x00.bb | 8 +- ...-Revert-MIPS-Add-fast-get_user_pages.patch | 9 +- ...dd-compound-tail-page-_mapcount-when.patch | 27 + ...ion-to-break-out-from-wait-lock-loop.patch | 30 - .../cxd2820r-enable-LNA-for-DVB-T.patch | 24 - .../linux/linux-etxx00/dvb-usb-a867.patch | 16 +- .../linux/linux-etxx00/dvb-usb-af9035.patch | 15543 ---------------- ...top-URBs-when-stopping-the-streaming.patch | 87 - .../linux/linux-etxx00/et4x00/defconfig | 452 +- .../linux/linux-etxx00/et5x00/defconfig | 462 +- .../linux/linux-etxx00/et6x00/defconfig | 462 +- .../linux/linux-etxx00/et9x00/defconfig | 467 +- ...t913x-fix-bulk-read-write-retry-loop.patch | 30 - ...-etxx00_3.4.3.bb => linux-etxx00_3.6.0.bb} | 34 +- 18 files changed, 1284 insertions(+), 16394 deletions(-) create mode 100644 meta-openpli/recipes-linux/linux/linux-etxx00/0001-Revert-MIPS-mm-Add-compound-tail-page-_mapcount-when.patch delete mode 100644 meta-openpli/recipes-linux/linux/linux-etxx00/cxd2820r-changed-condition-to-break-out-from-wait-lock-loop.patch delete mode 100644 meta-openpli/recipes-linux/linux/linux-etxx00/cxd2820r-enable-LNA-for-DVB-T.patch delete mode 100644 meta-openpli/recipes-linux/linux/linux-etxx00/dvb-usb-af9035.patch delete mode 100644 meta-openpli/recipes-linux/linux/linux-etxx00/em28xx-dvb-stop-URBs-when-stopping-the-streaming.patch delete mode 100644 meta-openpli/recipes-linux/linux/linux-etxx00/it913x-fix-bulk-read-write-retry-loop.patch rename meta-openpli/recipes-linux/linux/{linux-etxx00_3.4.3.bb => linux-etxx00_3.6.0.bb} (82%) diff --git a/meta-openpli/conf/machine/include/etxx00.inc b/meta-openpli/conf/machine/include/etxx00.inc index 7d4c186bd0..c020a59c49 100644 --- a/meta-openpli/conf/machine/include/etxx00.inc +++ b/meta-openpli/conf/machine/include/etxx00.inc @@ -26,7 +26,6 @@ GLIBC_EXTRA_OECONF = "--with-tls --with-__thread" PREFERRED_PROVIDER_virtual/kernel = "linux-etxx00" PREFERRED_PROVIDER_virtual/blindscan-dvbs = "et-blindscan-dvbs-utils" -PREFERRED_VERSION_linux-etxx00 = "3.4.3" PREFERRED_VERSION_linux-libc-headers = "3.3" KERNEL_IMAGETYPE = "vmlinux" @@ -56,4 +55,4 @@ MACHINE_FEATURES += "alsa usbhost wifi 3dtv switchoff textlcd osdposition hdmice require conf/machine/include/tune-mips32.inc -MACHINE_KERNEL_PR = "r2" +MACHINE_KERNEL_PR = "r3" diff --git a/meta-openpli/recipes-bsp/etxx00/et-dvb-modules-et4x00.bb b/meta-openpli/recipes-bsp/etxx00/et-dvb-modules-et4x00.bb index 449d5352e5..d3fe610a1b 100644 --- a/meta-openpli/recipes-bsp/etxx00/et-dvb-modules-et4x00.bb +++ b/meta-openpli/recipes-bsp/etxx00/et-dvb-modules-et4x00.bb @@ -1,7 +1,7 @@ -KV = "3.4.3" -SRCDATE = "20120914" +KV = "3.6.0" +SRCDATE = "20121017" require et-dvb-modules.inc -SRC_URI[md5sum] = "6ca00409c7a95baec56eace4175dea18" -SRC_URI[sha256sum] = "49d2293f3ce58bcf8ce00cc3cb66a0aa9859af9fa0a2b387c34111fdc8568a30" +SRC_URI[md5sum] = "cb04a9043fcf6e081320d077ce0a23c5" +SRC_URI[sha256sum] = "be287bd9a9235d56b377bfca045d4ffc3866e0914456b69ce054a1423d73b0a0" diff --git a/meta-openpli/recipes-bsp/etxx00/et-dvb-modules-et5x00.bb b/meta-openpli/recipes-bsp/etxx00/et-dvb-modules-et5x00.bb index 569f1c6b6c..7781bc40cf 100644 --- a/meta-openpli/recipes-bsp/etxx00/et-dvb-modules-et5x00.bb +++ b/meta-openpli/recipes-bsp/etxx00/et-dvb-modules-et5x00.bb @@ -1,9 +1,9 @@ -KV = "3.4.3" -SRCDATE = "20120714" +KV = "3.6.0" +SRCDATE = "20121017" RDEPENDS_${PN} += "et-fpupdate-${MACHINE}" require et-dvb-modules.inc -SRC_URI[md5sum] = "b59841fdcecc93f59ec98da7ba2f434b" -SRC_URI[sha256sum] = "f37a8067c0c69e0efd8f993f6ec15bf1c5b038a33f3119872d6d437891b8329f" +SRC_URI[md5sum] = "7800d54ad9d930501baec006f94f2fd8" +SRC_URI[sha256sum] = "9081bca43d7e68b6be4e9ec3b3b1576d3f2ceffbb04f92e748727be46b6d1930" diff --git a/meta-openpli/recipes-bsp/etxx00/et-dvb-modules-et6x00.bb b/meta-openpli/recipes-bsp/etxx00/et-dvb-modules-et6x00.bb index 09cde90fee..2c5a104844 100644 --- a/meta-openpli/recipes-bsp/etxx00/et-dvb-modules-et6x00.bb +++ b/meta-openpli/recipes-bsp/etxx00/et-dvb-modules-et6x00.bb @@ -1,9 +1,9 @@ -KV = "3.4.3" -SRCDATE = "20120714" +KV = "3.6.0" +SRCDATE = "20121017" RDEPENDS_${PN} += "et-fpupdate-${MACHINE}" require et-dvb-modules.inc -SRC_URI[md5sum] = "c6875891e677750b730d6eab2633dc73" -SRC_URI[sha256sum] = "263eb4757d07ca9c35a0dcfa47fb98e26e718f65b5a08ea1a57c6ddfacf09262" +SRC_URI[md5sum] = "622d5034e8650db2751b469826f7b3c1" +SRC_URI[sha256sum] = "051a93ce27a3a573114982180b84ecfca2d5129808b94dbe873da2790e58031b" diff --git a/meta-openpli/recipes-bsp/etxx00/et-dvb-modules-et9x00.bb b/meta-openpli/recipes-bsp/etxx00/et-dvb-modules-et9x00.bb index 091afd1659..8680c0ef4f 100644 --- a/meta-openpli/recipes-bsp/etxx00/et-dvb-modules-et9x00.bb +++ b/meta-openpli/recipes-bsp/etxx00/et-dvb-modules-et9x00.bb @@ -1,9 +1,9 @@ -KV = "3.4.3" -SRCDATE = "20120714" +KV = "3.6.0" +SRCDATE = "20121017" RDEPENDS_${PN} += "et-fpupdate-${MACHINE}" require et-dvb-modules.inc -SRC_URI[md5sum] = "278e62da9a6944056afaa3565918285c" -SRC_URI[sha256sum] = "17bbee7617f213586211ba56b3975eda20ae5adfc40d036b64ee06efd551eeca" +SRC_URI[md5sum] = "ae460f5462b13c0904eddd72613121aa" +SRC_URI[sha256sum] = "0ef0950622147745cad2c2b986bf88acec0ac3cdfe32159d4e1a985c608262d8" diff --git a/meta-openpli/recipes-linux/linux/linux-etxx00/0001-Revert-MIPS-Add-fast-get_user_pages.patch b/meta-openpli/recipes-linux/linux/linux-etxx00/0001-Revert-MIPS-Add-fast-get_user_pages.patch index 0e2a48e947..63b1eced06 100644 --- a/meta-openpli/recipes-linux/linux/linux-etxx00/0001-Revert-MIPS-Add-fast-get_user_pages.patch +++ b/meta-openpli/recipes-linux/linux/linux-etxx00/0001-Revert-MIPS-Add-fast-get_user_pages.patch @@ -17,14 +17,13 @@ diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index 982420d..a02133f 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile -@@ -3,8 +3,8 @@ +@@ -2,8 +2,8 @@ # obj-y += cache.o dma-default.o extable.o fault.o \ -- gup.o init.o mmap.o page.o tlbex.o \ -- tlbex-fault.o uasm.o -+ init.o mmap.o tlbex.o tlbex-fault.o uasm.o \ -+ page.o +- gup.o init.o mmap.o page.o page-funcs.o \ ++ init.o mmap.o tlbex.o page.o page-funcs.o \ + tlbex.o tlbex-fault.o uasm.o obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o obj-$(CONFIG_64BIT) += pgtable-64.o diff --git a/meta-openpli/recipes-linux/linux/linux-etxx00/0001-Revert-MIPS-mm-Add-compound-tail-page-_mapcount-when.patch b/meta-openpli/recipes-linux/linux/linux-etxx00/0001-Revert-MIPS-mm-Add-compound-tail-page-_mapcount-when.patch new file mode 100644 index 0000000000..5a095554e4 --- /dev/null +++ b/meta-openpli/recipes-linux/linux/linux-etxx00/0001-Revert-MIPS-mm-Add-compound-tail-page-_mapcount-when.patch @@ -0,0 +1,27 @@ +From fcd1155354da4ac9c14471ca81ee9e2a53b73d76 Mon Sep 17 00:00:00 2001 +From: slashdev +Date: Fri, 12 Oct 2012 14:26:03 +0200 +Subject: [PATCH] Revert "MIPS: mm: Add compound tail page _mapcount when + mapped" + +This reverts commit af89fa3986b9d034a286544ab1ed95096496a2f9. +--- + arch/mips/mm/gup.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/arch/mips/mm/gup.c b/arch/mips/mm/gup.c +index dcfd573..33aadbc 100644 +--- a/arch/mips/mm/gup.c ++++ b/arch/mips/mm/gup.c +@@ -152,8 +152,6 @@ static int gup_huge_pud(pud_t pud, unsigned long addr, unsigned long end, + do { + VM_BUG_ON(compound_head(page) != head); + pages[*nr] = page; +- if (PageTail(page)) +- get_huge_page_tail(page); + (*nr)++; + page++; + refs++; +-- +1.7.9.5 + diff --git a/meta-openpli/recipes-linux/linux/linux-etxx00/cxd2820r-changed-condition-to-break-out-from-wait-lock-loop.patch b/meta-openpli/recipes-linux/linux/linux-etxx00/cxd2820r-changed-condition-to-break-out-from-wait-lock-loop.patch deleted file mode 100644 index ed6a07b46f..0000000000 --- a/meta-openpli/recipes-linux/linux/linux-etxx00/cxd2820r-changed-condition-to-break-out-from-wait-lock-loop.patch +++ /dev/null @@ -1,30 +0,0 @@ -Changed condition to break out from wait lock loop; -return DVBFE_ALGO_SEARCH_SUCCESS only if we have a lock; - -From: Gianluca Gennari ---- - drivers/media/dvb/frontends/cxd2820r_core.c | 4 ++-- - 1 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/media/dvb/frontends/cxd2820r_core.c b/drivers/media/dvb/frontends/cxd2820r_core.c -index 5c7c2aa..3bba37d 100644 ---- a/drivers/media/dvb/frontends/cxd2820r_core.c -+++ b/drivers/media/dvb/frontends/cxd2820r_core.c -@@ -526,12 +526,12 @@ static enum dvbfe_search cxd2820r_search(struct dvb_frontend *fe) - if (ret) - goto error; - -- if (status & FE_HAS_SIGNAL) -+ if (status & FE_HAS_LOCK) - break; - } - - /* check if we have a valid signal */ -- if (status) { -+ if (status & FE_HAS_LOCK) { - priv->last_tune_failed = 0; - return DVBFE_ALGO_SEARCH_SUCCESS; - } else { --- -1.7.5.4 - diff --git a/meta-openpli/recipes-linux/linux/linux-etxx00/cxd2820r-enable-LNA-for-DVB-T.patch b/meta-openpli/recipes-linux/linux/linux-etxx00/cxd2820r-enable-LNA-for-DVB-T.patch deleted file mode 100644 index eba734303d..0000000000 --- a/meta-openpli/recipes-linux/linux/linux-etxx00/cxd2820r-enable-LNA-for-DVB-T.patch +++ /dev/null @@ -1,24 +0,0 @@ -cxd2820r: enable LNA for DVB-T - -Signed-off-by: Gianluca Gennari ---- - drivers/media/video/em28xx/em28xx-dvb.c | 3 ++- - 1 files changed, 2 insertions(+), 1 deletions(-) - -diff --git a/drivers/media/video/em28xx/em28xx-dvb.c b/drivers/media/video/em28xx/em28xx-dvb.c -index 503a8d5..21f3e55 100644 ---- a/drivers/media/video/em28xx/em28xx-dvb.c -+++ b/drivers/media/video/em28xx/em28xx-dvb.c -@@ -542,7 +542,8 @@ static struct cxd2820r_config em28xx_cxd2820r_config = { - .i2c_address = (0xd8 >> 1), - .ts_mode = CXD2820R_TS_SERIAL, - -- /* enable LNA for DVB-T2 and DVB-C */ -+ /* enable LNA for DVB-T, DVB-T2 and DVB-C */ -+ .gpio_dvbt[0] = CXD2820R_GPIO_E | CXD2820R_GPIO_O | CXD2820R_GPIO_L, - .gpio_dvbt2[0] = CXD2820R_GPIO_E | CXD2820R_GPIO_O | CXD2820R_GPIO_L, - .gpio_dvbc[0] = CXD2820R_GPIO_E | CXD2820R_GPIO_O | CXD2820R_GPIO_L, - }; --- -1.7.0.4 - diff --git a/meta-openpli/recipes-linux/linux/linux-etxx00/dvb-usb-a867.patch b/meta-openpli/recipes-linux/linux/linux-etxx00/dvb-usb-a867.patch index 537c3903dc..2f596eca04 100644 --- a/meta-openpli/recipes-linux/linux/linux-etxx00/dvb-usb-a867.patch +++ b/meta-openpli/recipes-linux/linux/linux-etxx00/dvb-usb-a867.patch @@ -103,11 +103,11 @@ diff --git a/drivers/media/dvb/dvb-usb/Kconfig b/drivers/media/dvb/dvb-usb/Kconf index d3ffd16..20024c9 100644 --- a/drivers/media/dvb/dvb-usb/Kconfig +++ b/drivers/media/dvb/dvb-usb/Kconfig -@@ -434,3 +434,11 @@ config DVB_USB_RTL28XXU - select MEDIA_TUNER_MXL5005S if !MEDIA_TUNER_CUSTOMISE - help - Say Y here to support the Realtek RTL28xxU DVB USB receiver. -+ +@@ -434,4 +434,10 @@ config DVB_USB_AF9035 + select MEDIA_TUNER_TDA18218 if !MEDIA_TUNER_CUSTOMISE + help + Say Y here to support the Afatech AF9035 based DVB USB receiver. +- +config DVB_USB_A867 + tristate "Avermedia A867 DVB support" + depends on DVB_USB @@ -119,9 +119,9 @@ diff --git a/drivers/media/dvb/dvb-usb/Makefile b/drivers/media/dvb/dvb-usb/Make index 32489a8..7e2bcbd 100644 --- a/drivers/media/dvb/dvb-usb/Makefile +++ b/drivers/media/dvb/dvb-usb/Makefile -@@ -114,6 +114,12 @@ obj-$(CONFIG_DVB_USB_MXL111SF) += mxl111sf-tuner.o - dvb-usb-rtl28xxu-objs = rtl28xxu.o - obj-$(CONFIG_DVB_USB_RTL28XXU) += dvb-usb-rtl28xxu.o +@@ -113,6 +113,12 @@ obj-$(CONFIG_DVB_USB_RTL28XXU) += dvb-usb-rtl28xxu.o + dvb-usb-af9035-objs = af9035.o + obj-$(CONFIG_DVB_USB_AF9035) += dvb-usb-af9035.o +dvb-usb-a867-objs := a867_af903x-core.o a867_af903x-devices.o a867_af903x-drv.o \ + a867_af903x-fe.o a867_af903x-tuner.o a867_cmd.o a867_standard.o \ diff --git a/meta-openpli/recipes-linux/linux/linux-etxx00/dvb-usb-af9035.patch b/meta-openpli/recipes-linux/linux/linux-etxx00/dvb-usb-af9035.patch deleted file mode 100644 index 495207249c..0000000000 --- a/meta-openpli/recipes-linux/linux/linux-etxx00/dvb-usb-af9035.patch +++ /dev/null @@ -1,15543 +0,0 @@ -driver for af9035 devices; -added support for kernel 3.2; -fixed SNR report in Enigma2/Kaffeine: SNR is now -scaled in the full 0-65536 range; the snrdb module -parameter of the af9033 demodulator enables the SNR output -in dBx10 as before; -modified frontend driver to work directly with the DVBv5 -data structure, as required in new kernel/v4l versions; -added missing select directives for tuners tda18218 and mxl5007T -in dvb-usb/Kconfig; -imported USB VID/PID from the proprietary Avermedia A867 driver; -use C99-style initializers with symbolic names for each index -in the USB table af9035_usb_table; - -From: Gianluca Gennari ---- - drivers/media/common/tuners/Kconfig | 7 + - drivers/media/common/tuners/Makefile | 1 + - drivers/media/common/tuners/tua9001.c | 286 + - drivers/media/common/tuners/tua9001.h | 46 + - drivers/media/common/tuners/tua9001_priv.h | 53 + - drivers/media/dvb/dvb-usb/Kconfig | 12 + - drivers/media/dvb/dvb-usb/Makefile | 4 + - drivers/media/dvb/dvb-usb/af9035.c | 1273 ++++ - drivers/media/dvb/dvb-usb/af9035.h | 187 + - drivers/media/dvb/dvb-usb/dvb-usb-ids.h | 18 + - drivers/media/dvb/frontends/Kconfig | 7 + - drivers/media/dvb/frontends/Makefile | 1 + - drivers/media/dvb/frontends/af9033.c | 1957 +++++ - drivers/media/dvb/frontends/af9033.h | 100 + - drivers/media/dvb/frontends/af9033_priv.h | 383 + - drivers/media/dvb/frontends/af9033_reg.h |11006 ++++++++++++++++++++++++++++ - 16 files changed, 15341 insertions(+), 0 deletions(-) - create mode 100644 drivers/media/common/tuners/tua9001.c - create mode 100644 drivers/media/common/tuners/tua9001.h - create mode 100644 drivers/media/common/tuners/tua9001_priv.h - create mode 100644 drivers/media/dvb/dvb-usb/af9035.c - create mode 100644 drivers/media/dvb/dvb-usb/af9035.h - create mode 100644 drivers/media/dvb/frontends/af9033.c - create mode 100644 drivers/media/dvb/frontends/af9033.h - create mode 100644 drivers/media/dvb/frontends/af9033_priv.h - create mode 100644 drivers/media/dvb/frontends/af9033_reg.h - -diff --git a/drivers/media/common/tuners/Kconfig b/drivers/media/common/tuners/Kconfig -index 4a6d5ce..2dd7b00 100644 ---- a/drivers/media/common/tuners/Kconfig -+++ b/drivers/media/common/tuners/Kconfig -@@ -204,6 +204,13 @@ config MEDIA_TUNER_TDA18218 - help - NXP TDA18218 silicon tuner driver. - -+config MEDIA_TUNER_TUA9001 -+ tristate "Infineon OMNITUNE TUA 9001 silicon tuner" -+ depends on VIDEO_MEDIA && I2C -+ default m -+ help -+ A driver for the silicon tuner OMNITUNE TUA 9001 from Infineon. -+ - config MEDIA_TUNER_TDA18212 - tristate "NXP TDA18212 silicon tuner" - depends on VIDEO_MEDIA && I2C -diff --git a/drivers/media/common/tuners/Makefile b/drivers/media/common/tuners/Makefile -index f80407e..d134015 100644 ---- a/drivers/media/common/tuners/Makefile -+++ b/drivers/media/common/tuners/Makefile -@@ -27,6 +27,7 @@ obj-$(CONFIG_MEDIA_TUNER_MXL5007T) += mxl5007t.o - obj-$(CONFIG_MEDIA_TUNER_MC44S803) += mc44s803.o - obj-$(CONFIG_MEDIA_TUNER_MAX2165) += max2165.o - obj-$(CONFIG_MEDIA_TUNER_TDA18218) += tda18218.o -+obj-$(CONFIG_MEDIA_TUNER_TUA9001) += tua9001.o - obj-$(CONFIG_MEDIA_TUNER_TDA18212) += tda18212.o - - ccflags-y += -I$(srctree)/drivers/media/dvb/dvb-core -diff --git a/drivers/media/common/tuners/tua9001.c b/drivers/media/common/tuners/tua9001.c -new file mode 100644 -index 0000000..9db9362 ---- /dev/null -+++ b/drivers/media/common/tuners/tua9001.c -@@ -0,0 +1,286 @@ -+/* -+ * Infineon TUA 9001 silicon tuner driver -+ * -+ * Copyright (C) 2009 Antti Palosaari -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+ -+#include /* for kzalloc/kfree */ -+#include -+#include "tua9001.h" -+#include "tua9001_priv.h" -+ -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,0)) || ((defined V4L2_VERSION) && (V4L2_VERSION >= 197120)) -+/* all DVB frontend drivers now work directly with the DVBv5 -+ * structure. This warrants that all drivers will be -+ * getting/setting frontend parameters on a consistent way, in -+ * order to avoid copying data from/to the DVBv3 structs -+ * without need. -+ */ -+#define V4L2_ONLY_DVB_V5 -+#endif -+ -+static int debug; -+module_param(debug, int, 0644); -+MODULE_PARM_DESC(debug, "debug"); -+ -+/* write register */ -+static int tua9001_writereg(struct tua9001_priv *priv, u8 reg, u16 val) -+{ -+ u8 buf[3] = {reg, val >> 8, val & 0xff}; -+ struct i2c_msg msg = { .addr = priv->cfg->i2c_address, -+ .flags = 0, .buf = buf, .len = 3 }; -+ -+ if (i2c_transfer(priv->i2c, &msg, 1) != 1) { -+ err("I2C write failed, reg:%02x", reg); -+ return -EREMOTEIO; -+ } -+ return 0; -+} -+ -+static int tua9001_release(struct dvb_frontend *fe) -+{ -+ kfree(fe->tuner_priv); -+ fe->tuner_priv = NULL; -+ return 0; -+} -+ -+static int tua9001_init(struct dvb_frontend *fe) -+{ -+ struct tua9001_priv *priv = fe->tuner_priv; -+ int ret = 0; -+ u8 i; -+ struct regdesc data[] = { -+ {0x1e, 0x6512}, -+ {0x25, 0xb888}, -+ {0x39, 0x5460}, -+ {0x3b, 0x00c0}, -+ {0x3a, 0xf000}, -+ {0x08, 0x0000}, -+ {0x32, 0x0030}, -+ {0x41, 0x703a}, -+ {0x40, 0x1c78}, -+ {0x2c, 0x1c00}, -+ {0x36, 0xc013}, -+ {0x37, 0x6f18}, -+ {0x27, 0x0008}, -+ {0x2a, 0x0001}, -+ {0x34, 0x0a40}, -+ }; -+ -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c-gate */ -+ -+ for (i = 0; i < ARRAY_SIZE(data); i++) { -+ ret = tua9001_writereg(priv, data[i].reg, data[i].val); -+ if (ret) -+ break; -+ } -+ -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c-gate */ -+ -+ if (ret) -+ deb_info("%s: failed:%d\n", __func__, ret); -+ -+ return ret; -+} -+ -+#ifdef V4L2_ONLY_DVB_V5 -+static int tua9001_set_params(struct dvb_frontend *fe) -+{ -+ struct dtv_frontend_properties *params = &fe->dtv_property_cache; -+ struct tua9001_priv *priv = fe->tuner_priv; -+ int ret; -+ u16 val; -+ u32 freq; -+ u8 i; -+ struct regdesc data[2]; -+ -+ switch (params->bandwidth_hz) { -+#if 0 -+ case 5000000: -+ val = 0x3000; -+ break; -+#endif -+ case 6000000: -+ val = 0x2000; -+ break; -+ case 7000000: -+ val = 0x1000; -+ break; -+ case 8000000: -+ default: -+ val = 0x0000; -+ break; -+ } -+ -+ data[0].reg = 0x04; -+ data[0].val = val; -+ -+freq = params->frequency; -+ -+#define OFFSET 150000000 -+freq = freq - OFFSET; -+freq = freq/1000; -+freq = 48 * freq; -+freq = freq/1000; -+ -+val = freq; -+ -+ data[1].reg = 0x1f; -+ data[1].val = val; -+ -+ -+ deb_info("%s: freq:%d bw:%d freq tuner:%d val:%d\n", __func__, -+ params->frequency, params->bandwidth_hz, priv->frequency, -+ val); -+ -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c-gate */ -+ -+ for (i = 0; i < ARRAY_SIZE(data); i++) { -+ ret = tua9001_writereg(priv, data[i].reg, data[i].val); -+ if (ret) -+ break; -+ } -+ -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c-gate */ -+ -+ if (ret) -+ deb_info("%s: failed:%d\n", __func__, ret); -+ -+ return ret; -+} -+#else -+static int tua9001_set_params(struct dvb_frontend *fe, -+ struct dvb_frontend_parameters *params) -+{ -+ struct tua9001_priv *priv = fe->tuner_priv; -+ int ret; -+ u16 val; -+ u32 freq; -+ u8 i; -+ struct regdesc data[2]; -+ -+ switch (params->u.ofdm.bandwidth) { -+#if 0 -+ case BANDWIDTH_5_MHZ: -+ val = 0x3000; -+ break; -+#endif -+ case BANDWIDTH_6_MHZ: -+ val = 0x2000; -+ break; -+ case BANDWIDTH_7_MHZ: -+ val = 0x1000; -+ break; -+ case BANDWIDTH_8_MHZ: -+ default: -+ val = 0x0000; -+ break; -+ } -+ -+ data[0].reg = 0x04; -+ data[0].val = val; -+ -+freq = params->frequency; -+ -+#define OFFSET 150000000 -+freq = freq - OFFSET; -+freq = freq/1000; -+freq = 48 * freq; -+freq = freq/1000; -+ -+val = freq; -+ -+ data[1].reg = 0x1f; -+ data[1].val = val; -+ -+ -+ deb_info("%s: freq:%d bw:%d freq tuner:%d val:%d\n", __func__, -+ params->frequency, params->u.ofdm.bandwidth, priv->frequency, -+ val); -+ -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c-gate */ -+ -+ for (i = 0; i < ARRAY_SIZE(data); i++) { -+ ret = tua9001_writereg(priv, data[i].reg, data[i].val); -+ if (ret) -+ break; -+ } -+ -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c-gate */ -+ -+ if (ret) -+ deb_info("%s: failed:%d\n", __func__, ret); -+ -+ return ret; -+} -+#endif -+ -+static int tua9001_get_frequency(struct dvb_frontend *fe, u32 *frequency) -+{ -+ struct tua9001_priv *priv = fe->tuner_priv; -+ *frequency = priv->frequency; -+ return 0; -+} -+ -+static const struct dvb_tuner_ops tua9001_tuner_ops = { -+ .info = { -+ .name = "Infineon TUA 9001", -+ -+ .frequency_min = 170000000, -+ .frequency_max = 860000000, -+ .frequency_step = 0, -+ }, -+ -+ .release = tua9001_release, -+ .init = tua9001_init, -+ -+ .set_params = tua9001_set_params, -+ -+ .get_frequency = tua9001_get_frequency, -+}; -+ -+struct dvb_frontend * tua9001_attach(struct dvb_frontend *fe, -+ struct i2c_adapter *i2c, struct tua9001_config *cfg) -+{ -+ struct tua9001_priv *priv = NULL; -+ -+ priv = kzalloc(sizeof(struct tua9001_priv), GFP_KERNEL); -+ if (priv == NULL) -+ return NULL; -+ -+ priv->cfg = cfg; -+ priv->i2c = i2c; -+ -+ info("Infineon TUA 9001 successfully attached."); -+ -+ memcpy(&fe->ops.tuner_ops, &tua9001_tuner_ops, -+ sizeof(struct dvb_tuner_ops)); -+ -+ fe->tuner_priv = priv; -+ return fe; -+} -+EXPORT_SYMBOL(tua9001_attach); -+ -+MODULE_DESCRIPTION("Infineon TUA 9001 silicon tuner driver"); -+MODULE_AUTHOR("Antti Palosaari "); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/media/common/tuners/tua9001.h b/drivers/media/common/tuners/tua9001.h -new file mode 100644 -index 0000000..dd7298d ---- /dev/null -+++ b/drivers/media/common/tuners/tua9001.h -@@ -0,0 +1,46 @@ -+/* -+ * Infineon TUA 9001 silicon tuner driver -+ * -+ * Copyright (C) 2009 Antti Palosaari -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+ -+#ifndef TUA9001_H -+#define TUA9001_H -+ -+#include "dvb_frontend.h" -+ -+struct tua9001_config { -+ u8 i2c_address; -+}; -+ -+#if defined(DETACHED_TERRATEC_MODULES) || \ -+ defined(CONFIG_MEDIA_TUNER_TUA9001) || \ -+ (defined(CONFIG_MEDIA_TUNER_TUA9001_MODULE) && defined(MODULE)) -+extern struct dvb_frontend *tua9001_attach(struct dvb_frontend *fe, -+ struct i2c_adapter *i2c, -+ struct tua9001_config *cfg); -+#else -+static inline struct dvb_frontend *tua9001_attach(struct dvb_frontend *fe, -+ struct i2c_adapter *i2c, -+ struct tua9001_config *cfg) -+{ -+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); -+ return NULL; -+} -+#endif -+ -+#endif -diff --git a/drivers/media/common/tuners/tua9001_priv.h b/drivers/media/common/tuners/tua9001_priv.h -new file mode 100644 -index 0000000..7588df1 ---- /dev/null -+++ b/drivers/media/common/tuners/tua9001_priv.h -@@ -0,0 +1,53 @@ -+/* -+ * Infineon TUA 9001 silicon tuner driver -+ * -+ * Copyright (C) 2009 Antti Palosaari -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+ -+#ifndef TUA9001_PRIV_H -+#define TUA9001_PRIV_H -+ -+#define LOG_PREFIX "tua9001" -+ -+#define dprintk(var, level, args...) \ -+ do { \ -+ if ((var & level)) \ -+ printk(args); \ -+ } while (0) -+ -+#define deb_info(args...) dprintk(debug, 0x01, args) -+ -+#undef err -+#define err(f, arg...) printk(KERN_ERR LOG_PREFIX": " f "\n" , ## arg) -+#undef info -+#define info(f, arg...) printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg) -+#undef warn -+#define warn(f, arg...) printk(KERN_WARNING LOG_PREFIX": " f "\n" , ## arg) -+ -+struct regdesc { -+ u8 reg; -+ u16 val; -+}; -+ -+struct tua9001_priv { -+ struct tua9001_config *cfg; -+ struct i2c_adapter *i2c; -+ -+ u32 frequency; -+}; -+ -+#endif -diff --git a/drivers/media/dvb/dvb-usb/Kconfig b/drivers/media/dvb/dvb-usb/Kconfig -index b1019e6..972a500 100644 ---- a/drivers/media/dvb/dvb-usb/Kconfig -+++ b/drivers/media/dvb/dvb-usb/Kconfig -@@ -281,6 +281,7 @@ config DVB_USB_DW2102 - select DVB_CX24116 if !DVB_FE_CUSTOMISE - select DVB_SI21XX if !DVB_FE_CUSTOMISE - select DVB_TDA10023 if !DVB_FE_CUSTOMISE -+ select DVB_TDA10021 if !DVB_FE_CUSTOMISE - select DVB_MT312 if !DVB_FE_CUSTOMISE - select DVB_ZL10039 if !DVB_FE_CUSTOMISE - select DVB_DS3000 if !DVB_FE_CUSTOMISE -@@ -339,6 +340,17 @@ config DVB_USB_AF9015 - help - Say Y here to support the Afatech AF9015 based DVB-T USB2.0 receiver - -+config DVB_USB_AF9035 -+ tristate "Afatech AF9035 DVB-T USB2.0 support" -+ depends on DVB_USB -+ default m -+ select DVB_AF9033 -+ select MEDIA_TUNER_TUA9001 if !MEDIA_TUNER_CUSTOMISE -+ select MEDIA_TUNER_TDA18218 if !MEDIA_TUNER_CUSTOMISE -+ select MEDIA_TUNER_MXL5007T if !MEDIA_TUNER_CUSTOMISE -+ help -+ Say Y here to support the Afatech AF9035 based DVB-T USB2.0 receiver -+ - config DVB_USB_CE6230 - tristate "Intel CE6230 DVB-T USB2.0 support" - depends on DVB_USB -diff --git a/drivers/media/dvb/dvb-usb/Makefile b/drivers/media/dvb/dvb-usb/Makefile -index 797c1b8..7e2bcbd 100644 ---- a/drivers/media/dvb/dvb-usb/Makefile -+++ b/drivers/media/dvb/dvb-usb/Makefile -@@ -1,3 +1,4 @@ -+ - dvb-usb-objs = dvb-usb-firmware.o dvb-usb-init.o dvb-usb-urb.o dvb-usb-i2c.o dvb-usb-dvb.o dvb-usb-remote.o usb-urb.o - obj-$(CONFIG_DVB_USB) += dvb-usb.o - -@@ -99,6 +100,9 @@ obj-$(CONFIG_DVB_USB_LME2510) += dvb-usb-lmedm04.o - dvb-usb-technisat-usb2-objs = technisat-usb2.o - obj-$(CONFIG_DVB_USB_TECHNISAT_USB2) += dvb-usb-technisat-usb2.o - -+dvb-usb-af9035-objs = af9035.o -+obj-$(CONFIG_DVB_USB_AF9035) += dvb-usb-af9035.o -+ - dvb-usb-it913x-objs := it913x.o - obj-$(CONFIG_DVB_USB_IT913X) += dvb-usb-it913x.o - -diff --git a/drivers/media/dvb/dvb-usb/af9035.c b/drivers/media/dvb/dvb-usb/af9035.c -new file mode 100644 -index 0000000..c065cdf ---- /dev/null -+++ b/drivers/media/dvb/dvb-usb/af9035.c -@@ -0,0 +1,1273 @@ -+/* -+ * Afatech AF9035 DVB USB driver -+ * -+ * Copyright (C) 2008 Afatech -+ * Copyright (C) 2009 Antti Palosaari -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ * -+ * -+ * Thanks to TerraTec for a support received. -+ */ -+ -+#include "af9035.h" -+#include "af9033.h" -+#include "tua9001.h" -+#include "mxl5007t.h" -+#include "tda18218.h" -+#include -+ -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0)) || ((defined V4L2_VERSION) && (V4L2_VERSION >= 196608)) -+#define V4L2_REFACTORED_MFE_CODE -+#endif -+ -+static int dvb_usb_af9035_debug; -+module_param_named(debug, dvb_usb_af9035_debug, int, 0644); -+MODULE_PARM_DESC(debug, "set debugging level" DVB_USB_DEBUG_STATUS); -+DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); -+ -+static DEFINE_MUTEX(af9035_usb_mutex); -+ -+static struct af9035_config af9035_config; -+static struct dvb_usb_device_properties af9035_properties[1]; -+static int af9035_properties_count = ARRAY_SIZE(af9035_properties); -+ -+static struct af9033_config af9035_af9033_config[] = { -+ { -+ .demod_address = 0, -+ .tuner_address = 0, -+ .output_mode = AF9033_TS_MODE_USB, -+ }, { -+ .demod_address = 0, -+ .tuner_address = 0, -+ .output_mode = AF9033_TS_MODE_SERIAL, -+ } -+}; -+ -+static u8 regmask[8] = {0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x7f, 0xff}; -+ -+static int af9035_rw_udev(struct usb_device *udev, struct af9035_req *req) -+{ -+#define BUF_SIZE 63 -+ int act_len, ret; -+ u8 buf[BUF_SIZE]; -+ u32 msg_len; -+ static u8 seq; /* packet sequence number */ -+ u16 checksum = 0; -+ u8 i; -+ -+ /* buffer overflow check */ -+ if (req->wlen > (BUF_SIZE - 6) || req->rlen > (BUF_SIZE - 5)) { -+ err("too much data wlen:%d rlen:%d", req->wlen, req->rlen); -+ return -EINVAL; -+ } -+ -+ if (mutex_lock_interruptible(&af9035_usb_mutex) < 0) -+ return -EAGAIN; -+ -+ buf[0] = req->wlen + 3 + 2; /* 3 header + 2 checksum */ -+ buf[1] = req->mbox; -+ buf[2] = req->cmd; -+ buf[3] = seq++; -+ if (req->wlen) -+ memcpy(&buf[4], req->wbuf, req->wlen); -+ -+ /* calc and add checksum */ -+ for (i = 1; i < buf[0]-1; i++) { -+ if (i % 2) -+ checksum += buf[i] << 8; -+ else -+ checksum += buf[i]; -+ } -+ checksum = ~checksum; -+ -+ buf[buf[0]-1] = (checksum >> 8); -+ buf[buf[0]-0] = (checksum & 0xff); -+ -+ msg_len = buf[0]+1; -+ -+ deb_xfer(">>> "); -+ debug_dump(buf, msg_len, deb_xfer); -+ -+ /* send req */ -+ ret = usb_bulk_msg(udev, usb_sndbulkpipe(udev, 0x02), buf, msg_len, -+ &act_len, AF9035_USB_TIMEOUT); -+ if (ret) -+ err("bulk message failed:%d (%d/%d)", ret, msg_len, act_len); -+ else -+ if (act_len != msg_len) -+ ret = -EIO; /* all data is not send */ -+ if (ret) -+ goto error_unlock; -+ -+ /* no ack for those packets */ -+ if (req->cmd == CMD_FW_DOWNLOAD) -+ goto exit_unlock; -+ -+ /* receive ack and data if read req */ -+ msg_len = 3 + req->rlen + 2; /* data len + status + seq + checksum */ -+ ret = usb_bulk_msg(udev, usb_rcvbulkpipe(udev, 0x81), buf, msg_len, -+ &act_len, AF9035_USB_TIMEOUT); -+ if (ret) { -+ err("recv bulk message failed:%d", ret); -+ ret = -EIO; -+ goto error_unlock; -+ } -+ -+ deb_xfer("<<< "); -+ debug_dump(buf, act_len, deb_xfer); -+ -+ /* check status */ -+ if (buf[2]) { -+ err("command:%02x failed:%d", req->cmd, buf[2]); -+ ret = -EIO; -+ goto error_unlock; -+ } -+ -+ /* read request, copy returned data to return buf */ -+ if (req->rlen) -+ memcpy(req->rbuf, &buf[3], req->rlen); -+error_unlock: -+exit_unlock: -+ mutex_unlock(&af9035_usb_mutex); -+ -+ return ret; -+} -+ -+static int af9035_write_regs_bis(struct usb_device *d, u8 mbox, u16 reg, -+u8 *val, u8 len) -+{ -+ u8 wbuf[6+len]; -+ struct af9035_req req = {CMD_REG_DEMOD_WRITE, mbox, sizeof(wbuf), wbuf, -+ 0, NULL}; -+ wbuf[0] = len; -+ wbuf[1] = 2; -+ wbuf[2] = 0; -+ wbuf[3] = 0; -+ wbuf[4] = reg >> 8; -+ wbuf[5] = reg & 0xff; -+ memcpy(&wbuf[6], val, len); -+ return af9035_rw_udev(d, &req); -+} -+ -+static int af9035_write_regs(struct dvb_usb_device *d, u8 mbox, u16 reg, -+u8 *val, u8 len) -+{ -+ return af9035_write_regs_bis(d->udev, mbox, reg, val, len); -+} -+ -+static int af9035_read_regs_bis(struct usb_device *d, u8 mbox, u16 reg, u8 *val, -+ u8 len) -+{ -+ u8 wbuf[] = {len, 2, 0, 0, reg >> 8, reg & 0xff}; -+ struct af9035_req req = {CMD_REG_DEMOD_READ, mbox, sizeof(wbuf), wbuf, -+ len, val}; -+ return af9035_rw_udev(d, &req); -+} -+ -+static int af9035_read_regs(struct dvb_usb_device *d, u8 mbox, u16 reg, u8 *val, -+ u8 len) -+{ -+ return af9035_read_regs_bis(d->udev, mbox, reg, val, len); -+} -+ -+static int af9035_write_reg_bis(struct usb_device *d, u8 mbox, u16 reg, u8 val) -+{ -+ return af9035_write_regs_bis(d, mbox, reg, &val, 1); -+} -+ -+static int af9035_write_reg(struct dvb_usb_device *d, u8 mbox, u16 reg, u8 val) -+{ -+ return af9035_write_regs_bis(d->udev, mbox, reg, &val, 1); -+} -+ -+static int af9035_read_reg_bis(struct usb_device *d, u8 mbox, u16 reg, u8 *val) -+{ -+ return af9035_read_regs_bis(d, mbox, reg, val, 1); -+} -+ -+static int af9035_write_reg_bits_bis(struct usb_device *d, u8 mbox, u16 reg, -+ u8 pos, u8 len, u8 val) -+{ -+ int ret; -+ u8 tmp, mask; -+ -+ ret = af9035_read_reg_bis(d, mbox, reg, &tmp); -+ if (ret) -+ return ret; -+ -+ mask = regmask[len - 1] << pos; -+ tmp = (tmp & ~mask) | ((val << pos) & mask); -+ -+ return af9035_write_reg_bis(d, mbox, reg, tmp); -+} -+ -+static int af9035_write_reg_bits(struct dvb_usb_device *d, u8 mbox, u16 reg, -+ u8 pos, u8 len, u8 val) -+{ -+ return af9035_write_reg_bits_bis(d->udev, mbox, reg, pos, len, val); -+} -+ -+static int af9035_read_reg_bits_bis(struct usb_device *d, u8 mbox, u16 reg, -+ u8 pos, u8 len, u8 *val) -+{ -+ int ret; -+ u8 tmp; -+ -+ ret = af9035_read_reg_bis(d, mbox, reg, &tmp); -+ if (ret) -+ return ret; -+ *val = (tmp >> pos) & regmask[len - 1]; -+ return 0; -+} -+ -+static int af9035_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], -+ int num) -+{ -+ struct dvb_usb_device *d = i2c_get_adapdata(adap); -+ int ret = 0, i = 0; -+ u16 reg; -+ u8 mbox; -+ -+ if (mutex_lock_interruptible(&d->i2c_mutex) < 0) -+ return -EAGAIN; -+ -+ while (i < num) { -+ mbox = msg[i].buf[0]; -+ reg = msg[i].buf[1] << 8; -+ reg += msg[i].buf[2]; -+ if (num > i + 1 && (msg[i+1].flags & I2C_M_RD)) { -+ if (msg[i].addr == -+ af9035_af9033_config[0].demod_address || -+ msg[i].addr == -+ af9035_af9033_config[1].demod_address) { -+ if (af9035_af9033_config[1].demod_address && (msg[i].addr == af9035_af9033_config[1].demod_address)) -+ mbox += 0x10; -+ ret = af9035_read_regs(d, mbox, reg, -+ &msg[i+1].buf[0], msg[i+1].len); -+ } else { -+ /* FIXME */ -+ u8 wbuf[5]; -+ u8 rbuf[BUF_SIZE]; -+ struct af9035_req req = {CMD_REG_TUNER_READ, -+ LINK, sizeof(wbuf), wbuf, msg[i + 1].len, -+ rbuf}; -+ if (af9035_af9033_config[1].tuner_address && -+ (msg[i].addr == af9035_af9033_config[1].tuner_address)) { -+ msg[i].addr = af9035_af9033_config[0].tuner_address; -+ req.mbox += 0x10; -+ } -+ wbuf[0] = msg[i + 1].len; /* read len */ -+ wbuf[1] = msg[i].addr; /* tuner i2c addr */ -+ wbuf[2] = 0x01; /* reg width */ -+ wbuf[3] = 0x00; /* reg MSB */ -+ wbuf[4] = msg[i].buf[0]; /* reg LSB */ -+ ret = af9035_rw_udev(d->udev, &req); -+ memcpy (msg[i + 1].buf, rbuf, msg[i + 1].len); -+ } -+ i += 2; -+ } else { -+ if (msg[i].addr == -+ af9035_af9033_config[0].demod_address || -+ msg[i].addr == -+ af9035_af9033_config[1].demod_address) { -+ if (af9035_af9033_config[1].demod_address && (msg[i].addr == af9035_af9033_config[1].demod_address)) -+ mbox += 0x10; -+ ret = af9035_write_regs(d, mbox, reg, -+ &msg[i].buf[3], msg[i].len-3); -+ } else { -+ u8 wbuf[BUF_SIZE]; -+ struct af9035_req req = {CMD_REG_TUNER_WRITE, -+ LINK, 4 + msg[i].len, wbuf, 0, NULL}; -+ if (af9035_af9033_config[1].tuner_address && -+ (msg[i].addr == af9035_af9033_config[1].tuner_address)) { -+ msg[i].addr = af9035_af9033_config[0].tuner_address; -+ req.mbox += 0x10; -+ } -+ wbuf[0] = msg[i].len - 1; /* write len */ -+ wbuf[1] = msg[i].addr; /* tuner i2c addr */ -+ wbuf[2] = 0x01; /* reg width */ -+ wbuf[3] = 0x00; /* reg MSB */ -+ memcpy (&wbuf[4], msg[i].buf, msg[i].len); -+ ret = af9035_rw_udev(d->udev, &req); -+ } -+ i += 1; -+ } -+ if (ret) -+ goto error; -+ -+ } -+ ret = i; -+error: -+ mutex_unlock(&d->i2c_mutex); -+ -+ return ret; -+} -+ -+static u32 af9035_i2c_func(struct i2c_adapter *adapter) -+{ -+ return I2C_FUNC_I2C; -+} -+ -+static struct i2c_algorithm af9035_i2c_algo = { -+ .master_xfer = af9035_i2c_xfer, -+ .functionality = af9035_i2c_func, -+#ifdef NEED_ALGO_CONTROL -+ .algo_control = dummy_algo_control, -+#endif -+}; -+ -+static int af9035_init_endpoint(struct dvb_usb_device *d) -+{ -+ int ret; -+ u16 frame_size; -+ u8 packet_size; -+ -+ if (d->udev->speed == USB_SPEED_FULL) { -+ frame_size = TS_USB11_FRAME_SIZE/4; -+ packet_size = TS_USB11_MAX_PACKET_SIZE/4; -+ } else { -+ frame_size = TS_USB20_FRAME_SIZE/4; -+ packet_size = TS_USB20_MAX_PACKET_SIZE/4; -+ } -+ -+ deb_info("%s: USB speed:%d frame_size:%04x packet_size:%02x\n", -+ __func__, d->udev->speed, frame_size, packet_size); -+ -+ /* enable EP4 reset */ -+ ret = af9035_write_reg_bits(d, OFDM, p_reg_mp2_sw_rst, -+ reg_mp2_sw_rst_pos, reg_mp2_sw_rst_len, 1); -+ if (ret) -+ goto error; -+ -+ /* enable EP5 reset */ -+ ret = af9035_write_reg_bits(d, OFDM, p_reg_mp2if2_sw_rst, -+ reg_mp2if2_sw_rst_pos, reg_mp2if2_sw_rst_len, 1); -+ if (ret) -+ goto error; -+ -+ /* disable EP4 */ -+ ret = af9035_write_reg_bits(d, LINK, p_reg_ep4_tx_en, -+ reg_ep4_tx_en_pos, reg_ep4_tx_en_len, 0); -+ if (ret) -+ goto error; -+ -+ /* disable EP5 */ -+ ret = af9035_write_reg_bits(d, LINK, p_reg_ep5_tx_en, -+ reg_ep5_tx_en_pos, reg_ep5_tx_en_len, 0); -+ if (ret) -+ goto error; -+ -+ /* disable EP4 NAK */ -+ ret = af9035_write_reg_bits(d, LINK, p_reg_ep4_tx_nak, -+ reg_ep4_tx_nak_pos, reg_ep4_tx_nak_len, 0); -+ if (ret) -+ goto error; -+ -+ /* disable EP5 NAK */ -+ ret = af9035_write_reg_bits(d, LINK, p_reg_ep5_tx_nak, -+ reg_ep5_tx_nak_pos, reg_ep5_tx_nak_len, 0); -+ if (ret) -+ goto error; -+ -+ /* enable EP4 */ -+ ret = af9035_write_reg_bits(d, LINK, p_reg_ep4_tx_en, -+ reg_ep4_tx_en_pos, reg_ep4_tx_en_len, 1); -+ if (ret) -+ goto error; -+ -+ /* EP4 xfer length */ -+ ret = af9035_write_regs(d, LINK, p_reg_ep4_tx_len_7_0, -+ (u8 *) &frame_size, sizeof(frame_size)); -+ if (ret) -+ goto error; -+ -+ /* EP4 packet size */ -+ ret = af9035_write_reg(d, LINK, p_reg_ep4_max_pkt, packet_size); -+ if (ret) -+ goto error; -+ -+ /* configure EP5 for dual mode */ -+ if (af9035_config.dual_mode) { -+ /* enable EP5 */ -+ ret = af9035_write_reg_bits(d, LINK, p_reg_ep5_tx_en, -+ reg_ep5_tx_en_pos, reg_ep5_tx_en_len, 1); -+ if (ret) -+ goto error; -+ -+ /* EP5 xfer length */ -+ ret = af9035_write_regs(d, LINK, p_reg_ep5_tx_len_7_0, -+ (u8 *) &frame_size, sizeof(frame_size)); -+ if (ret) -+ goto error; -+ -+ /* EP5 packet size */ -+ ret = af9035_write_reg(d, LINK, p_reg_ep5_max_pkt, packet_size); -+ if (ret) -+ goto error; -+ } -+ -+ /* enable / disable mp2if2 */ -+ ret = af9035_write_reg_bits(d, OFDM, p_reg_mp2if2_en, -+ reg_mp2if2_en_pos, reg_mp2if2_en_len, af9035_config.dual_mode); -+ if (ret) -+ goto error; -+ -+ /* enable / disable tsis */ -+ ret = af9035_write_reg_bits(d, OFDM, p_reg_tsis_en, reg_tsis_en_pos, -+ reg_tsis_en_len, af9035_config.dual_mode); -+ if (ret) -+ goto error; -+ -+ /* negate EP4 reset */ -+ ret = af9035_write_reg_bits(d, OFDM, p_reg_mp2_sw_rst, -+ reg_mp2_sw_rst_pos, reg_mp2_sw_rst_len, 0); -+ if (ret) -+ goto error; -+ -+ /* negate EP5 reset */ -+ ret = af9035_write_reg_bits(d, OFDM, p_reg_mp2if2_sw_rst, -+ reg_mp2if2_sw_rst_pos, reg_mp2if2_sw_rst_len, 0); -+ if (ret) -+ goto error; -+ -+error: -+ if (ret) -+ err("endpoint init failed:%d", ret); -+ return ret; -+} -+ -+static int af9035_init(struct dvb_usb_device *d) -+{ -+ int ret; -+ deb_info("%s:\n", __func__); -+ -+ ret = af9035_init_endpoint(d); -+ if (ret) -+ goto error; -+error: -+ return ret; -+} -+ -+static int af9035_download_firmware(struct usb_device *udev, -+ const struct firmware *fw) -+{ -+ u8 *fw_data_ptr = (u8 *) fw->data; -+ int i, j, len, packets, remainder, ret; -+ u8 wbuf[1]; -+ u8 rbuf[4]; -+ struct af9035_firmware_header fw_hdr; -+ struct af9035_req req = {0, LINK, 0, NULL, 1, rbuf}; -+ struct af9035_req req_fw_dl = {CMD_FW_DOWNLOAD, LINK, 0, NULL, 0, NULL}; -+ struct af9035_req req_rom = {CMD_SCATTER_WRITE, LINK, 0, NULL, 1, rbuf}; -+ struct af9035_req req_fw_ver = {CMD_QUERYINFO, LINK, 1, wbuf, 4, rbuf}; -+ -+ /* read firmware segment info from beginning of the firmware file */ -+ fw_hdr.segment_count = *fw_data_ptr++; -+ deb_info("%s: fw segment count:%d\n", __func__, fw_hdr.segment_count); -+ if (fw_hdr.segment_count > SEGMENT_MAX_COUNT) { -+ warn("too big firmware segmen count:%d", fw_hdr.segment_count); -+ fw_hdr.segment_count = SEGMENT_MAX_COUNT; -+ } -+ for (i = 0; i < fw_hdr.segment_count; i++) { -+ fw_hdr.segment[i].type = (*fw_data_ptr++); -+ fw_hdr.segment[i].len = (*fw_data_ptr++) << 24; -+ fw_hdr.segment[i].len += (*fw_data_ptr++) << 16; -+ fw_hdr.segment[i].len += (*fw_data_ptr++) << 8; -+ fw_hdr.segment[i].len += (*fw_data_ptr++) << 0; -+ deb_info("%s: fw segment type:%d len:%d\n", __func__, -+ fw_hdr.segment[i].type, fw_hdr.segment[i].len); -+ } -+ -+ #define FW_PACKET_MAX_DATA 57 /* 63-4-2, packet_size-header-checksum */ -+ -+ /* download all segments */ -+ for (i = 0; i < fw_hdr.segment_count; i++) { -+ deb_info("%s: segment type:%d\n", __func__, -+ fw_hdr.segment[i].type); -+ if (fw_hdr.segment[i].type == SEGMENT_FW_DOWNLOAD) { -+ /* download begin packet */ -+ req.cmd = CMD_FW_DOWNLOAD_BEGIN; -+ ret = af9035_rw_udev(udev, &req); -+ if (ret) { -+ err("firmware download failed:%d", ret); -+ goto error; -+ } -+ -+ packets = fw_hdr.segment[i].len / FW_PACKET_MAX_DATA; -+ remainder = fw_hdr.segment[i].len % FW_PACKET_MAX_DATA; -+ len = FW_PACKET_MAX_DATA; -+ for (j = 0; j <= packets; j++) { -+ if (j == packets) /* size of the last packet */ -+ len = remainder; -+ -+ req_fw_dl.wlen = len; -+ req_fw_dl.wbuf = fw_data_ptr; -+ ret = af9035_rw_udev(udev, &req_fw_dl); -+ if (ret) { -+ err("firmware download failed at " \ -+ "segment:%d packet:%d err:%d", \ -+ i, j, ret); -+ goto error; -+ } -+ fw_data_ptr += len; -+ } -+ /* download end packet */ -+ req.cmd = CMD_FW_DOWNLOAD_END; -+ ret = af9035_rw_udev(udev, &req); -+ if (ret) { -+ err("firmware download failed:%d", ret); -+ goto error; -+ } -+ } else if (fw_hdr.segment[i].type == SEGMENT_ROM_COPY){ -+ packets = fw_hdr.segment[i].len / FW_PACKET_MAX_DATA; -+ remainder = fw_hdr.segment[i].len % FW_PACKET_MAX_DATA; -+ len = FW_PACKET_MAX_DATA; -+ for (j = 0; j <= packets; j++) { -+ if (j == packets) /* size of the last packet */ -+ len = remainder; -+ -+ req_rom.wlen = len; -+ req_rom.wbuf = fw_data_ptr; -+ ret = af9035_rw_udev(udev, &req_rom); -+ if (ret) { -+ err("firmware download failed at " \ -+ "segment:%d packet:%d err:%d", \ -+ i, j, ret); -+ goto error; -+ } -+ fw_data_ptr += len; -+ } -+ } else { -+ deb_info("%s: segment type:%d not implemented\n", -+ __func__, fw_hdr.segment[i].type); -+ } -+ } -+ -+ /* firmware loaded, request boot */ -+ req.cmd = CMD_BOOT; -+ ret = af9035_rw_udev(udev, &req); -+ if (ret) -+ goto error; -+ -+ /* ensure firmware starts */ -+ wbuf[0] = 1; -+ ret = af9035_rw_udev(udev, &req_fw_ver); -+ if (ret) -+ goto error; -+ -+ deb_info("%s: reply:%02x %02x %02x %02x\n", __func__, -+ rbuf[0], rbuf[1], rbuf[2], rbuf[3]); -+ -+ if (!(rbuf[0] || rbuf[1] || rbuf[2] || rbuf[3])) { -+ err("firmware did not run"); -+ ret = -EIO; -+ } -+ -+error: -+ if (ret) -+ deb_info("%s: failed:%d\n", __func__, ret); -+ -+ return ret; -+} -+ -+static int af9035_read_eeprom_reg(struct usb_device *udev, u16 reg, u8 *val) -+{ -+ u8 wbuf[] = {1, 2, 0, 0, reg >> 8, reg & 0xff}; -+ struct af9035_req req = {CMD_REG_DEMOD_READ, LINK, sizeof(wbuf), wbuf, -+ 1, val}; -+ return af9035_rw_udev(udev, &req); -+} -+ -+static int af9035_read_config(struct usb_device *udev) -+{ -+ int ret; -+ u8 val, i, offset = 0; -+ -+ /* IR remote controller */ -+ ret = af9035_read_eeprom_reg(udev, EEPROM_IR_MODE, &val); -+ if (ret) -+ goto error; -+ deb_info("%s: IR mode:%d\n", __func__, val); -+ -+ /* TS mode - one or two receivers */ -+ ret = af9035_read_eeprom_reg(udev, EEPROM_TS_MODE, &val); -+ if (ret) -+ goto error; -+ af9035_config.dual_mode = val; -+ deb_info("%s: TS mode:%d\n", __func__, af9035_config.dual_mode); -+ -+ /* Set adapter0 buffer size according to USB port speed, adapter1 buffer -+ size can be static because it is enabled only USB2.0 */ -+ for (i = 0; i < af9035_properties_count; i++) { -+ /* USB1.1 set smaller buffersize and disable 2nd adapter */ -+ if (udev->speed == USB_SPEED_FULL) { -+#ifdef V4L2_REFACTORED_MFE_CODE -+ af9035_properties[i].adapter[0].fe[0].stream.u.bulk.buffersize -+#else -+ af9035_properties[i].adapter[0].stream.u.bulk.buffersize -+#endif -+ = TS_USB11_MAX_PACKET_SIZE; -+ /* disable 2nd adapter because we don't have -+ PID-filters */ -+ af9035_config.dual_mode = 0; -+ } else { -+#ifdef V4L2_REFACTORED_MFE_CODE -+ af9035_properties[i].adapter[0].fe[0].stream.u.bulk.buffersize -+#else -+ af9035_properties[i].adapter[0].stream.u.bulk.buffersize -+#endif -+ = TS_USB20_FRAME_SIZE; -+ } -+ } -+ -+ if (af9035_config.dual_mode) { -+ /* read 2nd demodulator I2C address */ -+ ret = af9035_read_eeprom_reg(udev, EEPROM_2WIREADDR, &val); -+ if (ret) -+ goto error; -+ deb_info("%s: 2nd demod I2C addr:%02x\n", __func__, val); -+ af9035_af9033_config[1].demod_address = val; -+ /* enable 2nd adapter */ -+ for (i = 0; i < af9035_properties_count; i++) -+ af9035_properties[i].num_adapters = 2; -+ } else { -+ /* disable 2nd adapter */ -+ for (i = 0; i < af9035_properties_count; i++) -+ af9035_properties[i].num_adapters = 1; -+ } -+ -+ for (i = 0; i < af9035_properties[0].num_adapters; i++) { -+ if (i == 1) -+ offset = EEPROM_SHIFT; -+ -+ /* saw BW */ -+ ret = af9035_read_eeprom_reg(udev, EEPROM_SAW_BW1 + offset, -+ &val); -+ if (ret) -+ goto error; -+ deb_info("%s: [%d] saw BW:%d\n", __func__, i, val); -+ -+ /* xtal */ -+ ret = af9035_read_eeprom_reg(udev, EEPROM_XTAL1 + offset, &val); -+ if (ret) -+ goto error; -+ deb_info("%s: [%d] xtal:%d\n", __func__, i, val); -+ -+ /* RF spectrum inversion */ -+ ret = af9035_read_eeprom_reg(udev, EEPROM_SPECINV1 + offset, -+ &val); -+ if (ret) -+ goto error; -+ deb_info("%s: [%d] RF spectrum inv:%d\n", __func__, i, val); -+ -+ /* IF */ -+ ret = af9035_read_eeprom_reg(udev, EEPROM_IFFREQH1 + offset, -+ &val); -+ if (ret) -+ goto error; -+ af9035_af9033_config[i].if_freq = val << 8; -+ ret = af9035_read_eeprom_reg(udev, EEPROM_IFFREQL1 + offset, -+ &val); -+ if (ret) -+ goto error; -+ af9035_af9033_config[i].if_freq += val; -+ deb_info("%s: [%d] IF:%d\n", __func__, i, -+ af9035_af9033_config[0].if_freq); -+ -+ /* MT2060 IF1 */ -+ ret = af9035_read_eeprom_reg(udev, EEPROM_IF1H1 + offset, &val); -+ if (ret) -+ goto error; -+ af9035_config.mt2060_if1[i] = val << 8; -+ ret = af9035_read_eeprom_reg(udev, EEPROM_IF1L1 + offset, &val); -+ if (ret) -+ goto error; -+ af9035_config.mt2060_if1[i] += val; -+ deb_info("%s: [%d] MT2060 IF1:%d\n", __func__, i, -+ af9035_config.mt2060_if1[i]); -+ -+ /* tuner */ -+ ret = af9035_read_eeprom_reg(udev, EEPROM_TUNER_ID1 + offset, -+ &val); -+ if (ret) -+ goto error; -+ switch (val) { -+ case AF9033_TUNER_TUA9001: -+ af9035_af9033_config[i].rf_spec_inv = 1; -+ break; -+ case AF9033_TUNER_MXL5007t: -+ af9035_af9033_config[i].rf_spec_inv = 1; -+ break; -+ case AF9033_TUNER_TDA18218: -+ af9035_af9033_config[i].rf_spec_inv = 1; -+ break; -+ default: -+ warn("tuner ID:%d not supported, please report!", val); -+ return -ENODEV; -+ }; -+ -+ af9035_af9033_config[i].tuner = val; -+ deb_info("%s: [%d] tuner ID:%d\n", __func__, i, val); -+ } -+ -+error: -+ if (ret) -+ err("eeprom read failed:%d", ret); -+ -+ if (le16_to_cpu(udev->descriptor.idVendor) == USB_VID_AVERMEDIA) { -+ switch (le16_to_cpu(udev->descriptor.idProduct)) { -+ case USB_PID_AVERMEDIA_A825: -+ case USB_PID_AVERMEDIA_A835: -+ case USB_PID_AVERMEDIA_B835: -+ case USB_PID_AVERMEDIA_A333: -+ case USB_PID_AVERMEDIA_B867: -+ case USB_PID_AVERMEDIA_1867: -+ case USB_PID_AVERMEDIA_0337: -+ case USB_PID_AVERMEDIA_A867: -+ case USB_PID_AVERMEDIA_0867: -+ case USB_PID_AVERMEDIA_F337: -+ case USB_PID_AVERMEDIA_3867: -+ deb_info("%s: AverMedia A825/A835/B835/A333/A867: overriding config\n", __func__); -+ /* set correct IF */ -+ for (i = 0; i < af9035_properties[0].num_adapters; i++) { -+ af9035_af9033_config[i].if_freq = 4570000; -+ } -+ break; -+ default: -+ break; -+ } -+ } -+ -+ return ret; -+} -+ -+static int af9035_aux_init(struct usb_device *d) -+{ -+ int ret; -+ u8 tmp, i; -+ -+ /* get demod crystal and ADC freqs */ -+ ret = af9035_read_reg_bits_bis(d, LINK, -+ r_io_mux_pwron_clk_strap, io_mux_pwron_clk_strap_pos, -+ io_mux_pwron_clk_strap_len, &tmp); -+ if (ret) -+ goto error; -+ -+ for (i = 0; i < af9035_properties[0].num_adapters; i++) { -+ af9035_af9033_config[i].crystal_clock = -+ clock_table[tmp].crystal; -+ af9035_af9033_config[i].adc_clock = -+ clock_table[tmp].adc; -+ } -+ -+ /* write 2nd demod I2C address to device */ -+ ret = af9035_write_reg_bis(d, LINK, 0x417f, -+ af9035_af9033_config[1].demod_address); -+ if (ret) -+ goto error; -+ -+ /* enable / disable clock out for 2nd demod for power saving */ -+ ret = af9035_write_reg_bis(d, LINK, p_reg_top_clkoen, -+ af9035_config.dual_mode); -+ -+error: -+ return ret; -+} -+ -+static int af9035_identify_state(struct usb_device *udev, -+ struct dvb_usb_device_properties *props, -+ struct dvb_usb_device_description **desc, -+ int *cold) -+{ -+ int ret; -+ u8 wbuf[1] = {1}; -+ u8 rbuf[4]; -+ struct af9035_req req = {CMD_QUERYINFO, 0, sizeof(wbuf), wbuf, -+ sizeof(rbuf), rbuf}; -+ -+ ret = af9035_rw_udev(udev, &req); -+ if (ret) -+ return ret; -+ -+ deb_info("%s: reply:%02x %02x %02x %02x\n", __func__, -+ rbuf[0], rbuf[1], rbuf[2], rbuf[3]); -+ if (rbuf[0] || rbuf[1] || rbuf[2] || rbuf[3]) -+ *cold = 0; -+ else -+ *cold = 1; -+ -+ return ret; -+} -+ -+static int af9035_af9033_frontend_attach(struct dvb_usb_adapter *adap) -+{ -+ /* attach demodulator */ -+#ifdef V4L2_REFACTORED_MFE_CODE -+ adap->fe_adap[0].fe = dvb_attach(af9033_attach, &af9035_af9033_config[adap->id], -+ &adap->dev->i2c_adap); -+ -+ return adap->fe_adap[0].fe == NULL ? -ENODEV : 0; -+#else -+ adap->fe = dvb_attach(af9033_attach, &af9035_af9033_config[adap->id], -+ &adap->dev->i2c_adap); -+ -+ return adap->fe == NULL ? -ENODEV : 0; -+#endif -+} -+ -+static struct tua9001_config af9035_tua9001_config[] = { -+ { -+ .i2c_address = 0xc0, -+ } , { -+ .i2c_address = 0xc1, -+ } -+}; -+ -+static struct mxl5007t_config af9035_mxl5007t_config[] = { -+ { -+ .xtal_freq_hz = MxL_XTAL_24_MHZ, -+ .if_freq_hz = MxL_IF_4_57_MHZ, -+ .invert_if = 0, -+ .loop_thru_enable = 0, -+ .clk_out_enable = 0, -+ .clk_out_amp = MxL_CLKOUT_AMP_0_94V, -+ } , { -+ .xtal_freq_hz = MxL_XTAL_24_MHZ, -+ .if_freq_hz = MxL_IF_4_57_MHZ, -+ .invert_if = 0, -+ .loop_thru_enable = 1, -+ .clk_out_enable = 1, -+ .clk_out_amp = MxL_CLKOUT_AMP_0_94V, -+ } -+}; -+ -+static struct tda18218_config af9035_tda18218_config[] = { -+ { -+ .i2c_address = 0xc0, -+ .i2c_wr_max = 21, /* max wr bytes AF9015 I2C adap can handle at once */ -+ } , { -+ .i2c_address = 0xc1, -+ .i2c_wr_max = 21, /* max wr bytes AF9015 I2C adap can handle at once */ -+ } -+}; -+ -+static int af9035_tuner_attach(struct dvb_usb_adapter *adap) -+{ -+ int ret; -+ deb_info("%s: \n", __func__); -+ -+ switch (af9035_af9033_config[adap->id].tuner) { -+ case AF9033_TUNER_TUA9001: -+ af9035_af9033_config[adap->id].tuner_address = af9035_tua9001_config[adap->id].i2c_address; -+ af9035_af9033_config[adap->id].tuner_address += adap->id; -+ if (adap->id == 0) { -+ /* gpiot3 TUA9001 RESETN -+ gpiot2 TUA9001 RXEN */ -+ ret = af9035_write_reg_bits(adap->dev, LINK, -+ p_reg_top_gpiot2_en, reg_top_gpiot2_en_pos, -+ reg_top_gpiot2_en_len, 1); -+ ret = af9035_write_reg_bits(adap->dev, LINK, -+ p_reg_top_gpiot2_on, reg_top_gpiot2_on_pos, -+ reg_top_gpiot2_on_len, 1); -+ ret = af9035_write_reg_bits(adap->dev, LINK, -+ p_reg_top_gpiot3_en, reg_top_gpiot3_en_pos, -+ reg_top_gpiot3_en_len, 1); -+ ret = af9035_write_reg_bits(adap->dev, LINK, -+ p_reg_top_gpiot3_on, reg_top_gpiot3_on_pos, -+ reg_top_gpiot3_on_len, 1); -+ -+ /* reset tuner */ -+ ret = af9035_write_reg_bits(adap->dev, LINK, p_reg_top_gpiot3_o, -+ reg_top_gpiot3_o_pos, reg_top_gpiot3_o_len, 0); -+ msleep(1); -+ ret = af9035_write_reg_bits(adap->dev, LINK, p_reg_top_gpiot3_o, -+ reg_top_gpiot3_o_pos, reg_top_gpiot3_o_len, 1); -+ -+ /* activate tuner - TODO: do that like I2C gate control */ -+ ret = af9035_write_reg_bits(adap->dev, LINK, p_reg_top_gpiot2_o, -+ reg_top_gpiot2_o_pos, reg_top_gpiot2_o_len, 1); -+ } -+ -+#ifdef V4L2_REFACTORED_MFE_CODE -+ ret = dvb_attach(tua9001_attach, adap->fe_adap[0].fe, &adap->dev->i2c_adap, -+#else -+ ret = dvb_attach(tua9001_attach, adap->fe, &adap->dev->i2c_adap, -+#endif -+ &af9035_tua9001_config[adap->id]) == NULL ? -ENODEV : 0; -+ -+ break; -+ case AF9033_TUNER_MXL5007t: -+ af9035_af9033_config[adap->id].tuner_address = 0xc0; -+ af9035_af9033_config[adap->id].tuner_address += adap->id; -+ if (adap->id == 0) { -+ ret = af9035_write_reg(adap->dev, LINK, -+ p_reg_top_gpioh12_en, -+ 1); -+ -+ ret = af9035_write_reg(adap->dev, LINK, -+ p_reg_top_gpioh12_on, -+ 1); -+ -+ ret = af9035_write_reg(adap->dev, LINK, -+ p_reg_top_gpioh12_o, -+ 0); -+ -+ msleep(30); -+ -+ ret = af9035_write_reg(adap->dev, LINK, -+ p_reg_top_gpioh12_o, -+ 1); -+ -+ msleep(300); -+ -+ ret = af9035_write_reg(adap->dev, LINK, -+ p_reg_top_gpioh4_en, -+ 1); -+ -+ ret = af9035_write_reg(adap->dev, LINK, -+ p_reg_top_gpioh4_on, -+ 1); -+ -+ ret = af9035_write_reg(adap->dev, LINK, -+ p_reg_top_gpioh4_o, -+ 0); -+ -+ ret = af9035_write_reg(adap->dev, LINK, -+ p_reg_top_gpioh3_en, -+ 1); -+ -+ ret = af9035_write_reg(adap->dev, LINK, -+ p_reg_top_gpioh3_on, -+ 1); -+ -+ ret = af9035_write_reg(adap->dev, LINK, -+ p_reg_top_gpioh3_o, -+ 1); -+ } -+ -+#ifdef V4L2_REFACTORED_MFE_CODE -+ ret = dvb_attach(mxl5007t_attach, adap->fe_adap[0].fe, &adap->dev->i2c_adap, -+#else -+ ret = dvb_attach(mxl5007t_attach, adap->fe, &adap->dev->i2c_adap, -+#endif -+ af9035_af9033_config[adap->id].tuner_address, -+ &af9035_mxl5007t_config[adap->id]) == NULL ? -ENODEV : 0; -+ -+ break; -+ case AF9033_TUNER_TDA18218: -+ af9035_af9033_config[adap->id].tuner_address = af9035_tda18218_config[adap->id].i2c_address; -+ af9035_af9033_config[adap->id].tuner_address += adap->id; -+ if (adap->id == 0) { -+ /* gpiot3 TUA9001 RESETN -+ gpiot2 TUA9001 RXEN */ -+ ret = af9035_write_reg_bits(adap->dev, LINK, -+ p_reg_top_gpiot2_en, reg_top_gpiot2_en_pos, -+ reg_top_gpiot2_en_len, 1); -+ ret = af9035_write_reg_bits(adap->dev, LINK, -+ p_reg_top_gpiot2_on, reg_top_gpiot2_on_pos, -+ reg_top_gpiot2_on_len, 1); -+ ret = af9035_write_reg_bits(adap->dev, LINK, -+ p_reg_top_gpiot3_en, reg_top_gpiot3_en_pos, -+ reg_top_gpiot3_en_len, 1); -+ ret = af9035_write_reg_bits(adap->dev, LINK, -+ p_reg_top_gpiot3_on, reg_top_gpiot3_on_pos, -+ reg_top_gpiot3_on_len, 1); -+ -+ /* reset tuner */ -+ ret = af9035_write_reg_bits(adap->dev, LINK, p_reg_top_gpiot3_o, -+ reg_top_gpiot3_o_pos, reg_top_gpiot3_o_len, 0); -+ msleep(1); -+ ret = af9035_write_reg_bits(adap->dev, LINK, p_reg_top_gpiot3_o, -+ reg_top_gpiot3_o_pos, reg_top_gpiot3_o_len, 1); -+ -+ /* activate tuner - TODO: do that like I2C gate control */ -+ ret = af9035_write_reg_bits(adap->dev, LINK, p_reg_top_gpiot2_o, -+ reg_top_gpiot2_o_pos, reg_top_gpiot2_o_len, 1); -+ } -+ -+#ifdef V4L2_REFACTORED_MFE_CODE -+ ret = dvb_attach(tda18218_attach, adap->fe_adap[0].fe, &adap->dev->i2c_adap, -+#else -+ ret = dvb_attach(tda18218_attach, adap->fe, &adap->dev->i2c_adap, -+#endif -+ &af9035_tda18218_config[adap->id]) == NULL ? -ENODEV : 0; -+ break; -+ default: -+ ret = -ENODEV; -+ err("unknown tuner ID:%d", -+ af9035_af9033_config[adap->id].tuner); -+ } -+ -+ return ret; -+} -+ -+/* -+ * enable devices supported by the Avemedia A867 proprietary driver; -+ * some device use an unsupported tuner type (AF9007), so it will not work; -+ * probably those devices belong to the A333 family; -+ */ -+#define ENABLE_A867_DEVICES -+ -+enum af9035_usb_table_entry { -+ AFATECH_AF9035_1000, -+ AFATECH_AF9035_1001, -+ AFATECH_AF9035_1002, -+ AFATECH_AF9035_1003, -+ AFATECH_AF9035_9035, -+ TERRATEC_CINERGY_T_STICK, -+ TERRATEC_CINERGY_T_STICK_2, -+ AVERMEDIA_TWINSTAR, -+ AVERMEDIA_VOLAR_HD, -+ AVERMEDIA_VOLAR_HD_PRO, -+#ifdef ENABLE_A867_DEVICES -+ AVERMEDIA_A333, -+ AVERMEDIA_B867, -+ AVERMEDIA_1867, -+ AVERMEDIA_0337, -+ AVERMEDIA_A867, -+ AVERMEDIA_0867, -+ AVERMEDIA_F337, -+ AVERMEDIA_3867, -+#endif -+}; -+ -+static struct usb_device_id af9035_usb_table[] = { -+ [AFATECH_AF9035_1000] = {USB_DEVICE(USB_VID_AFATECH, -+ USB_PID_AFATECH_AF9035_1000)}, -+ [AFATECH_AF9035_1001] = {USB_DEVICE(USB_VID_AFATECH, -+ USB_PID_AFATECH_AF9035_1001)}, -+ [AFATECH_AF9035_1002] = {USB_DEVICE(USB_VID_AFATECH, -+ USB_PID_AFATECH_AF9035_1002)}, -+ [AFATECH_AF9035_1003] = {USB_DEVICE(USB_VID_AFATECH, -+ USB_PID_AFATECH_AF9035_1003)}, -+ [AFATECH_AF9035_9035] = {USB_DEVICE(USB_VID_AFATECH, -+ USB_PID_AFATECH_AF9035_9035)}, -+ [TERRATEC_CINERGY_T_STICK] = {USB_DEVICE(USB_VID_TERRATEC, -+ USB_PID_TERRATEC_CINERGY_T_STICK)}, -+ [TERRATEC_CINERGY_T_STICK_2] = {USB_DEVICE(USB_VID_TERRATEC, -+ USB_PID_TERRATEC_CINERGY_T_STICK_2)}, -+ [AVERMEDIA_TWINSTAR] = {USB_DEVICE(USB_VID_AVERMEDIA, -+ USB_PID_AVERMEDIA_A825)}, -+ [AVERMEDIA_VOLAR_HD] = {USB_DEVICE(USB_VID_AVERMEDIA, -+ USB_PID_AVERMEDIA_A835)}, -+ [AVERMEDIA_VOLAR_HD_PRO] = {USB_DEVICE(USB_VID_AVERMEDIA, -+ USB_PID_AVERMEDIA_B835)}, -+#ifdef ENABLE_A867_DEVICES -+ [AVERMEDIA_A333] = {USB_DEVICE(USB_VID_AVERMEDIA, -+ USB_PID_AVERMEDIA_A333)}, -+ [AVERMEDIA_B867] = {USB_DEVICE(USB_VID_AVERMEDIA, -+ USB_PID_AVERMEDIA_B867)}, -+ [AVERMEDIA_1867] = {USB_DEVICE(USB_VID_AVERMEDIA, -+ USB_PID_AVERMEDIA_1867)}, -+ [AVERMEDIA_0337] = {USB_DEVICE(USB_VID_AVERMEDIA, -+ USB_PID_AVERMEDIA_0337)}, -+ [AVERMEDIA_A867] = {USB_DEVICE(USB_VID_AVERMEDIA, -+ USB_PID_AVERMEDIA_A867)}, -+ [AVERMEDIA_0867] = {USB_DEVICE(USB_VID_AVERMEDIA, -+ USB_PID_AVERMEDIA_0867)}, -+ [AVERMEDIA_F337] = {USB_DEVICE(USB_VID_AVERMEDIA, -+ USB_PID_AVERMEDIA_F337)}, -+ [AVERMEDIA_3867] = {USB_DEVICE(USB_VID_AVERMEDIA, -+ USB_PID_AVERMEDIA_3867)}, -+#endif -+ { }, -+}; -+ -+MODULE_DEVICE_TABLE(usb, af9035_usb_table); -+ -+static struct dvb_usb_device_properties af9035_properties[] = { -+ { -+ .caps = DVB_USB_IS_AN_I2C_ADAPTER, -+ -+ .usb_ctrl = DEVICE_SPECIFIC, -+ .download_firmware = af9035_download_firmware, -+ .firmware = "dvb-usb-af9035-01.fw", -+ .no_reconnect = 1, -+ -+ .size_of_priv = 0, -+ -+ .adapter = { -+ { -+#ifdef V4L2_REFACTORED_MFE_CODE -+ .num_frontends = 1, -+ .fe = {{ -+#endif -+ .frontend_attach = -+ af9035_af9033_frontend_attach, -+ .tuner_attach = af9035_tuner_attach, -+ .stream = { -+ .type = USB_BULK, -+ .count = 4, -+ .endpoint = 0x84, -+ }, -+#ifdef V4L2_REFACTORED_MFE_CODE -+ }}, -+#endif -+ }, -+ { -+#ifdef V4L2_REFACTORED_MFE_CODE -+ .num_frontends = 1, -+ .fe = {{ -+#endif -+ .frontend_attach = -+ af9035_af9033_frontend_attach, -+ .tuner_attach = af9035_tuner_attach, -+ .stream = { -+ .type = USB_BULK, -+ .count = 4, -+ .endpoint = 0x85, -+ .u = { -+ .bulk = { -+ .buffersize = -+ TS_USB20_FRAME_SIZE, -+ } -+ } -+ }, -+#ifdef V4L2_REFACTORED_MFE_CODE -+ }}, -+#endif -+ } -+ }, -+ -+ .identify_state = af9035_identify_state, -+ -+ .i2c_algo = &af9035_i2c_algo, -+ -+#ifdef ENABLE_A867_DEVICES -+ .num_device_descs = 6, -+#else -+ .num_device_descs = 4, -+#endif -+ .devices = { -+ { -+ .name = "Afatech AF9035 DVB-T USB2.0 stick", -+ .cold_ids = {&af9035_usb_table[AFATECH_AF9035_1000], -+ &af9035_usb_table[AFATECH_AF9035_1001], -+ &af9035_usb_table[AFATECH_AF9035_1002], -+ &af9035_usb_table[AFATECH_AF9035_1003], -+ &af9035_usb_table[AFATECH_AF9035_9035], NULL}, -+ .warm_ids = {NULL}, -+ }, -+ { -+ .name = "TerraTec Cinergy T Stick", -+ .cold_ids = {&af9035_usb_table[TERRATEC_CINERGY_T_STICK], -+ &af9035_usb_table[TERRATEC_CINERGY_T_STICK_2], NULL}, -+ .warm_ids = {NULL}, -+ }, -+ { -+ .name = "Avermedia TwinStar", -+ .cold_ids = {&af9035_usb_table[AVERMEDIA_TWINSTAR], NULL}, -+ .warm_ids = {NULL}, -+ }, -+ { -+ .name = "Avermedia AverTV Volar HD & HD PRO (A835)", -+ .cold_ids = {&af9035_usb_table[AVERMEDIA_VOLAR_HD], -+ &af9035_usb_table[AVERMEDIA_VOLAR_HD_PRO], NULL}, -+ .warm_ids = {NULL}, -+ }, -+#ifdef ENABLE_A867_DEVICES -+ { -+ .name = "Avermedia A333", -+ .cold_ids = {&af9035_usb_table[AVERMEDIA_A333], -+ &af9035_usb_table[AVERMEDIA_B867], NULL}, -+ .warm_ids = {NULL}, -+ }, -+ { -+ .name = "Avermedia A867", -+ .cold_ids = {&af9035_usb_table[AVERMEDIA_1867], -+ &af9035_usb_table[AVERMEDIA_0337], -+ &af9035_usb_table[AVERMEDIA_A867], -+ &af9035_usb_table[AVERMEDIA_0867], -+ &af9035_usb_table[AVERMEDIA_F337], -+ &af9035_usb_table[AVERMEDIA_3867], NULL}, -+ .warm_ids = {NULL}, -+ }, -+#endif -+ } -+ }, -+}; -+ -+static int af9035_usb_probe(struct usb_interface *intf, -+ const struct usb_device_id *id) -+{ -+ int ret = 0; -+ struct dvb_usb_device *d = NULL; -+ struct usb_device *udev = interface_to_usbdev(intf); -+ u8 i; -+ -+ deb_info("%s: interface:%d\n", __func__, -+ intf->cur_altsetting->desc.bInterfaceNumber); -+ -+ /* interface 0 is used by DVB-T receiver and -+ interface 1 is for remote controller (HID) */ -+ if (intf->cur_altsetting->desc.bInterfaceNumber == 0) { -+ ret = af9035_read_config(udev); -+ if (ret) -+ return ret; -+ -+ ret = af9035_aux_init(udev); -+ if (ret) -+ return ret; -+ -+ for (i = 0; i < af9035_properties_count; i++) { -+ ret = dvb_usb_device_init(intf, &af9035_properties[i], -+ THIS_MODULE, &d, adapter_nr); -+ if (!ret) -+ break; -+ if (ret != -ENODEV) -+ return ret; -+ } -+ if (ret) -+ return ret; -+ -+ if (d) -+ ret = af9035_init(d); -+ } -+ -+ return ret; -+} -+ -+/* usb specific object needed to register this driver with the usb subsystem */ -+static struct usb_driver af9035_usb_driver = { -+ .name = "dvb_usb_af9035", -+ .probe = af9035_usb_probe, -+ .disconnect = dvb_usb_device_exit, -+ .id_table = af9035_usb_table, -+}; -+ -+/* module stuff */ -+static int __init af9035_usb_module_init(void) -+{ -+ int ret; -+ ret = usb_register(&af9035_usb_driver); -+ if (ret) -+ err("module init failed:%d", ret); -+ -+ return ret; -+} -+ -+static void __exit af9035_usb_module_exit(void) -+{ -+ /* deregister this driver from the USB subsystem */ -+ usb_deregister(&af9035_usb_driver); -+} -+ -+module_init(af9035_usb_module_init); -+module_exit(af9035_usb_module_exit); -+ -+MODULE_AUTHOR("Antti Palosaari "); -+MODULE_DESCRIPTION("Afatech AF9035 driver"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/media/dvb/dvb-usb/af9035.h b/drivers/media/dvb/dvb-usb/af9035.h -new file mode 100644 -index 0000000..7c0c971 ---- /dev/null -+++ b/drivers/media/dvb/dvb-usb/af9035.h -@@ -0,0 +1,187 @@ -+/* -+ * Afatech AF9035 DVB USB driver -+ * -+ * Copyright (C) 2008 Afatech -+ * Copyright (C) 2009 Antti Palosaari -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ * -+ * -+ * Thanks to TerraTec for a support received. -+ */ -+ -+#ifndef AF9035_H -+#define AF9035_H -+#include "af9033_reg.h" -+ -+#define DVB_USB_LOG_PREFIX "af9035" -+#include "dvb-usb.h" -+ -+#define deb_info(args...) dprintk(dvb_usb_af9035_debug, 0x01, args) -+#define deb_rc(args...) dprintk(dvb_usb_af9035_debug, 0x02, args) -+#define deb_xfer(args...) dprintk(dvb_usb_af9035_debug, 0x04, args) -+#define deb_reg(args...) dprintk(dvb_usb_af9035_debug, 0x08, args) -+#define deb_i2c(args...) dprintk(dvb_usb_af9035_debug, 0x10, args) -+#define deb_fw(args...) dprintk(dvb_usb_af9035_debug, 0x20, args) -+ -+#define AF9035_USB_TIMEOUT 2000 -+ -+#define LINK 0x00 -+#define OFDM 0x80 -+ -+#define TS_MODE_SINGLE 0 -+#define TS_MODE_DCA_PIP 1 -+#define TS_MODE_DCA 2 /* any other value than 0, 1, 3 (?) */ -+#define TS_MODE_PIP 3 -+ -+#define TS_PACKET_SIZE 188 -+#define TS_USB20_PACKET_COUNT 348 -+#define TS_USB20_FRAME_SIZE (TS_PACKET_SIZE*TS_USB20_PACKET_COUNT) -+#define TS_USB11_PACKET_COUNT 21 -+#define TS_USB11_FRAME_SIZE (TS_PACKET_SIZE*TS_USB11_PACKET_COUNT) -+#define TS_USB20_MAX_PACKET_SIZE 512 -+#define TS_USB11_MAX_PACKET_SIZE 64 -+ -+/* EEPROM locations */ -+#define GANY_ONLY 0x42f5 -+#define EEPROM_FLB_OFS 8 -+#define EEPROM_BASE_ADDR (GANY_ONLY + EEPROM_FLB_OFS) -+#define EEPROM_SHIFT (0x10) -+ -+#define EEPROM_IR_MODE (EEPROM_BASE_ADDR+0x10) /* 00:disabled, 01:HID */ -+#define EEPROM_SELSUSPEND (EEPROM_BASE_ADDR+0x28) /* selective suspend mode */ -+#define EEPROM_TS_MODE (EEPROM_BASE_ADDR+0x28+1) /* 0:one ts, 1:dual ts */ -+#define EEPROM_2WIREADDR (EEPROM_BASE_ADDR+0x28+2) /* 2nd demod I2C addr */ -+#define EEPROM_SUSPEND (EEPROM_BASE_ADDR+0x28+3) /* suspend mode */ -+#define EEPROM_IR_TYPE (EEPROM_BASE_ADDR+0x28+4) /* 0:NEC, 1:RC6 */ -+ -+#define EEPROM_SAW_BW1 (EEPROM_BASE_ADDR+0x28+5) -+#define EEPROM_XTAL1 (EEPROM_BASE_ADDR+0x28+6) -+#define EEPROM_SPECINV1 (EEPROM_BASE_ADDR+0x28+7) -+#define EEPROM_TUNER_ID1 (EEPROM_BASE_ADDR+0x30+4) -+#define EEPROM_IFFREQL1 (EEPROM_BASE_ADDR+0x30) -+#define EEPROM_IFFREQH1 (EEPROM_BASE_ADDR+0x30+1) -+#define EEPROM_IF1L1 (EEPROM_BASE_ADDR+0x30+2) -+#define EEPROM_IF1H1 (EEPROM_BASE_ADDR+0x30+3) -+ -+#define EEPROM_SAW_BW2 (EEPROM_BASE_ADDR+EEPROM_SHIFT+0x28+5) -+#define EEPROM_XTAL2 (EEPROM_BASE_ADDR+EEPROM_SHIFT+0x28+6) -+#define EEPROM_SPECINV2 (EEPROM_BASE_ADDR+EEPROM_SHIFT+0x28+7) -+#define EEPROM_TUNER_ID2 (EEPROM_BASE_ADDR+EEPROM_SHIFT+0x30+4) -+#define EEPROM_IFFREQL2 (EEPROM_BASE_ADDR+EEPROM_SHIFT+0x30) -+#define EEPROM_IFFREQH2 (EEPROM_BASE_ADDR+EEPROM_SHIFT+0x30+1) -+#define EEPROM_IF1L2 (EEPROM_BASE_ADDR+EEPROM_SHIFT+0x30+2) -+#define EEPROM_IF1H2 (EEPROM_BASE_ADDR+EEPROM_SHIFT+0x30+3) -+ -+struct af9035_clock { -+ u32 crystal; -+ u32 adc; -+}; -+ -+static struct af9035_clock clock_table[] = { -+ {20480000, 20480000}, /* FPGA */ -+ {16384000, 20480000}, /* 16.38MHz */ -+ {20480000, 20480000}, /* 20.48MHz */ -+ {36000000, 20250000}, /* 36.00MHz */ -+ {30000000, 20156250}, /* 30.00MHz */ -+ {26000000, 20583333}, /* 26.00MHz */ -+ {28000000, 20416667}, /* 28.00MHz */ -+ {32000000, 20500000}, /* 32.00MHz */ -+ {34000000, 20187500}, /* 34.00MHz */ -+ {24000000, 20500000}, /* 24.00MHz */ -+ {22000000, 20625000}, /* 22.00MHz */ -+ {12000000, 20250000}, /* 12.00MHz */ -+}; -+ -+struct af9035_req { -+ u8 cmd; -+ u8 mbox; -+ u8 wlen; -+ u8 *wbuf; -+ u8 rlen; -+ u8 *rbuf; -+}; -+ -+/* USB commands */ -+#define CMD_REG_DEMOD_READ 0x00 -+#define CMD_REG_DEMOD_WRITE 0x01 -+#define CMD_REG_TUNER_READ 0x02 -+#define CMD_REG_TUNER_WRITE 0x03 -+#define CMD_REG_EEPROM_READ 0x04 -+#define CMD_REG_EEPROM_WRITE 0x05 -+#define CMD_VAR_READ 0x08 -+#define CMD_VAR_WRITE 0x09 -+ -+#define CMD_DATA_READ 0x06 -+ -+#define CMD_PLATFORM_GET 0x0A -+#define CMD_PLATFORM_SET 0x0B -+#define CMD_IP_CACHE 0x0D -+#define CMD_IP_ADD 0x0E -+#define CMD_IP_REMOVE 0x0F -+#define CMD_PID_ADD 0x10 -+#define CMD_PID_REMOVE 0x11 -+/* get SI/PSI table for specific PID "once" */ -+#define CMD_SIPSI_GET 0x12 -+#define CMD_SIPSI_MPE_RESET 0x13 -+#define CMD_H_PID_ADD 0x15 -+#define CMD_H_PID_REMOVE 0x16 -+#define CMD_ABORT 0x17 -+#define CMD_IR_GET 0x18 -+#define CMD_IR_SET 0x19 -+#define CMD_FW_DOWNLOAD_BEGIN 0x24 -+#define CMD_FW_DOWNLOAD 0x21 -+#define CMD_FW_DOWNLOAD_END 0x25 -+#define CMD_QUERYINFO 0x22 -+#define CMD_BOOT 0x23 -+#define CMD_REBOOT 0x23 -+#define CMD_RUN_CODE 0x26 -+#define CMD_SCATTER_READ 0x28 -+#define CMD_SCATTER_WRITE 0x29 -+#define CMD_GENERIC_READ 0x2A -+#define CMD_GENERIC_WRITE 0x2B -+ -+#define CMD_SERVICES_GET 0x83 -+#define CMD_COMPONENT_ADD 0x86 -+#define CMD_COMPONENT_REMOVE 0x87 -+#define CMD_FIG_ADD 0x88 -+#define CMD_FIG_REMOVE 0x89 -+ -+/* this Linux driver does not implement usage of "short command" at all */ -+#define CMD_SHORT_REG_DEMOD_READ 0x02 -+#define CMD_SHORT_REG_DEMOD_WRITE 0X03 -+#define CMD_SHORT_REG_TUNER_READ 0x04 -+#define CMD_SHORT_REG_TUNER_WRITE 0X05 -+ -+struct af9035_config { -+ u8 dual_mode:1; -+ u16 mt2060_if1[2]; -+}; -+ -+struct af9035_segment { -+#define SEGMENT_FW_DOWNLOAD 0 -+#define SEGMENT_ROM_COPY 1 -+#define SEGMENT_DIRECT_CMD 2 -+ u8 type; -+ u32 len; -+}; -+ -+struct af9035_firmware_header { -+#define SEGMENT_MAX_COUNT 50 -+ u8 segment_count; -+ struct af9035_segment segment[SEGMENT_MAX_COUNT]; -+}; -+ -+#endif -diff --git a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h -index 397d8f2..8444118 100644 ---- a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h -+++ b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h -@@ -76,6 +76,11 @@ - #define USB_PID_AFATECH_AF9005 0x9020 - #define USB_PID_AFATECH_AF9015_9015 0x9015 - #define USB_PID_AFATECH_AF9015_9016 0x9016 -+#define USB_PID_AFATECH_AF9035_1000 0x1000 -+#define USB_PID_AFATECH_AF9035_1001 0x1001 -+#define USB_PID_AFATECH_AF9035_1002 0x1002 -+#define USB_PID_AFATECH_AF9035_1003 0x1003 -+#define USB_PID_AFATECH_AF9035_9035 0x9035 - #define USB_PID_TREKSTOR_DVBT 0x901b - #define USB_VID_ALINK_DTU 0xf170 - #define USB_PID_ANSONIC_DVBT_USB 0x6000 -@@ -221,6 +226,17 @@ - #define USB_PID_AVERMEDIA_A850T 0x850b - #define USB_PID_AVERMEDIA_A805 0xa805 - #define USB_PID_AVERMEDIA_A815M 0x815a -+#define USB_PID_AVERMEDIA_A825 0x0825 -+#define USB_PID_AVERMEDIA_A835 0xa835 -+#define USB_PID_AVERMEDIA_B835 0xb835 -+#define USB_PID_AVERMEDIA_A333 0xa333 -+#define USB_PID_AVERMEDIA_B867 0xb867 -+#define USB_PID_AVERMEDIA_1867 0x1867 -+#define USB_PID_AVERMEDIA_0337 0x0337 -+#define USB_PID_AVERMEDIA_A867 0xa867 -+#define USB_PID_AVERMEDIA_0867 0x0867 -+#define USB_PID_AVERMEDIA_F337 0xf337 -+#define USB_PID_AVERMEDIA_3867 0x3867 - #define USB_PID_TECHNOTREND_CONNECT_S2400 0x3006 - #define USB_PID_TECHNOTREND_CONNECT_CT3650 0x300d - #define USB_PID_TERRATEC_CINERGY_DT_XS_DIVERSITY 0x005a -@@ -230,6 +246,8 @@ - #define USB_PID_TERRATEC_CINERGY_T_EXPRESS 0x0062 - #define USB_PID_TERRATEC_CINERGY_T_XXS 0x0078 - #define USB_PID_TERRATEC_CINERGY_T_XXS_2 0x00ab -+#define USB_PID_TERRATEC_CINERGY_T_STICK 0x0093 -+#define USB_PID_TERRATEC_CINERGY_T_STICK_2 0x00aa - #define USB_PID_TERRATEC_H7 0x10b4 - #define USB_PID_TERRATEC_H7_2 0x10a3 - #define USB_PID_TERRATEC_T3 0x10a0 -diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig -index 2995204..fc6cbc5 100644 ---- a/drivers/media/dvb/frontends/Kconfig -+++ b/drivers/media/dvb/frontends/Kconfig -@@ -397,6 +397,13 @@ config DVB_AF9013 - help - Say Y when you want to support this frontend. - -+config DVB_AF9033 -+ tristate "Afatech AF9033 demodulator" -+ depends on DVB_CORE && I2C -+ default m -+ help -+ Say Y when you want to support this frontend. -+ - config DVB_EC100 - tristate "E3C EC100" - depends on DVB_CORE && I2C -diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile -index 17519dc..bc3e962 100644 ---- a/drivers/media/dvb/frontends/Makefile -+++ b/drivers/media/dvb/frontends/Makefile -@@ -73,6 +73,7 @@ obj-$(CONFIG_DVB_LGS8GXX) += lgs8gxx.o - obj-$(CONFIG_DVB_ATBM8830) += atbm8830.o - obj-$(CONFIG_DVB_DUMMY_FE) += dvb_dummy_fe.o - obj-$(CONFIG_DVB_AF9013) += af9013.o -+obj-$(CONFIG_DVB_AF9033) += af9033.o - obj-$(CONFIG_DVB_CX24116) += cx24116.o - obj-$(CONFIG_DVB_SI21XX) += si21xx.o - obj-$(CONFIG_DVB_STV0288) += stv0288.o -diff --git a/drivers/media/dvb/frontends/af9033.c b/drivers/media/dvb/frontends/af9033.c -new file mode 100644 -index 0000000..747931f ---- /dev/null -+++ b/drivers/media/dvb/frontends/af9033.c -@@ -0,0 +1,1957 @@ -+/* -+ * Afatech AF9033 demodulator driver -+ * -+ * Copyright (C) 2008 Afatech -+ * Copyright (C) 2009 Antti Palosaari -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ * -+ * -+ * Thanks to TerraTec for a support received. -+ */ -+ -+#include "dvb_frontend.h" -+#include /* for kzalloc/kfree */ -+#include -+#include "af9033_priv.h" -+#include "af9033.h" -+#include "af9033_reg.h" -+ -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,0)) || ((defined V4L2_VERSION) && (V4L2_VERSION >= 197120)) -+/* all DVB frontend drivers now work directly with the DVBv5 -+ * structure. This warrants that all drivers will be -+ * getting/setting frontend parameters on a consistent way, in -+ * order to avoid copying data from/to the DVBv3 structs -+ * without need. -+ */ -+#define V4L2_ONLY_DVB_V5 -+#endif -+ -+static int af9033_debug; -+module_param_named(debug, af9033_debug, int, 0644); -+MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); -+static int af9033_snrdb; -+module_param_named(snrdb, af9033_snrdb, int, 0644); -+MODULE_PARM_DESC(snrdb, "Turn on/off SNR output as dBx10 (default:off)."); -+ -+struct af9033_state { -+ struct i2c_adapter *i2c; -+ struct dvb_frontend frontend; -+ struct af9033_config config; -+ -+ u16 signal_strength; -+ u32 ber; -+ u32 ucblocks; -+ u16 snr; -+ u32 frequency; -+ unsigned long next_statistics_check; -+}; -+ -+static u8 regmask[8] = {0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x7f, 0xff}; -+ -+/* write multiple registers */ -+static int af9033_write_regs(struct af9033_state *state, u8 mbox, u16 reg, -+ u8 *val, u8 len) -+{ -+ u8 buf[3+len]; -+ struct i2c_msg msg = { -+ .addr = state->config.demod_address, -+ .flags = 0, -+ .len = sizeof(buf), -+ .buf = buf }; -+ -+ buf[0] = mbox; -+ buf[1] = reg >> 8; -+ buf[2] = reg & 0xff; -+ memcpy(&buf[3], val, len); -+ -+ if (i2c_transfer(state->i2c, &msg, 1) != 1) { -+ warn("I2C write failed reg:%04x len:%d", reg, len); -+ return -EREMOTEIO; -+ } -+ return 0; -+} -+ -+/* read multiple registers */ -+static int af9033_read_regs(struct af9033_state *state, u8 mbox, u16 reg, -+ u8 *val, u8 len) -+{ -+ u8 obuf[3] = {mbox, reg >> 8, reg & 0xff}; -+ struct i2c_msg msg[2] = { -+ { -+ .addr = state->config.demod_address, -+ .flags = 0, -+ .len = sizeof(obuf), -+ .buf = obuf -+ }, { -+ .addr = state->config.demod_address, -+ .flags = I2C_M_RD, -+ .len = len, -+ .buf = val -+ } -+ }; -+ -+ if (i2c_transfer(state->i2c, msg, 2) != 2) { -+ warn("I2C read failed reg:%04x", reg); -+ return -EREMOTEIO; -+ } -+ return 0; -+} -+ -+/* write single register */ -+static int af9033_write_reg(struct af9033_state *state, u8 mbox, u16 reg, -+ u8 val) -+{ -+ return af9033_write_regs(state, mbox, reg, &val, 1); -+} -+ -+/* read single register */ -+static int af9033_read_reg(struct af9033_state *state, u8 mbox, u16 reg, -+ u8 *val) -+{ -+ return af9033_read_regs(state, mbox, reg, val, 1); -+} -+ -+/* write single register bits */ -+static int af9033_write_reg_bits(struct af9033_state *state, u8 mbox, u16 reg, -+ u8 pos, u8 len, u8 val) -+{ -+ int ret; -+ u8 tmp, mask; -+ -+ ret = af9033_read_reg(state, mbox, reg, &tmp); -+ if (ret) -+ return ret; -+ -+ mask = regmask[len - 1] << pos; -+ tmp = (tmp & ~mask) | ((val << pos) & mask); -+ -+ return af9033_write_reg(state, mbox, reg, tmp); -+} -+ -+/* read single register bits */ -+static int af9033_read_reg_bits(struct af9033_state *state, u8 mbox, u16 reg, -+ u8 pos, u8 len, u8 *val) -+{ -+ int ret; -+ u8 tmp; -+ -+ ret = af9033_read_reg(state, mbox, reg, &tmp); -+ if (ret) -+ return ret; -+ -+ *val = (tmp >> pos) & regmask[len - 1]; -+ return 0; -+} -+ -+static u32 af913_div(u32 a, u32 b, u32 x) -+{ -+ u32 r = 0, c = 0, i; -+ deb_info("%s: a:%d b:%d x:%d\n", __func__, a, b, x); -+ -+ if (a > b) { -+ c = a / b; -+ a = a - c * b; -+ } -+ -+ for (i = 0; i < x; i++) { -+ if (a >= b) { -+ r += 1; -+ a -= b; -+ } -+ a <<= 1; -+ r <<= 1; -+ } -+ r = (c << (u32)x) + r; -+ -+ deb_info("%s: a:%d b:%d x:%d r:%d r:%x\n", __func__, a, b, x, r, r); -+ return r; -+} -+ -+#ifdef V4L2_ONLY_DVB_V5 -+static int af9033_set_coeff(struct af9033_state *state, u32 bw) -+#else -+static int af9033_set_coeff(struct af9033_state *state, fe_bandwidth_t bw) -+#endif -+{ -+ int ret = 0; -+ u8 tmp, i = 0; -+ u8 buf[36]; -+ u32 uninitialized_var(coeff1_2048nu); -+ u32 uninitialized_var(coeff1_4096nu); -+ u32 uninitialized_var(coeff1_8191nu); -+ u32 uninitialized_var(coeff1_8192nu); -+ u32 uninitialized_var(coeff1_8193nu); -+ u32 uninitialized_var(coeff2_2k); -+ u32 uninitialized_var(coeff2_4k); -+ u32 uninitialized_var(coeff2_8k); -+ u16 uninitialized_var(bfsfcw_fftindex_ratio); -+ u16 uninitialized_var(fftindex_bfsfcw_ratio); -+ deb_info("%s: adc_clock:%d bw:%d\n", __func__, -+ state->config.adc_clock, bw); -+ -+#ifdef V4L2_ONLY_DVB_V5 -+#define BANDWIDTH_5_MHZ 5000000 -+#define BANDWIDTH_6_MHZ 6000000 -+#define BANDWIDTH_7_MHZ 7000000 -+#define BANDWIDTH_8_MHZ 8000000 -+#endif -+ -+ switch (state->config.adc_clock) { -+ case 20156250: -+ switch (bw) { -+#if 0 /* keep */ -+ case BANDWIDTH_5_MHZ: -+ coeff1_2048nu = 0x02449b5c; -+ coeff1_4096nu = 0x01224dae; -+ coeff1_8191nu = 0x00912b60; -+ coeff1_8192nu = 0x009126d7; -+ coeff1_8193nu = 0x0091224e; -+ coeff2_2k = 0x01224dae; -+ coeff2_4k = 0x009126d7; -+ coeff2_8k = 0x0048936b; -+ bfsfcw_fftindex_ratio = 0x0387; -+ fftindex_bfsfcw_ratio = 0x0122; -+ break; -+#endif -+ case BANDWIDTH_6_MHZ: -+ coeff1_2048nu = 0x02b8ba6e; -+ coeff1_4096nu = 0x015c5d37; -+ coeff1_8191nu = 0x00ae340d; -+ coeff1_8192nu = 0x00ae2e9b; -+ coeff1_8193nu = 0x00ae292a; -+ coeff2_2k = 0x015c5d37; -+ coeff2_4k = 0x00ae2e9b; -+ coeff2_8k = 0x0057174e; -+ bfsfcw_fftindex_ratio = 0x02f1; -+ fftindex_bfsfcw_ratio = 0x015c; -+ break; -+ case BANDWIDTH_7_MHZ: -+ coeff1_2048nu = 0x032cd980; -+ coeff1_4096nu = 0x01966cc0; -+ coeff1_8191nu = 0x00cb3cba; -+ coeff1_8192nu = 0x00cb3660; -+ coeff1_8193nu = 0x00cb3007; -+ coeff2_2k = 0x01966cc0; -+ coeff2_4k = 0x00cb3660; -+ coeff2_8k = 0x00659b30; -+ bfsfcw_fftindex_ratio = 0x0285; -+ fftindex_bfsfcw_ratio = 0x0196; -+ break; -+ case BANDWIDTH_8_MHZ: -+ coeff1_2048nu = 0x03a0f893; -+ coeff1_4096nu = 0x01d07c49; -+ coeff1_8191nu = 0x00e84567; -+ coeff1_8192nu = 0x00e83e25; -+ coeff1_8193nu = 0x00e836e3; -+ coeff2_2k = 0x01d07c49; -+ coeff2_4k = 0x00e83e25; -+ coeff2_8k = 0x00741f12; -+ bfsfcw_fftindex_ratio = 0x0234; -+ fftindex_bfsfcw_ratio = 0x01d0; -+ break; -+ default: -+ ret = -EINVAL; -+ } -+ break; -+ case 20187500: -+ switch (bw) { -+#if 0 /* keep */ -+ case BANDWIDTH_5_MHZ: -+ coeff1_2048nu = 0x0243b546; -+ coeff1_4096nu = 0x0121daa3; -+ coeff1_8191nu = 0x0090f1d9; -+ coeff1_8192nu = 0x0090ed51; -+ coeff1_8193nu = 0x0090e8ca; -+ coeff2_2k = 0x0121daa3; -+ coeff2_4k = 0x0090ed51; -+ coeff2_8k = 0x004876a9; -+ bfsfcw_fftindex_ratio = 0x0388; -+ fftindex_bfsfcw_ratio = 0x0122; -+ break; -+#endif -+ case BANDWIDTH_6_MHZ: -+ coeff1_2048nu = 0x02b7a654; -+ coeff1_4096nu = 0x015bd32a; -+ coeff1_8191nu = 0x00adef04; -+ coeff1_8192nu = 0x00ade995; -+ coeff1_8193nu = 0x00ade426; -+ coeff2_2k = 0x015bd32a; -+ coeff2_4k = 0x00ade995; -+ coeff2_8k = 0x0056f4ca; -+ bfsfcw_fftindex_ratio = 0x02f2; -+ fftindex_bfsfcw_ratio = 0x015c; -+ break; -+ case BANDWIDTH_7_MHZ: -+ coeff1_2048nu = 0x032b9761; -+ coeff1_4096nu = 0x0195cbb1; -+ coeff1_8191nu = 0x00caec30; -+ coeff1_8192nu = 0x00cae5d8; -+ coeff1_8193nu = 0x00cadf81; -+ coeff2_2k = 0x0195cbb1; -+ coeff2_4k = 0x00cae5d8; -+ coeff2_8k = 0x006572ec; -+ bfsfcw_fftindex_ratio = 0x0286; -+ fftindex_bfsfcw_ratio = 0x0196; -+ break; -+ case BANDWIDTH_8_MHZ: -+ coeff1_2048nu = 0x039f886f; -+ coeff1_4096nu = 0x01cfc438; -+ coeff1_8191nu = 0x00e7e95b; -+ coeff1_8192nu = 0x00e7e21c; -+ coeff1_8193nu = 0x00e7dadd; -+ coeff2_2k = 0x01cfc438; -+ coeff2_4k = 0x00e7e21c; -+ coeff2_8k = 0x0073f10e; -+ bfsfcw_fftindex_ratio = 0x0235; -+ fftindex_bfsfcw_ratio = 0x01d0; -+ break; -+ default: -+ ret = -EINVAL; -+ } -+ break; -+ case 20250000: -+ switch (bw) { -+#if 0 /* keep */ -+ case BANDWIDTH_5_MHZ: -+ coeff1_2048nu = 0x0241eb3b; -+ coeff1_4096nu = 0x0120f59e; -+ coeff1_8191nu = 0x00907f53; -+ coeff1_8192nu = 0x00907acf; -+ coeff1_8193nu = 0x0090764b; -+ coeff2_2k = 0x0120f59e; -+ coeff2_4k = 0x00907acf; -+ coeff2_8k = 0x00483d67; -+ bfsfcw_fftindex_ratio = 0x038b; -+ fftindex_bfsfcw_ratio = 0x0121; -+ break; -+#endif -+ case BANDWIDTH_6_MHZ: -+ coeff1_2048nu = 0x02b580ad; -+ coeff1_4096nu = 0x015ac057; -+ coeff1_8191nu = 0x00ad6597; -+ coeff1_8192nu = 0x00ad602b; -+ coeff1_8193nu = 0x00ad5ac1; -+ coeff2_2k = 0x015ac057; -+ coeff2_4k = 0x00ad602b; -+ coeff2_8k = 0x0056b016; -+ bfsfcw_fftindex_ratio = 0x02f4; -+ fftindex_bfsfcw_ratio = 0x015b; -+ break; -+ case BANDWIDTH_7_MHZ: -+ coeff1_2048nu = 0x03291620; -+ coeff1_4096nu = 0x01948b10; -+ coeff1_8191nu = 0x00ca4bda; -+ coeff1_8192nu = 0x00ca4588; -+ coeff1_8193nu = 0x00ca3f36; -+ coeff2_2k = 0x01948b10; -+ coeff2_4k = 0x00ca4588; -+ coeff2_8k = 0x006522c4; -+ bfsfcw_fftindex_ratio = 0x0288; -+ fftindex_bfsfcw_ratio = 0x0195; -+ break; -+ case BANDWIDTH_8_MHZ: -+ coeff1_2048nu = 0x039cab92; -+ coeff1_4096nu = 0x01ce55c9; -+ coeff1_8191nu = 0x00e7321e; -+ coeff1_8192nu = 0x00e72ae4; -+ coeff1_8193nu = 0x00e723ab; -+ coeff2_2k = 0x01ce55c9; -+ coeff2_4k = 0x00e72ae4; -+ coeff2_8k = 0x00739572; -+ bfsfcw_fftindex_ratio = 0x0237; -+ fftindex_bfsfcw_ratio = 0x01ce; -+ break; -+ default: -+ ret = -EINVAL; -+ } -+ break; -+ case 20583333: -+ switch (bw) { -+#if 0 /* keep */ -+ case BANDWIDTH_5_MHZ: -+ coeff1_2048nu = 0x02388f54; -+ coeff1_4096nu = 0x011c47aa; -+ coeff1_8191nu = 0x008e2846; -+ coeff1_8192nu = 0x008e23d5; -+ coeff1_8193nu = 0x008e1f64; -+ coeff2_2k = 0x011c47aa; -+ coeff2_4k = 0x008e23d5; -+ coeff2_8k = 0x004711ea; -+ bfsfcw_fftindex_ratio = 0x039a; -+ fftindex_bfsfcw_ratio = 0x011c; -+ break; -+#endif -+ case BANDWIDTH_6_MHZ: -+ coeff1_2048nu = 0x02aa4598; -+ coeff1_4096nu = 0x015522cc; -+ coeff1_8191nu = 0x00aa96bb; -+ coeff1_8192nu = 0x00aa9166; -+ coeff1_8193nu = 0x00aa8c12; -+ coeff2_2k = 0x015522cc; -+ coeff2_4k = 0x00aa9166; -+ coeff2_8k = 0x005548b3; -+ bfsfcw_fftindex_ratio = 0x0300; -+ fftindex_bfsfcw_ratio = 0x0155; -+ break; -+ case BANDWIDTH_7_MHZ: -+ coeff1_2048nu = 0x031bfbdc; -+ coeff1_4096nu = 0x018dfdee; -+ coeff1_8191nu = 0x00c7052f; -+ coeff1_8192nu = 0x00c6fef7; -+ coeff1_8193nu = 0x00c6f8bf; -+ coeff2_2k = 0x018dfdee; -+ coeff2_4k = 0x00c6fef7; -+ coeff2_8k = 0x00637f7b; -+ bfsfcw_fftindex_ratio = 0x0293; -+ fftindex_bfsfcw_ratio = 0x018e; -+ break; -+ case BANDWIDTH_8_MHZ: -+ coeff1_2048nu = 0x038db21f; -+ coeff1_4096nu = 0x01c6d910; -+ coeff1_8191nu = 0x00e373a3; -+ coeff1_8192nu = 0x00e36c88; -+ coeff1_8193nu = 0x00e3656d; -+ coeff2_2k = 0x01c6d910; -+ coeff2_4k = 0x00e36c88; -+ coeff2_8k = 0x0071b644; -+ bfsfcw_fftindex_ratio = 0x0240; -+ fftindex_bfsfcw_ratio = 0x01c7; -+ break; -+ default: -+ ret = -EINVAL; -+ } -+ break; -+ case 20416667: -+ switch (bw) { -+#if 0 /* keep */ -+ case BANDWIDTH_5_MHZ: -+ coeff1_2048nu = 0x023d337f; -+ coeff1_4096nu = 0x011e99c0; -+ coeff1_8191nu = 0x008f515a; -+ coeff1_8192nu = 0x008f4ce0; -+ coeff1_8193nu = 0x008f4865; -+ coeff2_2k = 0x011e99c0; -+ coeff2_4k = 0x008f4ce0; -+ coeff2_8k = 0x0047a670; -+ bfsfcw_fftindex_ratio = 0x0393; -+ fftindex_bfsfcw_ratio = 0x011f; -+ break; -+#endif -+ case BANDWIDTH_6_MHZ: -+ coeff1_2048nu = 0x02afd765; -+ coeff1_4096nu = 0x0157ebb3; -+ coeff1_8191nu = 0x00abfb39; -+ coeff1_8192nu = 0x00abf5d9; -+ coeff1_8193nu = 0x00abf07a; -+ coeff2_2k = 0x0157ebb3; -+ coeff2_4k = 0x00abf5d9; -+ coeff2_8k = 0x0055faed; -+ bfsfcw_fftindex_ratio = 0x02fa; -+ fftindex_bfsfcw_ratio = 0x0158; -+ break; -+ case BANDWIDTH_7_MHZ: -+ coeff1_2048nu = 0x03227b4b; -+ coeff1_4096nu = 0x01913da6; -+ coeff1_8191nu = 0x00c8a518; -+ coeff1_8192nu = 0x00c89ed3; -+ coeff1_8193nu = 0x00c8988e; -+ coeff2_2k = 0x01913da6; -+ coeff2_4k = 0x00c89ed3; -+ coeff2_8k = 0x00644f69; -+ bfsfcw_fftindex_ratio = 0x028d; -+ fftindex_bfsfcw_ratio = 0x0191; -+ break; -+ case BANDWIDTH_8_MHZ: -+ coeff1_2048nu = 0x03951f32; -+ coeff1_4096nu = 0x01ca8f99; -+ coeff1_8191nu = 0x00e54ef7; -+ coeff1_8192nu = 0x00e547cc; -+ coeff1_8193nu = 0x00e540a2; -+ coeff2_2k = 0x01ca8f99; -+ coeff2_4k = 0x00e547cc; -+ coeff2_8k = 0x0072a3e6; -+ bfsfcw_fftindex_ratio = 0x023c; -+ fftindex_bfsfcw_ratio = 0x01cb; -+ break; -+ default: -+ ret = -EINVAL; -+ } -+ break; -+ case 20480000: -+ switch (bw) { -+#if 0 /* keep */ -+ case BANDWIDTH_5_MHZ: -+ coeff1_2048nu = 0x023b6db7; -+ coeff1_4096nu = 0x011db6db; -+ coeff1_8191nu = 0x008edfe5; -+ coeff1_8192nu = 0x008edb6e; -+ coeff1_8193nu = 0x008ed6f7; -+ coeff2_2k = 0x011db6db; -+ coeff2_4k = 0x008edb6e; -+ coeff2_8k = 0x00476db7; -+ bfsfcw_fftindex_ratio = 0x0396; -+ fftindex_bfsfcw_ratio = 0x011e; -+ break; -+#endif -+ case BANDWIDTH_6_MHZ: -+ coeff1_2048nu = 0x02adb6db; -+ coeff1_4096nu = 0x0156db6e; -+ coeff1_8191nu = 0x00ab7312; -+ coeff1_8192nu = 0x00ab6db7; -+ coeff1_8193nu = 0x00ab685c; -+ coeff2_2k = 0x0156db6e; -+ coeff2_4k = 0x00ab6db7; -+ coeff2_8k = 0x0055b6db; -+ bfsfcw_fftindex_ratio = 0x02fd; -+ fftindex_bfsfcw_ratio = 0x0157; -+ break; -+ case BANDWIDTH_7_MHZ: -+ coeff1_2048nu = 0x03200000; -+ coeff1_4096nu = 0x01900000; -+ coeff1_8191nu = 0x00c80640; -+ coeff1_8192nu = 0x00c80000; -+ coeff1_8193nu = 0x00c7f9c0; -+ coeff2_2k = 0x01900000; -+ coeff2_4k = 0x00c80000; -+ coeff2_8k = 0x00640000; -+ bfsfcw_fftindex_ratio = 0x028f; -+ fftindex_bfsfcw_ratio = 0x0190; -+ break; -+ case BANDWIDTH_8_MHZ: -+ coeff1_2048nu = 0x03924925; -+ coeff1_4096nu = 0x01c92492; -+ coeff1_8191nu = 0x00e4996e; -+ coeff1_8192nu = 0x00e49249; -+ coeff1_8193nu = 0x00e48b25; -+ coeff2_2k = 0x01c92492; -+ coeff2_4k = 0x00e49249; -+ coeff2_8k = 0x00724925; -+ bfsfcw_fftindex_ratio = 0x023d; -+ fftindex_bfsfcw_ratio = 0x01c9; -+ break; -+ default: -+ ret = -EINVAL; -+ } -+ break; -+ case 20500000: -+ switch (bw) { -+#if 0 /* keep */ -+ case BANDWIDTH_5_MHZ: -+ coeff1_2048nu = 0x023adeff; -+ coeff1_4096nu = 0x011d6f80; -+ coeff1_8191nu = 0x008ebc36; -+ coeff1_8192nu = 0x008eb7c0; -+ coeff1_8193nu = 0x008eb34a; -+ coeff2_2k = 0x011d6f80; -+ coeff2_4k = 0x008eb7c0; -+ coeff2_8k = 0x00475be0; -+ bfsfcw_fftindex_ratio = 0x0396; -+ fftindex_bfsfcw_ratio = 0x011d; -+ break; -+#endif -+ case BANDWIDTH_6_MHZ: -+ coeff1_2048nu = 0x02ad0b99; -+ coeff1_4096nu = 0x015685cc; -+ coeff1_8191nu = 0x00ab4840; -+ coeff1_8192nu = 0x00ab42e6; -+ coeff1_8193nu = 0x00ab3d8c; -+ coeff2_2k = 0x015685cc; -+ coeff2_4k = 0x00ab42e6; -+ coeff2_8k = 0x0055a173; -+ bfsfcw_fftindex_ratio = 0x02fd; -+ fftindex_bfsfcw_ratio = 0x0157; -+ break; -+ case BANDWIDTH_7_MHZ: -+ coeff1_2048nu = 0x031f3832; -+ coeff1_4096nu = 0x018f9c19; -+ coeff1_8191nu = 0x00c7d44b; -+ coeff1_8192nu = 0x00c7ce0c; -+ coeff1_8193nu = 0x00c7c7ce; -+ coeff2_2k = 0x018f9c19; -+ coeff2_4k = 0x00c7ce0c; -+ coeff2_8k = 0x0063e706; -+ bfsfcw_fftindex_ratio = 0x0290; -+ fftindex_bfsfcw_ratio = 0x0190; -+ break; -+ case BANDWIDTH_8_MHZ: -+ coeff1_2048nu = 0x039164cb; -+ coeff1_4096nu = 0x01c8b266; -+ coeff1_8191nu = 0x00e46056; -+ coeff1_8192nu = 0x00e45933; -+ coeff1_8193nu = 0x00e45210; -+ coeff2_2k = 0x01c8b266; -+ coeff2_4k = 0x00e45933; -+ coeff2_8k = 0x00722c99; -+ bfsfcw_fftindex_ratio = 0x023e; -+ fftindex_bfsfcw_ratio = 0x01c9; -+ break; -+ default: -+ ret = -EINVAL; -+ } -+ break; -+ case 20625000: -+ switch (bw) { -+#if 0 /* keep */ -+ case BANDWIDTH_5_MHZ: -+ coeff1_2048nu = 0x02376948; -+ coeff1_4096nu = 0x011bb4a4; -+ coeff1_8191nu = 0x008ddec1; -+ coeff1_8192nu = 0x008dda52; -+ coeff1_8193nu = 0x008dd5e3; -+ coeff2_2k = 0x011bb4a4; -+ coeff2_4k = 0x008dda52; -+ coeff2_8k = 0x0046ed29; -+ bfsfcw_fftindex_ratio = 0x039c; -+ fftindex_bfsfcw_ratio = 0x011c; -+ break; -+#endif -+ case BANDWIDTH_6_MHZ: -+ coeff1_2048nu = 0x02a8e4bd; -+ coeff1_4096nu = 0x0154725e; -+ coeff1_8191nu = 0x00aa3e81; -+ coeff1_8192nu = 0x00aa392f; -+ coeff1_8193nu = 0x00aa33de; -+ coeff2_2k = 0x0154725e; -+ coeff2_4k = 0x00aa392f; -+ coeff2_8k = 0x00551c98; -+ bfsfcw_fftindex_ratio = 0x0302; -+ fftindex_bfsfcw_ratio = 0x0154; -+ break; -+ case BANDWIDTH_7_MHZ: -+ coeff1_2048nu = 0x031a6032; -+ coeff1_4096nu = 0x018d3019; -+ coeff1_8191nu = 0x00c69e41; -+ coeff1_8192nu = 0x00c6980c; -+ coeff1_8193nu = 0x00c691d8; -+ coeff2_2k = 0x018d3019; -+ coeff2_4k = 0x00c6980c; -+ coeff2_8k = 0x00634c06; -+ bfsfcw_fftindex_ratio = 0x0294; -+ fftindex_bfsfcw_ratio = 0x018d; -+ break; -+ case BANDWIDTH_8_MHZ: -+ coeff1_2048nu = 0x038bdba6; -+ coeff1_4096nu = 0x01c5edd3; -+ coeff1_8191nu = 0x00e2fe02; -+ coeff1_8192nu = 0x00e2f6ea; -+ coeff1_8193nu = 0x00e2efd2; -+ coeff2_2k = 0x01c5edd3; -+ coeff2_4k = 0x00e2f6ea; -+ coeff2_8k = 0x00717b75; -+ bfsfcw_fftindex_ratio = 0x0242; -+ fftindex_bfsfcw_ratio = 0x01c6; -+ break; -+ default: -+ ret = -EINVAL; -+ } -+ break; -+ default: -+ err("invalid xtal freq"); -+ return -EINVAL; -+ } -+ if (ret) { -+ err("invalid bandwidth"); -+ return ret; -+ } -+ -+#ifdef V4L2_ONLY_DVB_V5 -+#undef BANDWIDTH_5_MHZ -+#undef BANDWIDTH_6_MHZ -+#undef BANDWIDTH_7_MHZ -+#undef BANDWIDTH_8_MHZ -+#endif -+ -+ /* adc multiplier */ -+ ret = af9033_read_reg(state, OFDM, api_adcx2, &tmp); -+ if (ret) -+ return ret; -+ -+ if (tmp == 1) { -+ coeff1_2048nu /= 2; -+ coeff1_4096nu /= 2; -+ coeff1_8191nu /= 2; -+ coeff1_8192nu /= 2; -+ coeff1_8193nu /= 2 ; -+ coeff2_2k /= 2; -+ coeff2_4k /= 2; -+ coeff2_8k /= 2; -+ } -+ -+ buf[i++] = (u8) ((coeff1_2048nu & 0x03000000) >> 24); -+ buf[i++] = (u8) ((coeff1_2048nu & 0x00ff0000) >> 16); -+ buf[i++] = (u8) ((coeff1_2048nu & 0x0000ff00) >> 8); -+ buf[i++] = (u8) ((coeff1_2048nu & 0x000000ff)); -+ buf[i++] = (u8) ((coeff1_4096nu & 0x03000000) >> 24); -+ buf[i++] = (u8) ((coeff1_4096nu & 0x00ff0000) >> 16); -+ buf[i++] = (u8) ((coeff1_4096nu & 0x0000ff00) >> 8); -+ buf[i++] = (u8) ((coeff1_4096nu & 0x000000ff)); -+ buf[i++] = (u8) ((coeff1_8191nu & 0x03000000) >> 24); -+ buf[i++] = (u8) ((coeff1_8191nu & 0x00ff0000) >> 16); -+ buf[i++] = (u8) ((coeff1_8191nu & 0x0000ff00) >> 8); -+ buf[i++] = (u8) ((coeff1_8191nu & 0x000000ff)); -+ buf[i++] = (u8) ((coeff1_8192nu & 0x03000000) >> 24); -+ buf[i++] = (u8) ((coeff1_8192nu & 0x00ff0000) >> 16); -+ buf[i++] = (u8) ((coeff1_8192nu & 0x0000ff00) >> 8); -+ buf[i++] = (u8) ((coeff1_8192nu & 0x000000ff)); -+ buf[i++] = (u8) ((coeff1_8193nu & 0x03000000) >> 24); -+ buf[i++] = (u8) ((coeff1_8193nu & 0x00ff0000) >> 16); -+ buf[i++] = (u8) ((coeff1_8193nu & 0x0000ff00) >> 8); -+ buf[i++] = (u8) ((coeff1_8193nu & 0x000000ff)); -+ buf[i++] = (u8) ((coeff2_8k & 0x01000000) >> 24); -+ buf[i++] = (u8) ((coeff2_8k & 0x00ff0000) >> 16); -+ buf[i++] = (u8) ((coeff2_8k & 0x0000ff00) >> 8); -+ buf[i++] = (u8) ((coeff2_8k & 0x000000ff)); -+ buf[i++] = (u8) ((coeff2_2k & 0x01000000) >> 24); -+ buf[i++] = (u8) ((coeff2_2k & 0x00ff0000) >> 16); -+ buf[i++] = (u8) ((coeff2_2k & 0x0000ff00) >> 8); -+ buf[i++] = (u8) ((coeff2_2k & 0x000000ff)); -+ buf[i++] = (u8) ((coeff2_4k & 0x01000000) >> 24); -+ buf[i++] = (u8) ((coeff2_4k & 0x00ff0000) >> 16); -+ buf[i++] = (u8) ((coeff2_4k & 0x0000ff00) >> 8); -+ buf[i++] = (u8) ((coeff2_4k & 0x000000ff)); -+ buf[i++] = (u8) ((bfsfcw_fftindex_ratio & 0x00ff)); -+ buf[i++] = (u8) ((bfsfcw_fftindex_ratio & 0xff00) >> 8); -+ buf[i++] = (u8) ((fftindex_bfsfcw_ratio & 0x00ff)); -+ buf[i++] = (u8) ((fftindex_bfsfcw_ratio & 0xff00) >> 8); -+ -+ deb_info("%s: coeff:", __func__); -+ debug_dump(buf, sizeof(buf), deb_info); -+ -+ /* program */ -+ return af9033_write_regs(state, OFDM, api_cfoe_NS_2048_coeff1_25_24, -+ buf, sizeof(buf)); -+} -+ -+static int af9033_set_crystal_ctrl(struct af9033_state *state) -+{ -+ u8 buf[4]; -+ u32 crystal_cw; -+ deb_info("%s: crystal_clock:%d\n", __func__, -+ state->config.crystal_clock); -+ -+ crystal_cw = af913_div(state->config.crystal_clock, 1000000ul, 19ul); -+ -+ buf[0] = (u8) ((crystal_cw & 0x000000ff)); -+ buf[1] = (u8) ((crystal_cw & 0x0000ff00) >> 8); -+ buf[2] = (u8) ((crystal_cw & 0x00ff0000) >> 16); -+ buf[3] = (u8) ((crystal_cw & 0xff000000) >> 24); -+ -+ deb_info("%s: crystal_cw:", __func__); -+ debug_dump(buf, sizeof(buf), deb_info); -+ -+ /* program */ -+ return af9033_write_regs(state, OFDM, api_crystal_clk_7_0, buf, -+ sizeof(buf)); -+} -+ -+static int af9033_set_adc_ctrl(struct af9033_state *state) -+{ -+ u8 buf[3]; -+ u32 adc_cw; -+ deb_info("%s: adc_clock:%d\n", __func__, state->config.adc_clock); -+ -+ adc_cw = af913_div(state->config.adc_clock, 1000000ul, 19ul); -+ -+ buf[0] = (u8) ((adc_cw & 0x000000ff)); -+ buf[1] = (u8) ((adc_cw & 0x0000ff00) >> 8); -+ buf[2] = (u8) ((adc_cw & 0x00ff0000) >> 16); -+ -+ deb_info("%s: adc_cw:", __func__); -+ debug_dump(buf, sizeof(buf), deb_info); -+ -+ /* program */ -+ return af9033_write_regs(state, OFDM, p_reg_f_adc_7_0, buf, -+ sizeof(buf)); -+} -+ -+static int af9033_set_freq_ctrl(struct af9033_state *state) -+{ -+ int ret; -+ u8 buf[3], tmp; -+ u32 adc_freq, freq_cw; -+ s8 bfs_spec_inv; -+ int if_sample_freq; -+ -+ bfs_spec_inv = state->config.rf_spec_inv ? -1 : 1; -+ -+ adc_freq = state->config.adc_clock; -+ if_sample_freq = state->config.if_freq; -+ -+ while (if_sample_freq > (adc_freq / 2)) -+ if_sample_freq = if_sample_freq - adc_freq; -+ -+ if (if_sample_freq >= 0) -+ bfs_spec_inv = bfs_spec_inv * (-1); -+ else -+ if_sample_freq = if_sample_freq * (-1); -+ -+ freq_cw = af913_div(if_sample_freq, adc_freq, 23ul); -+ -+ if (bfs_spec_inv == -1) -+ freq_cw *= -1; -+ -+ /* adc multiplier */ -+ ret = af9033_read_reg(state, OFDM, api_adcx2, &tmp); -+ if (ret) -+ return ret; -+ -+ if (tmp == 1) -+ freq_cw /= 2; -+ -+ buf[0] = (u8) ((freq_cw & 0x000000ff)); -+ buf[1] = (u8) ((freq_cw & 0x0000ff00) >> 8); -+ buf[2] = (u8) ((freq_cw & 0x007f0000) >> 16); -+ -+ deb_info("%s: freq_cw:", __func__); -+ debug_dump(buf, sizeof(buf), deb_info); -+ -+ /* program */ -+ return af9033_write_regs(state, OFDM, api_bfs_fcw_7_0, buf, -+ sizeof(buf)); -+} -+static void af9033_release(struct dvb_frontend *fe) -+{ -+ struct af9033_state *state = fe->demodulator_priv; -+ kfree(state); -+} -+ -+static int af9033_init(struct dvb_frontend *fe) -+{ -+ struct af9033_state *state = fe->demodulator_priv; -+ int ret, i, len; -+ u8 tmp0, tmp1; -+ struct regdesc *init; -+ deb_info("%s\n", __func__); -+ -+ /* power on */ -+ ret = af9033_write_reg_bits(state, OFDM, p_reg_afe_mem0, 3, 1, 0); -+ if (ret) -+ goto error; -+ -+ ret = af9033_write_reg(state, OFDM, api_suspend_flag, 0); -+ if (ret) -+ goto error; -+ -+ /* tell to the firmware type of the tuner */ -+ ret = af9033_write_reg(state, LINK, p_reg_link_ofsm_dummy_15_8, -+ state->config.tuner); -+ if (ret) -+ goto error; -+ -+ /* set read-update bit for constellation */ -+ ret = af9033_write_reg_bits(state, OFDM, p_reg_feq_read_update, -+ reg_feq_read_update_pos, reg_feq_read_update_len, 1); -+ if (ret) -+ goto error; -+ -+ /* enable FEC monitor */ -+ ret = af9033_write_reg_bits(state, OFDM, p_fec_vtb_rsd_mon_en, -+ fec_vtb_rsd_mon_en_pos, fec_vtb_rsd_mon_en_len, 1); -+ if (ret) -+ goto error; -+ -+ /* program crystal control */ -+ ret = af9033_set_crystal_ctrl(state); -+ if (ret) -+ goto error; -+ -+ /* program ADC control */ -+ ret = af9033_set_adc_ctrl(state); -+ if (ret) -+ goto error; -+ -+ /* enable DVB-T interrupt */ -+ ret = af9033_write_reg_bits(state, LINK, p_reg_dvbt_inten, -+ reg_dvbt_inten_pos, reg_dvbt_inten_len, 1); -+ if (ret) -+ goto error; -+ -+ /* enable DVB-T mode */ -+ ret = af9033_write_reg_bits(state, LINK, p_reg_dvbt_en, -+ reg_dvbt_en_pos, reg_dvbt_en_len, 1); -+ if (ret) -+ goto error; -+ -+ /* set dca_upper_chip */ -+ ret = af9033_write_reg_bits(state, OFDM, p_reg_dca_upper_chip, -+ reg_dca_upper_chip_pos, reg_dca_upper_chip_len, 0); -+ if (ret) -+ goto error; -+ -+ ret = af9033_write_reg_bits(state, LINK, p_reg_top_hostb_dca_upper, -+ reg_top_hostb_dca_upper_pos, reg_top_hostb_dca_upper_len, 0); -+ if (ret) -+ goto error; -+ -+ ret = af9033_write_reg_bits(state, LINK, p_reg_top_hosta_dca_upper, -+ reg_top_hosta_dca_upper_pos, reg_top_hosta_dca_upper_len, 0); -+ if (ret) -+ goto error; -+ -+ /* set dca_lower_chip */ -+ ret = af9033_write_reg_bits(state, OFDM, p_reg_dca_lower_chip, -+ reg_dca_lower_chip_pos, reg_dca_lower_chip_len, 0); -+ if (ret) -+ goto error; -+ -+ ret = af9033_write_reg_bits(state, LINK, p_reg_top_hostb_dca_lower, -+ reg_top_hostb_dca_lower_pos, reg_top_hostb_dca_lower_len, 0); -+ if (ret) -+ goto error; -+ -+ ret = af9033_write_reg_bits(state, LINK, p_reg_top_hosta_dca_lower, -+ reg_top_hosta_dca_lower_pos, reg_top_hosta_dca_lower_len, 0); -+ if (ret) -+ goto error; -+ -+ /* set phase latch */ -+ ret = af9033_write_reg_bits(state, OFDM, p_reg_dca_platch, -+ reg_dca_platch_pos, reg_dca_platch_len, 0); -+ if (ret) -+ goto error; -+ -+ /* set fpga latch */ -+ ret = af9033_write_reg(state, OFDM, p_reg_dca_fpga_latch, 0); -+ if (ret) -+ goto error; -+ -+ /* set stand alone */ -+ ret = af9033_write_reg_bits(state, OFDM, p_reg_dca_stand_alone, -+ reg_dca_stand_alone_pos, reg_dca_stand_alone_len, 1); -+ if (ret) -+ goto error; -+ -+ /* set DCA enable */ -+ ret = af9033_write_reg_bits(state, OFDM, p_reg_dca_en, reg_dca_en_pos, -+ reg_dca_en_len, 0); -+ if (ret) -+ goto error; -+ -+ /* load OFSM settings */ -+ deb_info("%s: load ofsm settings\n", __func__); -+ len = ARRAY_SIZE(ofsm_init); -+ init = ofsm_init; -+ for (i = 0; i < len; i++) { -+ ret = af9033_write_reg(state, OFDM, init[i].addr, init[i].val); -+ if (ret) -+ goto error; -+ } -+ -+ /* load tuner specific settings */ -+ deb_info("%s: load tuner specific settings\n", __func__); -+ switch (state->config.tuner) { -+ case AF9033_TUNER_TUA9001: -+ len = ARRAY_SIZE(tuner_init_tua9001); -+ init = tuner_init_tua9001; -+ break; -+ case AF9033_TUNER_MXL5007t: -+ len = ARRAY_SIZE(tuner_init_mxl5007t); -+ init = tuner_init_mxl5007t; -+ break; -+ case AF9033_TUNER_TDA18218: -+ len = ARRAY_SIZE(tuner_init_tda18218); -+ init = tuner_init_tda18218; -+ break; -+ default: -+ len = 0; -+ init = NULL; -+ break; -+ } -+ for (i = 0; i < len; i++) { -+ ret = af9033_write_reg(state, OFDM, init[i].addr, init[i].val); -+ if (ret) -+ goto error; -+ } -+ -+ /* set H/W MPEG2 locked detection **/ -+ ret = af9033_write_reg(state, LINK, p_reg_top_lock3_out, 1); -+ if (ret) -+ goto error; -+ -+ /* set registers for driving power */ -+ ret = af9033_write_reg(state, LINK, p_reg_top_padmiscdr2, 1); -+ if (ret) -+ goto error; -+ -+ /* et registers for driving power */ -+ ret = af9033_write_reg(state, LINK, p_reg_top_padmiscdr4, 0); -+ if (ret) -+ goto error; -+ -+ /* set registers for driving power */ -+ ret = af9033_write_reg(state, LINK, p_reg_top_padmiscdr8, 0); -+ if (ret) -+ goto error; -+ -+ /* set TS mode */ -+ deb_info("%s: setting ts mode\n", __func__); -+ tmp0 = 0; /* parallel mode */ -+ tmp1 = 0; /* serial mode */ -+ switch (state->config.output_mode) { -+ case AF9033_TS_MODE_PARALLEL: -+ tmp0 = 1; -+ break; -+ case AF9033_TS_MODE_SERIAL: -+ tmp1 = 1; -+ break; -+ case AF9033_TS_MODE_USB: -+ /* usb mode for AF9035 */ -+ default: -+ break; -+ } -+ ret = af9033_write_reg_bits(state, OFDM, p_mp2if_mpeg_par_mode, -+ mp2if_mpeg_par_mode_pos, mp2if_mpeg_par_mode_len, tmp0); -+ if (ret) -+ goto error; -+ ret = af9033_write_reg_bits(state, OFDM, p_mp2if_mpeg_ser_mode, -+ mp2if_mpeg_ser_mode_pos, mp2if_mpeg_ser_mode_len, tmp1); -+ if (ret) -+ goto error; -+ -+ if (state->config.output_mode == AF9033_TS_MODE_SERIAL) { -+ ret = af9033_write_reg_bits(state, LINK, p_reg_top_hostb_mpeg_ser_mode, -+ reg_top_hostb_mpeg_ser_mode_pos, reg_top_hostb_mpeg_ser_mode_len, 1); -+ if (ret) -+ goto error; -+ } -+error: -+ if (ret) -+ deb_info("%s: failed:%d\n", __func__, ret); -+ -+ return ret; -+} -+ -+static int af9033_sleep(struct dvb_frontend *fe) -+{ -+ struct af9033_state *state = fe->demodulator_priv; -+ int ret; -+ u8 tmp, i; -+ deb_info("%s\n", __func__); -+ -+ ret = af9033_write_reg(state, OFDM, api_suspend_flag, 1); -+ if (ret) -+ goto error; -+ -+ ret = af9033_write_reg(state, OFDM, api_trigger_ofsm, 0); -+ if (ret) -+ goto error; -+ -+ for (i = 0; i < 150; i++) { -+ ret = af9033_read_reg(state, OFDM, api_suspend_flag, &tmp); -+ if (ret) -+ goto error; -+ if (!tmp) -+ break; -+ msleep(10); -+ } -+ if (tmp) { -+ deb_info("%s: power off time outs\n", __func__); -+ return -ETIMEDOUT; -+ } -+ -+ ret = af9033_write_reg_bits(state, OFDM, p_reg_afe_mem0, 3, 1, 1); -+ if (ret) -+ goto error; -+ -+ /* fixed current leakage (?) */ -+ if (state->config.output_mode != AF9033_TS_MODE_USB) { -+ /* enable parallel TS */ -+ ret = af9033_write_reg_bits(state, LINK, -+ p_reg_top_hosta_mpeg_ser_mode, -+ reg_top_hosta_mpeg_ser_mode_pos, -+ reg_top_hosta_mpeg_ser_mode_len, 0); -+ if (ret) -+ goto error; -+ -+ ret = af9033_write_reg_bits(state, LINK, -+ p_reg_top_hosta_mpeg_par_mode, -+ reg_top_hosta_mpeg_par_mode_pos, -+ reg_top_hosta_mpeg_par_mode_len, 1); -+ } -+ -+error: -+ if (ret) -+ deb_info("%s: failed:%d\n", __func__, ret); -+ -+ return ret; -+} -+ -+#ifdef V4L2_ONLY_DVB_V5 -+static int af9033_set_frontend(struct dvb_frontend *fe) -+{ -+ struct dtv_frontend_properties *params = &fe->dtv_property_cache; -+ struct af9033_state *state = fe->demodulator_priv; -+ int ret; -+ u8 tmp; -+ deb_info("%s: freq:%d bw:%d\n", __func__, params->frequency, -+ params->bandwidth_hz); -+ -+ state->frequency = params->frequency; -+ -+ /* program tuner */ -+ if (fe->ops.tuner_ops.set_params) -+ fe->ops.tuner_ops.set_params(fe); -+ -+ /* program CFOE coefficients */ -+ ret = af9033_set_coeff(state, params->bandwidth_hz); -+ if (ret) -+ goto error; -+ -+ /* program frequency control */ -+ ret = af9033_set_freq_ctrl(state); -+ if (ret) -+ goto error; -+ -+ /* program bandwidth */ -+ switch (params->bandwidth_hz) { -+ case 6000000: -+ tmp = 0; -+ break; -+ case 7000000: -+ tmp = 1; -+ break; -+ case 8000000: -+ tmp = 2; -+ break; -+#if 0 /* keep */ -+ case 5000000: -+ tmp = 3; -+ break; -+#endif -+ default: -+ deb_info("%s: invalid bandwidth\n", __func__); -+ return -EINVAL; -+ } -+ ret = af9033_write_reg_bits(state, OFDM, g_reg_bw, reg_bw_pos, -+ reg_bw_len, tmp); -+ if (ret) -+ goto error; -+ -+ /* clear easy mode flag */ -+ ret = af9033_write_reg(state, OFDM, api_Training_Mode, 0x00); -+ if (ret) -+ goto error; -+ -+ /* clear empty channel flag */ -+ ret = af9033_write_reg(state, OFDM, api_empty_channel_status, 0x00); -+ if (ret) -+ goto error; -+ -+ /* clear MPEG2 lock flag */ -+ ret = af9033_write_reg_bits(state, OFDM, r_mp2if_sync_byte_locked, -+ mp2if_sync_byte_locked_pos, mp2if_sync_byte_locked_len, 0x00); -+ if (ret) -+ goto error; -+ -+ /* set frequency band -+ 174 - 230 MHz VHF band = 0x00 -+ 350 - 900 MHz UHF band = 0x01 -+ 1670 - 1680 MHz L-BAND band = 0x02 -+ otherwise band = 0xff */ -+ /* TODO: are both min/max ranges really required... */ -+ if ((state->frequency >= 174000000) && (state->frequency <= 230000000)) -+ tmp = 0x00; /* VHF */ -+ else if ((state->frequency >= 350000000) && (state->frequency <= 900000000)) -+ tmp = 0x01; /* UHF */ -+ else if ((state->frequency >= 1670000000) && (state->frequency <= 1680000000)) -+ tmp = 0x02; /* L-BAND */ -+ else -+ tmp = 0xff; -+ -+ ret = af9033_write_reg(state, OFDM, api_FreBand, tmp); -+ if (ret) -+ goto error; -+ -+ /* trigger ofsm */ -+ ret = af9033_write_reg(state, OFDM, api_trigger_ofsm, 0); -+ if (ret) -+ goto error; -+error: -+ if (ret) -+ deb_info("%s: failed:%d\n", __func__, ret); -+ -+ return ret; -+} -+#else -+static int af9033_set_frontend(struct dvb_frontend *fe, -+ struct dvb_frontend_parameters *params) -+{ -+ struct af9033_state *state = fe->demodulator_priv; -+ int ret; -+ u8 tmp; -+ deb_info("%s: freq:%d bw:%d\n", __func__, params->frequency, -+ params->u.ofdm.bandwidth); -+ -+ state->frequency = params->frequency; -+ -+ /* program tuner */ -+ if (fe->ops.tuner_ops.set_params) -+ fe->ops.tuner_ops.set_params(fe, params); -+ -+ /* program CFOE coefficients */ -+ ret = af9033_set_coeff(state, params->u.ofdm.bandwidth); -+ if (ret) -+ goto error; -+ -+ /* program frequency control */ -+ ret = af9033_set_freq_ctrl(state); -+ if (ret) -+ goto error; -+ -+ /* program bandwidth */ -+ switch (params->u.ofdm.bandwidth) { -+ case BANDWIDTH_6_MHZ: -+ tmp = 0; -+ break; -+ case BANDWIDTH_7_MHZ: -+ tmp = 1; -+ break; -+ case BANDWIDTH_8_MHZ: -+ tmp = 2; -+ break; -+#if 0 /* keep */ -+ case BANDWIDTH_5_MHZ: -+ tmp = 3; -+ break; -+#endif -+ default: -+ deb_info("%s: invalid bandwidth\n", __func__); -+ return -EINVAL; -+ } -+ ret = af9033_write_reg_bits(state, OFDM, g_reg_bw, reg_bw_pos, -+ reg_bw_len, tmp); -+ if (ret) -+ goto error; -+ -+ /* clear easy mode flag */ -+ ret = af9033_write_reg(state, OFDM, api_Training_Mode, 0x00); -+ if (ret) -+ goto error; -+ -+ /* clear empty channel flag */ -+ ret = af9033_write_reg(state, OFDM, api_empty_channel_status, 0x00); -+ if (ret) -+ goto error; -+ -+ /* clear MPEG2 lock flag */ -+ ret = af9033_write_reg_bits(state, OFDM, r_mp2if_sync_byte_locked, -+ mp2if_sync_byte_locked_pos, mp2if_sync_byte_locked_len, 0x00); -+ if (ret) -+ goto error; -+ -+ /* set frequency band -+ 174 - 230 MHz VHF band = 0x00 -+ 350 - 900 MHz UHF band = 0x01 -+ 1670 - 1680 MHz L-BAND band = 0x02 -+ otherwise band = 0xff */ -+ /* TODO: are both min/max ranges really required... */ -+ if ((state->frequency >= 174000000) && (state->frequency <= 230000000)) -+ tmp = 0x00; /* VHF */ -+ else if ((state->frequency >= 350000000) && (state->frequency <= 900000000)) -+ tmp = 0x01; /* UHF */ -+ else if ((state->frequency >= 1670000000) && (state->frequency <= 1680000000)) -+ tmp = 0x02; /* L-BAND */ -+ else -+ tmp = 0xff; -+ -+ ret = af9033_write_reg(state, OFDM, api_FreBand, tmp); -+ if (ret) -+ goto error; -+ -+ /* trigger ofsm */ -+ ret = af9033_write_reg(state, OFDM, api_trigger_ofsm, 0); -+ if (ret) -+ goto error; -+error: -+ if (ret) -+ deb_info("%s: failed:%d\n", __func__, ret); -+ -+ return ret; -+} -+#endif -+ -+static int af9033_get_tune_settings(struct dvb_frontend *fe, -+ struct dvb_frontend_tune_settings *fesettings) -+{ -+ fesettings->min_delay_ms = 800; -+ fesettings->step_size = 0; -+ fesettings->max_drift = 0; -+ -+ return 0; -+} -+ -+#ifdef V4L2_ONLY_DVB_V5 -+static int af9033_get_frontend(struct dvb_frontend *fe) -+{ -+ struct dtv_frontend_properties *p = &fe->dtv_property_cache; -+ struct af9033_state *state = fe->demodulator_priv; -+ int ret; -+ u8 buf[8]; -+ deb_info("%s\n", __func__); -+#define TRANSMISSION_MODE (g_reg_tpsd_txmod - g_reg_tpsd_txmod) -+#define GUARD_INTERVAL (g_reg_tpsd_gi - g_reg_tpsd_txmod) -+#define HIERARCHY (g_reg_tpsd_hier - g_reg_tpsd_txmod) -+#define CONSTELLATION (g_reg_tpsd_const - g_reg_tpsd_txmod) -+#define BANDWIDTH (g_reg_bw - g_reg_tpsd_txmod) -+#define PRIORITY (g_reg_dec_pri - g_reg_tpsd_txmod) -+#define CODE_RATE_HP (g_reg_tpsd_hpcr - g_reg_tpsd_txmod) -+#define CODE_RATE_LP (g_reg_tpsd_lpcr - g_reg_tpsd_txmod) -+ -+ /* read all needed registers */ -+ ret = af9033_read_regs(state, OFDM, g_reg_tpsd_txmod, buf, sizeof(buf)); -+ if (ret) -+ goto error; -+ -+ deb_info("%s: ", __func__); -+ debug_dump(buf, sizeof(buf), deb_info); -+ -+ switch ((buf[CONSTELLATION] >> 0) & 3) { -+ case 0: -+ p->modulation = QPSK; -+ break; -+ case 1: -+ p->modulation = QAM_16; -+ break; -+ case 2: -+ p->modulation = QAM_64; -+ break; -+ } -+ -+ switch ((buf[TRANSMISSION_MODE] >> 0) & 3) { -+ case 0: -+ p->transmission_mode = TRANSMISSION_MODE_2K; -+ break; -+ case 1: -+ p->transmission_mode = TRANSMISSION_MODE_8K; -+ break; -+#if 0 /* keep */ -+ case 2: -+ p->transmission_mode = TRANSMISSION_MODE_4K; -+ break; -+#endif -+ } -+ -+ switch ((buf[GUARD_INTERVAL] >> 0) & 3) { -+ case 0: -+ p->guard_interval = GUARD_INTERVAL_1_32; -+ break; -+ case 1: -+ p->guard_interval = GUARD_INTERVAL_1_16; -+ break; -+ case 2: -+ p->guard_interval = GUARD_INTERVAL_1_8; -+ break; -+ case 3: -+ p->guard_interval = GUARD_INTERVAL_1_4; -+ break; -+ } -+ -+ switch ((buf[HIERARCHY] >> 0) & 7) { -+ case 0: -+ p->hierarchy = HIERARCHY_NONE; -+ break; -+ case 1: -+ p->hierarchy = HIERARCHY_1; -+ break; -+ case 2: -+ p->hierarchy = HIERARCHY_2; -+ break; -+ case 3: -+ p->hierarchy = HIERARCHY_4; -+ break; -+ } -+ -+ switch ((buf[CODE_RATE_HP] >> 0) & 7) { -+ case 0: -+ p->code_rate_HP = FEC_1_2; -+ break; -+ case 1: -+ p->code_rate_HP = FEC_2_3; -+ break; -+ case 2: -+ p->code_rate_HP = FEC_3_4; -+ break; -+ case 3: -+ p->code_rate_HP = FEC_5_6; -+ break; -+ case 4: -+ p->code_rate_HP = FEC_7_8; -+ break; -+ case 5: -+ p->code_rate_HP = FEC_NONE; -+ break; -+ } -+ -+ switch ((buf[CODE_RATE_LP] >> 0) & 7) { -+ case 0: -+ p->code_rate_LP = FEC_1_2; -+ break; -+ case 1: -+ p->code_rate_LP = FEC_2_3; -+ break; -+ case 2: -+ p->code_rate_LP = FEC_3_4; -+ break; -+ case 3: -+ p->code_rate_LP = FEC_5_6; -+ break; -+ case 4: -+ p->code_rate_LP = FEC_7_8; -+ break; -+ case 5: -+ p->code_rate_LP = FEC_NONE; -+ break; -+ } -+ -+ switch ((buf[BANDWIDTH] >> 0) & 3) { -+ case 0: -+ p->bandwidth_hz = 6000000; -+ break; -+ case 1: -+ p->bandwidth_hz = 7000000; -+ break; -+ case 2: -+ p->bandwidth_hz = 8000000; -+ break; -+#if 0 /* keep */ -+ case 3: -+ p->bandwidth_hz = 5000000; -+ break; -+#endif -+ } -+ -+ p->inversion = INVERSION_AUTO; -+ p->frequency = state->frequency; -+ -+error: -+ if (ret) -+ deb_info("%s: failed:%d\n", __func__, ret); -+ -+ return ret; -+} -+#else -+static int af9033_get_frontend(struct dvb_frontend *fe, -+ struct dvb_frontend_parameters *p) -+{ -+ struct af9033_state *state = fe->demodulator_priv; -+ int ret; -+ u8 buf[8]; -+ deb_info("%s\n", __func__); -+#define TRANSMISSION_MODE (g_reg_tpsd_txmod - g_reg_tpsd_txmod) -+#define GUARD_INTERVAL (g_reg_tpsd_gi - g_reg_tpsd_txmod) -+#define HIERARCHY (g_reg_tpsd_hier - g_reg_tpsd_txmod) -+#define CONSTELLATION (g_reg_tpsd_const - g_reg_tpsd_txmod) -+#define BANDWIDTH (g_reg_bw - g_reg_tpsd_txmod) -+#define PRIORITY (g_reg_dec_pri - g_reg_tpsd_txmod) -+#define CODE_RATE_HP (g_reg_tpsd_hpcr - g_reg_tpsd_txmod) -+#define CODE_RATE_LP (g_reg_tpsd_lpcr - g_reg_tpsd_txmod) -+ -+ /* read all needed registers */ -+ ret = af9033_read_regs(state, OFDM, g_reg_tpsd_txmod, buf, sizeof(buf)); -+ if (ret) -+ goto error; -+ -+ deb_info("%s: ", __func__); -+ debug_dump(buf, sizeof(buf), deb_info); -+ -+ switch ((buf[CONSTELLATION] >> 0) & 3) { -+ case 0: -+ p->u.ofdm.constellation = QPSK; -+ break; -+ case 1: -+ p->u.ofdm.constellation = QAM_16; -+ break; -+ case 2: -+ p->u.ofdm.constellation = QAM_64; -+ break; -+ } -+ -+ switch ((buf[TRANSMISSION_MODE] >> 0) & 3) { -+ case 0: -+ p->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K; -+ break; -+ case 1: -+ p->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; -+ break; -+#if 0 /* keep */ -+ case 2: -+ p->u.ofdm.transmission_mode = TRANSMISSION_MODE_4K; -+ break; -+#endif -+ } -+ -+ switch ((buf[GUARD_INTERVAL] >> 0) & 3) { -+ case 0: -+ p->u.ofdm.guard_interval = GUARD_INTERVAL_1_32; -+ break; -+ case 1: -+ p->u.ofdm.guard_interval = GUARD_INTERVAL_1_16; -+ break; -+ case 2: -+ p->u.ofdm.guard_interval = GUARD_INTERVAL_1_8; -+ break; -+ case 3: -+ p->u.ofdm.guard_interval = GUARD_INTERVAL_1_4; -+ break; -+ } -+ -+ switch ((buf[HIERARCHY] >> 0) & 7) { -+ case 0: -+ p->u.ofdm.hierarchy_information = HIERARCHY_NONE; -+ break; -+ case 1: -+ p->u.ofdm.hierarchy_information = HIERARCHY_1; -+ break; -+ case 2: -+ p->u.ofdm.hierarchy_information = HIERARCHY_2; -+ break; -+ case 3: -+ p->u.ofdm.hierarchy_information = HIERARCHY_4; -+ break; -+ } -+ -+ switch ((buf[CODE_RATE_HP] >> 0) & 7) { -+ case 0: -+ p->u.ofdm.code_rate_HP = FEC_1_2; -+ break; -+ case 1: -+ p->u.ofdm.code_rate_HP = FEC_2_3; -+ break; -+ case 2: -+ p->u.ofdm.code_rate_HP = FEC_3_4; -+ break; -+ case 3: -+ p->u.ofdm.code_rate_HP = FEC_5_6; -+ break; -+ case 4: -+ p->u.ofdm.code_rate_HP = FEC_7_8; -+ break; -+ case 5: -+ p->u.ofdm.code_rate_HP = FEC_NONE; -+ break; -+ } -+ -+ switch ((buf[CODE_RATE_LP] >> 0) & 7) { -+ case 0: -+ p->u.ofdm.code_rate_LP = FEC_1_2; -+ break; -+ case 1: -+ p->u.ofdm.code_rate_LP = FEC_2_3; -+ break; -+ case 2: -+ p->u.ofdm.code_rate_LP = FEC_3_4; -+ break; -+ case 3: -+ p->u.ofdm.code_rate_LP = FEC_5_6; -+ break; -+ case 4: -+ p->u.ofdm.code_rate_LP = FEC_7_8; -+ break; -+ case 5: -+ p->u.ofdm.code_rate_HP = FEC_NONE; -+ break; -+ } -+ -+ switch ((buf[BANDWIDTH] >> 0) & 3) { -+ case 0: -+ p->u.ofdm.bandwidth = BANDWIDTH_6_MHZ; -+ break; -+ case 1: -+ p->u.ofdm.bandwidth = BANDWIDTH_7_MHZ; -+ break; -+ case 2: -+ p->u.ofdm.bandwidth = BANDWIDTH_8_MHZ; -+ break; -+#if 0 /* keep */ -+ case 3: -+ p->u.ofdm.bandwidth = BANDWIDTH_5_MHZ; -+ break; -+#endif -+ } -+ -+ p->inversion = INVERSION_AUTO; -+ p->frequency = state->frequency; -+ -+error: -+ if (ret) -+ deb_info("%s: failed:%d\n", __func__, ret); -+ -+ return ret; -+} -+#endif -+ -+static int af9033_update_ber_ucblocks(struct dvb_frontend *fe) -+{ -+ struct af9033_state *state = fe->demodulator_priv; -+ int ret; -+ u8 buf[3]; -+ u32 error_bit_count = 0; -+ u32 total_bit_count = 0; -+ u16 abort_packet_count = 0; -+ -+ /* don't update ber / ucblocks unnecessary often */ -+ if (time_before(jiffies, state->next_statistics_check)) -+ return 0; -+ -+ /* set minimum ber / ucblocks update interval */ -+ state->next_statistics_check = jiffies + msecs_to_jiffies(500); -+ -+ state->ber = 0; -+ -+ /* no need to check ber / ucblocks in case of no lock */ -+ ret = af9033_read_reg_bits(state, OFDM, -+ r_mp2if_sync_byte_locked, mp2if_sync_byte_locked_pos, -+ mp2if_sync_byte_locked_len, buf); -+ if (ret) -+ goto error; -+ if (!buf[0]) -+ goto exit; -+ -+ /* get abort packet count */ -+ ret = af9033_read_regs(state, OFDM, api_rsd_abort_packet_cnt_7_0, buf, -+ sizeof(buf) - 1); -+ if (ret) -+ goto error; -+ -+ abort_packet_count = (buf[1] << 8) + buf[0]; -+ -+ /* get error bit count */ -+ ret = af9033_read_regs(state, OFDM, api_rsd_bit_err_cnt_7_0, buf, -+ sizeof(buf)); -+ if (ret) -+ goto error; -+ -+ error_bit_count = (buf[2] << 16) + (buf[1] << 8) + buf[0]; -+ error_bit_count = error_bit_count - abort_packet_count * 8 * 8; -+ -+ /* get used RSD counting period (it is 10000 by defaut) */ -+ ret = af9033_read_regs(state, OFDM, api_r_rsd_packet_unit_7_0, buf, -+ sizeof(buf) - 1); -+ if (ret) -+ goto error; -+ -+ total_bit_count = (buf[1] << 8) + buf[0]; -+ total_bit_count = total_bit_count - abort_packet_count; -+ total_bit_count = total_bit_count * 204 * 8; -+ -+ if (total_bit_count) -+ state->ber = error_bit_count * 1000000000 / total_bit_count; -+ -+ state->ucblocks += abort_packet_count; -+ -+ deb_info("%s: err bits:%d total bits:%d abort count:%d\n", __func__, -+ error_bit_count, total_bit_count, abort_packet_count); -+ -+error: -+ if (ret) -+ deb_info("%s: failed:%d\n", __func__, ret); -+exit: -+ return ret; -+} -+ -+static int af9033_update_snr(struct dvb_frontend *fe) -+{ -+ struct af9033_state *state = fe->demodulator_priv; -+ int ret; -+ u8 buf[3], i, len; -+ u32 snr_val; -+ struct snr_table *uninitialized_var(snr_table); -+ -+ /* read snr registers */ -+ ret = af9033_read_regs(state, OFDM, api_qnt_vbc_err_7_0, buf, -+ sizeof(buf)); -+ if (ret) -+ goto error; -+ snr_val = (buf[2] << 16) + (buf[1] << 8) + buf[0]; -+ -+ /* read current constellation */ -+ ret = af9033_read_reg_bits(state, OFDM, g_reg_tpsd_const, -+ reg_tpsd_const_pos, reg_tpsd_const_len, &buf[0]); -+ if (ret) -+ goto error; -+ -+ switch (buf[0]) { -+ case 0: -+ len = ARRAY_SIZE(qpsk_snr_table); -+ snr_table = qpsk_snr_table; -+ break; -+ case 1: -+ len = ARRAY_SIZE(qam16_snr_table); -+ snr_table = qam16_snr_table; -+ break; -+ case 2: -+ len = ARRAY_SIZE(qam64_snr_table); -+ snr_table = qam64_snr_table; -+ break; -+ default: -+ len = 0; -+ } -+ -+ /* get snr from lookup table */ -+ for (i = 0; i < len; i++) { -+ if (snr_val < snr_table[i].val) { -+ state->snr = snr_table[i].snr * 10; -+ break; -+ } -+ } -+ deb_info("%s: snr_val:%x snr:%x\n", __func__, snr_val, state->snr); -+ -+ if (len && !af9033_snrdb) -+ state->snr = (0xffff / (snr_table[len - 1].snr * 10)) * state->snr; -+ -+error: -+ return ret; -+} -+ -+static int af9033_update_signal_strength(struct dvb_frontend *fe) -+{ -+ struct af9033_state *state = fe->demodulator_priv; -+ int ret; -+ u8 strength; -+ -+ /* read signal strength from 0-100 scale */ -+ ret = af9033_read_reg(state, OFDM, api_signal_strength, &strength); -+ if (ret) -+ goto error; -+ -+ /* scale value to 0x0000-0xffff */ -+ state->signal_strength = strength * 0xffff / 100; -+ -+error: -+ return ret; -+} -+ -+static int af9033_read_status(struct dvb_frontend *fe, fe_status_t *status) -+{ -+ struct af9033_state *state = fe->demodulator_priv; -+ int ret = 0; -+ u8 tmp; -+ *status = 0; -+ -+ /* empty channel; 0:no result, 1:signal, 2:empty */ -+ ret = af9033_read_reg(state, OFDM, api_empty_channel_status, &tmp); -+ if (ret) -+ goto error; -+ if (tmp == 0x01) /* have signal */ -+ *status |= FE_HAS_SIGNAL; -+ -+ if (tmp != 0x02) { -+ /* TPS lock */ -+ ret = af9033_read_reg_bits(state, OFDM, p_fd_tpsd_lock, -+ fd_tpsd_lock_pos, fd_tpsd_lock_len, &tmp); -+ if (ret) -+ goto error; -+ if (tmp) -+ *status |= FE_HAS_VITERBI | FE_HAS_CARRIER; -+ -+ /* MPEG2 lock */ -+ ret = af9033_read_reg_bits(state, OFDM, -+ r_mp2if_sync_byte_locked, mp2if_sync_byte_locked_pos, -+ mp2if_sync_byte_locked_len, &tmp); -+ if (ret) -+ goto error; -+ if (tmp) -+ *status |= FE_HAS_SYNC | FE_HAS_LOCK; -+ } -+ -+ /* update ber / ucblocks */ -+ ret = af9033_update_ber_ucblocks(fe); -+ -+error: -+ if (ret) -+ deb_info("%s: failed:%d\n", __func__, ret); -+ -+ return ret; -+} -+ -+static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber) -+{ -+ struct af9033_state *state = fe->demodulator_priv; -+ int ret; -+ deb_info("%s\n", __func__); -+ ret = af9033_update_ber_ucblocks(fe); -+ *ber = state->ber; -+ return ret; -+} -+ -+static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength) -+{ -+ struct af9033_state *state = fe->demodulator_priv; -+ int ret; -+ deb_info("%s\n", __func__); -+ ret = af9033_update_signal_strength(fe); -+ if (ret) -+ goto error; -+ ret = af9033_update_ber_ucblocks(fe); -+ *strength = state->signal_strength; -+error: -+ return ret; -+} -+ -+static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr) -+{ -+ struct af9033_state *state = fe->demodulator_priv; -+ int ret; -+ deb_info("%s\n", __func__); -+ ret = af9033_update_snr(fe); -+ if (ret) -+ goto error; -+ ret = af9033_update_ber_ucblocks(fe); -+ *snr = state->snr; -+error: -+ return ret; -+} -+ -+static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) -+{ -+ struct af9033_state *state = fe->demodulator_priv; -+ int ret; -+ deb_info("%s\n", __func__); -+ ret = af9033_update_ber_ucblocks(fe); -+ *ucblocks = state->ucblocks; -+ return ret; -+} -+ -+static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) -+{ -+ struct af9033_state *state = fe->demodulator_priv; -+ deb_info("%s: enable:%d\n", __func__, enable); -+ -+ return af9033_write_reg_bits(state, LINK, p_reg_bypass_host2tuner, -+ reg_bypass_host2tuner_pos, reg_bypass_host2tuner_len, enable); -+} -+ -+static struct dvb_frontend_ops af9033_ops; -+ -+struct dvb_frontend *af9033_attach(const struct af9033_config *config, -+ struct i2c_adapter *i2c) -+{ -+ int ret; -+ struct af9033_state *state = NULL; -+ u8 buf[8]; -+ deb_info("%s:\n", __func__); -+ -+ /* allocate memory for the internal state */ -+ state = kzalloc(sizeof(struct af9033_state), GFP_KERNEL); -+ if (state == NULL) -+ goto error; -+ -+ /* setup the state */ -+ state->i2c = i2c; -+ memcpy(&state->config, config, sizeof(struct af9033_config)); -+ -+ /* firmware version */ -+ ret = af9033_read_regs(state, LINK, 0x83e9, &buf[0], sizeof(buf) / 2); -+ if (ret) -+ goto error; -+ -+ ret = af9033_read_regs(state, OFDM, 0x4191, &buf[4], sizeof(buf) / 2); -+ if (ret) -+ goto error; -+ -+ info("firmware version: LINK:%d.%d.%d.%d OFDM:%d.%d.%d.%d", -+ buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]); -+ -+ /* settings for mp2if */ -+ if (state->config.output_mode == AF9033_TS_MODE_USB) { -+ /* split 15 PSB to 1K + 1K and enable flow control */ -+ ret = af9033_write_reg_bits(state, OFDM, p_reg_mp2if2_half_psb, -+ reg_mp2if2_half_psb_pos, reg_mp2if2_half_psb_len, 0); -+ if (ret) -+ goto error; -+ ret = af9033_write_reg_bits(state, OFDM, p_reg_mp2if_stop_en, -+ reg_mp2if_stop_en_pos, reg_mp2if_stop_en_len, 1); -+ } else { -+ /* AF9033 set mpeg to full speed */ -+ ret = af9033_write_reg_bits(state, OFDM, p_reg_mpeg_full_speed, -+ reg_mpeg_full_speed_pos, reg_mpeg_full_speed_len, 0); -+ if (ret) -+ goto error; -+ ret = af9033_write_reg_bits(state, OFDM, p_reg_mp2if_stop_en, -+ reg_mp2if_stop_en_pos, reg_mp2if_stop_en_len, 0); -+ } -+ if (ret) -+ goto error; -+ -+ /* set to 0 as open drain for tuner i2c */ -+ ret = af9033_write_reg(state, LINK, p_reg_top_padodpu, 0); -+ if (ret) -+ goto error; -+ -+ /* set to 0 as push pull for tuner AGC */ -+ ret = af9033_write_reg(state, LINK, p_reg_top_agc_od, 0); -+ if (ret) -+ goto error; -+ -+ /* create dvb_frontend */ -+ memcpy(&state->frontend.ops, &af9033_ops, -+ sizeof(struct dvb_frontend_ops)); -+ state->frontend.demodulator_priv = state; -+ -+ return &state->frontend; -+error: -+ kfree(state); -+ return NULL; -+} -+EXPORT_SYMBOL(af9033_attach); -+ -+static struct dvb_frontend_ops af9033_ops = { -+#ifdef V4L2_ONLY_DVB_V5 -+ .delsys = { SYS_DVBT }, -+#endif -+ .info = { -+ .name = "Afatech AF9033 DVB-T", -+#ifndef V4L2_ONLY_DVB_V5 -+ .type = FE_OFDM, -+#endif -+ .frequency_min = 44250000, -+ .frequency_max = 867250000, -+ .frequency_stepsize = 62500, -+ .frequency_tolerance = 0, -+ .caps = -+ FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | -+ FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | -+ FE_CAN_QPSK | FE_CAN_QAM_16 | -+ FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | -+ FE_CAN_TRANSMISSION_MODE_AUTO | -+ FE_CAN_GUARD_INTERVAL_AUTO | -+ FE_CAN_HIERARCHY_AUTO | -+ FE_CAN_RECOVER | -+ FE_CAN_MUTE_TS -+ }, -+ -+ .release = af9033_release, -+ -+ .init = af9033_init, -+ .sleep = af9033_sleep, -+ -+ .set_frontend = af9033_set_frontend, -+ .get_tune_settings = af9033_get_tune_settings, -+ -+ .get_frontend = af9033_get_frontend, -+ -+ .read_status = af9033_read_status, -+ .read_ber = af9033_read_ber, -+ .read_signal_strength = af9033_read_signal_strength, -+ .read_snr = af9033_read_snr, -+ .read_ucblocks = af9033_read_ucblocks, -+ -+ .i2c_gate_ctrl = af9033_i2c_gate_ctrl, -+}; -+ -+MODULE_AUTHOR("Antti Palosaari "); -+MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/media/dvb/frontends/af9033.h b/drivers/media/dvb/frontends/af9033.h -new file mode 100644 -index 0000000..53d2e80 ---- /dev/null -+++ b/drivers/media/dvb/frontends/af9033.h -@@ -0,0 +1,100 @@ -+/* -+ * Afatech AF9033 demodulator driver -+ * -+ * Copyright (C) 2008 Afatech -+ * Copyright (C) 2009 Antti Palosaari -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ * -+ * -+ * Thanks to TerraTec for a support received. -+ */ -+ -+#ifndef AF9033_H -+#define AF9033_H -+ -+#include -+ -+enum af9033_ts_mode { -+ AF9033_TS_MODE_PARALLEL, -+ AF9033_TS_MODE_SERIAL, -+ AF9033_TS_MODE_USB, /* only for AF9035 */ -+}; -+ -+enum af9033_tuner { -+ AF9033_TUNER_TUA9001 = 0x27, /* Infineon TUA 9001 */ -+ AF9033_TUNER_FC0011 = 0x28, /* Fitipower FC0011 */ -+ AF9033_TUNER_MXL5007t = 0xa0, /* Maxlinear MXL5007t */ -+ AF9033_TUNER_TDA18218 = 0xa1, /* NXP TDA 18218HN */ -+}; -+ -+/* clock setting table: -+ ================================= -+ adc_clock crystal_clock Xtal -+ ================================= -+ 20480000 20480000 FPGA -+ 16384000 20480000 16.38MHz -+ 20480000 20480000 20.48MHz -+ 36000000 20250000 36.00MHz -+ 30000000 20156250 30.00MHz -+ 26000000 20583333 26.00MHz -+ 28000000 20416667 28.00MHz -+ 32000000 20500000 32.00MHz -+ 34000000 20187500 34.00MHz -+ 24000000 20500000 24.00MHz -+ 22000000 20625000 22.00MHz -+ 12000000 20250000 12.00MHz -+*/ -+ -+struct af9033_config { -+ /* demodulator's I2C address */ -+ u8 demod_address; -+ -+ u8 tuner_address; -+ -+ /* xtal clock Hz */ -+ u32 crystal_clock; -+ -+ /* ADC clock Hz */ -+ u32 adc_clock; -+ -+ /* tuner ID */ -+ u8 tuner; -+ -+ /* intermediate frequency Hz */ -+ u32 if_freq; -+ -+ /* TS data output mode */ -+ u8 output_mode:2; -+ -+ /* RF spectrum inversion */ -+ u8 rf_spec_inv:1; -+}; -+ -+ -+#if defined(CONFIG_DVB_AF9033) || \ -+ (defined(CONFIG_DVB_AF9033_MODULE) && defined(MODULE)) -+extern struct dvb_frontend *af9033_attach(const struct af9033_config *config, -+ struct i2c_adapter *i2c); -+#else -+static inline struct dvb_frontend *af9033_attach( -+const struct af9033_config *config, struct i2c_adapter *i2c) -+{ -+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); -+ return NULL; -+} -+#endif /* CONFIG_DVB_AF9033 */ -+ -+#endif /* AF9033_H */ -diff --git a/drivers/media/dvb/frontends/af9033_priv.h b/drivers/media/dvb/frontends/af9033_priv.h -new file mode 100644 -index 0000000..6474bfa ---- /dev/null -+++ b/drivers/media/dvb/frontends/af9033_priv.h -@@ -0,0 +1,383 @@ -+/* -+ * Afatech AF9033 demodulator driver -+ * -+ * Copyright (C) 2008 Afatech -+ * Copyright (C) 2009 Antti Palosaari -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ * -+ * -+ * Thanks to TerraTec for a support received. -+ */ -+ -+#ifndef AF9033_PRIV_H -+#define AF9033_PRIV_H -+ -+#define LOG_PREFIX "af9033" -+ -+#define dprintk(var, level, args...) \ -+ do { if ((var & level)) printk(args); } while (0) -+ -+#define debug_dump(b, l, func) {\ -+ int loop_; \ -+ for (loop_ = 0; loop_ < l; loop_++) \ -+ func("%02x ", b[loop_]); \ -+ func("\n");\ -+} -+ -+#define deb_info(args...) dprintk(af9033_debug, 0x01, args) -+ -+#undef err -+#define err(f, arg...) printk(KERN_ERR LOG_PREFIX": " f "\n" , ## arg) -+#undef info -+#define info(f, arg...) printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg) -+#undef warn -+#define warn(f, arg...) printk(KERN_WARNING LOG_PREFIX": " f "\n" , ## arg) -+ -+#define LINK 0x00 -+#define OFDM 0x80 -+ -+struct regdesc { -+ u16 addr; -+ u8 val; -+}; -+ -+struct snr_table { -+ u32 val; -+ u8 snr; -+}; -+ -+/* QPSK SNR lookup table */ -+static struct snr_table qpsk_snr_table[] = { -+ {0x000b4771, 0}, -+ {0x000c1aed, 1}, -+ {0x000d0d27, 2}, -+ {0x000e4d19, 3}, -+ {0x000e5da8, 4}, -+ {0x00107097, 5}, -+ {0x00116975, 6}, -+ {0x001252d9, 7}, -+ {0x00131fa4, 8}, -+ {0x0013d5e1, 9}, -+ {0x00148e53, 10}, -+ {0x0015358b, 11}, -+ {0x0015dd29, 12}, -+ {0x00168112, 13}, -+ {0x00170b61, 14}, -+ {0x0017a532, 15}, -+ {0x00180f94, 16}, -+ {0x00186ed2, 17}, -+ {0x0018b271, 18}, -+ {0x0018e118, 19}, -+ {0x0018ff4b, 20}, -+ {0x00190af1, 21}, -+ {0x00191451, 22}, -+ {0xffffffff, 23}, -+}; -+ -+/* QAM16 SNR lookup table */ -+static struct snr_table qam16_snr_table[] = { -+ {0x0004f0d5, 0}, -+ {0x0005387a, 1}, -+ {0x000573a4, 2}, -+ {0x0005a99e, 3}, -+ {0x0005cc80, 4}, -+ {0x0005eb62, 5}, -+ {0x0005fecf, 6}, -+ {0x00060b80, 7}, -+ {0x00062501, 8}, -+ {0x00064865, 9}, -+ {0x00069604, 10}, -+ {0x0006f356, 11}, -+ {0x0007706a, 12}, -+ {0x000804d3, 13}, -+ {0x00089d1a, 14}, -+ {0x00093e3d, 15}, -+ {0x0009e35d, 16}, -+ {0x000a7c3c, 17}, -+ {0x000afaf8, 18}, -+ {0x000b719d, 19}, -+ {0x000bda6a, 20}, -+ {0x000c0c75, 21}, -+ {0x000c3f7d, 22}, -+ {0x000c5e62, 23}, -+ {0x000c6c31, 24}, -+ {0x000c7925, 25}, -+ {0xffffffff, 26}, -+}; -+ -+/* QAM64 SNR lookup table */ -+static struct snr_table qam64_snr_table[] = { -+ {0x000256d0, 0}, -+ {0x00027a65, 1}, -+ {0x00029873, 2}, -+ {0x0002b7fe, 3}, -+ {0x0002cf1e, 4}, -+ {0x0002e234, 5}, -+ {0x0002f409, 6}, -+ {0x00030046, 7}, -+ {0x00030844, 8}, -+ {0x00030a02, 9}, -+ {0x00030cde, 10}, -+ {0x00031031, 11}, -+ {0x0003144c, 12}, -+ {0x000315dd, 13}, -+ {0x00031920, 14}, -+ {0x000322d0, 15}, -+ {0x000339fc, 16}, -+ {0x000364a1, 17}, -+ {0x00038bcc, 18}, -+ {0x0003c7d3, 19}, -+ {0x000408cc, 20}, -+ {0x00043bed, 21}, -+ {0x00048061, 22}, -+ {0x0004be95, 23}, -+ {0x0004fa7d, 24}, -+ {0x00052405, 25}, -+ {0x0005570d, 26}, -+ {0x00059feb, 27}, -+ {0x0005bf38, 28}, -+ {0xffffffff, 29}, -+}; -+ -+static struct regdesc ofsm_init[] = { -+ {0x0051, 0x01}, -+ {0x0070, 0x0A}, -+ {0x007E, 0x04}, -+ {0x0081, 0x0A}, -+ {0x008A, 0x01}, -+ {0x008E, 0x01}, -+ {0x0092, 0x06}, -+ {0x0099, 0x01}, -+ {0x009F, 0xE1}, -+ {0x00A0, 0xCF}, -+ {0x00A3, 0x01}, -+ {0x00A5, 0x01}, -+ {0x00A6, 0x01}, -+ {0x00A9, 0x00}, -+ {0x00AA, 0x01}, -+ {0x00AB, 0x01}, -+ {0x00B0, 0x01}, -+ {0x00C0, 0x05}, -+ {0x00C4, 0x19}, -+ {0xF000, 0x0F}, -+ {0xF016, 0x10}, -+ {0xF017, 0x04}, -+ {0xF018, 0x05}, -+ {0xF019, 0x04}, -+ {0xF01A, 0x05}, -+ {0xF021, 0x03}, -+ {0xF022, 0x0A}, -+ {0xF023, 0x0A}, -+ {0xF02B, 0x00}, -+ {0xF02C, 0x01}, -+ {0xF064, 0x03}, -+ {0xF065, 0xF9}, -+ {0xF066, 0x03}, -+ {0xF067, 0x01}, -+ {0xF06F, 0xE0}, -+ {0xF070, 0x03}, -+ {0xF072, 0x0F}, -+ {0xF073, 0x03}, -+ {0xF078, 0x00}, -+ {0xF087, 0x00}, -+ {0xF09B, 0x3F}, -+ {0xF09C, 0x00}, -+ {0xF09D, 0x20}, -+ {0xF09E, 0x00}, -+ {0xF09F, 0x0C}, -+ {0xF0A0, 0x00}, -+ {0xF130, 0x04}, -+ {0xF132, 0x04}, -+ {0xF144, 0x1A}, -+ {0xF146, 0x00}, -+ {0xF14A, 0x01}, -+ {0xF14C, 0x00}, -+ {0xF14D, 0x00}, -+ {0xF14F, 0x04}, -+ {0xF158, 0x7F}, -+ {0xF15A, 0x00}, -+ {0xF15B, 0x08}, -+ {0xF15D, 0x03}, -+ {0xF15E, 0x05}, -+ {0xF163, 0x05}, -+ {0xF166, 0x01}, -+ {0xF167, 0x40}, -+ {0xF168, 0x0F}, -+ {0xF17A, 0x00}, -+ {0xF17B, 0x00}, -+ {0xF183, 0x01}, -+ {0xF19D, 0x40}, -+ {0xF1BC, 0x36}, -+ {0xF1BD, 0x00}, -+ {0xF1CB, 0xA0}, -+ {0xF1CC, 0x01}, -+ {0xF204, 0x10}, -+ {0xF214, 0x00}, -+ {0xF40E, 0x0A}, -+ {0xF40F, 0x40}, -+ {0xF410, 0x08}, -+ {0xF55F, 0x0A}, -+ {0xF561, 0x15}, -+ {0xF562, 0x20}, -+ {0xF5DF, 0xFB}, -+ {0xF5E0, 0x00}, -+ {0xF5E3, 0x09}, -+ {0xF5E4, 0x01}, -+ {0xF5E5, 0x01}, -+ {0xF5F8, 0x01}, -+ {0xF5FD, 0x01}, -+ {0xF600, 0x05}, -+ {0xF601, 0x08}, -+ {0xF602, 0x0B}, -+ {0xF603, 0x0E}, -+ {0xF604, 0x11}, -+ {0xF605, 0x14}, -+ {0xF606, 0x17}, -+ {0xF607, 0x1F}, -+ {0xF60E, 0x00}, -+ {0xF60F, 0x04}, -+ {0xF610, 0x32}, -+ {0xF611, 0x10}, -+ {0xF707, 0xFC}, -+ {0xF708, 0x00}, -+ {0xF709, 0x37}, -+ {0xF70A, 0x00}, -+ {0xF78B, 0x01}, -+ {0xF80F, 0x40}, -+ {0xF810, 0x54}, -+ {0xF811, 0x5A}, -+ {0xF905, 0x01}, -+ {0xFB06, 0x03}, -+ {0xFD8B, 0x00} -+}; -+ -+/* Infineon TUA 9001 tuner init -+ AF9033_TUNER_TUA9001 = 0x27 */ -+static struct regdesc tuner_init_tua9001[] = { -+ {0x0046, 0x27}, -+ {0x0057, 0x00}, -+ {0x0058, 0x01}, -+ {0x005f, 0x00}, -+ {0x0060, 0x00}, -+ {0x006d, 0x00}, -+ {0x0071, 0x05}, -+ {0x0072, 0x02}, -+ {0x0074, 0x01}, -+ {0x0075, 0x03}, -+ {0x0076, 0x02}, -+ {0x0077, 0x00}, -+ {0x0078, 0x01}, -+ {0x0079, 0x00}, -+ {0x007a, 0x7E}, -+ {0x007b, 0x3E}, -+ {0x0093, 0x00}, -+ {0x0094, 0x01}, -+ {0x0095, 0x02}, -+ {0x0096, 0x01}, -+ {0x0098, 0x0A}, -+ {0x009b, 0x05}, -+ {0x009c, 0x80}, -+ {0x00b3, 0x00}, -+ {0x00c1, 0x01}, -+ {0x00c2, 0x00}, -+ {0xF007, 0x00}, -+ {0xF01F, 0x82}, -+ {0xF020, 0x00}, -+ {0xF029, 0x82}, -+ {0xF02A, 0x00}, -+ {0xF047, 0x00}, -+ {0xF054, 0x00}, -+ {0xF055, 0x00}, -+ {0xF077, 0x01}, -+ {0xF1E6, 0x00}, -+}; -+ -+/* NXP TDA18218 tuner init -+ AF9033_TUNER_TDA18218 = 161 */ -+static struct regdesc tuner_init_tda18218[] = { -+ {0x0046, 0x27}, -+ {0x0071, 0x05}, -+ {0x0072, 0x02}, -+ {0x0074, 0x01}, -+ {0x0075, 0x03}, -+ {0x0076, 0x02}, -+ {0x0077, 0x00}, -+ {0x0078, 0x01}, -+ {0x007a, 0x7e}, -+ {0x007b, 0x3e}, -+ {0x0098, 0x0a}, -+ {0x00b3, 0x00}, -+ {0xf007, 0x00}, -+ {0xf01f, 0x82}, -+ {0xf020, 0x00}, -+ {0xf047, 0x00}, -+ {0xf077, 0x01}, -+ {0xf1e6, 0x00}, -+ {0x0057, 0x00}, -+ {0x0058, 0x01}, -+ {0x005f, 0x00}, -+ {0x0060, 0x00}, -+ {0x006d, 0x00}, -+ {0x0079, 0x00}, -+ {0x0093, 0x00}, -+ {0x0094, 0x01}, -+ {0x0095, 0x02}, -+ {0x0096, 0x01}, -+ {0x009b, 0x05}, -+ {0x009c, 0x80}, -+ {0x00c1, 0x01}, -+ {0x00c2, 0x00}, -+ {0xf029, 0x82}, -+ {0xf02a, 0x00}, -+ {0xf054, 0x00}, -+ {0xf055, 0x00}, -+}; -+ -+static struct regdesc tuner_init_mxl5007t[] = { -+ {0x0046, 0x1b}, -+ {0x0057, 0x01}, -+ {0x0058, 0x01}, -+ {0x005f, 0x00}, -+ {0x0060, 0x00}, -+ {0x0068, 0x96}, -+ {0x0071, 0x05}, -+ {0x0072, 0x02}, -+ {0x0074, 0x01}, -+ {0x0079, 0x01}, -+ {0x0093, 0x00}, -+ {0x0094, 0x00}, -+ {0x0095, 0x00}, -+ {0x0096, 0x00}, -+ {0x00b3, 0x01}, -+ {0x00c1, 0x01}, -+ {0x00c2, 0x00}, -+ {0xF007, 0x00}, -+ {0xF00C, 0x19}, -+ {0xF00D, 0x1a}, -+ {0xF012, 0xda}, -+ {0xF013, 0x00}, -+ {0xF014, 0x00}, -+ {0xF015, 0x02}, -+ {0xF01F, 0x82}, -+ {0xF020, 0x00}, -+ {0xF029, 0x82}, -+ {0xF02A, 0x00}, -+ {0xF077, 0x02}, -+ {0xF1E6, 0x00}, -+}; -+ -+#endif /* AF9033_PRIV_H */ -+ -diff --git a/drivers/media/dvb/frontends/af9033_reg.h b/drivers/media/dvb/frontends/af9033_reg.h -new file mode 100644 -index 0000000..078276c ---- /dev/null -+++ b/drivers/media/dvb/frontends/af9033_reg.h -@@ -0,0 +1,11006 @@ -+/* -+ * Afatech AF9033 demodulator driver -+ * -+ * Copyright (C) 2008 Afatech -+ * Copyright (C) 2009 Antti Palosaari -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ * -+ * -+ * Thanks to TerraTec for a support received. -+ */ -+ -+#ifndef AF9033_REG_H -+#define AF9033_REG_H -+ -+/* these variables are initialized by API */ -+#define api_var_addr_base 0x418b -+#define api_log_addr_base 0x418d -+#define api_log_data_base 0x418f -+#define api_LowerLocalRetrain 0x43bb -+ -+#define api_trigger_ofsm 0x0000 -+#define api_cfoe_NS_2048_coeff1_25_24 0x0001 -+#define api_cfoe_NS_2048_coeff1_23_16 0x0002 -+#define api_cfoe_NS_2048_coeff1_15_8 0x0003 -+#define api_cfoe_NS_2048_coeff1_7_0 0x0004 -+#define api_cfoe_NS_2k_coeff2_24 0x0005 -+#define api_cfoe_NS_2k_coeff2_23_16 0x0006 -+#define api_cfoe_NS_2k_coeff2_15_8 0x0007 -+#define api_cfoe_NS_2k_coeff2_7_0 0x0008 -+#define api_cfoe_NS_8191_coeff1_25_24 0x0009 -+#define api_cfoe_NS_8191_coeff1_23_16 0x000a -+#define api_cfoe_NS_8191_coeff1_15_8 0x000b -+#define api_cfoe_NS_8191_coeff1_7_0 0x000c -+#define api_cfoe_NS_8192_coeff1_25_24 0x000d -+#define api_cfoe_NS_8192_coeff1_23_16 0x000e -+#define api_cfoe_NS_8192_coeff1_15_8 0x000f -+#define api_cfoe_NS_8192_coeff1_7_0 0x0010 -+#define api_cfoe_NS_8193_coeff1_25_24 0x0011 -+#define api_cfoe_NS_8193_coeff1_23_16 0x0012 -+#define api_cfoe_NS_8193_coeff1_15_8 0x0013 -+#define api_cfoe_NS_8193_coeff1_7_0 0x0014 -+#define api_cfoe_NS_8k_coeff2_24 0x0015 -+#define api_cfoe_NS_8k_coeff2_23_16 0x0016 -+#define api_cfoe_NS_8k_coeff2_15_8 0x0017 -+#define api_cfoe_NS_8k_coeff2_7_0 0x0018 -+#define api_cfoe_NS_4096_coeff1_25_24 0x0019 -+#define api_cfoe_NS_4096_coeff1_23_16 0x001a -+#define api_cfoe_NS_4096_coeff1_15_8 0x001b -+#define api_cfoe_NS_4096_coeff1_7_0 0x001c -+#define api_cfoe_NS_4k_coeff2_24 0x001d -+#define api_cfoe_NS_4k_coeff2_23_16 0x001e -+#define api_cfoe_NS_4k_coeff2_15_8 0x001f -+#define api_cfoe_NS_4k_coeff2_7_0 0x0020 -+ -+#define api_bfsfcw_fftindex_ratio_7_0 0x0021 -+#define api_bfsfcw_fftindex_ratio_15_8 0x0022 -+#define api_fftindex_bfsfcw_ratio_7_0 0x0023 -+#define api_fftindex_bfsfcw_ratio_15_8 0x0024 -+ -+#define api_crystal_clk_7_0 0x0025 -+#define api_crystal_clk_15_8 0x0026 -+#define api_crystal_clk_23_16 0x0027 -+#define api_crystal_clk_31_24 0x0028 -+ -+#define api_bfs_fcw_7_0 0x0029 -+#define api_bfs_fcw_15_8 0x002a -+#define api_bfs_fcw_22_16 0x002b -+ -+#define api_qnt_vbc_err_7_0 0x002c -+#define api_qnt_vbc_err_15_8 0x002d -+#define api_qnt_vbc_err_23_16 0x002e -+#define api_r_qnt_vbc_sframe_num 0x002f -+#define api_tpsd_const 0x0030 -+#define api_tpsd_txmod 0x0031 -+ -+#define api_rsd_abort_packet_cnt_7_0 0x0032 -+#define api_rsd_abort_packet_cnt_15_8 0x0033 -+#define api_rsd_bit_err_cnt_7_0 0x0034 -+#define api_rsd_bit_err_cnt_15_8 0x0035 -+#define api_rsd_bit_err_cnt_23_16 0x0036 -+#define api_r_rsd_packet_unit_7_0 0x0037 -+#define api_r_rsd_packet_unit_15_8 0x0038 -+ -+#define api_qnt_vbc_sframe_num 0x0039 -+#define api_rsd_packet_unit_7_0 0x003a -+#define api_rsd_packet_unit_15_8 0x003b -+ -+#define api_tpsd_lock 0x003c -+#define api_mpeg_lock 0x003d -+#define api_RsdSequence 0x003e -+#define api_VtbSequence 0x003f -+ -+#define api_Training_Mode 0x0040 -+#define api_RESET_STATE 0x0041 -+#define api_EXT_LNA_OFF 0x0042 -+#define api_aci_0 0x0043 -+#define api_aci_1 0x0044 -+ -+#define api_adcx2 0x0045 -+#define api_tuner_ID 0x0046 -+#define api_empty_channel_status 0x0047 -+#define api_signal_strength 0x0048 -+#define api_signal_quality 0x0049 -+#define api_est_rf_level_dbm 0x004a -+#define api_FreBand 0x004b -+#define api_suspend_flag 0x004c -+#define api_SupportRelayCommandWrite 0x004d -+#define api_RelayCommandWrite 0x004e -+ -+#define api_OfdmGuiRCN_H 0x004f -+#define api_OfdmGuiRCN_L 0x0050 -+#define api_antenna_unplugged 0x0051 -+#define api_strong_signal_detected 0x0052 -+#define api_channelFlatnessInd 0x0053 -+#define api_Flatness_Ind_nonCmb 0x0054 -+#define api_AutoDetectedSpectrumInv 0x0055 -+#define api_IsSpectrumInv 0x0056 -+#define api_strong_detect_bypass 0x0057 -+#define api_ss_dtop_bypass 0x0058 -+#define api_retrain_dtop_bypass 0x0059 -+#define api_EnableTimeSlice 0x005a -+#define api_SynchronizationType 0x005b -+#define api_ApplyFastSynchronizationToEchoChannel 0x005c -+#define api_ApplyPwmToRfIf 0x005d -+#define api_ChannelNo 0x005e -+ -+#define api_csi_bypass 0x005f -+#define api_mobile_bypass 0x0060 -+#define api_EnableSpeedLog 0x0061 -+ -+#define api_r_rsd_abort_total_packet_7_0 0x0062 -+#define api_r_rsd_abort_total_packet_15_8 0x0063 -+#define api_r_rsd_abort_total_packet_23_16 0x0064 -+#define api_MaxRsdSequence 0x0065 -+#define api_RsdFrameNo 0x0066 -+#define api_MPESuperFrameNo 0x0067 -+ -+#define api_AgcDesiredLevel 0x0068 -+#define api_MinRfGain 0x0069 -+#define api_MaxIfGain 0x006a -+#define api_RssiOffset 0x006b -+#define api_RssiResidual 0x006c -+ -+#define api_strong_weak_signal_default 0x006d -+#define api_PionDiodeDefaultResetInVHF 0x006e -+#define api_afe_mem4_rssi_comp 0x006f -+ -+#define api_aagc_speed_detect_count 0x0070 -+#define api_aagc_mobile_thr 0x0071 -+#define api_aagc_nonmobile_thr 0x0072 -+#define api_agc_counter 0x0073 -+#define api_DisableAagcTop 0x0074 -+#define api_AgcReset 0x0075 -+#define api_AgcUp 0x0076 -+#define api_AgcDown 0x0077 -+#define api_AgcHold 0x0078 -+#define api_PwmCtrlHw 0x0079 -+#define api_MaxAgcGain 0x007a -+#define api_IniAgcGain 0x007b -+#define api_mccid_bypass 0x007c -+#define api_CdpfEnDefaultEchoRange 0x007d -+#define api_CdpfIniTestNoSteady 0x007e -+#define api_timing_err_level 0x007f -+#define api_timing_retrain_cnt 0x0080 -+#define api_ChannelDiffThrSteady 0x0081 -+ -+#define api_adjacent_on 0x0082 -+#define api_near_adjacent_on 0x0083 -+#define api_adjacent_off 0x0084 -+#define api_near_adjacent_off 0x0085 -+#define api_max_rf_agc_7_0 0x0086 -+#define api_max_rf_agc_9_8 0x0087 -+#define api_rf_top_numerator_s_7_0 0x0088 -+#define api_rf_top_numerator_s_9_8 0x0089 -+ -+#define api_gui_tdi_lms_en 0x008a -+#define api_fccid_strobe_scale 0x008b -+#define api_fccid_strobe_numerator 0x008c -+#define api_fccid_strobe_base 0x008d -+#define api_use_fccid 0x008e -+#define api_fft_ave_symbol_num 0x008f -+#define api_large_tone_num_th_7_0 0x0090 -+#define api_large_tone_num_th_15_8 0x0091 -+#define api_use_3m_lpf_th 0x0092 -+#define api_ce_var_min_8k 0x0093 -+#define api_ce_var_min_4k 0x0094 -+#define api_ce_var_min_2k 0x0095 -+#define api_ce_var_min_8k_non_flat 0x0096 -+#define api_flatness_thr 0x0097 -+#define api_non_mobile_signal_level_offset 0x0098 -+#define api_gui_ar_csi_en 0x0099 -+#define api_h2_echo_detected 0x009a -+#define api_gain_offset_O 0x009b -+#define api_gain_slope_O 0x009c -+#define api_pin_diode_gain_loss 0x009d -+#define api_signal_strength_if_low 0x009e -+ -+#define api_flatness_thr_high 0x009f -+#define api_flatness_thr_low 0x00a0 -+ -+#define api_sbq1 0x00a1 -+#define api_sbq2 0x00a2 -+ -+#define api_dyna_dca_offset_en 0x00a3 -+#define api_dca_sbq_bad_th 0x00a4 -+#define api_detect_timing_err_en 0x00a5 -+#define api_flatness_from_h2_echo 0x00a6 -+ -+#define api_timging_error_detection 0x00a7 -+#define api_ce_forced_by_rotate 0x00a8 -+#define api_fccid_fft_mask_en 0x00a9 -+#define api_second_fctrl_unforce_en 0x00aa -+#define api_force_fdi0_at_high_mobile_en 0x00ab -+#define api_high_mobile_detected 0x00ac -+#define api_flatness_detection_en 0x00ad -+#define api_ChooseFsteCostFunctionFromCdpf 0x00ae -+#define api_signal_level 0x00af -+#define api_TryConf2En 0x00b0 -+#define api_Lower_tpsd_lock 0x00b1 -+#define api_Upper_tpsd_lock 0x00b2 -+ -+#define api_AgcCtrlType 0x00b3 -+#define api_opt_LNA_Rssi_scale 0x00b4 -+#define api_StopByTcl 0x00b5 -+#define api_RssiCalibration 0x00b6 -+#define api_AciDesiredSignalLevel_h 0x00b7 -+#define api_AciDesiredSignalLevel_l 0x00b8 -+#define api_ECO_ASIC 0x00b9 -+#define api_NXP_USE_I2C 0x00ba -+#define api_rf_freqency_23_16 0x00bb -+#define api_rf_freqency_15_8 0x00bc -+#define api_rf_freqency_7_0 0x00bd -+#define api_iqik_en 0x00be -+#define api_dcc_en 0x00bf -+#define api_CdpfIniTestNoMobile 0x00c0 -+#define api_ACIdetection 0x00c1 -+#define api_PinDiode 0x00c2 -+#define api_LNA_Gain 0x00c3 -+#define api_ChannelDiffThrMobile 0x00c4 -+#define api_var_end 0x00c5 -+ -+/* registers */ -+#define p_reg_p_aagc_log_2_acc 0xF000 -+#define reg_p_aagc_log_2_acc_pos 0 -+#define reg_p_aagc_log_2_acc_len 4 -+#define reg_p_aagc_log_2_acc_lsb 0 -+#define p_reg_p_aagc_signal_level_rdy 0xF001 -+#define reg_p_aagc_signal_level_rdy_pos 0 -+#define reg_p_aagc_signal_level_rdy_len 1 -+#define reg_p_aagc_signal_level_rdy_lsb 0 -+#define r_reg_r_aagc_signal_level_7_0 0xF002 -+#define reg_r_aagc_signal_level_7_0_pos 0 -+#define reg_r_aagc_signal_level_7_0_len 8 -+#define reg_r_aagc_signal_level_7_0_lsb 0 -+#define r_reg_r_aagc_signal_level_9_8 0xF003 -+#define reg_r_aagc_signal_level_9_8_pos 0 -+#define reg_r_aagc_signal_level_9_8_len 2 -+#define reg_r_aagc_signal_level_9_8_lsb 8 -+#define p_reg_p_aagc_rf_if_swap 0xF004 -+#define reg_p_aagc_rf_if_swap_pos 0 -+#define reg_p_aagc_rf_if_swap_len 1 -+#define reg_p_aagc_rf_if_swap_lsb 0 -+#define p_reg_p_pwm_rf_if_from_hw 0xF006 -+#define reg_p_pwm_rf_if_from_hw_pos 0 -+#define reg_p_pwm_rf_if_from_hw_len 1 -+#define reg_p_pwm_rf_if_from_hw_lsb 0 -+#define p_reg_aagc_out_if_inv 0xF007 -+#define reg_aagc_out_if_inv_pos 0 -+#define reg_aagc_out_if_inv_len 1 -+#define reg_aagc_out_if_inv_lsb 0 -+#define p_reg_aagc_int_en 0xF008 -+#define reg_aagc_int_en_pos 0 -+#define reg_aagc_int_en_len 1 -+#define reg_aagc_int_en_lsb 0 -+#define p_reg_aagc_lock_change_flag 0xF009 -+#define reg_aagc_lock_change_flag_pos 0 -+#define reg_aagc_lock_change_flag_len 1 -+#define reg_aagc_lock_change_flag_lsb 0 -+#define p_reg_aagc_rf_loop_bw_scale_acquire 0xF00A -+#define reg_aagc_rf_loop_bw_scale_acquire_pos 0 -+#define reg_aagc_rf_loop_bw_scale_acquire_len 5 -+#define reg_aagc_rf_loop_bw_scale_acquire_lsb 0 -+#define p_reg_aagc_rf_loop_bw_scale_track 0xF00B -+#define reg_aagc_rf_loop_bw_scale_track_pos 0 -+#define reg_aagc_rf_loop_bw_scale_track_len 5 -+#define reg_aagc_rf_loop_bw_scale_track_lsb 0 -+#define p_reg_aagc_if_loop_bw_scale_acquire 0xF00C -+#define reg_aagc_if_loop_bw_scale_acquire_pos 0 -+#define reg_aagc_if_loop_bw_scale_acquire_len 5 -+#define reg_aagc_if_loop_bw_scale_acquire_lsb 0 -+#define p_reg_aagc_if_loop_bw_scale_track 0xF00D -+#define reg_aagc_if_loop_bw_scale_track_pos 0 -+#define reg_aagc_if_loop_bw_scale_track_len 5 -+#define reg_aagc_if_loop_bw_scale_track_lsb 0 -+#define p_reg_aagc_max_rf_agc_7_0 0xF00E -+#define reg_aagc_max_rf_agc_7_0_pos 0 -+#define reg_aagc_max_rf_agc_7_0_len 8 -+#define reg_aagc_max_rf_agc_7_0_lsb 0 -+#define p_reg_aagc_max_rf_agc_9_8 0xF00F -+#define reg_aagc_max_rf_agc_9_8_pos 0 -+#define reg_aagc_max_rf_agc_9_8_len 2 -+#define reg_aagc_max_rf_agc_9_8_lsb 8 -+#define p_reg_aagc_min_rf_agc_7_0 0xF010 -+#define reg_aagc_min_rf_agc_7_0_pos 0 -+#define reg_aagc_min_rf_agc_7_0_len 8 -+#define reg_aagc_min_rf_agc_7_0_lsb 0 -+#define p_reg_aagc_min_rf_agc_9_8 0xF011 -+#define reg_aagc_min_rf_agc_9_8_pos 0 -+#define reg_aagc_min_rf_agc_9_8_len 2 -+#define reg_aagc_min_rf_agc_9_8_lsb 8 -+#define p_reg_aagc_max_if_agc_7_0 0xF012 -+#define reg_aagc_max_if_agc_7_0_pos 0 -+#define reg_aagc_max_if_agc_7_0_len 8 -+#define reg_aagc_max_if_agc_7_0_lsb 0 -+#define p_reg_aagc_max_if_agc_9_8 0xF013 -+#define reg_aagc_max_if_agc_9_8_pos 0 -+#define reg_aagc_max_if_agc_9_8_len 2 -+#define reg_aagc_max_if_agc_9_8_lsb 8 -+#define p_reg_aagc_min_if_agc_7_0 0xF014 -+#define reg_aagc_min_if_agc_7_0_pos 0 -+#define reg_aagc_min_if_agc_7_0_len 8 -+#define reg_aagc_min_if_agc_7_0_lsb 0 -+#define p_reg_aagc_min_if_agc_9_8 0xF015 -+#define reg_aagc_min_if_agc_9_8_pos 0 -+#define reg_aagc_min_if_agc_9_8_len 2 -+#define reg_aagc_min_if_agc_9_8_lsb 8 -+#define p_reg_aagc_lock_sample_scale 0xF016 -+#define reg_aagc_lock_sample_scale_pos 0 -+#define reg_aagc_lock_sample_scale_len 5 -+#define reg_aagc_lock_sample_scale_lsb 0 -+#define p_reg_aagc_rf_agc_lock_scale_acquire 0xF017 -+#define reg_aagc_rf_agc_lock_scale_acquire_pos 0 -+#define reg_aagc_rf_agc_lock_scale_acquire_len 3 -+#define reg_aagc_rf_agc_lock_scale_acquire_lsb 0 -+#define p_reg_aagc_rf_agc_lock_scale_track 0xF018 -+#define reg_aagc_rf_agc_lock_scale_track_pos 0 -+#define reg_aagc_rf_agc_lock_scale_track_len 3 -+#define reg_aagc_rf_agc_lock_scale_track_lsb 0 -+#define p_reg_aagc_if_agc_lock_scale_acquire 0xF019 -+#define reg_aagc_if_agc_lock_scale_acquire_pos 0 -+#define reg_aagc_if_agc_lock_scale_acquire_len 3 -+#define reg_aagc_if_agc_lock_scale_acquire_lsb 0 -+#define p_reg_aagc_if_agc_lock_scale_track 0xF01A -+#define reg_aagc_if_agc_lock_scale_track_pos 0 -+#define reg_aagc_if_agc_lock_scale_track_len 3 -+#define reg_aagc_if_agc_lock_scale_track_lsb 0 -+#define p_reg_aagc_rf_top_numerator_s_7_0 0xF01B -+#define reg_aagc_rf_top_numerator_s_7_0_pos 0 -+#define reg_aagc_rf_top_numerator_s_7_0_len 8 -+#define reg_aagc_rf_top_numerator_s_7_0_lsb 0 -+#define p_reg_aagc_rf_top_numerator_s_9_8 0xF01C -+#define reg_aagc_rf_top_numerator_s_9_8_pos 0 -+#define reg_aagc_rf_top_numerator_s_9_8_len 2 -+#define reg_aagc_rf_top_numerator_s_9_8_lsb 8 -+#define p_reg_aagc_if_top_numerator_s_7_0 0xF01D -+#define reg_aagc_if_top_numerator_s_7_0_pos 0 -+#define reg_aagc_if_top_numerator_s_7_0_len 8 -+#define reg_aagc_if_top_numerator_s_7_0_lsb 0 -+#define p_reg_aagc_if_top_numerator_s_9_8 0xF01E -+#define reg_aagc_if_top_numerator_s_9_8_pos 0 -+#define reg_aagc_if_top_numerator_s_9_8_len 2 -+#define reg_aagc_if_top_numerator_s_9_8_lsb 8 -+#define p_reg_aagc_adc_out_desired_s_7_0 0xF01F -+#define reg_aagc_adc_out_desired_s_7_0_pos 0 -+#define reg_aagc_adc_out_desired_s_7_0_len 8 -+#define reg_aagc_adc_out_desired_s_7_0_lsb 0 -+#define p_reg_aagc_adc_out_desired_s_8 0xF020 -+#define reg_aagc_adc_out_desired_s_8_pos 0 -+#define reg_aagc_adc_out_desired_s_8_len 1 -+#define reg_aagc_adc_out_desired_s_8_lsb 8 -+#define p_reg_aagc_lock_count_th 0xF021 -+#define reg_aagc_lock_count_th_pos 0 -+#define reg_aagc_lock_count_th_len 4 -+#define reg_aagc_lock_count_th_lsb 0 -+#define p_reg_aagc_rf_agc_unlock_numerator 0xF022 -+#define reg_aagc_rf_agc_unlock_numerator_pos 0 -+#define reg_aagc_rf_agc_unlock_numerator_len 6 -+#define reg_aagc_rf_agc_unlock_numerator_lsb 0 -+#define p_reg_aagc_if_agc_unlock_numerator 0xF023 -+#define reg_aagc_if_agc_unlock_numerator_pos 0 -+#define reg_aagc_if_agc_unlock_numerator_len 6 -+#define reg_aagc_if_agc_unlock_numerator_lsb 0 -+#define p_reg_aagc_rf_top_numerator_m_7_0 0xF025 -+#define reg_aagc_rf_top_numerator_m_7_0_pos 0 -+#define reg_aagc_rf_top_numerator_m_7_0_len 8 -+#define reg_aagc_rf_top_numerator_m_7_0_lsb 0 -+#define p_reg_aagc_rf_top_numerator_m_9_8 0xF026 -+#define reg_aagc_rf_top_numerator_m_9_8_pos 0 -+#define reg_aagc_rf_top_numerator_m_9_8_len 2 -+#define reg_aagc_rf_top_numerator_m_9_8_lsb 8 -+#define p_reg_aagc_if_top_numerator_m_7_0 0xF027 -+#define reg_aagc_if_top_numerator_m_7_0_pos 0 -+#define reg_aagc_if_top_numerator_m_7_0_len 8 -+#define reg_aagc_if_top_numerator_m_7_0_lsb 0 -+#define p_reg_aagc_if_top_numerator_m_9_8 0xF028 -+#define reg_aagc_if_top_numerator_m_9_8_pos 0 -+#define reg_aagc_if_top_numerator_m_9_8_len 2 -+#define reg_aagc_if_top_numerator_m_9_8_lsb 8 -+#define p_reg_aagc_adc_out_desired_m_7_0 0xF029 -+#define reg_aagc_adc_out_desired_m_7_0_pos 0 -+#define reg_aagc_adc_out_desired_m_7_0_len 8 -+#define reg_aagc_adc_out_desired_m_7_0_lsb 0 -+#define p_reg_aagc_adc_out_desired_m_8 0xF02A -+#define reg_aagc_adc_out_desired_m_8_pos 0 -+#define reg_aagc_adc_out_desired_m_8_len 1 -+#define reg_aagc_adc_out_desired_m_8_lsb 8 -+#define p_reg_aagc_mobile_sel 0xF02B -+#define reg_aagc_mobile_sel_pos 0 -+#define reg_aagc_mobile_sel_len 1 -+#define reg_aagc_mobile_sel_lsb 0 -+#define p_reg_aagc_top_reload 0xF02C -+#define reg_aagc_top_reload_pos 0 -+#define reg_aagc_top_reload_len 1 -+#define reg_aagc_top_reload_lsb 0 -+#define p_reg_aagc_rf_delta_voltage_en 0xF02D -+#define reg_aagc_rf_delta_voltage_en_pos 0 -+#define reg_aagc_rf_delta_voltage_en_len 1 -+#define reg_aagc_rf_delta_voltage_en_lsb 0 -+#define p_reg_aagc_rf_voltage_inc 0xF02E -+#define reg_aagc_rf_voltage_inc_pos 0 -+#define reg_aagc_rf_voltage_inc_len 1 -+#define reg_aagc_rf_voltage_inc_lsb 0 -+#define p_reg_aagc_if_delta_voltage_en 0xF02F -+#define reg_aagc_if_delta_voltage_en_pos 0 -+#define reg_aagc_if_delta_voltage_en_len 1 -+#define reg_aagc_if_delta_voltage_en_lsb 0 -+#define p_reg_aagc_if_voltage_inc 0xF030 -+#define reg_aagc_if_voltage_inc_pos 0 -+#define reg_aagc_if_voltage_inc_len 1 -+#define reg_aagc_if_voltage_inc_lsb 0 -+#define p_reg_aagc_rf_delta_voltage_7_0 0xF032 -+#define reg_aagc_rf_delta_voltage_7_0_pos 0 -+#define reg_aagc_rf_delta_voltage_7_0_len 8 -+#define reg_aagc_rf_delta_voltage_7_0_lsb 0 -+#define p_reg_aagc_rf_delta_voltage_15_8 0xF033 -+#define reg_aagc_rf_delta_voltage_15_8_pos 0 -+#define reg_aagc_rf_delta_voltage_15_8_len 8 -+#define reg_aagc_rf_delta_voltage_15_8_lsb 8 -+#define p_reg_aagc_rf_delta_voltage_23_16 0xF034 -+#define reg_aagc_rf_delta_voltage_23_16_pos 0 -+#define reg_aagc_rf_delta_voltage_23_16_len 8 -+#define reg_aagc_rf_delta_voltage_23_16_lsb 16 -+#define p_reg_aagc_rf_delta_voltage_29_24 0xF035 -+#define reg_aagc_rf_delta_voltage_29_24_pos 0 -+#define reg_aagc_rf_delta_voltage_29_24_len 6 -+#define reg_aagc_rf_delta_voltage_29_24_lsb 24 -+#define p_reg_aagc_if_delta_voltage_7_0 0xF036 -+#define reg_aagc_if_delta_voltage_7_0_pos 0 -+#define reg_aagc_if_delta_voltage_7_0_len 8 -+#define reg_aagc_if_delta_voltage_7_0_lsb 0 -+#define p_reg_aagc_if_delta_voltage_15_8 0xF037 -+#define reg_aagc_if_delta_voltage_15_8_pos 0 -+#define reg_aagc_if_delta_voltage_15_8_len 8 -+#define reg_aagc_if_delta_voltage_15_8_lsb 8 -+#define p_reg_aagc_if_delta_voltage_23_16 0xF038 -+#define reg_aagc_if_delta_voltage_23_16_pos 0 -+#define reg_aagc_if_delta_voltage_23_16_len 8 -+#define reg_aagc_if_delta_voltage_23_16_lsb 16 -+#define p_reg_aagc_if_delta_voltage_29_24 0xF039 -+#define reg_aagc_if_delta_voltage_29_24_pos 0 -+#define reg_aagc_if_delta_voltage_29_24_len 6 -+#define reg_aagc_if_delta_voltage_29_24_lsb 24 -+#define p_reg_aagc_delta_voltage_hold_time 0xF03A -+#define reg_aagc_delta_voltage_hold_time_pos 0 -+#define reg_aagc_delta_voltage_hold_time_len 8 -+#define reg_aagc_delta_voltage_hold_time_lsb 0 -+#define p_reg_aagc_top_th_dis 0xF041 -+#define reg_aagc_top_th_dis_pos 0 -+#define reg_aagc_top_th_dis_len 1 -+#define reg_aagc_top_th_dis_lsb 0 -+#define p_reg_p_aagc_rf_floor_dca 0xF042 -+#define reg_p_aagc_rf_floor_dca_pos 0 -+#define reg_p_aagc_rf_floor_dca_len 8 -+#define reg_p_aagc_rf_floor_dca_lsb 0 -+#define p_reg_p_aagc_if_floor_dca 0xF043 -+#define reg_p_aagc_if_floor_dca_pos 0 -+#define reg_p_aagc_if_floor_dca_len 8 -+#define reg_p_aagc_if_floor_dca_lsb 0 -+#define p_reg_p_aagc_rf_gain_scale_dca 0xF044 -+#define reg_p_aagc_rf_gain_scale_dca_pos 0 -+#define reg_p_aagc_rf_gain_scale_dca_len 3 -+#define reg_p_aagc_rf_gain_scale_dca_lsb 0 -+#define p_reg_p_aagc_if_gain_scale_dca 0xF045 -+#define reg_p_aagc_if_gain_scale_dca_pos 0 -+#define reg_p_aagc_if_gain_scale_dca_len 3 -+#define reg_p_aagc_if_gain_scale_dca_lsb 0 -+#define r_reg_r_aagc_ufl_gain 0xF046 -+#define reg_r_aagc_ufl_gain_pos 0 -+#define reg_r_aagc_ufl_gain_len 8 -+#define reg_r_aagc_ufl_gain_lsb 0 -+#define p_reg_aagc_out_rf_inv 0xF047 -+#define reg_aagc_out_rf_inv_pos 0 -+#define reg_aagc_out_rf_inv_len 1 -+#define reg_aagc_out_rf_inv_lsb 0 -+#define p_reg_p_aagc_save_agc_control 0xF048 -+#define reg_p_aagc_save_agc_control_pos 0 -+#define reg_p_aagc_save_agc_control_len 1 -+#define reg_p_aagc_save_agc_control_lsb 0 -+#define p_reg_aagc_fw_sel 0xF049 -+#define reg_aagc_fw_sel_pos 0 -+#define reg_aagc_fw_sel_len 1 -+#define reg_aagc_fw_sel_lsb 0 -+#define r_reg_r_aagc_rf_control_7_0 0xF04A -+#define reg_r_aagc_rf_control_7_0_pos 0 -+#define reg_r_aagc_rf_control_7_0_len 8 -+#define reg_r_aagc_rf_control_7_0_lsb 0 -+#define r_reg_r_aagc_rf_control_9_8 0xF04B -+#define reg_r_aagc_rf_control_9_8_pos 0 -+#define reg_r_aagc_rf_control_9_8_len 2 -+#define reg_r_aagc_rf_control_9_8_lsb 8 -+#define r_reg_r_aagc_if_control_7_0 0xF04C -+#define reg_r_aagc_if_control_7_0_pos 0 -+#define reg_r_aagc_if_control_7_0_len 8 -+#define reg_r_aagc_if_control_7_0_lsb 0 -+#define r_reg_r_aagc_if_control_9_8 0xF04D -+#define reg_r_aagc_if_control_9_8_pos 0 -+#define reg_r_aagc_if_control_9_8_len 2 -+#define reg_r_aagc_if_control_9_8_lsb 8 -+#define p_reg_aagc_adc_out_desired_from_fw_7_0 0xF04E -+#define reg_aagc_adc_out_desired_from_fw_7_0_pos 0 -+#define reg_aagc_adc_out_desired_from_fw_7_0_len 8 -+#define reg_aagc_adc_out_desired_from_fw_7_0_lsb 0 -+#define p_reg_aagc_adc_out_desired_from_fw_8 0xF04F -+#define reg_aagc_adc_out_desired_from_fw_8_pos 0 -+#define reg_aagc_adc_out_desired_from_fw_8_len 1 -+#define reg_aagc_adc_out_desired_from_fw_8_lsb 8 -+#define p_reg_aagc_init_rf_agc_7_0 0xF050 -+#define reg_aagc_init_rf_agc_7_0_pos 0 -+#define reg_aagc_init_rf_agc_7_0_len 8 -+#define reg_aagc_init_rf_agc_7_0_lsb 0 -+#define p_reg_aagc_init_rf_agc_9_8 0xF051 -+#define reg_aagc_init_rf_agc_9_8_pos 0 -+#define reg_aagc_init_rf_agc_9_8_len 2 -+#define reg_aagc_init_rf_agc_9_8_lsb 8 -+#define p_reg_aagc_init_if_agc_7_0 0xF052 -+#define reg_aagc_init_if_agc_7_0_pos 0 -+#define reg_aagc_init_if_agc_7_0_len 8 -+#define reg_aagc_init_if_agc_7_0_lsb 0 -+#define p_reg_aagc_init_if_agc_9_8 0xF053 -+#define reg_aagc_init_if_agc_9_8_pos 0 -+#define reg_aagc_init_if_agc_9_8_len 2 -+#define reg_aagc_init_if_agc_9_8_lsb 8 -+#define p_reg_p_pwm_if_high_unit_num 0xF054 -+#define reg_p_pwm_if_high_unit_num_pos 0 -+#define reg_p_pwm_if_high_unit_num_len 8 -+#define reg_p_pwm_if_high_unit_num_lsb 0 -+#define p_reg_p_pwm_rf_high_unit_num 0xF055 -+#define reg_p_pwm_rf_high_unit_num_pos 0 -+#define reg_p_pwm_rf_high_unit_num_len 8 -+#define reg_p_pwm_rf_high_unit_num_lsb 0 -+#define p_reg_p_pwm_rf_gpio 0xF058 -+#define reg_p_pwm_rf_gpio_pos 0 -+#define reg_p_pwm_rf_gpio_len 1 -+#define reg_p_pwm_rf_gpio_lsb 0 -+#define p_reg_p_pwm_if_gpio 0xF058 -+#define reg_p_pwm_if_gpio_pos 1 -+#define reg_p_pwm_if_gpio_len 1 -+#define reg_p_pwm_if_gpio_lsb 0 -+#define p_reg_aagc_in_sat_cnt_7_0 0xF05A -+#define reg_aagc_in_sat_cnt_7_0_pos 0 -+#define reg_aagc_in_sat_cnt_7_0_len 8 -+#define reg_aagc_in_sat_cnt_7_0_lsb 0 -+#define p_reg_aagc_in_sat_cnt_15_8 0xF05B -+#define reg_aagc_in_sat_cnt_15_8_pos 0 -+#define reg_aagc_in_sat_cnt_15_8_len 8 -+#define reg_aagc_in_sat_cnt_15_8_lsb 8 -+#define p_reg_aagc_in_sat_cnt_23_16 0xF05C -+#define reg_aagc_in_sat_cnt_23_16_pos 0 -+#define reg_aagc_in_sat_cnt_23_16_len 8 -+#define reg_aagc_in_sat_cnt_23_16_lsb 16 -+#define p_reg_aagc_in_sat_cnt_31_24 0xF05D -+#define reg_aagc_in_sat_cnt_31_24_pos 0 -+#define reg_aagc_in_sat_cnt_31_24_len 8 -+#define reg_aagc_in_sat_cnt_31_24_lsb 24 -+#define p_reg_p_pwm_cycle_unit 0xF05E -+#define reg_p_pwm_cycle_unit_pos 0 -+#define reg_p_pwm_cycle_unit_len 4 -+#define reg_p_pwm_cycle_unit_lsb 0 -+#define p_reg_p_pwm_en 0xF05F -+#define reg_p_pwm_en_pos 0 -+#define reg_p_pwm_en_len 1 -+#define reg_p_pwm_en_lsb 0 -+#define r_reg_aagc_rf_gain 0xF060 -+#define reg_aagc_rf_gain_pos 0 -+#define reg_aagc_rf_gain_len 8 -+#define reg_aagc_rf_gain_lsb 0 -+#define r_reg_aagc_if_gain 0xF061 -+#define reg_aagc_if_gain_pos 0 -+#define reg_aagc_if_gain_len 8 -+#define reg_aagc_if_gain_lsb 0 -+#define r_reg_aagc_current_desired_level_7_0 0xF062 -+#define reg_aagc_current_desired_level_7_0_pos 0 -+#define reg_aagc_current_desired_level_7_0_len 8 -+#define reg_aagc_current_desired_level_7_0_lsb 0 -+#define r_reg_aagc_current_desired_level_8 0xF063 -+#define reg_aagc_current_desired_level_8_pos 0 -+#define reg_aagc_current_desired_level_8_len 1 -+#define reg_aagc_current_desired_level_8_lsb 8 -+#define p_reg_tinr_fifo_size 0xF064 -+#define reg_tinr_fifo_size_pos 0 -+#define reg_tinr_fifo_size_len 5 -+#define reg_tinr_fifo_size_lsb 0 -+#define p_reg_tinr_saturation_th_7_0 0xF065 -+#define reg_tinr_saturation_th_7_0_pos 0 -+#define reg_tinr_saturation_th_7_0_len 8 -+#define reg_tinr_saturation_th_7_0_lsb 0 -+#define p_reg_tinr_saturation_th_9_8 0xF066 -+#define reg_tinr_saturation_th_9_8_pos 0 -+#define reg_tinr_saturation_th_9_8_len 2 -+#define reg_tinr_saturation_th_9_8_lsb 8 -+#define p_reg_tinr_saturation_cnt_th 0xF067 -+#define reg_tinr_saturation_cnt_th_pos 0 -+#define reg_tinr_saturation_cnt_th_len 4 -+#define reg_tinr_saturation_cnt_th_lsb 0 -+#define r_reg_tinr_counter_7_0 0xF068 -+#define reg_tinr_counter_7_0_pos 0 -+#define reg_tinr_counter_7_0_len 8 -+#define reg_tinr_counter_7_0_lsb 0 -+#define r_reg_tinr_counter_15_8 0xF069 -+#define reg_tinr_counter_15_8_pos 0 -+#define reg_tinr_counter_15_8_len 8 -+#define reg_tinr_counter_15_8_lsb 8 -+#define p_reg_tinr_counter_rst 0xF06C -+#define reg_tinr_counter_rst_pos 0 -+#define reg_tinr_counter_rst_len 1 -+#define reg_tinr_counter_rst_lsb 0 -+#define p_reg_tinr_ins_th_7_0 0xF06F -+#define reg_tinr_ins_th_7_0_pos 0 -+#define reg_tinr_ins_th_7_0_len 8 -+#define reg_tinr_ins_th_7_0_lsb 0 -+#define p_reg_tinr_ins_th_9_8 0xF070 -+#define reg_tinr_ins_th_9_8_pos 0 -+#define reg_tinr_ins_th_9_8_len 2 -+#define reg_tinr_ins_th_9_8_lsb 8 -+#define p_reg_tinr_ins_en 0xF071 -+#define reg_tinr_ins_en_pos 0 -+#define reg_tinr_ins_en_len 1 -+#define reg_tinr_ins_en_lsb 0 -+#define p_reg_tinr_ins_size 0xF072 -+#define reg_tinr_ins_size_pos 0 -+#define reg_tinr_ins_size_len 4 -+#define reg_tinr_ins_size_lsb 0 -+#define p_reg_tinr_ins_hnum 0xF073 -+#define reg_tinr_ins_hnum_pos 0 -+#define reg_tinr_ins_hnum_len 4 -+#define reg_tinr_ins_hnum_lsb 0 -+#define r_reg_tinr_ins_hcnt_7_0 0xF074 -+#define reg_tinr_ins_hcnt_7_0_pos 0 -+#define reg_tinr_ins_hcnt_7_0_len 8 -+#define reg_tinr_ins_hcnt_7_0_lsb 0 -+#define r_reg_tinr_ins_hcnt_15_8 0xF075 -+#define reg_tinr_ins_hcnt_15_8_pos 0 -+#define reg_tinr_ins_hcnt_15_8_len 8 -+#define reg_tinr_ins_hcnt_15_8_lsb 8 -+#define p_reg_tinr_in_conj 0xF076 -+#define reg_tinr_in_conj_pos 0 -+#define reg_tinr_in_conj_len 1 -+#define reg_tinr_in_conj_lsb 0 -+#define p_reg_tinr_in_zero_if 0xF077 -+#define reg_tinr_in_zero_if_pos 0 -+#define reg_tinr_in_zero_if_len 2 -+#define reg_tinr_in_zero_if_lsb 0 -+#define p_reg_tinr_in_shift 0xF078 -+#define reg_tinr_in_shift_pos 0 -+#define reg_tinr_in_shift_len 1 -+#define reg_tinr_in_shift_lsb 0 -+#define p_reg_tinr_in_conj_sat_counter_rst 0xF079 -+#define reg_tinr_in_conj_sat_counter_rst_pos 0 -+#define reg_tinr_in_conj_sat_counter_rst_len 1 -+#define reg_tinr_in_conj_sat_counter_rst_lsb 0 -+#define r_reg_tinr_in_conj_sat_counter_7_0 0xF07A -+#define reg_tinr_in_conj_sat_counter_7_0_pos 0 -+#define reg_tinr_in_conj_sat_counter_7_0_len 8 -+#define reg_tinr_in_conj_sat_counter_7_0_lsb 0 -+#define r_reg_tinr_in_conj_sat_counter_14_8 0xF07B -+#define reg_tinr_in_conj_sat_counter_14_8_pos 0 -+#define reg_tinr_in_conj_sat_counter_14_8_len 7 -+#define reg_tinr_in_conj_sat_counter_14_8_lsb 8 -+#define p_reg_p_antif_en 0xF07C -+#define reg_p_antif_en_pos 0 -+#define reg_p_antif_en_len 1 -+#define reg_p_antif_en_lsb 0 -+#define p_reg_p_antif_rst 0xF07D -+#define reg_p_antif_rst_pos 0 -+#define reg_p_antif_rst_len 1 -+#define reg_p_antif_rst_lsb 0 -+#define p_reg_p_antif_byp 0xF07E -+#define reg_p_antif_byp_pos 0 -+#define reg_p_antif_byp_len 1 -+#define reg_p_antif_byp_lsb 0 -+#define p_reg_p_antif_mode 0xF07F -+#define reg_p_antif_mode_pos 0 -+#define reg_p_antif_mode_len 1 -+#define reg_p_antif_mode_lsb 0 -+#define p_reg_p_ds_byp 0xF080 -+#define reg_p_ds_byp_pos 0 -+#define reg_p_ds_byp_len 1 -+#define reg_p_ds_byp_lsb 0 -+#define p_reg_p_antif_dagc5_mode 0xF081 -+#define reg_p_antif_dagc5_mode_pos 0 -+#define reg_p_antif_dagc5_mode_len 2 -+#define reg_p_antif_dagc5_mode_lsb 0 -+#define p_reg_p_antif_dagc5_desired_level_7_0 0xF082 -+#define reg_p_antif_dagc5_desired_level_7_0_pos 0 -+#define reg_p_antif_dagc5_desired_level_7_0_len 8 -+#define reg_p_antif_dagc5_desired_level_7_0_lsb 0 -+#define p_reg_p_antif_dagc5_desired_level_8 0xF083 -+#define reg_p_antif_dagc5_desired_level_8_pos 0 -+#define reg_p_antif_dagc5_desired_level_8_len 1 -+#define reg_p_antif_dagc5_desired_level_8_lsb 8 -+#define p_reg_p_antif_dagc5_apply_delay 0xF084 -+#define reg_p_antif_dagc5_apply_delay_pos 0 -+#define reg_p_antif_dagc5_apply_delay_len 7 -+#define reg_p_antif_dagc5_apply_delay_lsb 0 -+#define p_reg_p_antif_dagc5_fixed_gain_7_0 0xF085 -+#define reg_p_antif_dagc5_fixed_gain_7_0_pos 0 -+#define reg_p_antif_dagc5_fixed_gain_7_0_len 8 -+#define reg_p_antif_dagc5_fixed_gain_7_0_lsb 0 -+#define p_reg_p_antif_dagc5_fixed_gain_11_8 0xF086 -+#define reg_p_antif_dagc5_fixed_gain_11_8_pos 0 -+#define reg_p_antif_dagc5_fixed_gain_11_8_len 4 -+#define reg_p_antif_dagc5_fixed_gain_11_8_lsb 8 -+#define p_reg_p_antif_dagc5_use_despow 0xF087 -+#define reg_p_antif_dagc5_use_despow_pos 0 -+#define reg_p_antif_dagc5_use_despow_len 1 -+#define reg_p_antif_dagc5_use_despow_lsb 0 -+#define p_reg_p_antif_dagc5_log_2_accumulate_num 0xF088 -+#define reg_p_antif_dagc5_log_2_accumulate_num_pos 0 -+#define reg_p_antif_dagc5_log_2_accumulate_num_len 5 -+#define reg_p_antif_dagc5_log_2_accumulate_num_lsb 0 -+#define p_reg_p_antif_dagc5_in_sat_cnt_7_0 0xF089 -+#define reg_p_antif_dagc5_in_sat_cnt_7_0_pos 0 -+#define reg_p_antif_dagc5_in_sat_cnt_7_0_len 8 -+#define reg_p_antif_dagc5_in_sat_cnt_7_0_lsb 0 -+#define p_reg_p_antif_dagc5_in_sat_cnt_15_8 0xF08A -+#define reg_p_antif_dagc5_in_sat_cnt_15_8_pos 0 -+#define reg_p_antif_dagc5_in_sat_cnt_15_8_len 8 -+#define reg_p_antif_dagc5_in_sat_cnt_15_8_lsb 8 -+#define p_reg_p_antif_dagc5_in_sat_cnt_23_16 0xF08B -+#define reg_p_antif_dagc5_in_sat_cnt_23_16_pos 0 -+#define reg_p_antif_dagc5_in_sat_cnt_23_16_len 8 -+#define reg_p_antif_dagc5_in_sat_cnt_23_16_lsb 16 -+#define p_reg_p_antif_dagc5_in_sat_cnt_31_24 0xF08C -+#define reg_p_antif_dagc5_in_sat_cnt_31_24_pos 0 -+#define reg_p_antif_dagc5_in_sat_cnt_31_24_len 8 -+#define reg_p_antif_dagc5_in_sat_cnt_31_24_lsb 24 -+#define p_reg_p_antif_dagc5_out_sat_cnt_7_0 0xF08D -+#define reg_p_antif_dagc5_out_sat_cnt_7_0_pos 0 -+#define reg_p_antif_dagc5_out_sat_cnt_7_0_len 8 -+#define reg_p_antif_dagc5_out_sat_cnt_7_0_lsb 0 -+#define p_reg_p_antif_dagc5_out_sat_cnt_15_8 0xF08E -+#define reg_p_antif_dagc5_out_sat_cnt_15_8_pos 0 -+#define reg_p_antif_dagc5_out_sat_cnt_15_8_len 8 -+#define reg_p_antif_dagc5_out_sat_cnt_15_8_lsb 8 -+#define p_reg_p_antif_dagc5_out_sat_cnt_23_16 0xF08F -+#define reg_p_antif_dagc5_out_sat_cnt_23_16_pos 0 -+#define reg_p_antif_dagc5_out_sat_cnt_23_16_len 8 -+#define reg_p_antif_dagc5_out_sat_cnt_23_16_lsb 16 -+#define p_reg_p_antif_dagc5_out_sat_cnt_31_24 0xF090 -+#define reg_p_antif_dagc5_out_sat_cnt_31_24_pos 0 -+#define reg_p_antif_dagc5_out_sat_cnt_31_24_len 8 -+#define reg_p_antif_dagc5_out_sat_cnt_31_24_lsb 24 -+#define p_reg_p_antif_dagc5_rst 0xF091 -+#define reg_p_antif_dagc5_rst_pos 0 -+#define reg_p_antif_dagc5_rst_len 1 -+#define reg_p_antif_dagc5_rst_lsb 0 -+#define p_reg_p_antif_dagc5_en 0xF092 -+#define reg_p_antif_dagc5_en_pos 0 -+#define reg_p_antif_dagc5_en_len 1 -+#define reg_p_antif_dagc5_en_lsb 0 -+#define p_reg_p_antif_sc_mode 0xF093 -+#define reg_p_antif_sc_mode_pos 0 -+#define reg_p_antif_sc_mode_len 4 -+#define reg_p_antif_sc_mode_lsb 0 -+#define p_reg_p_antif_dagc5_done 0xF094 -+#define reg_p_antif_dagc5_done_pos 0 -+#define reg_p_antif_dagc5_done_len 1 -+#define reg_p_antif_dagc5_done_lsb 0 -+#define r_reg_r_antif_sc_7_0 0xF095 -+#define reg_r_antif_sc_7_0_pos 0 -+#define reg_r_antif_sc_7_0_len 8 -+#define reg_r_antif_sc_7_0_lsb 0 -+#define r_reg_r_antif_sc_15_8 0xF096 -+#define reg_r_antif_sc_15_8_pos 0 -+#define reg_r_antif_sc_15_8_len 8 -+#define reg_r_antif_sc_15_8_lsb 8 -+#define r_reg_r_antif_dagc5_multiplier_7_0 0xF097 -+#define reg_r_antif_dagc5_multiplier_7_0_pos 0 -+#define reg_r_antif_dagc5_multiplier_7_0_len 8 -+#define reg_r_antif_dagc5_multiplier_7_0_lsb 0 -+#define r_reg_r_antif_dagc5_multiplier_15_8 0xF098 -+#define reg_r_antif_dagc5_multiplier_15_8_pos 0 -+#define reg_r_antif_dagc5_multiplier_15_8_len 8 -+#define reg_r_antif_dagc5_multiplier_15_8_lsb 8 -+#define r_reg_r_antif_dagc5_right_shift_bits 0xF099 -+#define reg_r_antif_dagc5_right_shift_bits_pos 0 -+#define reg_r_antif_dagc5_right_shift_bits_len 4 -+#define reg_r_antif_dagc5_right_shift_bits_lsb 0 -+#define p_reg_p_antif_dagc5_bypass_scale_ctl 0xF09A -+#define reg_p_antif_dagc5_bypass_scale_ctl_pos 0 -+#define reg_p_antif_dagc5_bypass_scale_ctl_len 3 -+#define reg_p_antif_dagc5_bypass_scale_ctl_lsb 0 -+#define p_reg_mccid_ccirunno_7_0 0xF09B -+#define reg_mccid_ccirunno_7_0_pos 0 -+#define reg_mccid_ccirunno_7_0_len 8 -+#define reg_mccid_ccirunno_7_0_lsb 0 -+#define p_reg_mccid_ccirunno_8 0xF09C -+#define reg_mccid_ccirunno_8_pos 0 -+#define reg_mccid_ccirunno_8_len 1 -+#define reg_mccid_ccirunno_8_lsb 8 -+#define p_reg_mccid_acirunno_7_0 0xF09D -+#define reg_mccid_acirunno_7_0_pos 0 -+#define reg_mccid_acirunno_7_0_len 8 -+#define reg_mccid_acirunno_7_0_lsb 0 -+#define p_reg_mccid_acirunno_8 0xF09E -+#define reg_mccid_acirunno_8_pos 0 -+#define reg_mccid_acirunno_8_len 1 -+#define reg_mccid_acirunno_8_lsb 8 -+#define p_reg_mccid_maxtonenearrange_7_0 0xF09F -+#define reg_mccid_maxtonenearrange_7_0_pos 0 -+#define reg_mccid_maxtonenearrange_7_0_len 8 -+#define reg_mccid_maxtonenearrange_7_0_lsb 0 -+#define p_reg_mccid_maxtonenearrange_8 0xF0A0 -+#define reg_mccid_maxtonenearrange_8_pos 0 -+#define reg_mccid_maxtonenearrange_8_len 1 -+#define reg_mccid_maxtonenearrange_8_lsb 8 -+#define r_reg_mccid_maxacipower_7_0 0xF0A1 -+#define reg_mccid_maxacipower_7_0_pos 0 -+#define reg_mccid_maxacipower_7_0_len 8 -+#define reg_mccid_maxacipower_7_0_lsb 0 -+#define r_reg_mccid_maxacipower_15_8 0xF0A2 -+#define reg_mccid_maxacipower_15_8_pos 0 -+#define reg_mccid_maxacipower_15_8_len 8 -+#define reg_mccid_maxacipower_15_8_lsb 8 -+#define r_reg_mccid_maxacipower_19_16 0xF0A3 -+#define reg_mccid_maxacipower_19_16_pos 0 -+#define reg_mccid_maxacipower_19_16_len 4 -+#define reg_mccid_maxacipower_19_16_lsb 16 -+#define p_reg_p_dcoe_en 0xF0D5 -+#define reg_p_dcoe_en_pos 0 -+#define reg_p_dcoe_en_len 1 -+#define reg_p_dcoe_en_lsb 0 -+#define p_reg_p_dcoe_rst 0xF0D6 -+#define reg_p_dcoe_rst_pos 0 -+#define reg_p_dcoe_rst_len 1 -+#define reg_p_dcoe_rst_lsb 0 -+#define p_reg_p_dcoe_clear 0xF0D7 -+#define reg_p_dcoe_clear_pos 0 -+#define reg_p_dcoe_clear_len 1 -+#define reg_p_dcoe_clear_lsb 0 -+#define p_reg_p_dcoe_applyloc_7_0 0xF0D8 -+#define reg_p_dcoe_applyloc_7_0_pos 0 -+#define reg_p_dcoe_applyloc_7_0_len 8 -+#define reg_p_dcoe_applyloc_7_0_lsb 0 -+#define p_reg_p_dcoe_applyloc_12_8 0xF0D9 -+#define reg_p_dcoe_applyloc_12_8_pos 0 -+#define reg_p_dcoe_applyloc_12_8_len 5 -+#define reg_p_dcoe_applyloc_12_8_lsb 8 -+#define p_reg_p_dcoe_accnums 0xF0DA -+#define reg_p_dcoe_accnums_pos 0 -+#define reg_p_dcoe_accnums_len 3 -+#define reg_p_dcoe_accnums_lsb 0 -+#define p_reg_p_dcoe_accweightsum_sh 0xF0DB -+#define reg_p_dcoe_accweightsum_sh_pos 0 -+#define reg_p_dcoe_accweightsum_sh_len 3 -+#define reg_p_dcoe_accweightsum_sh_lsb 0 -+#define p_reg_p_dcoe_accweightcurr 0xF0DC -+#define reg_p_dcoe_accweightcurr_pos 0 -+#define reg_p_dcoe_accweightcurr_len 8 -+#define reg_p_dcoe_accweightcurr_lsb 0 -+#define p_reg_dcoe_apply_rd 0xF0DF -+#define reg_dcoe_apply_rd_pos 0 -+#define reg_dcoe_apply_rd_len 1 -+#define reg_dcoe_apply_rd_lsb 0 -+#define r_reg_dcoe_apply_i 0xF0E0 -+#define reg_dcoe_apply_i_pos 0 -+#define reg_dcoe_apply_i_len 8 -+#define reg_dcoe_apply_i_lsb 0 -+#define r_reg_dcoe_apply_q 0xF0E1 -+#define reg_dcoe_apply_q_pos 0 -+#define reg_dcoe_apply_q_len 8 -+#define reg_dcoe_apply_q_lsb 0 -+#define p_reg_p_dcrm_en 0xF0E2 -+#define reg_p_dcrm_en_pos 0 -+#define reg_p_dcrm_en_len 1 -+#define reg_p_dcrm_en_lsb 0 -+#define p_reg_p_dcrm_fir 0xF0E3 -+#define reg_p_dcrm_fir_pos 0 -+#define reg_p_dcrm_fir_len 1 -+#define reg_p_dcrm_fir_lsb 0 -+#define p_reg_p_dcrm_log2_firlen 0xF0E4 -+#define reg_p_dcrm_log2_firlen_pos 0 -+#define reg_p_dcrm_log2_firlen_len 3 -+#define reg_p_dcrm_log2_firlen_lsb 0 -+#define r_reg_dcoe_apply_fir_i 0xF0E5 -+#define reg_dcoe_apply_fir_i_pos 0 -+#define reg_dcoe_apply_fir_i_len 8 -+#define reg_dcoe_apply_fir_i_lsb 0 -+#define r_reg_dcoe_apply_fir_q 0xF0E6 -+#define reg_dcoe_apply_fir_q_pos 0 -+#define reg_dcoe_apply_fir_q_len 8 -+#define reg_dcoe_apply_fir_q_lsb 0 -+#define p_reg_p_dcrm_force_en 0xF0E7 -+#define reg_p_dcrm_force_en_pos 0 -+#define reg_p_dcrm_force_en_len 1 -+#define reg_p_dcrm_force_en_lsb 0 -+#define p_reg_p_dcrm_force_value_i 0xF0E8 -+#define reg_p_dcrm_force_value_i_pos 0 -+#define reg_p_dcrm_force_value_i_len 8 -+#define reg_p_dcrm_force_value_i_lsb 0 -+#define p_reg_p_dcrm_force_value_q 0xF0E9 -+#define reg_p_dcrm_force_value_q_pos 0 -+#define reg_p_dcrm_force_value_q_len 8 -+#define reg_p_dcrm_force_value_q_lsb 0 -+#define p_reg_p_iqip_en 0xF0EA -+#define reg_p_iqip_en_pos 0 -+#define reg_p_iqip_en_len 1 -+#define reg_p_iqip_en_lsb 0 -+#define p_reg_p_iqip_rst 0xF0EB -+#define reg_p_iqip_rst_pos 0 -+#define reg_p_iqip_rst_len 1 -+#define reg_p_iqip_rst_lsb 0 -+#define p_reg_iqip_mu_ld 0xF0EC -+#define reg_iqip_mu_ld_pos 0 -+#define reg_iqip_mu_ld_len 1 -+#define reg_iqip_mu_ld_lsb 0 -+#define p_reg_p_iqip_mu_7_0 0xF0ED -+#define reg_p_iqip_mu_7_0_pos 0 -+#define reg_p_iqip_mu_7_0_len 8 -+#define reg_p_iqip_mu_7_0_lsb 0 -+#define p_reg_p_iqip_mu_11_8 0xF0EE -+#define reg_p_iqip_mu_11_8_pos 0 -+#define reg_p_iqip_mu_11_8_len 4 -+#define reg_p_iqip_mu_11_8_lsb 8 -+#define p_reg_iqip_gs_ld 0xF0EF -+#define reg_iqip_gs_ld_pos 0 -+#define reg_iqip_gs_ld_len 1 -+#define reg_iqip_gs_ld_lsb 0 -+#define p_reg_p_iqip_gsnums 0xF0F0 -+#define reg_p_iqip_gsnums_pos 0 -+#define reg_p_iqip_gsnums_len 4 -+#define reg_p_iqip_gsnums_lsb 0 -+#define p_reg_p_iqip_gsites_7_0 0xF0F1 -+#define reg_p_iqip_gsites_7_0_pos 0 -+#define reg_p_iqip_gsites_7_0_len 8 -+#define reg_p_iqip_gsites_7_0_lsb 0 -+#define p_reg_p_iqip_gsites_15_8 0xF0F2 -+#define reg_p_iqip_gsites_15_8_pos 0 -+#define reg_p_iqip_gsites_15_8_len 8 -+#define reg_p_iqip_gsites_15_8_lsb 8 -+#define p_reg_iqip_w_ld 0xF0F3 -+#define reg_iqip_w_ld_pos 0 -+#define reg_iqip_w_ld_len 1 -+#define reg_iqip_w_ld_lsb 0 -+#define p_reg_p_iqip_w_re_7_0 0xF0F4 -+#define reg_p_iqip_w_re_7_0_pos 0 -+#define reg_p_iqip_w_re_7_0_len 8 -+#define reg_p_iqip_w_re_7_0_lsb 0 -+#define p_reg_p_iqip_w_re_15_8 0xF0F5 -+#define reg_p_iqip_w_re_15_8_pos 0 -+#define reg_p_iqip_w_re_15_8_len 8 -+#define reg_p_iqip_w_re_15_8_lsb 8 -+#define p_reg_p_iqip_w_re_16 0xF0F6 -+#define reg_p_iqip_w_re_16_pos 0 -+#define reg_p_iqip_w_re_16_len 1 -+#define reg_p_iqip_w_re_16_lsb 16 -+#define p_reg_p_iqip_w_im_7_0 0xF0F7 -+#define reg_p_iqip_w_im_7_0_pos 0 -+#define reg_p_iqip_w_im_7_0_len 8 -+#define reg_p_iqip_w_im_7_0_lsb 0 -+#define p_reg_p_iqip_w_im_15_8 0xF0F8 -+#define reg_p_iqip_w_im_15_8_pos 0 -+#define reg_p_iqip_w_im_15_8_len 8 -+#define reg_p_iqip_w_im_15_8_lsb 8 -+#define p_reg_p_iqip_w_im_16 0xF0F9 -+#define reg_p_iqip_w_im_16_pos 0 -+#define reg_p_iqip_w_im_16_len 1 -+#define reg_p_iqip_w_im_16_lsb 16 -+#define p_reg_iqip_accnums_rd 0xF0FA -+#define reg_iqip_accnums_rd_pos 0 -+#define reg_iqip_accnums_rd_len 1 -+#define reg_iqip_accnums_rd_lsb 0 -+#define p_reg_p_iqip_accnums 0xF0FB -+#define reg_p_iqip_accnums_pos 0 -+#define reg_p_iqip_accnums_len 2 -+#define reg_p_iqip_accnums_lsb 0 -+#define p_reg_iqip_accnums_rdy 0xF0FC -+#define reg_iqip_accnums_rdy_pos 0 -+#define reg_iqip_accnums_rdy_len 1 -+#define reg_iqip_accnums_rdy_lsb 0 -+#define r_reg_r_iqip_wacc_re_7_0 0xF0FD -+#define reg_r_iqip_wacc_re_7_0_pos 0 -+#define reg_r_iqip_wacc_re_7_0_len 8 -+#define reg_r_iqip_wacc_re_7_0_lsb 0 -+#define r_reg_r_iqip_wacc_re_15_8 0xF0FE -+#define reg_r_iqip_wacc_re_15_8_pos 0 -+#define reg_r_iqip_wacc_re_15_8_len 8 -+#define reg_r_iqip_wacc_re_15_8_lsb 8 -+#define r_reg_r_iqip_wacc_re_16 0xF0FF -+#define reg_r_iqip_wacc_re_16_pos 0 -+#define reg_r_iqip_wacc_re_16_len 1 -+#define reg_r_iqip_wacc_re_16_lsb 16 -+#define r_reg_r_iqip_wacc_im_7_0 0xF100 -+#define reg_r_iqip_wacc_im_7_0_pos 0 -+#define reg_r_iqip_wacc_im_7_0_len 8 -+#define reg_r_iqip_wacc_im_7_0_lsb 0 -+#define r_reg_r_iqip_wacc_im_15_8 0xF101 -+#define reg_r_iqip_wacc_im_15_8_pos 0 -+#define reg_r_iqip_wacc_im_15_8_len 8 -+#define reg_r_iqip_wacc_im_15_8_lsb 8 -+#define r_reg_r_iqip_wacc_im_16 0xF102 -+#define reg_r_iqip_wacc_im_16_pos 0 -+#define reg_r_iqip_wacc_im_16_len 1 -+#define reg_r_iqip_wacc_im_16_lsb 16 -+#define r_reg_r_iqip_out2cacc_re_7_0 0xF103 -+#define reg_r_iqip_out2cacc_re_7_0_pos 0 -+#define reg_r_iqip_out2cacc_re_7_0_len 8 -+#define reg_r_iqip_out2cacc_re_7_0_lsb 0 -+#define r_reg_r_iqip_out2cacc_re_15_8 0xF104 -+#define reg_r_iqip_out2cacc_re_15_8_pos 0 -+#define reg_r_iqip_out2cacc_re_15_8_len 8 -+#define reg_r_iqip_out2cacc_re_15_8_lsb 8 -+#define r_reg_r_iqip_out2cacc_re_21_16 0xF105 -+#define reg_r_iqip_out2cacc_re_21_16_pos 0 -+#define reg_r_iqip_out2cacc_re_21_16_len 6 -+#define reg_r_iqip_out2cacc_re_21_16_lsb 16 -+#define r_reg_r_iqip_out2cacc_im_7_0 0xF106 -+#define reg_r_iqip_out2cacc_im_7_0_pos 0 -+#define reg_r_iqip_out2cacc_im_7_0_len 8 -+#define reg_r_iqip_out2cacc_im_7_0_lsb 0 -+#define r_reg_r_iqip_out2cacc_im_15_8 0xF107 -+#define reg_r_iqip_out2cacc_im_15_8_pos 0 -+#define reg_r_iqip_out2cacc_im_15_8_len 8 -+#define reg_r_iqip_out2cacc_im_15_8_lsb 8 -+#define r_reg_r_iqip_out2cacc_im_21_16 0xF108 -+#define reg_r_iqip_out2cacc_im_21_16_pos 0 -+#define reg_r_iqip_out2cacc_im_21_16_len 6 -+#define reg_r_iqip_out2cacc_im_21_16_lsb 16 -+#define p_reg_mccid_ccif0_scstrobe 0xF109 -+#define reg_mccid_ccif0_scstrobe_pos 0 -+#define reg_mccid_ccif0_scstrobe_len 7 -+#define reg_mccid_ccif0_scstrobe_lsb 0 -+#define p_reg_mccid_cciftrigger 0xF10A -+#define reg_mccid_cciftrigger_pos 0 -+#define reg_mccid_cciftrigger_len 1 -+#define reg_mccid_cciftrigger_lsb 0 -+#define p_reg_mccid_ccif1_scstrobe 0xF10B -+#define reg_mccid_ccif1_scstrobe_pos 0 -+#define reg_mccid_ccif1_scstrobe_len 7 -+#define reg_mccid_ccif1_scstrobe_lsb 0 -+#define p_reg_mccid_ccif0_fcwccif_7_0 0xF10E -+#define reg_mccid_ccif0_fcwccif_7_0_pos 0 -+#define reg_mccid_ccif0_fcwccif_7_0_len 8 -+#define reg_mccid_ccif0_fcwccif_7_0_lsb 0 -+#define p_reg_mccid_ccif0_fcwccif_13_8 0xF10F -+#define reg_mccid_ccif0_fcwccif_13_8_pos 0 -+#define reg_mccid_ccif0_fcwccif_13_8_len 6 -+#define reg_mccid_ccif0_fcwccif_13_8_lsb 8 -+#define p_reg_mccid_ccif0_state 0xF110 -+#define reg_mccid_ccif0_state_pos 0 -+#define reg_mccid_ccif0_state_len 1 -+#define reg_mccid_ccif0_state_lsb 0 -+#define p_reg_mccid_ccif0_acistate 0xF111 -+#define reg_mccid_ccif0_acistate_pos 0 -+#define reg_mccid_ccif0_acistate_len 1 -+#define reg_mccid_ccif0_acistate_lsb 0 -+#define p_reg_mccid_ccif1_fcwccif_7_0 0xF112 -+#define reg_mccid_ccif1_fcwccif_7_0_pos 0 -+#define reg_mccid_ccif1_fcwccif_7_0_len 8 -+#define reg_mccid_ccif1_fcwccif_7_0_lsb 0 -+#define p_reg_mccid_ccif1_fcwccif_13_8 0xF113 -+#define reg_mccid_ccif1_fcwccif_13_8_pos 0 -+#define reg_mccid_ccif1_fcwccif_13_8_len 6 -+#define reg_mccid_ccif1_fcwccif_13_8_lsb 8 -+#define p_reg_mccid_ccif1_state 0xF114 -+#define reg_mccid_ccif1_state_pos 0 -+#define reg_mccid_ccif1_state_len 1 -+#define reg_mccid_ccif1_state_lsb 0 -+#define p_reg_mccid_ccif1_acistate 0xF115 -+#define reg_mccid_ccif1_acistate_pos 0 -+#define reg_mccid_ccif1_acistate_len 1 -+#define reg_mccid_ccif1_acistate_lsb 0 -+#define r_reg_r_acif_saturate 0xF117 -+#define reg_r_acif_saturate_pos 0 -+#define reg_r_acif_saturate_len 8 -+#define reg_r_acif_saturate_lsb 0 -+#define p_reg_tmr_timer0_threshold_7_0 0xF118 -+#define reg_tmr_timer0_threshold_7_0_pos 0 -+#define reg_tmr_timer0_threshold_7_0_len 8 -+#define reg_tmr_timer0_threshold_7_0_lsb 0 -+#define p_reg_tmr_timer0_threshold_15_8 0xF119 -+#define reg_tmr_timer0_threshold_15_8_pos 0 -+#define reg_tmr_timer0_threshold_15_8_len 8 -+#define reg_tmr_timer0_threshold_15_8_lsb 8 -+#define p_reg_tmr_timer0_enable 0xF11A -+#define reg_tmr_timer0_enable_pos 0 -+#define reg_tmr_timer0_enable_len 1 -+#define reg_tmr_timer0_enable_lsb 0 -+#define p_reg_tmr_timer0_clk_sel 0xF11B -+#define reg_tmr_timer0_clk_sel_pos 0 -+#define reg_tmr_timer0_clk_sel_len 1 -+#define reg_tmr_timer0_clk_sel_lsb 0 -+#define p_reg_tmr_timer0_int 0xF11C -+#define reg_tmr_timer0_int_pos 0 -+#define reg_tmr_timer0_int_len 1 -+#define reg_tmr_timer0_int_lsb 0 -+#define p_reg_tmr_timer0_rst 0xF11D -+#define reg_tmr_timer0_rst_pos 0 -+#define reg_tmr_timer0_rst_len 1 -+#define reg_tmr_timer0_rst_lsb 0 -+#define r_reg_tmr_timer0_count_7_0 0xF11E -+#define reg_tmr_timer0_count_7_0_pos 0 -+#define reg_tmr_timer0_count_7_0_len 8 -+#define reg_tmr_timer0_count_7_0_lsb 0 -+#define r_reg_tmr_timer0_count_15_8 0xF11F -+#define reg_tmr_timer0_count_15_8_pos 0 -+#define reg_tmr_timer0_count_15_8_len 8 -+#define reg_tmr_timer0_count_15_8_lsb 8 -+#define p_reg_suspend 0xF120 -+#define reg_suspend_pos 0 -+#define reg_suspend_len 1 -+#define reg_suspend_lsb 0 -+#define p_reg_suspend_rdy 0xF121 -+#define reg_suspend_rdy_pos 0 -+#define reg_suspend_rdy_len 1 -+#define reg_suspend_rdy_lsb 0 -+#define p_reg_resume 0xF122 -+#define reg_resume_pos 0 -+#define reg_resume_len 1 -+#define reg_resume_lsb 0 -+#define p_reg_resume_rdy 0xF123 -+#define reg_resume_rdy_pos 0 -+#define reg_resume_rdy_len 1 -+#define reg_resume_rdy_lsb 0 -+#define p_reg_gp_trigger 0xF124 -+#define reg_gp_trigger_pos 0 -+#define reg_gp_trigger_len 1 -+#define reg_gp_trigger_lsb 0 -+#define p_reg_trigger_sel 0xF125 -+#define reg_trigger_sel_pos 0 -+#define reg_trigger_sel_len 2 -+#define reg_trigger_sel_lsb 0 -+#define p_reg_debug_ofdm 0xF126 -+#define reg_debug_ofdm_pos 0 -+#define reg_debug_ofdm_len 2 -+#define reg_debug_ofdm_lsb 0 -+#define p_reg_trigger_module_sel 0xF127 -+#define reg_trigger_module_sel_pos 0 -+#define reg_trigger_module_sel_len 6 -+#define reg_trigger_module_sel_lsb 0 -+#define p_reg_trigger_set_sel 0xF128 -+#define reg_trigger_set_sel_pos 0 -+#define reg_trigger_set_sel_len 6 -+#define reg_trigger_set_sel_lsb 0 -+#define p_reg_fw_int_mask_n 0xF129 -+#define reg_fw_int_mask_n_pos 0 -+#define reg_fw_int_mask_n_len 1 -+#define reg_fw_int_mask_n_lsb 0 -+#define p_reg_dioif_rst 0xF12A -+#define reg_dioif_rst_pos 0 -+#define reg_dioif_rst_len 1 -+#define reg_dioif_rst_lsb 0 -+#define p_reg_debug_group 0xF12B -+#define reg_debug_group_pos 0 -+#define reg_debug_group_len 4 -+#define reg_debug_group_lsb 0 -+#define p_reg_odbg_clk_sel 0xF12C -+#define reg_odbg_clk_sel_pos 0 -+#define reg_odbg_clk_sel_len 3 -+#define reg_odbg_clk_sel_lsb 0 -+#define p_reg_p_ccif_shift_fre 0xF12F -+#define reg_p_ccif_shift_fre_pos 0 -+#define reg_p_ccif_shift_fre_len 1 -+#define reg_p_ccif_shift_fre_lsb 0 -+#define p_reg_p_ccif_bandwidth_factor 0xF130 -+#define reg_p_ccif_bandwidth_factor_pos 0 -+#define reg_p_ccif_bandwidth_factor_len 3 -+#define reg_p_ccif_bandwidth_factor_lsb 0 -+#define p_reg_ccif_rst 0xF131 -+#define reg_ccif_rst_pos 0 -+#define reg_ccif_rst_len 1 -+#define reg_ccif_rst_lsb 0 -+#define p_reg_p_ccif_min_bandwidth 0xF132 -+#define reg_p_ccif_min_bandwidth_pos 0 -+#define reg_p_ccif_min_bandwidth_len 7 -+#define reg_p_ccif_min_bandwidth_lsb 0 -+#define p_reg_ccif_bq0_state 0xF133 -+#define reg_ccif_bq0_state_pos 0 -+#define reg_ccif_bq0_state_len 1 -+#define reg_ccif_bq0_state_lsb 0 -+#define p_reg_ccif_bq0_outputscaling 0xF134 -+#define reg_ccif_bq0_outputscaling_pos 0 -+#define reg_ccif_bq0_outputscaling_len 5 -+#define reg_ccif_bq0_outputscaling_lsb 0 -+#define p_reg_ccif_bq1_state 0xF135 -+#define reg_ccif_bq1_state_pos 0 -+#define reg_ccif_bq1_state_len 1 -+#define reg_ccif_bq1_state_lsb 0 -+#define p_reg_ccif_bq1_outputscaling 0xF136 -+#define reg_ccif_bq1_outputscaling_pos 0 -+#define reg_ccif_bq1_outputscaling_len 5 -+#define reg_ccif_bq1_outputscaling_lsb 0 -+#define p_reg_ccif_bq0_a1_7_0 0xF137 -+#define reg_ccif_bq0_a1_7_0_pos 0 -+#define reg_ccif_bq0_a1_7_0_len 8 -+#define reg_ccif_bq0_a1_7_0_lsb 0 -+#define p_reg_ccif_bq0_a1_13_8 0xF138 -+#define reg_ccif_bq0_a1_13_8_pos 0 -+#define reg_ccif_bq0_a1_13_8_len 6 -+#define reg_ccif_bq0_a1_13_8_lsb 8 -+#define p_reg_ccif_bq1_a1_7_0 0xF139 -+#define reg_ccif_bq1_a1_7_0_pos 0 -+#define reg_ccif_bq1_a1_7_0_len 8 -+#define reg_ccif_bq1_a1_7_0_lsb 0 -+#define p_reg_ccif_bq1_a1_13_8 0xF13A -+#define reg_ccif_bq1_a1_13_8_pos 0 -+#define reg_ccif_bq1_a1_13_8_len 6 -+#define reg_ccif_bq1_a1_13_8_lsb 8 -+#define p_reg_ccif_bq0_b1_7_0 0xF13B -+#define reg_ccif_bq0_b1_7_0_pos 0 -+#define reg_ccif_bq0_b1_7_0_len 8 -+#define reg_ccif_bq0_b1_7_0_lsb 0 -+#define p_reg_ccif_bq0_b1_13_8 0xF13C -+#define reg_ccif_bq0_b1_13_8_pos 0 -+#define reg_ccif_bq0_b1_13_8_len 6 -+#define reg_ccif_bq0_b1_13_8_lsb 8 -+#define p_reg_ccif_bq1_b1_7_0 0xF13D -+#define reg_ccif_bq1_b1_7_0_pos 0 -+#define reg_ccif_bq1_b1_7_0_len 8 -+#define reg_ccif_bq1_b1_7_0_lsb 0 -+#define p_reg_ccif_bq1_b1_13_8 0xF13E -+#define reg_ccif_bq1_b1_13_8_pos 0 -+#define reg_ccif_bq1_b1_13_8_len 6 -+#define reg_ccif_bq1_b1_13_8_lsb 8 -+#define p_reg_ccif_bq0_b2_7_0 0xF13F -+#define reg_ccif_bq0_b2_7_0_pos 0 -+#define reg_ccif_bq0_b2_7_0_len 8 -+#define reg_ccif_bq0_b2_7_0_lsb 0 -+#define p_reg_ccif_bq0_b2_13_8 0xF140 -+#define reg_ccif_bq0_b2_13_8_pos 0 -+#define reg_ccif_bq0_b2_13_8_len 6 -+#define reg_ccif_bq0_b2_13_8_lsb 8 -+#define p_reg_ccif_bq1_b2_7_0 0xF141 -+#define reg_ccif_bq1_b2_7_0_pos 0 -+#define reg_ccif_bq1_b2_7_0_len 8 -+#define reg_ccif_bq1_b2_7_0_lsb 0 -+#define p_reg_ccif_bq1_b2_13_8 0xF142 -+#define reg_ccif_bq1_b2_13_8_pos 0 -+#define reg_ccif_bq1_b2_13_8_len 6 -+#define reg_ccif_bq1_b2_13_8_lsb 8 -+#define p_reg_ccif_debug_rst 0xF143 -+#define reg_ccif_debug_rst_pos 0 -+#define reg_ccif_debug_rst_len 1 -+#define reg_ccif_debug_rst_lsb 0 -+#define p_reg_mccid_defaultccifscstrobe 0xF144 -+#define reg_mccid_defaultccifscstrobe_pos 0 -+#define reg_mccid_defaultccifscstrobe_len 7 -+#define reg_mccid_defaultccifscstrobe_lsb 0 -+#define p_reg_mccid_monitoringaci 0xF145 -+#define reg_mccid_monitoringaci_pos 0 -+#define reg_mccid_monitoringaci_len 1 -+#define reg_mccid_monitoringaci_lsb 0 -+#define p_reg_mccid_ispassmode 0xF146 -+#define reg_mccid_ispassmode_pos 0 -+#define reg_mccid_ispassmode_len 1 -+#define reg_mccid_ispassmode_lsb 0 -+#define p_reg_mccid_issteadystatemode 0xF147 -+#define reg_mccid_issteadystatemode_pos 0 -+#define reg_mccid_issteadystatemode_len 1 -+#define reg_mccid_issteadystatemode_lsb 0 -+#define p_reg_mccid_fixedgaincmp 0xF148 -+#define reg_mccid_fixedgaincmp_pos 0 -+#define reg_mccid_fixedgaincmp_len 1 -+#define reg_mccid_fixedgaincmp_lsb 0 -+#define p_reg_mccid_misscounter_reset 0xF149 -+#define reg_mccid_misscounter_reset_pos 0 -+#define reg_mccid_misscounter_reset_len 1 -+#define reg_mccid_misscounter_reset_lsb 0 -+#define p_reg_mccid_acwgcheckcciexist 0xF14A -+#define reg_mccid_acwgcheckcciexist_pos 0 -+#define reg_mccid_acwgcheckcciexist_len 1 -+#define reg_mccid_acwgcheckcciexist_lsb 0 -+#define p_reg_mccid_acidone 0xF14B -+#define reg_mccid_acidone_pos 0 -+#define reg_mccid_acidone_len 1 -+#define reg_mccid_acidone_lsb 0 -+#define p_reg_mccid_sxdesiredpower_7_0 0xF14C -+#define reg_mccid_sxdesiredpower_7_0_pos 0 -+#define reg_mccid_sxdesiredpower_7_0_len 8 -+#define reg_mccid_sxdesiredpower_7_0_lsb 0 -+#define p_reg_mccid_sxdesiredpower_9_8 0xF14D -+#define reg_mccid_sxdesiredpower_9_8_pos 0 -+#define reg_mccid_sxdesiredpower_9_8_len 2 -+#define reg_mccid_sxdesiredpower_9_8_lsb 8 -+#define p_reg_mccid_defaultccitimertriggerno 0xF14E -+#define reg_mccid_defaultccitimertriggerno_pos 0 -+#define reg_mccid_defaultccitimertriggerno_len 8 -+#define reg_mccid_defaultccitimertriggerno_lsb 0 -+#define p_reg_mccid_detectedmaxtonecountshift 0xF14F -+#define reg_mccid_detectedmaxtonecountshift_pos 0 -+#define reg_mccid_detectedmaxtonecountshift_len 3 -+#define reg_mccid_detectedmaxtonecountshift_lsb 0 -+#define p_reg_mccid_moveffttoccif_en 0xF151 -+#define reg_mccid_moveffttoccif_en_pos 0 -+#define reg_mccid_moveffttoccif_en_len 1 -+#define reg_mccid_moveffttoccif_en_lsb 0 -+#define p_reg_mccid_fftindextobfsfcwfactor_7_0 0xF152 -+#define reg_mccid_fftindextobfsfcwfactor_7_0_pos 0 -+#define reg_mccid_fftindextobfsfcwfactor_7_0_len 8 -+#define reg_mccid_fftindextobfsfcwfactor_7_0_lsb 0 -+#define p_reg_mccid_fftindextobfsfcwfactor_9_8 0xF153 -+#define reg_mccid_fftindextobfsfcwfactor_9_8_pos 0 -+#define reg_mccid_fftindextobfsfcwfactor_9_8_len 2 -+#define reg_mccid_fftindextobfsfcwfactor_9_8_lsb 8 -+#define p_reg_mccid_bfsfcwffttoindexfactor_7_0 0xF154 -+#define reg_mccid_bfsfcwffttoindexfactor_7_0_pos 0 -+#define reg_mccid_bfsfcwffttoindexfactor_7_0_len 8 -+#define reg_mccid_bfsfcwffttoindexfactor_7_0_lsb 0 -+#define p_reg_mccid_bfsfcwffttoindexfactor_10_8 0xF155 -+#define reg_mccid_bfsfcwffttoindexfactor_10_8_pos 0 -+#define reg_mccid_bfsfcwffttoindexfactor_10_8_len 3 -+#define reg_mccid_bfsfcwffttoindexfactor_10_8_lsb 8 -+#define p_reg_mccid_detectedaci 0xF156 -+#define reg_mccid_detectedaci_pos 0 -+#define reg_mccid_detectedaci_len 1 -+#define reg_mccid_detectedaci_lsb 0 -+#define r_reg_mccid_filter_enable 0xF157 -+#define reg_mccid_filter_enable_pos 0 -+#define reg_mccid_filter_enable_len 1 -+#define reg_mccid_filter_enable_lsb 0 -+#define p_reg_mccid_aciscstrobe 0xF158 -+#define reg_mccid_aciscstrobe_pos 0 -+#define reg_mccid_aciscstrobe_len 7 -+#define reg_mccid_aciscstrobe_lsb 0 -+#define p_reg_mccid_scanningaci 0xF159 -+#define reg_mccid_scanningaci_pos 0 -+#define reg_mccid_scanningaci_len 1 -+#define reg_mccid_scanningaci_lsb 0 -+#define p_reg_mccid_windowsizeacciwdcount_7_0 0xF15A -+#define reg_mccid_windowsizeacciwdcount_7_0_pos 0 -+#define reg_mccid_windowsizeacciwdcount_7_0_len 8 -+#define reg_mccid_windowsizeacciwdcount_7_0_lsb 0 -+#define p_reg_mccid_windowsizeacciwdcount_12_8 0xF15B -+#define reg_mccid_windowsizeacciwdcount_12_8_pos 0 -+#define reg_mccid_windowsizeacciwdcount_12_8_len 5 -+#define reg_mccid_windowsizeacciwdcount_12_8_lsb 8 -+#define p_reg_mccid_scannedacionly 0xF15C -+#define reg_mccid_scannedacionly_pos 0 -+#define reg_mccid_scannedacionly_len 1 -+#define reg_mccid_scannedacionly_lsb 0 -+#define p_reg_mccid_scfactor 0xF15D -+#define reg_mccid_scfactor_pos 0 -+#define reg_mccid_scfactor_len 5 -+#define reg_mccid_scfactor_lsb 0 -+#define p_reg_mccid_defaultevaluatingbandwidthfactor 0xF15E -+#define reg_mccid_defaultevaluatingbandwidthfactor_pos 0 -+#define reg_mccid_defaultevaluatingbandwidthfactor_len 3 -+#define reg_mccid_defaultevaluatingbandwidthfactor_lsb 0 -+#define p_reg_mccid_defaultacipowerlevel 0xF15F -+#define reg_mccid_defaultacipowerlevel_pos 0 -+#define reg_mccid_defaultacipowerlevel_len 3 -+#define reg_mccid_defaultacipowerlevel_lsb 0 -+#define r_reg_mccid_outputdagc1gain_7_0 0xF160 -+#define reg_mccid_outputdagc1gain_7_0_pos 0 -+#define reg_mccid_outputdagc1gain_7_0_len 8 -+#define reg_mccid_outputdagc1gain_7_0_lsb 0 -+#define r_reg_mccid_outputdagc1gain_9_8 0xF161 -+#define reg_mccid_outputdagc1gain_9_8_pos 0 -+#define reg_mccid_outputdagc1gain_9_8_len 2 -+#define reg_mccid_outputdagc1gain_9_8_lsb 8 -+#define r_reg_mccid_outputdagc1gainshift 0xF162 -+#define reg_mccid_outputdagc1gainshift_pos 0 -+#define reg_mccid_outputdagc1gainshift_len 4 -+#define reg_mccid_outputdagc1gainshift_lsb 0 -+#define p_reg_mccid_defaultacwgcheckccipowerlevel 0xF163 -+#define reg_mccid_defaultacwgcheckccipowerlevel_pos 0 -+#define reg_mccid_defaultacwgcheckccipowerlevel_len 3 -+#define reg_mccid_defaultacwgcheckccipowerlevel_lsb 0 -+#define p_reg_mccid_ccipowerlevelfactor 0xF166 -+#define reg_mccid_ccipowerlevelfactor_pos 0 -+#define reg_mccid_ccipowerlevelfactor_len 3 -+#define reg_mccid_ccipowerlevelfactor_lsb 0 -+#define p_reg_mccid_scstrobesearchingrange 0xF167 -+#define reg_mccid_scstrobesearchingrange_pos 0 -+#define reg_mccid_scstrobesearchingrange_len 8 -+#define reg_mccid_scstrobesearchingrange_lsb 0 -+#define p_reg_mccid_searchingno 0xF168 -+#define reg_mccid_searchingno_pos 0 -+#define reg_mccid_searchingno_len 6 -+#define reg_mccid_searchingno_lsb 0 -+#define p_reg_mccid_scannedacifrequencyresolution 0xF169 -+#define reg_mccid_scannedacifrequencyresolution_pos 0 -+#define reg_mccid_scannedacifrequencyresolution_len 4 -+#define reg_mccid_scannedacifrequencyresolution_lsb 0 -+#define p_reg_mccid_fft0_maskmaxtoneindex_7_0 0xF16A -+#define reg_mccid_fft0_maskmaxtoneindex_7_0_pos 0 -+#define reg_mccid_fft0_maskmaxtoneindex_7_0_len 8 -+#define reg_mccid_fft0_maskmaxtoneindex_7_0_lsb 0 -+#define p_reg_mccid_fft0_maskmaxtoneindex_12_8 0xF16B -+#define reg_mccid_fft0_maskmaxtoneindex_12_8_pos 0 -+#define reg_mccid_fft0_maskmaxtoneindex_12_8_len 5 -+#define reg_mccid_fft0_maskmaxtoneindex_12_8_lsb 8 -+#define p_reg_mccid_fft0_state 0xF16C -+#define reg_mccid_fft0_state_pos 0 -+#define reg_mccid_fft0_state_len 1 -+#define reg_mccid_fft0_state_lsb 0 -+#define p_reg_mccid_fft1_state 0xF16D -+#define reg_mccid_fft1_state_pos 0 -+#define reg_mccid_fft1_state_len 1 -+#define reg_mccid_fft1_state_lsb 0 -+#define p_reg_mccid_fft0_maskmintoneindex_7_0 0xF16E -+#define reg_mccid_fft0_maskmintoneindex_7_0_pos 0 -+#define reg_mccid_fft0_maskmintoneindex_7_0_len 8 -+#define reg_mccid_fft0_maskmintoneindex_7_0_lsb 0 -+#define p_reg_mccid_fft0_maskmintoneindex_12_8 0xF16F -+#define reg_mccid_fft0_maskmintoneindex_12_8_pos 0 -+#define reg_mccid_fft0_maskmintoneindex_12_8_len 5 -+#define reg_mccid_fft0_maskmintoneindex_12_8_lsb 8 -+#define p_reg_mccid_acipowerlevelfactor 0xF170 -+#define reg_mccid_acipowerlevelfactor_pos 0 -+#define reg_mccid_acipowerlevelfactor_len 3 -+#define reg_mccid_acipowerlevelfactor_lsb 0 -+#define p_reg_mccid_fft1_maskmaxtoneindex_7_0 0xF171 -+#define reg_mccid_fft1_maskmaxtoneindex_7_0_pos 0 -+#define reg_mccid_fft1_maskmaxtoneindex_7_0_len 8 -+#define reg_mccid_fft1_maskmaxtoneindex_7_0_lsb 0 -+#define p_reg_mccid_fft1_maskmaxtoneindex_12_8 0xF172 -+#define reg_mccid_fft1_maskmaxtoneindex_12_8_pos 0 -+#define reg_mccid_fft1_maskmaxtoneindex_12_8_len 5 -+#define reg_mccid_fft1_maskmaxtoneindex_12_8_lsb 8 -+#define p_reg_mccid_fft1_maskmintoneindex_7_0 0xF173 -+#define reg_mccid_fft1_maskmintoneindex_7_0_pos 0 -+#define reg_mccid_fft1_maskmintoneindex_7_0_len 8 -+#define reg_mccid_fft1_maskmintoneindex_7_0_lsb 0 -+#define p_reg_mccid_fft1_maskmintoneindex_12_8 0xF174 -+#define reg_mccid_fft1_maskmintoneindex_12_8_pos 0 -+#define reg_mccid_fft1_maskmintoneindex_12_8_len 5 -+#define reg_mccid_fft1_maskmintoneindex_12_8_lsb 8 -+#define p_reg_mccid_reset 0xF175 -+#define reg_mccid_reset_pos 0 -+#define reg_mccid_reset_len 1 -+#define reg_mccid_reset_lsb 0 -+#define p_reg_mccid_gaincmpreset 0xF176 -+#define reg_mccid_gaincmpreset_pos 0 -+#define reg_mccid_gaincmpreset_len 1 -+#define reg_mccid_gaincmpreset_lsb 0 -+#define p_reg_mccid_acwgreset 0xF177 -+#define reg_mccid_acwgreset_pos 0 -+#define reg_mccid_acwgreset_len 1 -+#define reg_mccid_acwgreset_lsb 0 -+#define p_reg_mccid_ccif0_ofsmstateenable 0xF178 -+#define reg_mccid_ccif0_ofsmstateenable_pos 0 -+#define reg_mccid_ccif0_ofsmstateenable_len 1 -+#define reg_mccid_ccif0_ofsmstateenable_lsb 0 -+#define p_reg_mccid_ccif1_ofsmstateenable 0xF179 -+#define reg_mccid_ccif1_ofsmstateenable_pos 0 -+#define reg_mccid_ccif1_ofsmstateenable_len 1 -+#define reg_mccid_ccif1_ofsmstateenable_lsb 0 -+#define p_reg_mccid_fft0_ofsmstateenable 0xF17A -+#define reg_mccid_fft0_ofsmstateenable_pos 0 -+#define reg_mccid_fft0_ofsmstateenable_len 1 -+#define reg_mccid_fft0_ofsmstateenable_lsb 0 -+#define p_reg_mccid_fft1_ofsmstateenable 0xF17B -+#define reg_mccid_fft1_ofsmstateenable_pos 0 -+#define reg_mccid_fft1_ofsmstateenable_len 1 -+#define reg_mccid_fft1_ofsmstateenable_lsb 0 -+#define p_reg_mccid_fftfiltermaskchange 0xF17C -+#define reg_mccid_fftfiltermaskchange_pos 0 -+#define reg_mccid_fftfiltermaskchange_len 1 -+#define reg_mccid_fftfiltermaskchange_lsb 0 -+#define r_reg_mccid_maxacipowertone_7_0 0xF17D -+#define reg_mccid_maxacipowertone_7_0_pos 0 -+#define reg_mccid_maxacipowertone_7_0_len 8 -+#define reg_mccid_maxacipowertone_7_0_lsb 0 -+#define r_reg_mccid_maxacipowertone_12_8 0xF17E -+#define reg_mccid_maxacipowertone_12_8_pos 0 -+#define reg_mccid_maxacipowertone_12_8_len 5 -+#define reg_mccid_maxacipowertone_12_8_lsb 8 -+#define r_reg_mccid_ccidisappear 0xF17F -+#define reg_mccid_ccidisappear_pos 0 -+#define reg_mccid_ccidisappear_len 1 -+#define reg_mccid_ccidisappear_lsb 0 -+#define r_reg_mccid_ccilocatordone 0xF182 -+#define reg_mccid_ccilocatordone_pos 0 -+#define reg_mccid_ccilocatordone_len 1 -+#define reg_mccid_ccilocatordone_lsb 0 -+#define p_reg_mccid_enablecciftrigger 0xF183 -+#define reg_mccid_enablecciftrigger_pos 0 -+#define reg_mccid_enablecciftrigger_len 1 -+#define reg_mccid_enablecciftrigger_lsb 0 -+#define p_reg_mccid_disableacwglaunchevaluationbandwidthtrigger 0xF184 -+#define reg_mccid_disableacwglaunchevaluationbandwidthtrigger_pos 0 -+#define reg_mccid_disableacwglaunchevaluationbandwidthtrigger_len 1 -+#define reg_mccid_disableacwglaunchevaluationbandwidthtrigger_lsb 0 -+#define p_reg_mccid_control_by_ofsm 0xF185 -+#define reg_mccid_control_by_ofsm_pos 0 -+#define reg_mccid_control_by_ofsm_len 1 -+#define reg_mccid_control_by_ofsm_lsb 0 -+#define p_reg_mccid_ofsmcontrolccilocator 0xF186 -+#define reg_mccid_ofsmcontrolccilocator_pos 0 -+#define reg_mccid_ofsmcontrolccilocator_len 1 -+#define reg_mccid_ofsmcontrolccilocator_lsb 0 -+#define p_reg_mccid_disablepotentialccitriggerccilocator 0xF187 -+#define reg_mccid_disablepotentialccitriggerccilocator_pos 0 -+#define reg_mccid_disablepotentialccitriggerccilocator_len 1 -+#define reg_mccid_disablepotentialccitriggerccilocator_lsb 0 -+#define p_reg_mccid_ofsmcontrolccitesting 0xF188 -+#define reg_mccid_ofsmcontrolccitesting_pos 0 -+#define reg_mccid_ofsmcontrolccitesting_len 1 -+#define reg_mccid_ofsmcontrolccitesting_lsb 0 -+#define p_reg_mccid_disableccitestingtriggercheckcci 0xF189 -+#define reg_mccid_disableccitestingtriggercheckcci_pos 0 -+#define reg_mccid_disableccitestingtriggercheckcci_len 1 -+#define reg_mccid_disableccitestingtriggercheckcci_lsb 0 -+#define p_reg_mccid_ofsmcontrolacwgsetccifscstrobe 0xF18A -+#define reg_mccid_ofsmcontrolacwgsetccifscstrobe_pos 0 -+#define reg_mccid_ofsmcontrolacwgsetccifscstrobe_len 1 -+#define reg_mccid_ofsmcontrolacwgsetccifscstrobe_lsb 0 -+#define p_reg_mccid_disableacwgevaluatingbandwidthtrigger 0xF18B -+#define reg_mccid_disableacwgevaluatingbandwidthtrigger_pos 0 -+#define reg_mccid_disableacwgevaluatingbandwidthtrigger_len 1 -+#define reg_mccid_disableacwgevaluatingbandwidthtrigger_lsb 0 -+#define p_reg_mccid_ofsmcontrolevaluatingbandwidth 0xF18C -+#define reg_mccid_ofsmcontrolevaluatingbandwidth_pos 0 -+#define reg_mccid_ofsmcontrolevaluatingbandwidth_len 1 -+#define reg_mccid_ofsmcontrolevaluatingbandwidth_lsb 0 -+#define p_reg_mccid_ofsmcontrolscanningaci 0xF18D -+#define reg_mccid_ofsmcontrolscanningaci_pos 0 -+#define reg_mccid_ofsmcontrolscanningaci_len 1 -+#define reg_mccid_ofsmcontrolscanningaci_lsb 0 -+#define p_reg_mccid_disablescanningaci 0xF18E -+#define reg_mccid_disablescanningaci_pos 0 -+#define reg_mccid_disablescanningaci_len 1 -+#define reg_mccid_disablescanningaci_lsb 0 -+#define p_reg_mccid_disableacwgccidetecting 0xF18F -+#define reg_mccid_disableacwgccidetecting_pos 0 -+#define reg_mccid_disableacwgccidetecting_len 1 -+#define reg_mccid_disableacwgccidetecting_lsb 0 -+#define p_reg_mccid_ofsmcontrolccitimertrigger 0xF190 -+#define reg_mccid_ofsmcontrolccitimertrigger_pos 0 -+#define reg_mccid_ofsmcontrolccitimertrigger_len 1 -+#define reg_mccid_ofsmcontrolccitimertrigger_lsb 0 -+#define p_reg_mccid_disableccitimertrigger 0xF191 -+#define reg_mccid_disableccitimertrigger_pos 0 -+#define reg_mccid_disableccitimertrigger_len 1 -+#define reg_mccid_disableccitimertrigger_lsb 0 -+#define p_reg_mccid_ofsmdisableccitriggercounting 0xF192 -+#define reg_mccid_ofsmdisableccitriggercounting_pos 0 -+#define reg_mccid_ofsmdisableccitriggercounting_len 1 -+#define reg_mccid_ofsmdisableccitriggercounting_lsb 0 -+#define p_reg_mccid_enableccifilteraci 0xF193 -+#define reg_mccid_enableccifilteraci_pos 0 -+#define reg_mccid_enableccifilteraci_len 1 -+#define reg_mccid_enableccifilteraci_lsb 0 -+#define p_reg_mccid_scannedfcwbfs_7_0 0xF194 -+#define reg_mccid_scannedfcwbfs_7_0_pos 0 -+#define reg_mccid_scannedfcwbfs_7_0_len 8 -+#define reg_mccid_scannedfcwbfs_7_0_lsb 0 -+#define p_reg_mccid_scannedfcwbfs_13_8 0xF195 -+#define reg_mccid_scannedfcwbfs_13_8_pos 0 -+#define reg_mccid_scannedfcwbfs_13_8_len 6 -+#define reg_mccid_scannedfcwbfs_13_8_lsb 8 -+#define p_reg_mccid_acwgevaluatingbandwidth 0xF196 -+#define reg_mccid_acwgevaluatingbandwidth_pos 0 -+#define reg_mccid_acwgevaluatingbandwidth_len 1 -+#define reg_mccid_acwgevaluatingbandwidth_lsb 0 -+#define p_reg_mccid_acwglaunchevaluationbandwidth 0xF197 -+#define reg_mccid_acwglaunchevaluationbandwidth_pos 0 -+#define reg_mccid_acwglaunchevaluationbandwidth_len 1 -+#define reg_mccid_acwglaunchevaluationbandwidth_lsb 0 -+#define p_reg_mccid_scannedcandidate 0xF198 -+#define reg_mccid_scannedcandidate_pos 0 -+#define reg_mccid_scannedcandidate_len 3 -+#define reg_mccid_scannedcandidate_lsb 0 -+#define p_reg_mccid_scstrobesearchingcandidate 0xF199 -+#define reg_mccid_scstrobesearchingcandidate_pos 0 -+#define reg_mccid_scstrobesearchingcandidate_len 2 -+#define reg_mccid_scstrobesearchingcandidate_lsb 0 -+#define p_reg_mccid_potentialcci 0xF19A -+#define reg_mccid_potentialcci_pos 0 -+#define reg_mccid_potentialcci_len 1 -+#define reg_mccid_potentialcci_lsb 0 -+#define p_reg_mccid_cciftimertrigger 0xF19B -+#define reg_mccid_cciftimertrigger_pos 0 -+#define reg_mccid_cciftimertrigger_len 1 -+#define reg_mccid_cciftimertrigger_lsb 0 -+#define p_reg_mccid_ccitesting 0xF19C -+#define reg_mccid_ccitesting_pos 0 -+#define reg_mccid_ccitesting_len 1 -+#define reg_mccid_ccitesting_lsb 0 -+#define p_reg_mccid_defaultccilocatormissno 0xF19D -+#define reg_mccid_defaultccilocatormissno_pos 0 -+#define reg_mccid_defaultccilocatormissno_len 8 -+#define reg_mccid_defaultccilocatormissno_lsb 0 -+#define p_reg_mccid_dagc1_use_despow 0xF19E -+#define reg_mccid_dagc1_use_despow_pos 0 -+#define reg_mccid_dagc1_use_despow_len 1 -+#define reg_mccid_dagc1_use_despow_lsb 0 -+#define p_reg_mccid_scannedacifrequencybegin_7_0 0xF19F -+#define reg_mccid_scannedacifrequencybegin_7_0_pos 0 -+#define reg_mccid_scannedacifrequencybegin_7_0_len 8 -+#define reg_mccid_scannedacifrequencybegin_7_0_lsb 0 -+#define p_reg_mccid_scannedacifrequencybegin_13_8 0xF1A0 -+#define reg_mccid_scannedacifrequencybegin_13_8_pos 0 -+#define reg_mccid_scannedacifrequencybegin_13_8_len 6 -+#define reg_mccid_scannedacifrequencybegin_13_8_lsb 8 -+#define p_reg_mccid_scannedacifrequencyend_7_0 0xF1A1 -+#define reg_mccid_scannedacifrequencyend_7_0_pos 0 -+#define reg_mccid_scannedacifrequencyend_7_0_len 8 -+#define reg_mccid_scannedacifrequencyend_7_0_lsb 0 -+#define p_reg_mccid_scannedacifrequencyend_13_8 0xF1A2 -+#define reg_mccid_scannedacifrequencyend_13_8_pos 0 -+#define reg_mccid_scannedacifrequencyend_13_8_len 6 -+#define reg_mccid_scannedacifrequencyend_13_8_lsb 8 -+#define p_reg_bfs_fcw_7_0 0xF1A3 -+#define reg_bfs_fcw_7_0_pos 0 -+#define reg_bfs_fcw_7_0_len 8 -+#define reg_bfs_fcw_7_0_lsb 0 -+#define p_reg_bfs_fcw_15_8 0xF1A4 -+#define reg_bfs_fcw_15_8_pos 0 -+#define reg_bfs_fcw_15_8_len 8 -+#define reg_bfs_fcw_15_8_lsb 8 -+#define p_reg_bfs_fcw_22_16 0xF1A5 -+#define reg_bfs_fcw_22_16_pos 0 -+#define reg_bfs_fcw_22_16_len 7 -+#define reg_bfs_fcw_22_16_lsb 16 -+#define p_reg_cfoe_fcw_inv 0xF1A6 -+#define reg_cfoe_fcw_inv_pos 0 -+#define reg_cfoe_fcw_inv_len 1 -+#define reg_cfoe_fcw_inv_lsb 0 -+#define p_reg_bfs_0if 0xF1A7 -+#define reg_bfs_0if_pos 0 -+#define reg_bfs_0if_len 1 -+#define reg_bfs_0if_lsb 0 -+#define p_reg_sadc_clk 0xF1A9 -+#define reg_sadc_clk_pos 0 -+#define reg_sadc_clk_len 1 -+#define reg_sadc_clk_lsb 0 -+#define p_reg_sadc_tx 0xF1AA -+#define reg_sadc_tx_pos 0 -+#define reg_sadc_tx_len 1 -+#define reg_sadc_tx_lsb 0 -+#define p_reg_sadc_rx 0xF1AB -+#define reg_sadc_rx_pos 0 -+#define reg_sadc_rx_len 1 -+#define reg_sadc_rx_lsb 0 -+#define p_reg_sadc_cs 0xF1AC -+#define reg_sadc_cs_pos 0 -+#define reg_sadc_cs_len 1 -+#define reg_sadc_cs_lsb 0 -+#define p_reg_fix_fcw_7_0 0xF1AD -+#define reg_fix_fcw_7_0_pos 0 -+#define reg_fix_fcw_7_0_len 8 -+#define reg_fix_fcw_7_0_lsb 0 -+#define p_reg_fix_fcw_15_8 0xF1AE -+#define reg_fix_fcw_15_8_pos 0 -+#define reg_fix_fcw_15_8_len 8 -+#define reg_fix_fcw_15_8_lsb 8 -+#define p_reg_fix_fcw_22_16 0xF1AF -+#define reg_fix_fcw_22_16_pos 0 -+#define reg_fix_fcw_22_16_len 7 -+#define reg_fix_fcw_22_16_lsb 16 -+#define r_reg_bfs_fcw_offset_7_0 0xF1B0 -+#define reg_bfs_fcw_offset_7_0_pos 0 -+#define reg_bfs_fcw_offset_7_0_len 8 -+#define reg_bfs_fcw_offset_7_0_lsb 0 -+#define r_reg_bfs_fcw_offset_15_8 0xF1B1 -+#define reg_bfs_fcw_offset_15_8_pos 0 -+#define reg_bfs_fcw_offset_15_8_len 8 -+#define reg_bfs_fcw_offset_15_8_lsb 8 -+#define r_reg_bfs_fcw_offset_22_16 0xF1B2 -+#define reg_bfs_fcw_offset_22_16_pos 0 -+#define reg_bfs_fcw_offset_22_16_len 7 -+#define reg_bfs_fcw_offset_22_16_lsb 16 -+#define r_bfs_fcw_q_7_0 0xF1B3 -+#define bfs_fcw_q_7_0_pos 0 -+#define bfs_fcw_q_7_0_len 8 -+#define bfs_fcw_q_7_0_lsb 0 -+#define r_bfs_fcw_q_15_8 0xF1B4 -+#define bfs_fcw_q_15_8_pos 0 -+#define bfs_fcw_q_15_8_len 8 -+#define bfs_fcw_q_15_8_lsb 8 -+#define r_bfs_fcw_q_22_16 0xF1B5 -+#define bfs_fcw_q_22_16_pos 0 -+#define bfs_fcw_q_22_16_len 7 -+#define bfs_fcw_q_22_16_lsb 16 -+#define p_reg_dagc3_use_despow 0xF1B6 -+#define reg_dagc3_use_despow_pos 0 -+#define reg_dagc3_use_despow_len 1 -+#define reg_dagc3_use_despow_lsb 0 -+#define p_reg_dagc3_log_2_accumulate 0xF1B7 -+#define reg_dagc3_log_2_accumulate_pos 0 -+#define reg_dagc3_log_2_accumulate_len 5 -+#define reg_dagc3_log_2_accumulate_lsb 0 -+#define p_reg_dagc3_desired_level_7_0 0xF1BC -+#define reg_dagc3_desired_level_7_0_pos 0 -+#define reg_dagc3_desired_level_7_0_len 8 -+#define reg_dagc3_desired_level_7_0_lsb 0 -+#define p_reg_dagc3_desired_level_8 0xF1BD -+#define reg_dagc3_desired_level_8_pos 0 -+#define reg_dagc3_desired_level_8_len 1 -+#define reg_dagc3_desired_level_8_lsb 8 -+#define p_reg_dagc3_apply_delay 0xF1BE -+#define reg_dagc3_apply_delay_pos 0 -+#define reg_dagc3_apply_delay_len 7 -+#define reg_dagc3_apply_delay_lsb 0 -+#define p_reg_dagc3_bp_scale 0xF1BF -+#define reg_dagc3_bp_scale_pos 0 -+#define reg_dagc3_bp_scale_len 3 -+#define reg_dagc3_bp_scale_lsb 0 -+#define p_reg_dagc3_in_sat_cnt_7_0 0xF1C0 -+#define reg_dagc3_in_sat_cnt_7_0_pos 0 -+#define reg_dagc3_in_sat_cnt_7_0_len 8 -+#define reg_dagc3_in_sat_cnt_7_0_lsb 0 -+#define p_reg_dagc3_in_sat_cnt_15_8 0xF1C1 -+#define reg_dagc3_in_sat_cnt_15_8_pos 0 -+#define reg_dagc3_in_sat_cnt_15_8_len 8 -+#define reg_dagc3_in_sat_cnt_15_8_lsb 8 -+#define p_reg_dagc3_in_sat_cnt_23_16 0xF1C2 -+#define reg_dagc3_in_sat_cnt_23_16_pos 0 -+#define reg_dagc3_in_sat_cnt_23_16_len 8 -+#define reg_dagc3_in_sat_cnt_23_16_lsb 16 -+#define p_reg_dagc3_in_sat_cnt_31_24 0xF1C3 -+#define reg_dagc3_in_sat_cnt_31_24_pos 0 -+#define reg_dagc3_in_sat_cnt_31_24_len 8 -+#define reg_dagc3_in_sat_cnt_31_24_lsb 24 -+#define p_reg_dagc3_out_sat_cnt_7_0 0xF1C4 -+#define reg_dagc3_out_sat_cnt_7_0_pos 0 -+#define reg_dagc3_out_sat_cnt_7_0_len 8 -+#define reg_dagc3_out_sat_cnt_7_0_lsb 0 -+#define p_reg_dagc3_out_sat_cnt_15_8 0xF1C5 -+#define reg_dagc3_out_sat_cnt_15_8_pos 0 -+#define reg_dagc3_out_sat_cnt_15_8_len 8 -+#define reg_dagc3_out_sat_cnt_15_8_lsb 8 -+#define p_reg_dagc3_out_sat_cnt_23_16 0xF1C6 -+#define reg_dagc3_out_sat_cnt_23_16_pos 0 -+#define reg_dagc3_out_sat_cnt_23_16_len 8 -+#define reg_dagc3_out_sat_cnt_23_16_lsb 16 -+#define p_reg_dagc3_out_sat_cnt_31_24 0xF1C7 -+#define reg_dagc3_out_sat_cnt_31_24_pos 0 -+#define reg_dagc3_out_sat_cnt_31_24_len 8 -+#define reg_dagc3_out_sat_cnt_31_24_lsb 24 -+#define r_bfs_dagc3_multiplier_7_0 0xF1C8 -+#define bfs_dagc3_multiplier_7_0_pos 0 -+#define bfs_dagc3_multiplier_7_0_len 8 -+#define bfs_dagc3_multiplier_7_0_lsb 0 -+#define r_bfs_dagc3_multiplier_15_8 0xF1C9 -+#define bfs_dagc3_multiplier_15_8_pos 0 -+#define bfs_dagc3_multiplier_15_8_len 8 -+#define bfs_dagc3_multiplier_15_8_lsb 8 -+#define r_bfs_dagc3_right_shift_bits 0xF1CA -+#define bfs_dagc3_right_shift_bits_pos 0 -+#define bfs_dagc3_right_shift_bits_len 4 -+#define bfs_dagc3_right_shift_bits_lsb 0 -+#define p_reg_dagc3_fixed_gain_7_0 0xF1CB -+#define reg_dagc3_fixed_gain_7_0_pos 0 -+#define reg_dagc3_fixed_gain_7_0_len 8 -+#define reg_dagc3_fixed_gain_7_0_lsb 0 -+#define p_reg_dagc3_fixed_gain_11_8 0xF1CC -+#define reg_dagc3_fixed_gain_11_8_pos 0 -+#define reg_dagc3_fixed_gain_11_8_len 4 -+#define reg_dagc3_fixed_gain_11_8_lsb 8 -+#define p_reg_f_adc_7_0 0xF1CD -+#define reg_f_adc_7_0_pos 0 -+#define reg_f_adc_7_0_len 8 -+#define reg_f_adc_7_0_lsb 0 -+#define p_reg_f_adc_15_8 0xF1CE -+#define reg_f_adc_15_8_pos 0 -+#define reg_f_adc_15_8_len 8 -+#define reg_f_adc_15_8_lsb 8 -+#define p_reg_f_adc_23_16 0xF1CF -+#define reg_f_adc_23_16_pos 0 -+#define reg_f_adc_23_16_len 8 -+#define reg_f_adc_23_16_lsb 16 -+#define p_reg_fste_frac_step_size_7_0 0xF1D0 -+#define reg_fste_frac_step_size_7_0_pos 0 -+#define reg_fste_frac_step_size_7_0_len 8 -+#define reg_fste_frac_step_size_7_0_lsb 0 -+#define p_reg_fste_frac_step_size_15_8 0xF1D1 -+#define reg_fste_frac_step_size_15_8_pos 0 -+#define reg_fste_frac_step_size_15_8_len 8 -+#define reg_fste_frac_step_size_15_8_lsb 8 -+#define p_reg_fste_frac_step_size_19_16 0xF1D2 -+#define reg_fste_frac_step_size_19_16_pos 0 -+#define reg_fste_frac_step_size_19_16_len 4 -+#define reg_fste_frac_step_size_19_16_lsb 16 -+#define r_intp_mu_7_0 0xF1D3 -+#define intp_mu_7_0_pos 0 -+#define intp_mu_7_0_len 8 -+#define intp_mu_7_0_lsb 0 -+#define r_intp_mu_15_8 0xF1D4 -+#define intp_mu_15_8_pos 0 -+#define intp_mu_15_8_len 8 -+#define intp_mu_15_8_lsb 8 -+#define r_intp_mu_23_16 0xF1D5 -+#define intp_mu_23_16_pos 0 -+#define intp_mu_23_16_len 8 -+#define intp_mu_23_16_lsb 16 -+#define r_intp_mu_25_24 0xF1D6 -+#define intp_mu_25_24_pos 0 -+#define intp_mu_25_24_len 2 -+#define intp_mu_25_24_lsb 24 -+#define p_intp_muq_7_0 0xF1D7 -+#define intp_muq_7_0_pos 0 -+#define intp_muq_7_0_len 8 -+#define intp_muq_7_0_lsb 0 -+#define p_intp_muq_15_8 0xF1D8 -+#define intp_muq_15_8_pos 0 -+#define intp_muq_15_8_len 8 -+#define intp_muq_15_8_lsb 8 -+#define p_intp_muq_23_16 0xF1D9 -+#define intp_muq_23_16_pos 0 -+#define intp_muq_23_16_len 8 -+#define intp_muq_23_16_lsb 16 -+#define p_reg_sfoe_inv 0xF1DA -+#define reg_sfoe_inv_pos 0 -+#define reg_sfoe_inv_len 1 -+#define reg_sfoe_inv_lsb 0 -+#define p_intp_ext_en 0xF1DB -+#define intp_ext_en_pos 0 -+#define intp_ext_en_len 1 -+#define intp_ext_en_lsb 0 -+#define r_intp_ext_done 0xF1DC -+#define intp_ext_done_pos 0 -+#define intp_ext_done_len 1 -+#define intp_ext_done_lsb 0 -+#define p_intp_ext_in_7_0 0xF1DD -+#define intp_ext_in_7_0_pos 0 -+#define intp_ext_in_7_0_len 8 -+#define intp_ext_in_7_0_lsb 0 -+#define p_intp_ext_in_15_8 0xF1DE -+#define intp_ext_in_15_8_pos 0 -+#define intp_ext_in_15_8_len 8 -+#define intp_ext_in_15_8_lsb 8 -+#define p_intp_ext_in_23_16 0xF1DF -+#define intp_ext_in_23_16_pos 0 -+#define intp_ext_in_23_16_len 8 -+#define intp_ext_in_23_16_lsb 16 -+#define p_intp_ext_in_25_24 0xF1E0 -+#define intp_ext_in_25_24_pos 0 -+#define intp_ext_in_25_24_len 2 -+#define intp_ext_in_25_24_lsb 24 -+#define r_intp_ext_out_7_0 0xF1E1 -+#define intp_ext_out_7_0_pos 0 -+#define intp_ext_out_7_0_len 8 -+#define intp_ext_out_7_0_lsb 0 -+#define r_intp_ext_out_15_8 0xF1E2 -+#define intp_ext_out_15_8_pos 0 -+#define intp_ext_out_15_8_len 8 -+#define intp_ext_out_15_8_lsb 8 -+#define r_intp_ext_out_23_16 0xF1E3 -+#define intp_ext_out_23_16_pos 0 -+#define intp_ext_out_23_16_len 8 -+#define intp_ext_out_23_16_lsb 16 -+#define r_intp_ext_out_28_24 0xF1E4 -+#define intp_ext_out_28_24_pos 0 -+#define intp_ext_out_28_24_len 5 -+#define intp_ext_out_28_24_lsb 24 -+#define p_reg_agc_rst 0xF1E5 -+#define reg_agc_rst_pos 0 -+#define reg_agc_rst_len 1 -+#define reg_agc_rst_lsb 0 -+#define p_rf_agc_en 0xF1E6 -+#define rf_agc_en_pos 0 -+#define rf_agc_en_len 1 -+#define rf_agc_en_lsb 0 -+#define p_agc_lock 0xF1E7 -+#define agc_lock_pos 0 -+#define agc_lock_len 1 -+#define agc_lock_lsb 0 -+#define p_reg_tinr_rst 0xF1E8 -+#define reg_tinr_rst_pos 0 -+#define reg_tinr_rst_len 1 -+#define reg_tinr_rst_lsb 0 -+#define p_reg_tinr_en 0xF1E9 -+#define reg_tinr_en_pos 0 -+#define reg_tinr_en_len 1 -+#define reg_tinr_en_lsb 0 -+#define p_reg_bfs_en 0xF1EA -+#define reg_bfs_en_pos 0 -+#define reg_bfs_en_len 1 -+#define reg_bfs_en_lsb 0 -+#define p_reg_bfs_rst 0xF1EB -+#define reg_bfs_rst_pos 0 -+#define reg_bfs_rst_len 1 -+#define reg_bfs_rst_lsb 0 -+#define p_reg_bfs_byp 0xF1EC -+#define reg_bfs_byp_pos 0 -+#define reg_bfs_byp_len 1 -+#define reg_bfs_byp_lsb 0 -+#define p_intp_en 0xF1EF -+#define intp_en_pos 0 -+#define intp_en_len 1 -+#define intp_en_lsb 0 -+#define p_intp_rst 0xF1F0 -+#define intp_rst_pos 0 -+#define intp_rst_len 1 -+#define intp_rst_lsb 0 -+#define p_reg_p_acif_en 0xF1F2 -+#define reg_p_acif_en_pos 0 -+#define reg_p_acif_en_len 1 -+#define reg_p_acif_en_lsb 0 -+#define p_reg_p_acif_rst 0xF1F3 -+#define reg_p_acif_rst_pos 0 -+#define reg_p_acif_rst_len 1 -+#define reg_p_acif_rst_lsb 0 -+#define p_reg_p_acif_byp 0xF1F4 -+#define reg_p_acif_byp_pos 0 -+#define reg_p_acif_byp_len 1 -+#define reg_p_acif_byp_lsb 0 -+#define p_dagc2_rst 0xF1F6 -+#define dagc2_rst_pos 0 -+#define dagc2_rst_len 1 -+#define dagc2_rst_lsb 0 -+#define p_dagc2_en 0xF1F7 -+#define dagc2_en_pos 0 -+#define dagc2_en_len 1 -+#define dagc2_en_lsb 0 -+#define p_dagc2_mode 0xF1F8 -+#define dagc2_mode_pos 0 -+#define dagc2_mode_len 2 -+#define dagc2_mode_lsb 0 -+#define p_dagc2_done 0xF1F9 -+#define dagc2_done_pos 0 -+#define dagc2_done_len 1 -+#define dagc2_done_lsb 0 -+#define p_dagc3_rst 0xF1FA -+#define dagc3_rst_pos 0 -+#define dagc3_rst_len 1 -+#define dagc3_rst_lsb 0 -+#define p_dagc3_en 0xF1FB -+#define dagc3_en_pos 0 -+#define dagc3_en_len 1 -+#define dagc3_en_lsb 0 -+#define p_dagc3_mode 0xF1FC -+#define dagc3_mode_pos 0 -+#define dagc3_mode_len 2 -+#define dagc3_mode_lsb 0 -+#define p_dagc3_done 0xF1FD -+#define dagc3_done_pos 0 -+#define dagc3_done_len 1 -+#define dagc3_done_lsb 0 -+#define p_reg_dagc2_desired_level_7_0 0xF202 -+#define reg_dagc2_desired_level_7_0_pos 0 -+#define reg_dagc2_desired_level_7_0_len 8 -+#define reg_dagc2_desired_level_7_0_lsb 0 -+#define p_reg_dagc2_desired_level_8 0xF203 -+#define reg_dagc2_desired_level_8_pos 0 -+#define reg_dagc2_desired_level_8_len 1 -+#define reg_dagc2_desired_level_8_lsb 8 -+#define p_reg_dagc2_apply_delay 0xF204 -+#define reg_dagc2_apply_delay_pos 0 -+#define reg_dagc2_apply_delay_len 7 -+#define reg_dagc2_apply_delay_lsb 0 -+#define p_reg_dagc2_bypass_scale_ctl 0xF205 -+#define reg_dagc2_bypass_scale_ctl_pos 0 -+#define reg_dagc2_bypass_scale_ctl_len 3 -+#define reg_dagc2_bypass_scale_ctl_lsb 0 -+#define p_reg_dagc2_programmable_shift2 0xF206 -+#define reg_dagc2_programmable_shift2_pos 0 -+#define reg_dagc2_programmable_shift2_len 8 -+#define reg_dagc2_programmable_shift2_lsb 0 -+#define p_reg_dagc2_in_sat_cnt_7_0 0xF207 -+#define reg_dagc2_in_sat_cnt_7_0_pos 0 -+#define reg_dagc2_in_sat_cnt_7_0_len 8 -+#define reg_dagc2_in_sat_cnt_7_0_lsb 0 -+#define p_reg_dagc2_in_sat_cnt_15_8 0xF208 -+#define reg_dagc2_in_sat_cnt_15_8_pos 0 -+#define reg_dagc2_in_sat_cnt_15_8_len 8 -+#define reg_dagc2_in_sat_cnt_15_8_lsb 8 -+#define p_reg_dagc2_in_sat_cnt_23_16 0xF209 -+#define reg_dagc2_in_sat_cnt_23_16_pos 0 -+#define reg_dagc2_in_sat_cnt_23_16_len 8 -+#define reg_dagc2_in_sat_cnt_23_16_lsb 16 -+#define p_reg_dagc2_in_sat_cnt_31_24 0xF20A -+#define reg_dagc2_in_sat_cnt_31_24_pos 0 -+#define reg_dagc2_in_sat_cnt_31_24_len 8 -+#define reg_dagc2_in_sat_cnt_31_24_lsb 24 -+#define p_reg_dagc2_out_sat_cnt_7_0 0xF20B -+#define reg_dagc2_out_sat_cnt_7_0_pos 0 -+#define reg_dagc2_out_sat_cnt_7_0_len 8 -+#define reg_dagc2_out_sat_cnt_7_0_lsb 0 -+#define p_reg_dagc2_out_sat_cnt_15_8 0xF20C -+#define reg_dagc2_out_sat_cnt_15_8_pos 0 -+#define reg_dagc2_out_sat_cnt_15_8_len 8 -+#define reg_dagc2_out_sat_cnt_15_8_lsb 8 -+#define p_reg_dagc2_out_sat_cnt_23_16 0xF20D -+#define reg_dagc2_out_sat_cnt_23_16_pos 0 -+#define reg_dagc2_out_sat_cnt_23_16_len 8 -+#define reg_dagc2_out_sat_cnt_23_16_lsb 16 -+#define p_reg_dagc2_out_sat_cnt_31_24 0xF20E -+#define reg_dagc2_out_sat_cnt_31_24_pos 0 -+#define reg_dagc2_out_sat_cnt_31_24_len 8 -+#define reg_dagc2_out_sat_cnt_31_24_lsb 24 -+#define r_reg_dagc2_multiplier_7_0 0xF20F -+#define reg_dagc2_multiplier_7_0_pos 0 -+#define reg_dagc2_multiplier_7_0_len 8 -+#define reg_dagc2_multiplier_7_0_lsb 0 -+#define r_reg_dagc2_multiplier_15_8 0xF210 -+#define reg_dagc2_multiplier_15_8_pos 0 -+#define reg_dagc2_multiplier_15_8_len 8 -+#define reg_dagc2_multiplier_15_8_lsb 8 -+#define r_reg_dagc2_right_shift_bits 0xF211 -+#define reg_dagc2_right_shift_bits_pos 0 -+#define reg_dagc2_right_shift_bits_len 4 -+#define reg_dagc2_right_shift_bits_lsb 0 -+#define p_reg_dagc2_smbuf_err 0xF212 -+#define reg_dagc2_smbuf_err_pos 0 -+#define reg_dagc2_smbuf_err_len 1 -+#define reg_dagc2_smbuf_err_lsb 0 -+#define p_reg_dagc2_cplxconj 0xF213 -+#define reg_dagc2_cplxconj_pos 0 -+#define reg_dagc2_cplxconj_len 1 -+#define reg_dagc2_cplxconj_lsb 0 -+#define p_reg_dagc2_use_despow 0xF214 -+#define reg_dagc2_use_despow_pos 0 -+#define reg_dagc2_use_despow_len 1 -+#define reg_dagc2_use_despow_lsb 0 -+#define p_reg_dagc2_log_2_accumulate 0xF215 -+#define reg_dagc2_log_2_accumulate_pos 0 -+#define reg_dagc2_log_2_accumulate_len 5 -+#define reg_dagc2_log_2_accumulate_lsb 0 -+#define r_dagc2_dca_gain 0xF216 -+#define dagc2_dca_gain_pos 0 -+#define dagc2_dca_gain_len 8 -+#define dagc2_dca_gain_lsb 0 -+#define p_reg_dca_gain_offset 0xF217 -+#define reg_dca_gain_offset_pos 0 -+#define reg_dca_gain_offset_len 8 -+#define reg_dca_gain_offset_lsb 0 -+#define p_reg_dagc2_FG_mode 0xF218 -+#define reg_dagc2_FG_mode_pos 0 -+#define reg_dagc2_FG_mode_len 1 -+#define reg_dagc2_FG_mode_lsb 0 -+#define p_reg_dagc2_fixed_gain_7_0 0xF219 -+#define reg_dagc2_fixed_gain_7_0_pos 0 -+#define reg_dagc2_fixed_gain_7_0_len 8 -+#define reg_dagc2_fixed_gain_7_0_lsb 0 -+#define p_reg_dagc2_fixed_gain_11_8 0xF21A -+#define reg_dagc2_fixed_gain_11_8_pos 0 -+#define reg_dagc2_fixed_gain_11_8_len 4 -+#define reg_dagc2_fixed_gain_11_8_lsb 8 -+#define p_reg_td_debug_7_0 0xF21B -+#define reg_td_debug_7_0_pos 0 -+#define reg_td_debug_7_0_len 8 -+#define reg_td_debug_7_0_lsb 0 -+#define p_reg_td_debug_15_8 0xF21C -+#define reg_td_debug_15_8_pos 0 -+#define reg_td_debug_15_8_len 8 -+#define reg_td_debug_15_8_lsb 8 -+#define p_reg_td_debug_23_16 0xF21D -+#define reg_td_debug_23_16_pos 0 -+#define reg_td_debug_23_16_len 8 -+#define reg_td_debug_23_16_lsb 16 -+#define p_reg_td_debug_30_24 0xF21E -+#define reg_td_debug_30_24_pos 0 -+#define reg_td_debug_30_24_len 7 -+#define reg_td_debug_30_24_lsb 24 -+#define g_reg_clk_sys40 0xF90E -+#define reg_clk_sys40_pos 0 -+#define reg_clk_sys40_len 1 -+#define reg_clk_sys40_lsb 0 -+#define g_reg_intp_sys_polarity 0xF90F -+#define reg_intp_sys_polarity_pos 0 -+#define reg_intp_sys_polarity_len 1 -+#define reg_intp_sys_polarity_lsb 0 -+#define g_reg_intp_sys_sc_7_0 0xF910 -+#define reg_intp_sys_sc_7_0_pos 0 -+#define reg_intp_sys_sc_7_0_len 8 -+#define reg_intp_sys_sc_7_0_lsb 0 -+#define g_reg_intp_sys_sc_15_8 0xF911 -+#define reg_intp_sys_sc_15_8_pos 0 -+#define reg_intp_sys_sc_15_8_len 8 -+#define reg_intp_sys_sc_15_8_lsb 8 -+#define g_reg_intp_sys_sc_23_16 0xF912 -+#define reg_intp_sys_sc_23_16_pos 0 -+#define reg_intp_sys_sc_23_16_len 8 -+#define reg_intp_sys_sc_23_16_lsb 16 -+#define g_reg_intp_sys_sc_26_24 0xF913 -+#define reg_intp_sys_sc_26_24_pos 0 -+#define reg_intp_sys_sc_26_24_len 3 -+#define reg_intp_sys_sc_26_24_lsb 24 -+#define g_reg_ofsm_clk 0xF914 -+#define reg_ofsm_clk_pos 0 -+#define reg_ofsm_clk_len 3 -+#define reg_ofsm_clk_lsb 0 -+#define g_reg_fclk_cfg 0xF915 -+#define reg_fclk_cfg_pos 0 -+#define reg_fclk_cfg_len 1 -+#define reg_fclk_cfg_lsb 0 -+#define g_reg_fclk_idi 0xF916 -+#define reg_fclk_idi_pos 0 -+#define reg_fclk_idi_len 1 -+#define reg_fclk_idi_lsb 0 -+#define g_reg_fclk_odi 0xF917 -+#define reg_fclk_odi_pos 0 -+#define reg_fclk_odi_len 1 -+#define reg_fclk_odi_lsb 0 -+#define g_reg_fclk_rsd 0xF918 -+#define reg_fclk_rsd_pos 0 -+#define reg_fclk_rsd_len 1 -+#define reg_fclk_rsd_lsb 0 -+#define g_reg_fclk_vtb 0xF919 -+#define reg_fclk_vtb_pos 0 -+#define reg_fclk_vtb_len 1 -+#define reg_fclk_vtb_lsb 0 -+#define g_reg_fclk_cste 0xF91A -+#define reg_fclk_cste_pos 0 -+#define reg_fclk_cste_len 1 -+#define reg_fclk_cste_lsb 0 -+#define g_reg_fclk_mp2if 0xF91B -+#define reg_fclk_mp2if_pos 0 -+#define reg_fclk_mp2if_len 1 -+#define reg_fclk_mp2if_lsb 0 -+#define p_reg_adcout_sync 0xFA00 -+#define reg_adcout_sync_pos 0 -+#define reg_adcout_sync_len 1 -+#define reg_adcout_sync_lsb 0 -+#define p_reg_dagc2o_edge1 0xFA01 -+#define reg_dagc2o_edge1_pos 0 -+#define reg_dagc2o_edge1_len 1 -+#define reg_dagc2o_edge1_lsb 0 -+#define p_reg_dagc2o_edge0 0xFA02 -+#define reg_dagc2o_edge0_pos 0 -+#define reg_dagc2o_edge0_len 1 -+#define reg_dagc2o_edge0_lsb 0 -+#define p_reg_second_rom_on 0xFA03 -+#define reg_second_rom_on_pos 0 -+#define reg_second_rom_on_len 1 -+#define reg_second_rom_on_lsb 0 -+#define p_reg_bypass_host2tuner 0xFA04 -+#define reg_bypass_host2tuner_pos 0 -+#define reg_bypass_host2tuner_len 1 -+#define reg_bypass_host2tuner_lsb 0 -+#define p_cfoe_NS_coeff1_7_0 0xF400 -+#define cfoe_NS_coeff1_7_0_pos 0 -+#define cfoe_NS_coeff1_7_0_len 8 -+#define cfoe_NS_coeff1_7_0_lsb 0 -+#define p_cfoe_NS_coeff1_15_8 0xF401 -+#define cfoe_NS_coeff1_15_8_pos 0 -+#define cfoe_NS_coeff1_15_8_len 8 -+#define cfoe_NS_coeff1_15_8_lsb 8 -+#define p_cfoe_NS_coeff1_23_16 0xF402 -+#define cfoe_NS_coeff1_23_16_pos 0 -+#define cfoe_NS_coeff1_23_16_len 8 -+#define cfoe_NS_coeff1_23_16_lsb 16 -+#define p_cfoe_NS_coeff1_25_24 0xF403 -+#define cfoe_NS_coeff1_25_24_pos 0 -+#define cfoe_NS_coeff1_25_24_len 2 -+#define cfoe_NS_coeff1_25_24_lsb 24 -+#define p_cfoe_NS_coeff2_7_0 0xF404 -+#define cfoe_NS_coeff2_7_0_pos 0 -+#define cfoe_NS_coeff2_7_0_len 8 -+#define cfoe_NS_coeff2_7_0_lsb 0 -+#define p_cfoe_NS_coeff2_15_8 0xF405 -+#define cfoe_NS_coeff2_15_8_pos 0 -+#define cfoe_NS_coeff2_15_8_len 8 -+#define cfoe_NS_coeff2_15_8_lsb 8 -+#define p_cfoe_NS_coeff2_23_16 0xF406 -+#define cfoe_NS_coeff2_23_16_pos 0 -+#define cfoe_NS_coeff2_23_16_len 8 -+#define cfoe_NS_coeff2_23_16_lsb 16 -+#define p_cfoe_NS_coeff2_24 0xF407 -+#define cfoe_NS_coeff2_24_pos 0 -+#define cfoe_NS_coeff2_24_len 1 -+#define cfoe_NS_coeff2_24_lsb 24 -+#define p_cfoe_lf_c1_7_0 0xF408 -+#define cfoe_lf_c1_7_0_pos 0 -+#define cfoe_lf_c1_7_0_len 8 -+#define cfoe_lf_c1_7_0_lsb 0 -+#define p_cfoe_lf_c1_9_8 0xF409 -+#define cfoe_lf_c1_9_8_pos 0 -+#define cfoe_lf_c1_9_8_len 2 -+#define cfoe_lf_c1_9_8_lsb 8 -+#define p_cfoe_lf_c2_7_0 0xF40A -+#define cfoe_lf_c2_7_0_pos 0 -+#define cfoe_lf_c2_7_0_len 8 -+#define cfoe_lf_c2_7_0_lsb 0 -+#define p_cfoe_lf_c2_9_8 0xF40B -+#define cfoe_lf_c2_9_8_pos 0 -+#define cfoe_lf_c2_9_8_len 2 -+#define cfoe_lf_c2_9_8_lsb 8 -+#define p_cfoe_ifod_7_0 0xF40C -+#define cfoe_ifod_7_0_pos 0 -+#define cfoe_ifod_7_0_len 8 -+#define cfoe_ifod_7_0_lsb 0 -+#define p_cfoe_ifod_10_8 0xF40D -+#define cfoe_ifod_10_8_pos 0 -+#define cfoe_ifod_10_8_len 3 -+#define cfoe_ifod_10_8_lsb 8 -+#define p_cfoe_Divg_ctr_th 0xF40E -+#define cfoe_Divg_ctr_th_pos 0 -+#define cfoe_Divg_ctr_th_len 4 -+#define cfoe_Divg_ctr_th_lsb 0 -+#define p_cfoe_FOT_divg_th 0xF40F -+#define cfoe_FOT_divg_th_pos 0 -+#define cfoe_FOT_divg_th_len 8 -+#define cfoe_FOT_divg_th_lsb 0 -+#define p_cfoe_FOT_cnvg_th 0xF410 -+#define cfoe_FOT_cnvg_th_pos 0 -+#define cfoe_FOT_cnvg_th_len 8 -+#define cfoe_FOT_cnvg_th_lsb 0 -+#define p_reg_cfoe_offset_7_0 0xF411 -+#define reg_cfoe_offset_7_0_pos 0 -+#define reg_cfoe_offset_7_0_len 8 -+#define reg_cfoe_offset_7_0_lsb 0 -+#define p_reg_cfoe_offset_10_8 0xF412 -+#define reg_cfoe_offset_10_8_pos 0 -+#define reg_cfoe_offset_10_8_len 3 -+#define reg_cfoe_offset_10_8_lsb 8 -+#define p_reg_cfoe_ifoe_sign_corr 0xF413 -+#define reg_cfoe_ifoe_sign_corr_pos 0 -+#define reg_cfoe_ifoe_sign_corr_len 1 -+#define reg_cfoe_ifoe_sign_corr_lsb 0 -+#define p_cfoe_FOT_pullin_cnt_clr 0xF414 -+#define cfoe_FOT_pullin_cnt_clr_pos 0 -+#define cfoe_FOT_pullin_cnt_clr_len 1 -+#define cfoe_FOT_pullin_cnt_clr_lsb 0 -+#define p_cfoe_FOT_spec_inv 0xF415 -+#define cfoe_FOT_spec_inv_pos 0 -+#define cfoe_FOT_spec_inv_len 1 -+#define cfoe_FOT_spec_inv_lsb 0 -+#define p_cfoe_FOT_pullin_ctr_th 0xF416 -+#define cfoe_FOT_pullin_ctr_th_pos 0 -+#define cfoe_FOT_pullin_ctr_th_len 4 -+#define cfoe_FOT_pullin_ctr_th_lsb 0 -+#define p_cfoe_FOT_sf_ctr_th 0xF417 -+#define cfoe_FOT_sf_ctr_th_pos 0 -+#define cfoe_FOT_sf_ctr_th_len 4 -+#define cfoe_FOT_sf_ctr_th_lsb 0 -+#define p_cfoe_FOT_pullin_th 0xF418 -+#define cfoe_FOT_pullin_th_pos 0 -+#define cfoe_FOT_pullin_th_len 8 -+#define cfoe_FOT_pullin_th_lsb 0 -+#define p_cfoe_FOT_kalman_cnt 0xF419 -+#define cfoe_FOT_kalman_cnt_pos 0 -+#define cfoe_FOT_kalman_cnt_len 4 -+#define cfoe_FOT_kalman_cnt_lsb 0 -+#define p_cfoe_FOT_fsm_info 0xF41A -+#define cfoe_FOT_fsm_info_pos 0 -+#define cfoe_FOT_fsm_info_len 4 -+#define cfoe_FOT_fsm_info_lsb 0 -+#define r_cfoe_FOT_pullin_cnt 0xF41B -+#define cfoe_FOT_pullin_cnt_pos 0 -+#define cfoe_FOT_pullin_cnt_len 4 -+#define cfoe_FOT_pullin_cnt_lsb 0 -+#define r_cfoe_FOT_sf_cnt 0xF41C -+#define cfoe_FOT_sf_cnt_pos 0 -+#define cfoe_FOT_sf_cnt_len 4 -+#define cfoe_FOT_sf_cnt_lsb 0 -+#define r_reg_r_cfoe_ifoe_ifo_metric 0xF41D -+#define reg_r_cfoe_ifoe_ifo_metric_pos 0 -+#define reg_r_cfoe_ifoe_ifo_metric_len 8 -+#define reg_r_cfoe_ifoe_ifo_metric_lsb 0 -+#define r_reg_r_cfoe_ifoe_cos2num_7_0 0xF41E -+#define reg_r_cfoe_ifoe_cos2num_7_0_pos 0 -+#define reg_r_cfoe_ifoe_cos2num_7_0_len 8 -+#define reg_r_cfoe_ifoe_cos2num_7_0_lsb 0 -+#define r_reg_r_cfoe_ifoe_cos2num_15_8 0xF41F -+#define reg_r_cfoe_ifoe_cos2num_15_8_pos 0 -+#define reg_r_cfoe_ifoe_cos2num_15_8_len 8 -+#define reg_r_cfoe_ifoe_cos2num_15_8_lsb 8 -+#define r_reg_r_cfoe_ifoe_cos2num_19_16 0xF420 -+#define reg_r_cfoe_ifoe_cos2num_19_16_pos 0 -+#define reg_r_cfoe_ifoe_cos2num_19_16_len 4 -+#define reg_r_cfoe_ifoe_cos2num_19_16_lsb 16 -+#define p_ste_Nu 0xF460 -+#define ste_Nu_pos 0 -+#define ste_Nu_len 3 -+#define ste_Nu_lsb 0 -+#define p_ste_GI 0xF461 -+#define ste_GI_pos 0 -+#define ste_GI_len 3 -+#define ste_GI_lsb 0 -+#define p_ste_symbol_num 0xF463 -+#define ste_symbol_num_pos 0 -+#define ste_symbol_num_len 3 -+#define ste_symbol_num_lsb 0 -+#define p_ste_sample_num 0xF464 -+#define ste_sample_num_pos 0 -+#define ste_sample_num_len 2 -+#define ste_sample_num_lsb 0 -+#define p_ste_symbol_num_4K 0xF465 -+#define ste_symbol_num_4K_pos 0 -+#define ste_symbol_num_4K_len 3 -+#define ste_symbol_num_4K_lsb 0 -+#define p_ste_FFT_offset_7_0 0xF466 -+#define ste_FFT_offset_7_0_pos 0 -+#define ste_FFT_offset_7_0_len 8 -+#define ste_FFT_offset_7_0_lsb 0 -+#define p_ste_FFT_offset_13_8 0xF467 -+#define ste_FFT_offset_13_8_pos 0 -+#define ste_FFT_offset_13_8_len 6 -+#define ste_FFT_offset_13_8_lsb 8 -+#define p_ste_sample_num_4K 0xF468 -+#define ste_sample_num_4K_pos 0 -+#define ste_sample_num_4K_len 2 -+#define ste_sample_num_4K_lsb 0 -+#define p_ste_adv_start_7_0 0xF469 -+#define ste_adv_start_7_0_pos 0 -+#define ste_adv_start_7_0_len 8 -+#define ste_adv_start_7_0_lsb 0 -+#define p_ste_adv_start_10_8 0xF46A -+#define ste_adv_start_10_8_pos 0 -+#define ste_adv_start_10_8_len 3 -+#define ste_adv_start_10_8_lsb 8 -+#define p_ste_symbol_num_8K 0xF46B -+#define ste_symbol_num_8K_pos 0 -+#define ste_symbol_num_8K_len 3 -+#define ste_symbol_num_8K_lsb 0 -+#define p_ste_sample_num_8K 0xF46C -+#define ste_sample_num_8K_pos 0 -+#define ste_sample_num_8K_len 2 -+#define ste_sample_num_8K_lsb 0 -+#define p_ste_adv_stop 0xF46D -+#define ste_adv_stop_pos 0 -+#define ste_adv_stop_len 8 -+#define ste_adv_stop_lsb 0 -+#define r_ste_P_value_7_0 0xF46E -+#define ste_P_value_7_0_pos 0 -+#define ste_P_value_7_0_len 8 -+#define ste_P_value_7_0_lsb 0 -+#define r_ste_P_value_10_8 0xF46F -+#define ste_P_value_10_8_pos 0 -+#define ste_P_value_10_8_len 3 -+#define ste_P_value_10_8_lsb 8 -+#define p_reg_ste_tstmod 0xF470 -+#define reg_ste_tstmod_pos 0 -+#define reg_ste_tstmod_len 1 -+#define reg_ste_tstmod_lsb 0 -+#define p_reg_ste_buf_en 0xF471 -+#define reg_ste_buf_en_pos 0 -+#define reg_ste_buf_en_len 1 -+#define reg_ste_buf_en_lsb 0 -+#define r_ste_M_value_7_0 0xF472 -+#define ste_M_value_7_0_pos 0 -+#define ste_M_value_7_0_len 8 -+#define ste_M_value_7_0_lsb 0 -+#define r_ste_M_value_10_8 0xF473 -+#define ste_M_value_10_8_pos 0 -+#define ste_M_value_10_8_len 3 -+#define ste_M_value_10_8_lsb 8 -+#define r_ste_H1 0xF474 -+#define ste_H1_pos 0 -+#define ste_H1_len 7 -+#define ste_H1_lsb 0 -+#define r_ste_H2 0xF475 -+#define ste_H2_pos 0 -+#define ste_H2_len 7 -+#define ste_H2_lsb 0 -+#define r_ste_H3 0xF476 -+#define ste_H3_pos 0 -+#define ste_H3_len 7 -+#define ste_H3_lsb 0 -+#define r_ste_H4 0xF477 -+#define ste_H4_pos 0 -+#define ste_H4_len 7 -+#define ste_H4_lsb 0 -+#define r_ste_Corr_value_I_7_0 0xF478 -+#define ste_Corr_value_I_7_0_pos 0 -+#define ste_Corr_value_I_7_0_len 8 -+#define ste_Corr_value_I_7_0_lsb 0 -+#define r_ste_Corr_value_I_15_8 0xF479 -+#define ste_Corr_value_I_15_8_pos 0 -+#define ste_Corr_value_I_15_8_len 8 -+#define ste_Corr_value_I_15_8_lsb 8 -+#define r_ste_Corr_value_I_23_16 0xF47A -+#define ste_Corr_value_I_23_16_pos 0 -+#define ste_Corr_value_I_23_16_len 8 -+#define ste_Corr_value_I_23_16_lsb 16 -+#define r_ste_Corr_value_I_27_24 0xF47B -+#define ste_Corr_value_I_27_24_pos 0 -+#define ste_Corr_value_I_27_24_len 4 -+#define ste_Corr_value_I_27_24_lsb 24 -+#define r_ste_Corr_value_Q_7_0 0xF47C -+#define ste_Corr_value_Q_7_0_pos 0 -+#define ste_Corr_value_Q_7_0_len 8 -+#define ste_Corr_value_Q_7_0_lsb 0 -+#define r_ste_Corr_value_Q_15_8 0xF47D -+#define ste_Corr_value_Q_15_8_pos 0 -+#define ste_Corr_value_Q_15_8_len 8 -+#define ste_Corr_value_Q_15_8_lsb 8 -+#define r_ste_Corr_value_Q_23_16 0xF47E -+#define ste_Corr_value_Q_23_16_pos 0 -+#define ste_Corr_value_Q_23_16_len 8 -+#define ste_Corr_value_Q_23_16_lsb 16 -+#define r_ste_Corr_value_Q_27_24 0xF47F -+#define ste_Corr_value_Q_27_24_pos 0 -+#define ste_Corr_value_Q_27_24_len 4 -+#define ste_Corr_value_Q_27_24_lsb 24 -+#define r_ste_J_num_7_0 0xF480 -+#define ste_J_num_7_0_pos 0 -+#define ste_J_num_7_0_len 8 -+#define ste_J_num_7_0_lsb 0 -+#define r_ste_J_num_15_8 0xF481 -+#define ste_J_num_15_8_pos 0 -+#define ste_J_num_15_8_len 8 -+#define ste_J_num_15_8_lsb 8 -+#define r_ste_J_num_23_16 0xF482 -+#define ste_J_num_23_16_pos 0 -+#define ste_J_num_23_16_len 8 -+#define ste_J_num_23_16_lsb 16 -+#define r_ste_J_num_31_24 0xF483 -+#define ste_J_num_31_24_pos 0 -+#define ste_J_num_31_24_len 8 -+#define ste_J_num_31_24_lsb 24 -+#define r_ste_J_den_7_0 0xF484 -+#define ste_J_den_7_0_pos 0 -+#define ste_J_den_7_0_len 8 -+#define ste_J_den_7_0_lsb 0 -+#define r_ste_J_den_15_8 0xF485 -+#define ste_J_den_15_8_pos 0 -+#define ste_J_den_15_8_len 8 -+#define ste_J_den_15_8_lsb 8 -+#define r_ste_J_den_18_16 0xF486 -+#define ste_J_den_18_16_pos 0 -+#define ste_J_den_18_16_len 3 -+#define ste_J_den_18_16_lsb 16 -+#define r_ste_Beacon_Indicator 0xF488 -+#define ste_Beacon_Indicator_pos 0 -+#define ste_Beacon_Indicator_len 1 -+#define ste_Beacon_Indicator_lsb 0 -+#define p_ste_got_sntc_bcn 0xF48B -+#define ste_got_sntc_bcn_pos 0 -+#define ste_got_sntc_bcn_len 1 -+#define ste_got_sntc_bcn_lsb 0 -+#define r_tpsd_Frame_Num 0xF4C0 -+#define tpsd_Frame_Num_pos 0 -+#define tpsd_Frame_Num_len 2 -+#define tpsd_Frame_Num_lsb 0 -+#define r_tpsd_Constel 0xF4C1 -+#define tpsd_Constel_pos 0 -+#define tpsd_Constel_len 2 -+#define tpsd_Constel_lsb 0 -+#define r_tpsd_GI 0xF4C2 -+#define tpsd_GI_pos 0 -+#define tpsd_GI_len 2 -+#define tpsd_GI_lsb 0 -+#define r_tpsd_Mode 0xF4C3 -+#define tpsd_Mode_pos 0 -+#define tpsd_Mode_len 2 -+#define tpsd_Mode_lsb 0 -+#define r_tpsd_CR_HP 0xF4C4 -+#define tpsd_CR_HP_pos 0 -+#define tpsd_CR_HP_len 3 -+#define tpsd_CR_HP_lsb 0 -+#define r_tpsd_CR_LP 0xF4C5 -+#define tpsd_CR_LP_pos 0 -+#define tpsd_CR_LP_len 3 -+#define tpsd_CR_LP_lsb 0 -+#define r_tpsd_Hie 0xF4C6 -+#define tpsd_Hie_pos 0 -+#define tpsd_Hie_len 3 -+#define tpsd_Hie_lsb 0 -+#define r_tpsd_Res_Bits 0xF4C7 -+#define tpsd_Res_Bits_pos 0 -+#define tpsd_Res_Bits_len 5 -+#define tpsd_Res_Bits_lsb 0 -+#define r_tpsd_Res_Bits_0 0xF4C8 -+#define tpsd_Res_Bits_0_pos 0 -+#define tpsd_Res_Bits_0_len 1 -+#define tpsd_Res_Bits_0_lsb 0 -+#define r_tpsd_LengthInd 0xF4C9 -+#define tpsd_LengthInd_pos 0 -+#define tpsd_LengthInd_len 6 -+#define tpsd_LengthInd_lsb 0 -+#define r_tpsd_Cell_Id_7_0 0xF4CA -+#define tpsd_Cell_Id_7_0_pos 0 -+#define tpsd_Cell_Id_7_0_len 8 -+#define tpsd_Cell_Id_7_0_lsb 0 -+#define r_tpsd_Cell_Id_15_8 0xF4CB -+#define tpsd_Cell_Id_15_8_pos 0 -+#define tpsd_Cell_Id_15_8_len 8 -+#define tpsd_Cell_Id_15_8_lsb 0 -+#define r_tpsd_use_InDepthInt 0xF4CC -+#define tpsd_use_InDepthInt_pos 0 -+#define tpsd_use_InDepthInt_len 1 -+#define tpsd_use_InDepthInt_lsb 0 -+#define r_tpsd_use_TimeSlicing_HP 0xF4CD -+#define tpsd_use_TimeSlicing_HP_pos 0 -+#define tpsd_use_TimeSlicing_HP_len 1 -+#define tpsd_use_TimeSlicing_HP_lsb 0 -+#define r_tpsd_use_mpe_fec_HP 0xF4CE -+#define tpsd_use_mpe_fec_HP_pos 0 -+#define tpsd_use_mpe_fec_HP_len 1 -+#define tpsd_use_mpe_fec_HP_lsb 0 -+#define r_tpsd_use_TimeSlicing_LP 0xF4CF -+#define tpsd_use_TimeSlicing_LP_pos 0 -+#define tpsd_use_TimeSlicing_LP_len 1 -+#define tpsd_use_TimeSlicing_LP_lsb 0 -+#define r_tpsd_use_mpe_fec_LP 0xF4D0 -+#define tpsd_use_mpe_fec_LP_pos 0 -+#define tpsd_use_mpe_fec_LP_len 1 -+#define tpsd_use_mpe_fec_LP_lsb 0 -+#define r_tpsd_leng23_ind_return 0xF4D1 -+#define tpsd_leng23_ind_return_pos 0 -+#define tpsd_leng23_ind_return_len 1 -+#define tpsd_leng23_ind_return_lsb 0 -+#define p_reg_fft_re_exp 0xF500 -+#define reg_fft_re_exp_pos 0 -+#define reg_fft_re_exp_len 4 -+#define reg_fft_re_exp_lsb 0 -+#define p_reg_fft_re_mts 0xF501 -+#define reg_fft_re_mts_pos 0 -+#define reg_fft_re_mts_len 8 -+#define reg_fft_re_mts_lsb 0 -+#define p_reg_fft_im_exp 0xF502 -+#define reg_fft_im_exp_pos 0 -+#define reg_fft_im_exp_len 4 -+#define reg_fft_im_exp_lsb 0 -+#define p_reg_fft_im_mts 0xF503 -+#define reg_fft_im_mts_pos 0 -+#define reg_fft_im_mts_len 8 -+#define reg_fft_im_mts_lsb 0 -+#define p_reg_fft_conjugate 0xF504 -+#define reg_fft_conjugate_pos 0 -+#define reg_fft_conjugate_len 1 -+#define reg_fft_conjugate_lsb 0 -+#define p_reg_fft_power_en 0xF505 -+#define reg_fft_power_en_pos 0 -+#define reg_fft_power_en_len 1 -+#define reg_fft_power_en_lsb 0 -+#define p_reg_fft_power_factor 0xF506 -+#define reg_fft_power_factor_pos 0 -+#define reg_fft_power_factor_len 6 -+#define reg_fft_power_factor_lsb 0 -+#define p_reg_fft_power_in 0xF507 -+#define reg_fft_power_in_pos 0 -+#define reg_fft_power_in_len 8 -+#define reg_fft_power_in_lsb 0 -+#define p_reg_fft_mask_from0_7_0 0xF508 -+#define reg_fft_mask_from0_7_0_pos 0 -+#define reg_fft_mask_from0_7_0_len 8 -+#define reg_fft_mask_from0_7_0_lsb 0 -+#define p_reg_fft_mask_from0_12_8 0xF509 -+#define reg_fft_mask_from0_12_8_pos 0 -+#define reg_fft_mask_from0_12_8_len 5 -+#define reg_fft_mask_from0_12_8_lsb 8 -+#define p_reg_fft_mask_to0_7_0 0xF50A -+#define reg_fft_mask_to0_7_0_pos 0 -+#define reg_fft_mask_to0_7_0_len 8 -+#define reg_fft_mask_to0_7_0_lsb 0 -+#define p_reg_fft_mask_to0_12_8 0xF50B -+#define reg_fft_mask_to0_12_8_pos 0 -+#define reg_fft_mask_to0_12_8_len 5 -+#define reg_fft_mask_to0_12_8_lsb 8 -+#define p_reg_fft_mask_from1_7_0 0xF50C -+#define reg_fft_mask_from1_7_0_pos 0 -+#define reg_fft_mask_from1_7_0_len 8 -+#define reg_fft_mask_from1_7_0_lsb 0 -+#define p_reg_fft_mask_from1_12_8 0xF50D -+#define reg_fft_mask_from1_12_8_pos 0 -+#define reg_fft_mask_from1_12_8_len 5 -+#define reg_fft_mask_from1_12_8_lsb 8 -+#define p_reg_fft_mask_to1_7_0 0xF50E -+#define reg_fft_mask_to1_7_0_pos 0 -+#define reg_fft_mask_to1_7_0_len 8 -+#define reg_fft_mask_to1_7_0_lsb 0 -+#define p_reg_fft_mask_to1_12_8 0xF50F -+#define reg_fft_mask_to1_12_8_pos 0 -+#define reg_fft_mask_to1_12_8_len 5 -+#define reg_fft_mask_to1_12_8_lsb 8 -+#define p_reg_fft_mask_from2_7_0 0xF510 -+#define reg_fft_mask_from2_7_0_pos 0 -+#define reg_fft_mask_from2_7_0_len 8 -+#define reg_fft_mask_from2_7_0_lsb 0 -+#define p_reg_fft_mask_from2_12_8 0xF511 -+#define reg_fft_mask_from2_12_8_pos 0 -+#define reg_fft_mask_from2_12_8_len 5 -+#define reg_fft_mask_from2_12_8_lsb 8 -+#define p_reg_fft_mask_to2_7_0 0xF512 -+#define reg_fft_mask_to2_7_0_pos 0 -+#define reg_fft_mask_to2_7_0_len 8 -+#define reg_fft_mask_to2_7_0_lsb 0 -+#define p_reg_fft_mask_to2_12_8 0xF513 -+#define reg_fft_mask_to2_12_8_pos 0 -+#define reg_fft_mask_to2_12_8_len 5 -+#define reg_fft_mask_to2_12_8_lsb 8 -+#define p_reg_fft_mask_from3_7_0 0xF514 -+#define reg_fft_mask_from3_7_0_pos 0 -+#define reg_fft_mask_from3_7_0_len 8 -+#define reg_fft_mask_from3_7_0_lsb 0 -+#define p_reg_fft_mask_from3_12_8 0xF515 -+#define reg_fft_mask_from3_12_8_pos 0 -+#define reg_fft_mask_from3_12_8_len 5 -+#define reg_fft_mask_from3_12_8_lsb 8 -+#define p_reg_fft_mask_to3_7_0 0xF516 -+#define reg_fft_mask_to3_7_0_pos 0 -+#define reg_fft_mask_to3_7_0_len 8 -+#define reg_fft_mask_to3_7_0_lsb 0 -+#define p_reg_fft_mask_to3_12_8 0xF517 -+#define reg_fft_mask_to3_12_8_pos 0 -+#define reg_fft_mask_to3_12_8_len 5 -+#define reg_fft_mask_to3_12_8_lsb 8 -+#define r_fd_sntc_frame_num 0xF518 -+#define fd_sntc_frame_num_pos 0 -+#define fd_sntc_frame_num_len 2 -+#define fd_sntc_frame_num_lsb 0 -+#define r_fd_sntc_symbol_count 0xF519 -+#define fd_sntc_symbol_count_pos 0 -+#define fd_sntc_symbol_count_len 7 -+#define fd_sntc_symbol_count_lsb 0 -+#define p_reg_sntc_cnt_lo 0xF51A -+#define reg_sntc_cnt_lo_pos 0 -+#define reg_sntc_cnt_lo_len 8 -+#define reg_sntc_cnt_lo_lsb 0 -+#define p_reg_sntc_cnt_hi 0xF51B -+#define reg_sntc_cnt_hi_pos 0 -+#define reg_sntc_cnt_hi_len 7 -+#define reg_sntc_cnt_hi_lsb 0 -+#define p_reg_sntc_fft_in 0xF51C -+#define reg_sntc_fft_in_pos 0 -+#define reg_sntc_fft_in_len 1 -+#define reg_sntc_fft_in_lsb 0 -+#define r_fd_sntc_en 0xF51D -+#define fd_sntc_en_pos 0 -+#define fd_sntc_en_len 1 -+#define fd_sntc_en_lsb 0 -+#define p_reg_sntc_x2 0xF51E -+#define reg_sntc_x2_pos 0 -+#define reg_sntc_x2_len 1 -+#define reg_sntc_x2_lsb 0 -+#define p_reg_cge_en_7_0 0xF51F -+#define reg_cge_en_7_0_pos 0 -+#define reg_cge_en_7_0_len 8 -+#define reg_cge_en_7_0_lsb 0 -+#define p_reg_cge_en_15_8 0xF520 -+#define reg_cge_en_15_8_pos 0 -+#define reg_cge_en_15_8_len 8 -+#define reg_cge_en_15_8_lsb 8 -+#define p_reg_cge_en_23_16 0xF521 -+#define reg_cge_en_23_16_pos 0 -+#define reg_cge_en_23_16_len 8 -+#define reg_cge_en_23_16_lsb 16 -+#define p_reg_cge_en_31_24 0xF522 -+#define reg_cge_en_31_24_pos 0 -+#define reg_cge_en_31_24_len 8 -+#define reg_cge_en_31_24_lsb 24 -+#define p_reg_cge_en_39_32 0xF523 -+#define reg_cge_en_39_32_pos 0 -+#define reg_cge_en_39_32_len 8 -+#define reg_cge_en_39_32_lsb 32 -+#define p_reg_cge_en_43_40 0xF524 -+#define reg_cge_en_43_40_pos 0 -+#define reg_cge_en_43_40_len 4 -+#define reg_cge_en_43_40_lsb 40 -+#define p_reg_fft_sat_en 0xF525 -+#define reg_fft_sat_en_pos 0 -+#define reg_fft_sat_en_len 1 -+#define reg_fft_sat_en_lsb 0 -+#define p_reg_fft_sat_count_clr 0xF526 -+#define reg_fft_sat_count_clr_pos 0 -+#define reg_fft_sat_count_clr_len 1 -+#define reg_fft_sat_count_clr_lsb 0 -+#define p_reg_fft_rescale_round 0xF527 -+#define reg_fft_rescale_round_pos 0 -+#define reg_fft_rescale_round_len 1 -+#define reg_fft_rescale_round_lsb 0 -+#define r_reg_fft_sat_count_12_7_0 0xF528 -+#define reg_fft_sat_count_12_7_0_pos 0 -+#define reg_fft_sat_count_12_7_0_len 8 -+#define reg_fft_sat_count_12_7_0_lsb 0 -+#define r_reg_fft_sat_count_12_15_8 0xF529 -+#define reg_fft_sat_count_12_15_8_pos 0 -+#define reg_fft_sat_count_12_15_8_len 8 -+#define reg_fft_sat_count_12_15_8_lsb 8 -+#define r_reg_fft_sat_count_10_7_0 0xF52A -+#define reg_fft_sat_count_10_7_0_pos 0 -+#define reg_fft_sat_count_10_7_0_len 8 -+#define reg_fft_sat_count_10_7_0_lsb 0 -+#define r_reg_fft_sat_count_10_15_8 0xF52B -+#define reg_fft_sat_count_10_15_8_pos 0 -+#define reg_fft_sat_count_10_15_8_len 8 -+#define reg_fft_sat_count_10_15_8_lsb 8 -+#define p_reg_fft_capture_idx_7_0 0xF52C -+#define reg_fft_capture_idx_7_0_pos 0 -+#define reg_fft_capture_idx_7_0_len 8 -+#define reg_fft_capture_idx_7_0_lsb 0 -+#define p_reg_fft_capture_idx_12_8 0xF52D -+#define reg_fft_capture_idx_12_8_pos 0 -+#define reg_fft_capture_idx_12_8_len 5 -+#define reg_fft_capture_idx_12_8_lsb 8 -+#define p_reg_fft_capture 0xF52E -+#define reg_fft_capture_pos 0 -+#define reg_fft_capture_len 1 -+#define reg_fft_capture_lsb 0 -+#define p_reg_gp_trigger_fd 0xF52F -+#define reg_gp_trigger_fd_pos 0 -+#define reg_gp_trigger_fd_len 1 -+#define reg_gp_trigger_fd_lsb 0 -+#define p_reg_trigger_sel_fd 0xF530 -+#define reg_trigger_sel_fd_pos 0 -+#define reg_trigger_sel_fd_len 2 -+#define reg_trigger_sel_fd_lsb 0 -+#define p_reg_trigger_module_sel_fd 0xF531 -+#define reg_trigger_module_sel_fd_pos 0 -+#define reg_trigger_module_sel_fd_len 6 -+#define reg_trigger_module_sel_fd_lsb 0 -+#define p_reg_trigger_set_sel_fd 0xF532 -+#define reg_trigger_set_sel_fd_pos 0 -+#define reg_trigger_set_sel_fd_len 6 -+#define reg_trigger_set_sel_fd_lsb 0 -+#define r_reg_fft_idx_pre_max_7_0 0xF533 -+#define reg_fft_idx_pre_max_7_0_pos 0 -+#define reg_fft_idx_pre_max_7_0_len 8 -+#define reg_fft_idx_pre_max_7_0_lsb 0 -+#define r_reg_fft_idx_pre_max_12_8 0xF534 -+#define reg_fft_idx_pre_max_12_8_pos 0 -+#define reg_fft_idx_pre_max_12_8_len 5 -+#define reg_fft_idx_pre_max_12_8_lsb 8 -+#define r_reg_fft_crc 0xF535 -+#define reg_fft_crc_pos 0 -+#define reg_fft_crc_len 8 -+#define reg_fft_crc_lsb 0 -+#define p_fd_fft_shift_max 0xF536 -+#define fd_fft_shift_max_pos 0 -+#define fd_fft_shift_max_len 4 -+#define fd_fft_shift_max_lsb 0 -+#define p_fd_fft_frame_num 0xF537 -+#define fd_fft_frame_num_pos 0 -+#define fd_fft_frame_num_len 2 -+#define fd_fft_frame_num_lsb 0 -+#define p_fd_fft_symbol_count 0xF538 -+#define fd_fft_symbol_count_pos 0 -+#define fd_fft_symbol_count_len 7 -+#define fd_fft_symbol_count_lsb 0 -+#define r_reg_fft_idx_max_7_0 0xF539 -+#define reg_fft_idx_max_7_0_pos 0 -+#define reg_fft_idx_max_7_0_len 8 -+#define reg_fft_idx_max_7_0_lsb 0 -+#define r_reg_fft_idx_max_12_8 0xF53A -+#define reg_fft_idx_max_12_8_pos 0 -+#define reg_fft_idx_max_12_8_len 5 -+#define reg_fft_idx_max_12_8_lsb 8 -+#define p_reg_fft_rotate_en 0xF53B -+#define reg_fft_rotate_en_pos 0 -+#define reg_fft_rotate_en_len 1 -+#define reg_fft_rotate_en_lsb 0 -+#define p_reg_fft_rotate_base_7_0 0xF53C -+#define reg_fft_rotate_base_7_0_pos 0 -+#define reg_fft_rotate_base_7_0_len 8 -+#define reg_fft_rotate_base_7_0_lsb 0 -+#define p_reg_fft_rotate_base_12_8 0xF53D -+#define reg_fft_rotate_base_12_8_pos 0 -+#define reg_fft_rotate_base_12_8_len 5 -+#define reg_fft_rotate_base_12_8_lsb 8 -+#define r_fd_fpcc_cp_corr_signn 0xF53E -+#define fd_fpcc_cp_corr_signn_pos 0 -+#define fd_fpcc_cp_corr_signn_len 8 -+#define fd_fpcc_cp_corr_signn_lsb 0 -+#define p_reg_feq_s1 0xF53F -+#define reg_feq_s1_pos 0 -+#define reg_feq_s1_len 5 -+#define reg_feq_s1_lsb 0 -+#define p_reg_feq_sat_ind 0xF540 -+#define reg_feq_sat_ind_pos 0 -+#define reg_feq_sat_ind_len 3 -+#define reg_feq_sat_ind_lsb 0 -+#define p_reg_p_csi_cal_en 0xF541 -+#define reg_p_csi_cal_en_pos 0 -+#define reg_p_csi_cal_en_len 1 -+#define reg_p_csi_cal_en_lsb 0 -+#define p_reg_p_csi_ar_mode 0xF542 -+#define reg_p_csi_ar_mode_pos 0 -+#define reg_p_csi_ar_mode_len 2 -+#define reg_p_csi_ar_mode_lsb 0 -+#define p_reg_p_csi_accu_sym_num 0xF543 -+#define reg_p_csi_accu_sym_num_pos 0 -+#define reg_p_csi_accu_sym_num_len 8 -+#define reg_p_csi_accu_sym_num_lsb 0 -+#define p_reg_p_csi_eh2_shift_thr 0xF544 -+#define reg_p_csi_eh2_shift_thr_pos 0 -+#define reg_p_csi_eh2_shift_thr_len 4 -+#define reg_p_csi_eh2_shift_thr_lsb 0 -+#define p_reg_p_feq_protect_eh2_shift_thr 0xF545 -+#define reg_p_feq_protect_eh2_shift_thr_pos 0 -+#define reg_p_feq_protect_eh2_shift_thr_len 4 -+#define reg_p_feq_protect_eh2_shift_thr_lsb 0 -+#define p_reg_p_csi_error_accu_s1 0xF546 -+#define reg_p_csi_error_accu_s1_pos 0 -+#define reg_p_csi_error_accu_s1_len 6 -+#define reg_p_csi_error_accu_s1_lsb 0 -+#define p_reg_p_csi_shift2 0xF547 -+#define reg_p_csi_shift2_pos 0 -+#define reg_p_csi_shift2_len 4 -+#define reg_p_csi_shift2_lsb 0 -+#define p_reg_p_csi_mul2 0xF548 -+#define reg_p_csi_mul2_pos 0 -+#define reg_p_csi_mul2_len 8 -+#define reg_p_csi_mul2_lsb 0 -+#define p_reg_p_csi_level2_7_0 0xF549 -+#define reg_p_csi_level2_7_0_pos 0 -+#define reg_p_csi_level2_7_0_len 8 -+#define reg_p_csi_level2_7_0_lsb 0 -+#define p_reg_p_csi_level2_8 0xF54A -+#define reg_p_csi_level2_8_pos 0 -+#define reg_p_csi_level2_8_len 1 -+#define reg_p_csi_level2_8_lsb 8 -+#define p_reg_p_feq_protect_ratio 0xF54B -+#define reg_p_feq_protect_ratio_pos 0 -+#define reg_p_feq_protect_ratio_len 8 -+#define reg_p_feq_protect_ratio_lsb 0 -+#define r_reg_csi_rdy 0xF54C -+#define reg_csi_rdy_pos 0 -+#define reg_csi_rdy_len 1 -+#define reg_csi_rdy_lsb 0 -+#define p_reg_p_feq_h2protect_en 0xF54D -+#define reg_p_feq_h2protect_en_pos 0 -+#define reg_p_feq_h2protect_en_len 1 -+#define reg_p_feq_h2protect_en_lsb 0 -+#define r_reg_tpsd_lock_f0 0xF54E -+#define reg_tpsd_lock_f0_pos 0 -+#define reg_tpsd_lock_f0_len 1 -+#define reg_tpsd_lock_f0_lsb 0 -+#define r_reg_tpsd_lock_f1 0xF54F -+#define reg_tpsd_lock_f1_pos 0 -+#define reg_tpsd_lock_f1_len 1 -+#define reg_tpsd_lock_f1_lsb 0 -+#define p_reg_p_csi_sp_idx_7_0 0xF550 -+#define reg_p_csi_sp_idx_7_0_pos 0 -+#define reg_p_csi_sp_idx_7_0_len 8 -+#define reg_p_csi_sp_idx_7_0_lsb 0 -+#define p_reg_p_csi_sp_idx_11_8 0xF551 -+#define reg_p_csi_sp_idx_11_8_pos 0 -+#define reg_p_csi_sp_idx_11_8_len 4 -+#define reg_p_csi_sp_idx_11_8_lsb 8 -+#define p_fd_fpcc_cp_corr_tone_th 0xF552 -+#define fd_fpcc_cp_corr_tone_th_pos 0 -+#define fd_fpcc_cp_corr_tone_th_len 6 -+#define fd_fpcc_cp_corr_tone_th_lsb 0 -+#define p_fd_fpcc_cp_corr_symbol_log_th 0xF553 -+#define fd_fpcc_cp_corr_symbol_log_th_pos 0 -+#define fd_fpcc_cp_corr_symbol_log_th_len 4 -+#define fd_fpcc_cp_corr_symbol_log_th_lsb 0 -+#define p_fd_fpcc_cp_corr_int 0xF554 -+#define fd_fpcc_cp_corr_int_pos 0 -+#define fd_fpcc_cp_corr_int_len 1 -+#define fd_fpcc_cp_corr_int_lsb 0 -+#define p_reg_fpcc_cp_memidx 0xF555 -+#define reg_fpcc_cp_memidx_pos 0 -+#define reg_fpcc_cp_memidx_len 8 -+#define reg_fpcc_cp_memidx_lsb 0 -+#define p_reg_fpcc_cpmask_en 0xF556 -+#define reg_fpcc_cpmask_en_pos 0 -+#define reg_fpcc_cpmask_en_len 1 -+#define reg_fpcc_cpmask_en_lsb 0 -+#define p_reg_fpcc_cp_grpidx 0xF557 -+#define reg_fpcc_cp_grpidx_pos 0 -+#define reg_fpcc_cp_grpidx_len 5 -+#define reg_fpcc_cp_grpidx_lsb 0 -+#define r_reg_fpcc_cp_sts 0xF558 -+#define reg_fpcc_cp_sts_pos 0 -+#define reg_fpcc_cp_sts_len 1 -+#define reg_fpcc_cp_sts_lsb 0 -+#define p_reg_sfoe_ns_7_0 0xF559 -+#define reg_sfoe_ns_7_0_pos 0 -+#define reg_sfoe_ns_7_0_len 8 -+#define reg_sfoe_ns_7_0_lsb 0 -+#define p_reg_sfoe_ns_14_8 0xF55A -+#define reg_sfoe_ns_14_8_pos 0 -+#define reg_sfoe_ns_14_8_len 7 -+#define reg_sfoe_ns_14_8_lsb 8 -+#define p_reg_sfoe_c1_7_0 0xF55B -+#define reg_sfoe_c1_7_0_pos 0 -+#define reg_sfoe_c1_7_0_len 8 -+#define reg_sfoe_c1_7_0_lsb 0 -+#define p_reg_sfoe_c1_9_8 0xF55C -+#define reg_sfoe_c1_9_8_pos 0 -+#define reg_sfoe_c1_9_8_len 2 -+#define reg_sfoe_c1_9_8_lsb 8 -+#define p_reg_sfoe_c2_7_0 0xF55D -+#define reg_sfoe_c2_7_0_pos 0 -+#define reg_sfoe_c2_7_0_len 8 -+#define reg_sfoe_c2_7_0_lsb 0 -+#define p_reg_sfoe_c2_9_8 0xF55E -+#define reg_sfoe_c2_9_8_pos 0 -+#define reg_sfoe_c2_9_8_len 2 -+#define reg_sfoe_c2_9_8_lsb 8 -+#define p_reg_sfoe_lm_counter_th 0xF55F -+#define reg_sfoe_lm_counter_th_pos 0 -+#define reg_sfoe_lm_counter_th_len 4 -+#define reg_sfoe_lm_counter_th_lsb 0 -+#define p_reg_sfoe_spec_inv 0xF560 -+#define reg_sfoe_spec_inv_pos 0 -+#define reg_sfoe_spec_inv_len 1 -+#define reg_sfoe_spec_inv_lsb 0 -+#define p_reg_sfoe_convg_th 0xF561 -+#define reg_sfoe_convg_th_pos 0 -+#define reg_sfoe_convg_th_len 8 -+#define reg_sfoe_convg_th_lsb 0 -+#define p_reg_sfoe_divg_th 0xF562 -+#define reg_sfoe_divg_th_pos 0 -+#define reg_sfoe_divg_th_len 8 -+#define reg_sfoe_divg_th_lsb 0 -+#define p_reg_sfoe_pullin_ctr_th 0xF563 -+#define reg_sfoe_pullin_ctr_th_pos 0 -+#define reg_sfoe_pullin_ctr_th_len 4 -+#define reg_sfoe_pullin_ctr_th_lsb 0 -+#define p_reg_sfoe_sf_ctr_th 0xF564 -+#define reg_sfoe_sf_ctr_th_pos 0 -+#define reg_sfoe_sf_ctr_th_len 4 -+#define reg_sfoe_sf_ctr_th_lsb 0 -+#define p_reg_sfoe_pullin_th 0xF565 -+#define reg_sfoe_pullin_th_pos 0 -+#define reg_sfoe_pullin_th_len 8 -+#define reg_sfoe_pullin_th_lsb 0 -+#define p_reg_sfoe_kalman_cnt 0xF566 -+#define reg_sfoe_kalman_cnt_pos 0 -+#define reg_sfoe_kalman_cnt_len 4 -+#define reg_sfoe_kalman_cnt_lsb 0 -+#define p_reg_sfoe_fsm_info 0xF567 -+#define reg_sfoe_fsm_info_pos 0 -+#define reg_sfoe_fsm_info_len 4 -+#define reg_sfoe_fsm_info_lsb 0 -+#define r_reg_sfoe_pullin_cnt 0xF568 -+#define reg_sfoe_pullin_cnt_pos 0 -+#define reg_sfoe_pullin_cnt_len 4 -+#define reg_sfoe_pullin_cnt_lsb 0 -+#define r_reg_sfoe_sf_cnt 0xF569 -+#define reg_sfoe_sf_cnt_pos 0 -+#define reg_sfoe_sf_cnt_len 4 -+#define reg_sfoe_sf_cnt_lsb 0 -+#define p_reg_fste_phase_ini_7_0 0xF56A -+#define reg_fste_phase_ini_7_0_pos 0 -+#define reg_fste_phase_ini_7_0_len 8 -+#define reg_fste_phase_ini_7_0_lsb 0 -+#define p_reg_fste_phase_ini_11_8 0xF56B -+#define reg_fste_phase_ini_11_8_pos 0 -+#define reg_fste_phase_ini_11_8_len 4 -+#define reg_fste_phase_ini_11_8_lsb 8 -+#define p_reg_fste_phase_inc_7_0 0xF56C -+#define reg_fste_phase_inc_7_0_pos 0 -+#define reg_fste_phase_inc_7_0_len 8 -+#define reg_fste_phase_inc_7_0_lsb 0 -+#define p_reg_fste_phase_inc_11_8 0xF56D -+#define reg_fste_phase_inc_11_8_pos 0 -+#define reg_fste_phase_inc_11_8_len 4 -+#define reg_fste_phase_inc_11_8_lsb 8 -+#define p_reg_fste_acum_cost_cnt_max 0xF56E -+#define reg_fste_acum_cost_cnt_max_pos 0 -+#define reg_fste_acum_cost_cnt_max_len 4 -+#define reg_fste_acum_cost_cnt_max_lsb 0 -+#define p_reg_fste_step_size_std 0xF56F -+#define reg_fste_step_size_std_pos 0 -+#define reg_fste_step_size_std_len 4 -+#define reg_fste_step_size_std_lsb 0 -+#define p_reg_fste_step_size_max 0xF570 -+#define reg_fste_step_size_max_pos 0 -+#define reg_fste_step_size_max_len 4 -+#define reg_fste_step_size_max_lsb 0 -+#define p_reg_fste_rpd_dir_cnt_max 0xF571 -+#define reg_fste_rpd_dir_cnt_max_pos 0 -+#define reg_fste_rpd_dir_cnt_max_len 4 -+#define reg_fste_rpd_dir_cnt_max_lsb 0 -+#define p_reg_fste_frac_cost_cnt_max_7_0 0xF572 -+#define reg_fste_frac_cost_cnt_max_7_0_pos 0 -+#define reg_fste_frac_cost_cnt_max_7_0_len 8 -+#define reg_fste_frac_cost_cnt_max_7_0_lsb 0 -+#define p_reg_fste_frac_cost_cnt_max_9_8 0xF573 -+#define reg_fste_frac_cost_cnt_max_9_8_pos 0 -+#define reg_fste_frac_cost_cnt_max_9_8_len 2 -+#define reg_fste_frac_cost_cnt_max_9_8_lsb 8 -+#define p_reg_fste_isLongWeakTail 0xF574 -+#define reg_fste_isLongWeakTail_pos 0 -+#define reg_fste_isLongWeakTail_len 1 -+#define reg_fste_isLongWeakTail_lsb 0 -+#define p_reg_fste_isLongWeakHead 0xF575 -+#define reg_fste_isLongWeakHead_pos 0 -+#define reg_fste_isLongWeakHead_len 1 -+#define reg_fste_isLongWeakHead_lsb 0 -+#define p_reg_fste_w0_7_0 0xF576 -+#define reg_fste_w0_7_0_pos 0 -+#define reg_fste_w0_7_0_len 8 -+#define reg_fste_w0_7_0_lsb 0 -+#define p_reg_fste_w0_9_8 0xF577 -+#define reg_fste_w0_9_8_pos 0 -+#define reg_fste_w0_9_8_len 2 -+#define reg_fste_w0_9_8_lsb 8 -+#define p_reg_fste_w1_7_0 0xF578 -+#define reg_fste_w1_7_0_pos 0 -+#define reg_fste_w1_7_0_len 8 -+#define reg_fste_w1_7_0_lsb 0 -+#define p_reg_fste_w1_9_8 0xF579 -+#define reg_fste_w1_9_8_pos 0 -+#define reg_fste_w1_9_8_len 2 -+#define reg_fste_w1_9_8_lsb 8 -+#define p_reg_fste_w2_7_0 0xF57A -+#define reg_fste_w2_7_0_pos 0 -+#define reg_fste_w2_7_0_len 8 -+#define reg_fste_w2_7_0_lsb 0 -+#define p_reg_fste_w2_9_8 0xF57B -+#define reg_fste_w2_9_8_pos 0 -+#define reg_fste_w2_9_8_len 2 -+#define reg_fste_w2_9_8_lsb 8 -+#define p_reg_fste_w3_7_0 0xF57C -+#define reg_fste_w3_7_0_pos 0 -+#define reg_fste_w3_7_0_len 8 -+#define reg_fste_w3_7_0_lsb 0 -+#define p_reg_fste_w3_9_8 0xF57D -+#define reg_fste_w3_9_8_pos 0 -+#define reg_fste_w3_9_8_len 2 -+#define reg_fste_w3_9_8_lsb 8 -+#define p_reg_fste_w4_7_0 0xF57E -+#define reg_fste_w4_7_0_pos 0 -+#define reg_fste_w4_7_0_len 8 -+#define reg_fste_w4_7_0_lsb 0 -+#define p_reg_fste_w4_9_8 0xF57F -+#define reg_fste_w4_9_8_pos 0 -+#define reg_fste_w4_9_8_len 2 -+#define reg_fste_w4_9_8_lsb 8 -+#define p_reg_fste_w5_7_0 0xF580 -+#define reg_fste_w5_7_0_pos 0 -+#define reg_fste_w5_7_0_len 8 -+#define reg_fste_w5_7_0_lsb 0 -+#define p_reg_fste_w5_9_8 0xF581 -+#define reg_fste_w5_9_8_pos 0 -+#define reg_fste_w5_9_8_len 2 -+#define reg_fste_w5_9_8_lsb 8 -+#define p_reg_fste_w6_7_0 0xF582 -+#define reg_fste_w6_7_0_pos 0 -+#define reg_fste_w6_7_0_len 8 -+#define reg_fste_w6_7_0_lsb 0 -+#define p_reg_fste_w6_9_8 0xF583 -+#define reg_fste_w6_9_8_pos 0 -+#define reg_fste_w6_9_8_len 2 -+#define reg_fste_w6_9_8_lsb 8 -+#define p_reg_fste_w7_7_0 0xF584 -+#define reg_fste_w7_7_0_pos 0 -+#define reg_fste_w7_7_0_len 8 -+#define reg_fste_w7_7_0_lsb 0 -+#define p_reg_fste_w7_9_8 0xF585 -+#define reg_fste_w7_9_8_pos 0 -+#define reg_fste_w7_9_8_len 2 -+#define reg_fste_w7_9_8_lsb 8 -+#define p_reg_fste_w8_7_0 0xF586 -+#define reg_fste_w8_7_0_pos 0 -+#define reg_fste_w8_7_0_len 8 -+#define reg_fste_w8_7_0_lsb 0 -+#define p_reg_fste_w8_9_8 0xF587 -+#define reg_fste_w8_9_8_pos 0 -+#define reg_fste_w8_9_8_len 2 -+#define reg_fste_w8_9_8_lsb 8 -+#define p_reg_fste_w9_7_0 0xF588 -+#define reg_fste_w9_7_0_pos 0 -+#define reg_fste_w9_7_0_len 8 -+#define reg_fste_w9_7_0_lsb 0 -+#define p_reg_fste_w9_9_8 0xF589 -+#define reg_fste_w9_9_8_pos 0 -+#define reg_fste_w9_9_8_len 2 -+#define reg_fste_w9_9_8_lsb 8 -+#define p_reg_fste_wa_7_0 0xF58A -+#define reg_fste_wa_7_0_pos 0 -+#define reg_fste_wa_7_0_len 8 -+#define reg_fste_wa_7_0_lsb 0 -+#define p_reg_fste_wa_9_8 0xF58B -+#define reg_fste_wa_9_8_pos 0 -+#define reg_fste_wa_9_8_len 2 -+#define reg_fste_wa_9_8_lsb 8 -+#define p_reg_fste_wb_7_0 0xF58C -+#define reg_fste_wb_7_0_pos 0 -+#define reg_fste_wb_7_0_len 8 -+#define reg_fste_wb_7_0_lsb 0 -+#define p_reg_fste_wb_9_8 0xF58D -+#define reg_fste_wb_9_8_pos 0 -+#define reg_fste_wb_9_8_len 2 -+#define reg_fste_wb_9_8_lsb 8 -+#define p_reg_fste_wc_7_0 0xF58E -+#define reg_fste_wc_7_0_pos 0 -+#define reg_fste_wc_7_0_len 8 -+#define reg_fste_wc_7_0_lsb 0 -+#define p_reg_fste_wc_9_8 0xF58F -+#define reg_fste_wc_9_8_pos 0 -+#define reg_fste_wc_9_8_len 2 -+#define reg_fste_wc_9_8_lsb 8 -+#define p_reg_fste_wd_7_0 0xF590 -+#define reg_fste_wd_7_0_pos 0 -+#define reg_fste_wd_7_0_len 8 -+#define reg_fste_wd_7_0_lsb 0 -+#define p_reg_fste_wd_9_8 0xF591 -+#define reg_fste_wd_9_8_pos 0 -+#define reg_fste_wd_9_8_len 2 -+#define reg_fste_wd_9_8_lsb 8 -+#define p_reg_fste_we_7_0 0xF592 -+#define reg_fste_we_7_0_pos 0 -+#define reg_fste_we_7_0_len 8 -+#define reg_fste_we_7_0_lsb 0 -+#define p_reg_fste_we_9_8 0xF593 -+#define reg_fste_we_9_8_pos 0 -+#define reg_fste_we_9_8_len 2 -+#define reg_fste_we_9_8_lsb 8 -+#define p_reg_fste_wf_7_0 0xF594 -+#define reg_fste_wf_7_0_pos 0 -+#define reg_fste_wf_7_0_len 8 -+#define reg_fste_wf_7_0_lsb 0 -+#define p_reg_fste_wf_9_8 0xF595 -+#define reg_fste_wf_9_8_pos 0 -+#define reg_fste_wf_9_8_len 2 -+#define reg_fste_wf_9_8_lsb 8 -+#define p_reg_fste_wg_7_0 0xF596 -+#define reg_fste_wg_7_0_pos 0 -+#define reg_fste_wg_7_0_len 8 -+#define reg_fste_wg_7_0_lsb 0 -+#define p_reg_fste_wg_9_8 0xF597 -+#define reg_fste_wg_9_8_pos 0 -+#define reg_fste_wg_9_8_len 2 -+#define reg_fste_wg_9_8_lsb 8 -+#define p_reg_fste_wh_7_0 0xF598 -+#define reg_fste_wh_7_0_pos 0 -+#define reg_fste_wh_7_0_len 8 -+#define reg_fste_wh_7_0_lsb 0 -+#define p_reg_fste_wh_9_8 0xF599 -+#define reg_fste_wh_9_8_pos 0 -+#define reg_fste_wh_9_8_len 2 -+#define reg_fste_wh_9_8_lsb 8 -+#define r_fd_fste_i_adj_org 0xF59A -+#define fd_fste_i_adj_org_pos 0 -+#define fd_fste_i_adj_org_len 5 -+#define fd_fste_i_adj_org_lsb 0 -+#define r_fd_fste_f_adj_7_0 0xF59B -+#define fd_fste_f_adj_7_0_pos 0 -+#define fd_fste_f_adj_7_0_len 8 -+#define fd_fste_f_adj_7_0_lsb 0 -+#define r_fd_fste_f_adj_15_8 0xF59C -+#define fd_fste_f_adj_15_8_pos 0 -+#define fd_fste_f_adj_15_8_len 8 -+#define fd_fste_f_adj_15_8_lsb 8 -+#define r_fd_fste_f_adj_19_16 0xF59D -+#define fd_fste_f_adj_19_16_pos 0 -+#define fd_fste_f_adj_19_16_len 4 -+#define fd_fste_f_adj_19_16_lsb 16 -+#define p_reg_fste_ehw_7_0 0xF59E -+#define reg_fste_ehw_7_0_pos 0 -+#define reg_fste_ehw_7_0_len 8 -+#define reg_fste_ehw_7_0_lsb 0 -+#define p_reg_fste_ehw_12_8 0xF59F -+#define reg_fste_ehw_12_8_pos 0 -+#define reg_fste_ehw_12_8_len 5 -+#define reg_fste_ehw_12_8_lsb 8 -+#define p_reg_fste_i_adj_vld 0xF5A0 -+#define reg_fste_i_adj_vld_pos 0 -+#define reg_fste_i_adj_vld_len 1 -+#define reg_fste_i_adj_vld_lsb 0 -+#define p_reg_fste_ceTimesPhasor_real 0xF5A1 -+#define reg_fste_ceTimesPhasor_real_pos 0 -+#define reg_fste_ceTimesPhasor_real_len 1 -+#define reg_fste_ceTimesPhasor_real_lsb 0 -+#define p_reg_fste_ceTimesPhasor_imag 0xF5A2 -+#define reg_fste_ceTimesPhasor_imag_pos 0 -+#define reg_fste_ceTimesPhasor_imag_len 1 -+#define reg_fste_ceTimesPhasor_imag_lsb 0 -+#define p_reg_fste_cerTimesW_real 0xF5A3 -+#define reg_fste_cerTimesW_real_pos 0 -+#define reg_fste_cerTimesW_real_len 1 -+#define reg_fste_cerTimesW_real_lsb 0 -+#define p_reg_fste_cerTimesW_imag 0xF5A4 -+#define reg_fste_cerTimesW_imag_pos 0 -+#define reg_fste_cerTimesW_imag_len 1 -+#define reg_fste_cerTimesW_imag_lsb 0 -+#define p_reg_fste_cerTimesWAccum_real 0xF5A5 -+#define reg_fste_cerTimesWAccum_real_pos 0 -+#define reg_fste_cerTimesWAccum_real_len 1 -+#define reg_fste_cerTimesWAccum_real_lsb 0 -+#define p_reg_fste_cerTimesWAccum_imag 0xF5A6 -+#define reg_fste_cerTimesWAccum_imag_pos 0 -+#define reg_fste_cerTimesWAccum_imag_len 1 -+#define reg_fste_cerTimesWAccum_imag_lsb 0 -+#define p_reg_fste_cost 0xF5A7 -+#define reg_fste_cost_pos 0 -+#define reg_fste_cost_len 1 -+#define reg_fste_cost_lsb 0 -+#define p_fd_tpsd_en 0xF5A8 -+#define fd_tpsd_en_pos 0 -+#define fd_tpsd_en_len 1 -+#define fd_tpsd_en_lsb 0 -+#define p_fd_tpsd_lock 0xF5A9 -+#define fd_tpsd_lock_pos 0 -+#define fd_tpsd_lock_len 1 -+#define fd_tpsd_lock_lsb 0 -+#define r_fd_tpsd_s19 0xF5AA -+#define fd_tpsd_s19_pos 0 -+#define fd_tpsd_s19_len 1 -+#define fd_tpsd_s19_lsb 0 -+#define r_fd_tpsd_s17 0xF5AB -+#define fd_tpsd_s17_pos 0 -+#define fd_tpsd_s17_len 1 -+#define fd_tpsd_s17_lsb 0 -+#define p_fd_sfr_ste_en 0xF5AC -+#define fd_sfr_ste_en_pos 0 -+#define fd_sfr_ste_en_len 1 -+#define fd_sfr_ste_en_lsb 0 -+#define p_fd_sfr_ste_mode 0xF5AD -+#define fd_sfr_ste_mode_pos 0 -+#define fd_sfr_ste_mode_len 2 -+#define fd_sfr_ste_mode_lsb 0 -+#define p_fd_sfr_ste_done 0xF5AE -+#define fd_sfr_ste_done_pos 0 -+#define fd_sfr_ste_done_len 1 -+#define fd_sfr_ste_done_lsb 0 -+#define p_reg_cfoe_ffoe_en 0xF5AF -+#define reg_cfoe_ffoe_en_pos 0 -+#define reg_cfoe_ffoe_en_len 1 -+#define reg_cfoe_ffoe_en_lsb 0 -+#define p_reg_cfoe_ifoe_en 0xF5B0 -+#define reg_cfoe_ifoe_en_pos 0 -+#define reg_cfoe_ifoe_en_len 1 -+#define reg_cfoe_ifoe_en_lsb 0 -+#define p_reg_cfoe_fot_en 0xF5B1 -+#define reg_cfoe_fot_en_pos 0 -+#define reg_cfoe_fot_en_len 1 -+#define reg_cfoe_fot_en_lsb 0 -+#define p_reg_cfoe_fot_lm_en 0xF5B2 -+#define reg_cfoe_fot_lm_en_pos 0 -+#define reg_cfoe_fot_lm_en_len 1 -+#define reg_cfoe_fot_lm_en_lsb 0 -+#define p_reg_cfoe_fot_rst 0xF5B3 -+#define reg_cfoe_fot_rst_pos 0 -+#define reg_cfoe_fot_rst_len 1 -+#define reg_cfoe_fot_rst_lsb 0 -+#define r_fd_cfoe_ffoe_done 0xF5B4 -+#define fd_cfoe_ffoe_done_pos 0 -+#define fd_cfoe_ffoe_done_len 1 -+#define fd_cfoe_ffoe_done_lsb 0 -+#define p_fd_cfoe_metric_vld 0xF5B5 -+#define fd_cfoe_metric_vld_pos 0 -+#define fd_cfoe_metric_vld_len 1 -+#define fd_cfoe_metric_vld_lsb 0 -+#define p_reg_cfoe_ifod_vld 0xF5B6 -+#define reg_cfoe_ifod_vld_pos 0 -+#define reg_cfoe_ifod_vld_len 1 -+#define reg_cfoe_ifod_vld_lsb 0 -+#define r_fd_cfoe_ifoe_done 0xF5B7 -+#define fd_cfoe_ifoe_done_pos 0 -+#define fd_cfoe_ifoe_done_len 1 -+#define fd_cfoe_ifoe_done_lsb 0 -+#define p_reg_cfoe_ifoe_spec_inv 0xF5B8 -+#define reg_cfoe_ifoe_spec_inv_pos 0 -+#define reg_cfoe_ifoe_spec_inv_len 1 -+#define reg_cfoe_ifoe_spec_inv_lsb 0 -+#define p_reg_cfoe_divg_int 0xF5B9 -+#define reg_cfoe_divg_int_pos 0 -+#define reg_cfoe_divg_int_len 1 -+#define reg_cfoe_divg_int_lsb 0 -+#define r_reg_cfoe_divg_flag 0xF5BA -+#define reg_cfoe_divg_flag_pos 0 -+#define reg_cfoe_divg_flag_len 1 -+#define reg_cfoe_divg_flag_lsb 0 -+#define p_reg_sfoe_en 0xF5BB -+#define reg_sfoe_en_pos 0 -+#define reg_sfoe_en_len 1 -+#define reg_sfoe_en_lsb 0 -+#define p_reg_sfoe_dis 0xF5BC -+#define reg_sfoe_dis_pos 0 -+#define reg_sfoe_dis_len 1 -+#define reg_sfoe_dis_lsb 0 -+#define p_reg_sfoe_rst 0xF5BD -+#define reg_sfoe_rst_pos 0 -+#define reg_sfoe_rst_len 1 -+#define reg_sfoe_rst_lsb 0 -+#define p_reg_sfoe_vld_int 0xF5BE -+#define reg_sfoe_vld_int_pos 0 -+#define reg_sfoe_vld_int_len 1 -+#define reg_sfoe_vld_int_lsb 0 -+#define p_reg_sfoe_lm_en 0xF5BF -+#define reg_sfoe_lm_en_pos 0 -+#define reg_sfoe_lm_en_len 1 -+#define reg_sfoe_lm_en_lsb 0 -+#define p_reg_sfoe_divg_int 0xF5C0 -+#define reg_sfoe_divg_int_pos 0 -+#define reg_sfoe_divg_int_len 1 -+#define reg_sfoe_divg_int_lsb 0 -+#define r_reg_sfoe_divg_flag 0xF5C1 -+#define reg_sfoe_divg_flag_pos 0 -+#define reg_sfoe_divg_flag_len 1 -+#define reg_sfoe_divg_flag_lsb 0 -+#define p_reg_fft_rst 0xF5C2 -+#define reg_fft_rst_pos 0 -+#define reg_fft_rst_len 1 -+#define reg_fft_rst_lsb 0 -+#define p_reg_fft_mask2_en 0xF5C3 -+#define reg_fft_mask2_en_pos 0 -+#define reg_fft_mask2_en_len 1 -+#define reg_fft_mask2_en_lsb 0 -+#define p_reg_fft_mask3_en 0xF5C4 -+#define reg_fft_mask3_en_pos 0 -+#define reg_fft_mask3_en_len 1 -+#define reg_fft_mask3_en_lsb 0 -+#define p_reg_fft_crc_en 0xF5C5 -+#define reg_fft_crc_en_pos 0 -+#define reg_fft_crc_en_len 1 -+#define reg_fft_crc_en_lsb 0 -+#define p_reg_fft_mask0_en 0xF5C6 -+#define reg_fft_mask0_en_pos 0 -+#define reg_fft_mask0_en_len 1 -+#define reg_fft_mask0_en_lsb 0 -+#define p_reg_fft_mask1_en 0xF5C7 -+#define reg_fft_mask1_en_pos 0 -+#define reg_fft_mask1_en_len 1 -+#define reg_fft_mask1_en_lsb 0 -+#define p_fd_fste_en 0xF5C8 -+#define fd_fste_en_pos 0 -+#define fd_fste_en_len 1 -+#define fd_fste_en_lsb 0 -+#define p_reg_feq_eh2_comp_en 0xF5C9 -+#define reg_feq_eh2_comp_en_pos 0 -+#define reg_feq_eh2_comp_en_len 1 -+#define reg_feq_eh2_comp_en_lsb 0 -+#define p_reg_feq_read_update 0xF5CA -+#define reg_feq_read_update_pos 0 -+#define reg_feq_read_update_len 1 -+#define reg_feq_read_update_lsb 0 -+#define p_reg_feq_data_vld 0xF5CB -+#define reg_feq_data_vld_pos 0 -+#define reg_feq_data_vld_len 1 -+#define reg_feq_data_vld_lsb 0 -+#define p_reg_feq_tone_idx_7_0 0xF5CC -+#define reg_feq_tone_idx_7_0_pos 0 -+#define reg_feq_tone_idx_7_0_len 8 -+#define reg_feq_tone_idx_7_0_lsb 0 -+#define p_reg_feq_tone_idx_12_8 0xF5CD -+#define reg_feq_tone_idx_12_8_pos 0 -+#define reg_feq_tone_idx_12_8_len 5 -+#define reg_feq_tone_idx_12_8_lsb 8 -+#define r_reg_feq_data_re_7_0 0xF5CE -+#define reg_feq_data_re_7_0_pos 0 -+#define reg_feq_data_re_7_0_len 8 -+#define reg_feq_data_re_7_0_lsb 0 -+#define r_reg_feq_data_re_15_8 0xF5CF -+#define reg_feq_data_re_15_8_pos 0 -+#define reg_feq_data_re_15_8_len 8 -+#define reg_feq_data_re_15_8_lsb 8 -+#define r_reg_feq_data_re_21_16 0xF5D0 -+#define reg_feq_data_re_21_16_pos 0 -+#define reg_feq_data_re_21_16_len 6 -+#define reg_feq_data_re_21_16_lsb 16 -+#define r_reg_feq_data_im_7_0 0xF5D1 -+#define reg_feq_data_im_7_0_pos 0 -+#define reg_feq_data_im_7_0_len 8 -+#define reg_feq_data_im_7_0_lsb 0 -+#define r_reg_feq_data_im_15_8 0xF5D2 -+#define reg_feq_data_im_15_8_pos 0 -+#define reg_feq_data_im_15_8_len 8 -+#define reg_feq_data_im_15_8_lsb 8 -+#define r_reg_feq_data_im_21_16 0xF5D3 -+#define reg_feq_data_im_21_16_pos 0 -+#define reg_feq_data_im_21_16_len 6 -+#define reg_feq_data_im_21_16_lsb 16 -+#define r_reg_feq_data_h2_7_0 0xF5D4 -+#define reg_feq_data_h2_7_0_pos 0 -+#define reg_feq_data_h2_7_0_len 8 -+#define reg_feq_data_h2_7_0_lsb 0 -+#define r_reg_feq_data_h2_15_8 0xF5D5 -+#define reg_feq_data_h2_15_8_pos 0 -+#define reg_feq_data_h2_15_8_len 8 -+#define reg_feq_data_h2_15_8_lsb 8 -+#define r_reg_feq_data_h2_18_16 0xF5D6 -+#define reg_feq_data_h2_18_16_pos 0 -+#define reg_feq_data_h2_18_16_len 3 -+#define reg_feq_data_h2_18_16_lsb 16 -+#define p_reg_fs_en 0xF5D7 -+#define reg_fs_en_pos 0 -+#define reg_fs_en_len 1 -+#define reg_fs_en_lsb 0 -+#define p_reg_fs_offset 0xF5D8 -+#define reg_fs_offset_pos 0 -+#define reg_fs_offset_len 3 -+#define reg_fs_offset_lsb 0 -+#define p_reg_fs_debug 0xF5D9 -+#define reg_fs_debug_pos 0 -+#define reg_fs_debug_len 1 -+#define reg_fs_debug_lsb 0 -+#define p_reg_fs_half_inv 0xF5DA -+#define reg_fs_half_inv_pos 0 -+#define reg_fs_half_inv_len 1 -+#define reg_fs_half_inv_lsb 0 -+#define p_reg_cdpf_currentfftposition_7_0 0xF5DB -+#define reg_cdpf_currentfftposition_7_0_pos 0 -+#define reg_cdpf_currentfftposition_7_0_len 8 -+#define reg_cdpf_currentfftposition_7_0_lsb 0 -+#define p_reg_cdpf_currentfftposition_14_8 0xF5DC -+#define reg_cdpf_currentfftposition_14_8_pos 0 -+#define reg_cdpf_currentfftposition_14_8_len 7 -+#define reg_cdpf_currentfftposition_14_8_lsb 8 -+#define r_reg_cdpf_fftshift_7_0 0xF5DD -+#define reg_cdpf_fftshift_7_0_pos 0 -+#define reg_cdpf_fftshift_7_0_len 8 -+#define reg_cdpf_fftshift_7_0_lsb 0 -+#define r_reg_cdpf_fftshift_13_8 0xF5DE -+#define reg_cdpf_fftshift_13_8_pos 0 -+#define reg_cdpf_fftshift_13_8_len 6 -+#define reg_cdpf_fftshift_13_8_lsb 8 -+#define p_reg_cdpf_channelpowerdown_7_0 0xF5DF -+#define reg_cdpf_channelpowerdown_7_0_pos 0 -+#define reg_cdpf_channelpowerdown_7_0_len 8 -+#define reg_cdpf_channelpowerdown_7_0_lsb 0 -+#define p_reg_cdpf_channelpowerdown_10_8 0xF5E0 -+#define reg_cdpf_channelpowerdown_10_8_pos 0 -+#define reg_cdpf_channelpowerdown_10_8_len 3 -+#define reg_cdpf_channelpowerdown_10_8_lsb 8 -+#define p_reg_cdpf_state 0xF5E1 -+#define reg_cdpf_state_pos 0 -+#define reg_cdpf_state_len 4 -+#define reg_cdpf_state_lsb 0 -+#define p_reg_cdpf_echotestsearchingrange 0xF5E2 -+#define reg_cdpf_echotestsearchingrange_pos 0 -+#define reg_cdpf_echotestsearchingrange_len 8 -+#define reg_cdpf_echotestsearchingrange_lsb 0 -+#define p_reg_cdpf_rxsymboldelay 0xF5E3 -+#define reg_cdpf_rxsymboldelay_pos 0 -+#define reg_cdpf_rxsymboldelay_len 4 -+#define reg_cdpf_rxsymboldelay_lsb 0 -+#define p_reg_cdpf_ceavesymbolno 0xF5E4 -+#define reg_cdpf_ceavesymbolno_pos 0 -+#define reg_cdpf_ceavesymbolno_len 4 -+#define reg_cdpf_ceavesymbolno_lsb 0 -+#define p_reg_cdpf_ceshift 0xF5E5 -+#define reg_cdpf_ceshift_pos 0 -+#define reg_cdpf_ceshift_len 3 -+#define reg_cdpf_ceshift_lsb 0 -+#define p_reg_cdpf_postpreechotry 0xF5E6 -+#define reg_cdpf_postpreechotry_pos 0 -+#define reg_cdpf_postpreechotry_len 2 -+#define reg_cdpf_postpreechotry_lsb 0 -+#define p_reg_cdpf_en 0xF5E7 -+#define reg_cdpf_en_pos 0 -+#define reg_cdpf_en_len 1 -+#define reg_cdpf_en_lsb 0 -+#define p_reg_cdpf_stateready 0xF5E8 -+#define reg_cdpf_stateready_pos 0 -+#define reg_cdpf_stateready_len 1 -+#define reg_cdpf_stateready_lsb 0 -+#define r_reg_cdpf_prepostpowercompare 0xF5E9 -+#define reg_cdpf_prepostpowercompare_pos 0 -+#define reg_cdpf_prepostpowercompare_len 1 -+#define reg_cdpf_prepostpowercompare_lsb 0 -+#define r_reg_cdpf_candidateno 0xF5EA -+#define reg_cdpf_candidateno_pos 0 -+#define reg_cdpf_candidateno_len 6 -+#define reg_cdpf_candidateno_lsb 0 -+#define p_reg_cdpf_preechopower_7_0 0xF5EB -+#define reg_cdpf_preechopower_7_0_pos 0 -+#define reg_cdpf_preechopower_7_0_len 8 -+#define reg_cdpf_preechopower_7_0_lsb 0 -+#define p_reg_cdpf_preechopower_15_8 0xF5EC -+#define reg_cdpf_preechopower_15_8_pos 0 -+#define reg_cdpf_preechopower_15_8_len 8 -+#define reg_cdpf_preechopower_15_8_lsb 8 -+#define p_reg_cdpf_postechopower_7_0 0xF5ED -+#define reg_cdpf_postechopower_7_0_pos 0 -+#define reg_cdpf_postechopower_7_0_len 8 -+#define reg_cdpf_postechopower_7_0_lsb 0 -+#define p_reg_cdpf_postechopower_15_8 0xF5EE -+#define reg_cdpf_postechopower_15_8_pos 0 -+#define reg_cdpf_postechopower_15_8_len 8 -+#define reg_cdpf_postechopower_15_8_lsb 8 -+#define p_reg_cdpf_searchingend 0xF5EF -+#define reg_cdpf_searchingend_pos 0 -+#define reg_cdpf_searchingend_len 8 -+#define reg_cdpf_searchingend_lsb 0 -+#define r_reg_cdpf_candidate_7_0 0xF5F0 -+#define reg_cdpf_candidate_7_0_pos 0 -+#define reg_cdpf_candidate_7_0_len 8 -+#define reg_cdpf_candidate_7_0_lsb 0 -+#define r_reg_cdpf_candidate_15_8 0xF5F1 -+#define reg_cdpf_candidate_15_8_pos 0 -+#define reg_cdpf_candidate_15_8_len 8 -+#define reg_cdpf_candidate_15_8_lsb 8 -+#define p_reg_cdpf_candidate_rptr 0xF5F2 -+#define reg_cdpf_candidate_rptr_pos 0 -+#define reg_cdpf_candidate_rptr_len 7 -+#define reg_cdpf_candidate_rptr_lsb 0 -+#define p_reg_cdpf_candidate_rptr_force 0xF5F3 -+#define reg_cdpf_candidate_rptr_force_pos 0 -+#define reg_cdpf_candidate_rptr_force_len 1 -+#define reg_cdpf_candidate_rptr_force_lsb 0 -+#define p_reg_cdpf_trialshiftoffset_7_0 0xF5F4 -+#define reg_cdpf_trialshiftoffset_7_0_pos 0 -+#define reg_cdpf_trialshiftoffset_7_0_len 8 -+#define reg_cdpf_trialshiftoffset_7_0_lsb 0 -+#define p_reg_cdpf_trialshiftoffset_13_8 0xF5F5 -+#define reg_cdpf_trialshiftoffset_13_8_pos 0 -+#define reg_cdpf_trialshiftoffset_13_8_len 6 -+#define reg_cdpf_trialshiftoffset_13_8_lsb 8 -+#define p_reg_cdpf_channellength_7_0 0xF5F6 -+#define reg_cdpf_channellength_7_0_pos 0 -+#define reg_cdpf_channellength_7_0_len 8 -+#define reg_cdpf_channellength_7_0_lsb 0 -+#define p_reg_cdpf_channellength_12_8 0xF5F7 -+#define reg_cdpf_channellength_12_8_pos 0 -+#define reg_cdpf_channellength_12_8_len 5 -+#define reg_cdpf_channellength_12_8_lsb 8 -+#define p_reg_cdpf_hardwaresort 0xF5F8 -+#define reg_cdpf_hardwaresort_pos 0 -+#define reg_cdpf_hardwaresort_len 1 -+#define reg_cdpf_hardwaresort_lsb 0 -+#define p_reg_cdpf_maxcandidateno 0xF5F9 -+#define reg_cdpf_maxcandidateno_pos 0 -+#define reg_cdpf_maxcandidateno_len 3 -+#define reg_cdpf_maxcandidateno_lsb 0 -+#define p_reg_cdpf_channelleftindex 0xF5FA -+#define reg_cdpf_channelleftindex_pos 0 -+#define reg_cdpf_channelleftindex_len 4 -+#define reg_cdpf_channelleftindex_lsb 0 -+#define r_reg_cdpf_fdishift_7_0 0xF5FB -+#define reg_cdpf_fdishift_7_0_pos 0 -+#define reg_cdpf_fdishift_7_0_len 8 -+#define reg_cdpf_fdishift_7_0_lsb 0 -+#define r_reg_cdpf_fdishift_15_8 0xF5FC -+#define reg_cdpf_fdishift_15_8_pos 0 -+#define reg_cdpf_fdishift_15_8_len 8 -+#define reg_cdpf_fdishift_15_8_lsb 8 -+#define p_reg_cdpf_guardband 0xF5FD -+#define reg_cdpf_guardband_pos 0 -+#define reg_cdpf_guardband_len 5 -+#define reg_cdpf_guardband_lsb 0 -+#define p_reg_cdpf_maxtonemaxindex_7_0 0xF5FE -+#define reg_cdpf_maxtonemaxindex_7_0_pos 0 -+#define reg_cdpf_maxtonemaxindex_7_0_len 8 -+#define reg_cdpf_maxtonemaxindex_7_0_lsb 0 -+#define p_reg_cdpf_maxtonemaxindex_12_8 0xF5FF -+#define reg_cdpf_maxtonemaxindex_12_8_pos 0 -+#define reg_cdpf_maxtonemaxindex_12_8_len 5 -+#define reg_cdpf_maxtonemaxindex_12_8_lsb 8 -+#define p_reg_cdpf_fdiw0 0xF600 -+#define reg_cdpf_fdiw0_pos 0 -+#define reg_cdpf_fdiw0_len 7 -+#define reg_cdpf_fdiw0_lsb 0 -+#define p_reg_cdpf_fdiw1 0xF601 -+#define reg_cdpf_fdiw1_pos 0 -+#define reg_cdpf_fdiw1_len 7 -+#define reg_cdpf_fdiw1_lsb 0 -+#define p_reg_cdpf_fdiw2 0xF602 -+#define reg_cdpf_fdiw2_pos 0 -+#define reg_cdpf_fdiw2_len 7 -+#define reg_cdpf_fdiw2_lsb 0 -+#define p_reg_cdpf_fdiw3 0xF603 -+#define reg_cdpf_fdiw3_pos 0 -+#define reg_cdpf_fdiw3_len 7 -+#define reg_cdpf_fdiw3_lsb 0 -+#define p_reg_cdpf_fdiw4 0xF604 -+#define reg_cdpf_fdiw4_pos 0 -+#define reg_cdpf_fdiw4_len 7 -+#define reg_cdpf_fdiw4_lsb 0 -+#define p_reg_cdpf_fdiw5 0xF605 -+#define reg_cdpf_fdiw5_pos 0 -+#define reg_cdpf_fdiw5_len 7 -+#define reg_cdpf_fdiw5_lsb 0 -+#define p_reg_cdpf_fdiw6 0xF606 -+#define reg_cdpf_fdiw6_pos 0 -+#define reg_cdpf_fdiw6_len 7 -+#define reg_cdpf_fdiw6_lsb 0 -+#define p_reg_cdpf_fdiw7 0xF607 -+#define reg_cdpf_fdiw7_pos 0 -+#define reg_cdpf_fdiw7_len 7 -+#define reg_cdpf_fdiw7_lsb 0 -+#define r_reg_cdpf_fdiwindowsize 0xF608 -+#define reg_cdpf_fdiwindowsize_pos 0 -+#define reg_cdpf_fdiwindowsize_len 4 -+#define reg_cdpf_fdiwindowsize_lsb 0 -+#define p_reg_stes_mode 0xF609 -+#define reg_stes_mode_pos 0 -+#define reg_stes_mode_len 1 -+#define reg_stes_mode_lsb 0 -+#define p_reg_stes_done_st 0xF60A -+#define reg_stes_done_st_pos 0 -+#define reg_stes_done_st_len 2 -+#define reg_stes_done_st_lsb 0 -+#define p_reg_stes_done 0xF60B -+#define reg_stes_done_pos 0 -+#define reg_stes_done_len 1 -+#define reg_stes_done_lsb 0 -+#define p_reg_stes_timing_7_0 0xF60C -+#define reg_stes_timing_7_0_pos 0 -+#define reg_stes_timing_7_0_len 8 -+#define reg_stes_timing_7_0_lsb 0 -+#define p_reg_stes_timing_15_8 0xF60D -+#define reg_stes_timing_15_8_pos 0 -+#define reg_stes_timing_15_8_len 8 -+#define reg_stes_timing_15_8_lsb 8 -+#define p_reg_stes_sym_tot_adj_thre_7_0 0xF60E -+#define reg_stes_sym_tot_adj_thre_7_0_pos 0 -+#define reg_stes_sym_tot_adj_thre_7_0_len 8 -+#define reg_stes_sym_tot_adj_thre_7_0_lsb 0 -+#define p_reg_stes_sym_tot_adj_thre_15_8 0xF60F -+#define reg_stes_sym_tot_adj_thre_15_8_pos 0 -+#define reg_stes_sym_tot_adj_thre_15_8_len 8 -+#define reg_stes_sym_tot_adj_thre_15_8_lsb 8 -+#define p_reg_stes_sym_thre_9_2 0xF610 -+#define reg_stes_sym_thre_9_2_pos 0 -+#define reg_stes_sym_thre_9_2_len 8 -+#define reg_stes_sym_thre_9_2_lsb 0 -+#define p_reg_stes_sym_wo_adj_thre_9_2 0xF611 -+#define reg_stes_sym_wo_adj_thre_9_2_pos 0 -+#define reg_stes_sym_wo_adj_thre_9_2_len 8 -+#define reg_stes_sym_wo_adj_thre_9_2_lsb 0 -+#define p_reg_fste_i_adj_7_0 0xF612 -+#define reg_fste_i_adj_7_0_pos 0 -+#define reg_fste_i_adj_7_0_len 8 -+#define reg_fste_i_adj_7_0_lsb 0 -+#define p_reg_fste_i_adj_15_8 0xF613 -+#define reg_fste_i_adj_15_8_pos 0 -+#define reg_fste_i_adj_15_8_len 8 -+#define reg_fste_i_adj_15_8_lsb 8 -+#define r_fd_stes_iadj_val_7_0 0xF614 -+#define fd_stes_iadj_val_7_0_pos 0 -+#define fd_stes_iadj_val_7_0_len 8 -+#define fd_stes_iadj_val_7_0_lsb 0 -+#define r_fd_stes_iadj_val_15_8 0xF615 -+#define fd_stes_iadj_val_15_8_pos 0 -+#define fd_stes_iadj_val_15_8_len 8 -+#define fd_stes_iadj_val_15_8_lsb 8 -+#define r_fd_stes_symb_cnt_9_2 0xF616 -+#define fd_stes_symb_cnt_9_2_pos 0 -+#define fd_stes_symb_cnt_9_2_len 8 -+#define fd_stes_symb_cnt_9_2_lsb 0 -+#define r_fd_stes_snoi_cnt_9_2 0xF617 -+#define fd_stes_snoi_cnt_9_2_pos 0 -+#define fd_stes_snoi_cnt_9_2_len 8 -+#define fd_stes_snoi_cnt_9_2_lsb 0 -+#define r_fd_last_iadj_val_7_0 0xF618 -+#define fd_last_iadj_val_7_0_pos 0 -+#define fd_last_iadj_val_7_0_len 8 -+#define fd_last_iadj_val_7_0_lsb 0 -+#define r_fd_last_iadj_val_15_8 0xF619 -+#define fd_last_iadj_val_15_8_pos 0 -+#define fd_last_iadj_val_15_8_len 8 -+#define fd_last_iadj_val_15_8_lsb 8 -+#define p_reg_stes_bypass 0xF61A -+#define reg_stes_bypass_pos 0 -+#define reg_stes_bypass_len 1 -+#define reg_stes_bypass_lsb 0 -+#define p_reg_stes_best_timing_idx 0xF61B -+#define reg_stes_best_timing_idx_pos 0 -+#define reg_stes_best_timing_idx_len 4 -+#define reg_stes_best_timing_idx_lsb 0 -+#define p_reg_stes_iadj_val_7_0 0xF61C -+#define reg_stes_iadj_val_7_0_pos 0 -+#define reg_stes_iadj_val_7_0_len 8 -+#define reg_stes_iadj_val_7_0_lsb 0 -+#define p_reg_stes_iadj_val_15_8 0xF61D -+#define reg_stes_iadj_val_15_8_pos 0 -+#define reg_stes_iadj_val_15_8_len 8 -+#define reg_stes_iadj_val_15_8_lsb 8 -+#define p_reg_p_ste_start_guard_7_0 0xF620 -+#define reg_p_ste_start_guard_7_0_pos 0 -+#define reg_p_ste_start_guard_7_0_len 8 -+#define reg_p_ste_start_guard_7_0_lsb 0 -+#define p_reg_p_ste_start_guard_9_8 0xF621 -+#define reg_p_ste_start_guard_9_8_pos 0 -+#define reg_p_ste_start_guard_9_8_len 2 -+#define reg_p_ste_start_guard_9_8_lsb 8 -+#define p_reg_p_ste_end_guard_7_0 0xF622 -+#define reg_p_ste_end_guard_7_0_pos 0 -+#define reg_p_ste_end_guard_7_0_len 8 -+#define reg_p_ste_end_guard_7_0_lsb 0 -+#define p_reg_p_ste_end_guard_9_8 0xF623 -+#define reg_p_ste_end_guard_9_8_pos 0 -+#define reg_p_ste_end_guard_9_8_len 2 -+#define reg_p_ste_end_guard_9_8_lsb 8 -+#define r_reg_r_ste_wrong_beacon_count 0xF624 -+#define reg_r_ste_wrong_beacon_count_pos 0 -+#define reg_r_ste_wrong_beacon_count_len 7 -+#define reg_r_ste_wrong_beacon_count_lsb 0 -+#define p_reg_p_fccid_en 0xF625 -+#define reg_p_fccid_en_pos 0 -+#define reg_p_fccid_en_len 1 -+#define reg_p_fccid_en_lsb 0 -+#define p_reg_p_fccid_fft_ave_symbol_num 0xF626 -+#define reg_p_fccid_fft_ave_symbol_num_pos 0 -+#define reg_p_fccid_fft_ave_symbol_num_len 6 -+#define reg_p_fccid_fft_ave_symbol_num_lsb 0 -+#define p_reg_p_fccid_fft_work_start_tone_7_0 0xF627 -+#define reg_p_fccid_fft_work_start_tone_7_0_pos 0 -+#define reg_p_fccid_fft_work_start_tone_7_0_len 8 -+#define reg_p_fccid_fft_work_start_tone_7_0_lsb 0 -+#define p_reg_p_fccid_fft_work_start_tone_12_8 0xF628 -+#define reg_p_fccid_fft_work_start_tone_12_8_pos 0 -+#define reg_p_fccid_fft_work_start_tone_12_8_len 5 -+#define reg_p_fccid_fft_work_start_tone_12_8_lsb 8 -+#define p_reg_p_fccid_fft_work_end_tone_7_0 0xF629 -+#define reg_p_fccid_fft_work_end_tone_7_0_pos 0 -+#define reg_p_fccid_fft_work_end_tone_7_0_len 8 -+#define reg_p_fccid_fft_work_end_tone_7_0_lsb 0 -+#define p_reg_p_fccid_fft_work_end_tone_12_8 0xF62A -+#define reg_p_fccid_fft_work_end_tone_12_8_pos 0 -+#define reg_p_fccid_fft_work_end_tone_12_8_len 5 -+#define reg_p_fccid_fft_work_end_tone_12_8_lsb 8 -+#define p_reg_p_fccid_peak_to_th_divider 0xF62B -+#define reg_p_fccid_peak_to_th_divider_pos 0 -+#define reg_p_fccid_peak_to_th_divider_len 4 -+#define reg_p_fccid_peak_to_th_divider_lsb 0 -+#define p_reg_p_fccid_peak_to_th_mode 0xF62C -+#define reg_p_fccid_peak_to_th_mode_pos 0 -+#define reg_p_fccid_peak_to_th_mode_len 2 -+#define reg_p_fccid_peak_to_th_mode_lsb 0 -+#define p_reg_p_fccid_search_mode 0xF62D -+#define reg_p_fccid_search_mode_pos 0 -+#define reg_p_fccid_search_mode_len 1 -+#define reg_p_fccid_search_mode_lsb 0 -+#define p_reg_p_fccid_group_th 0xF62E -+#define reg_p_fccid_group_th_pos 0 -+#define reg_p_fccid_group_th_len 7 -+#define reg_p_fccid_group_th_lsb 0 -+#define p_reg_p_fccid_search_rdy 0xF62F -+#define reg_p_fccid_search_rdy_pos 0 -+#define reg_p_fccid_search_rdy_len 1 -+#define reg_p_fccid_search_rdy_lsb 0 -+#define r_reg_r_fccid_fft_ave_read_out_7_0 0xF630 -+#define reg_r_fccid_fft_ave_read_out_7_0_pos 0 -+#define reg_r_fccid_fft_ave_read_out_7_0_len 8 -+#define reg_r_fccid_fft_ave_read_out_7_0_lsb 0 -+#define r_reg_r_fccid_fft_ave_read_out_15_8 0xF631 -+#define reg_r_fccid_fft_ave_read_out_15_8_pos 0 -+#define reg_r_fccid_fft_ave_read_out_15_8_len 8 -+#define reg_r_fccid_fft_ave_read_out_15_8_lsb 8 -+#define r_reg_r_fccid_large_tone_num_7_0 0xF632 -+#define reg_r_fccid_large_tone_num_7_0_pos 0 -+#define reg_r_fccid_large_tone_num_7_0_len 8 -+#define reg_r_fccid_large_tone_num_7_0_lsb 0 -+#define r_reg_r_fccid_large_tone_num_12_8 0xF633 -+#define reg_r_fccid_large_tone_num_12_8_pos 0 -+#define reg_r_fccid_large_tone_num_12_8_len 5 -+#define reg_r_fccid_large_tone_num_12_8_lsb 8 -+#define r_reg_r_fccid_cci1_start_tone_7_0 0xF634 -+#define reg_r_fccid_cci1_start_tone_7_0_pos 0 -+#define reg_r_fccid_cci1_start_tone_7_0_len 8 -+#define reg_r_fccid_cci1_start_tone_7_0_lsb 0 -+#define r_reg_r_fccid_cci1_start_tone_12_8 0xF635 -+#define reg_r_fccid_cci1_start_tone_12_8_pos 0 -+#define reg_r_fccid_cci1_start_tone_12_8_len 5 -+#define reg_r_fccid_cci1_start_tone_12_8_lsb 8 -+#define r_reg_r_fccid_cci1_end_tone_7_0 0xF636 -+#define reg_r_fccid_cci1_end_tone_7_0_pos 0 -+#define reg_r_fccid_cci1_end_tone_7_0_len 8 -+#define reg_r_fccid_cci1_end_tone_7_0_lsb 0 -+#define r_reg_r_fccid_cci1_end_tone_12_8 0xF637 -+#define reg_r_fccid_cci1_end_tone_12_8_pos 0 -+#define reg_r_fccid_cci1_end_tone_12_8_len 5 -+#define reg_r_fccid_cci1_end_tone_12_8_lsb 8 -+#define r_reg_r_fccid_cci1_peak_7_0 0xF638 -+#define reg_r_fccid_cci1_peak_7_0_pos 0 -+#define reg_r_fccid_cci1_peak_7_0_len 8 -+#define reg_r_fccid_cci1_peak_7_0_lsb 0 -+#define r_reg_r_fccid_cci1_peak_15_8 0xF639 -+#define reg_r_fccid_cci1_peak_15_8_pos 0 -+#define reg_r_fccid_cci1_peak_15_8_len 8 -+#define reg_r_fccid_cci1_peak_15_8_lsb 8 -+#define r_reg_r_fccid_cci2_start_tone_7_0 0xF63A -+#define reg_r_fccid_cci2_start_tone_7_0_pos 0 -+#define reg_r_fccid_cci2_start_tone_7_0_len 8 -+#define reg_r_fccid_cci2_start_tone_7_0_lsb 0 -+#define r_reg_r_fccid_cci2_start_tone_12_8 0xF63B -+#define reg_r_fccid_cci2_start_tone_12_8_pos 0 -+#define reg_r_fccid_cci2_start_tone_12_8_len 5 -+#define reg_r_fccid_cci2_start_tone_12_8_lsb 8 -+#define r_reg_r_fccid_cci2_end_tone_7_0 0xF63C -+#define reg_r_fccid_cci2_end_tone_7_0_pos 0 -+#define reg_r_fccid_cci2_end_tone_7_0_len 8 -+#define reg_r_fccid_cci2_end_tone_7_0_lsb 0 -+#define r_reg_r_fccid_cci2_end_tone_12_8 0xF63D -+#define reg_r_fccid_cci2_end_tone_12_8_pos 0 -+#define reg_r_fccid_cci2_end_tone_12_8_len 5 -+#define reg_r_fccid_cci2_end_tone_12_8_lsb 8 -+#define r_reg_r_fccid_cci2_peak_7_0 0xF63E -+#define reg_r_fccid_cci2_peak_7_0_pos 0 -+#define reg_r_fccid_cci2_peak_7_0_len 8 -+#define reg_r_fccid_cci2_peak_7_0_lsb 0 -+#define r_reg_r_fccid_cci2_peak_15_8 0xF63F -+#define reg_r_fccid_cci2_peak_15_8_pos 0 -+#define reg_r_fccid_cci2_peak_15_8_len 8 -+#define reg_r_fccid_cci2_peak_15_8_lsb 8 -+#define r_reg_r_fccid_cci3_start_tone_7_0 0xF640 -+#define reg_r_fccid_cci3_start_tone_7_0_pos 0 -+#define reg_r_fccid_cci3_start_tone_7_0_len 8 -+#define reg_r_fccid_cci3_start_tone_7_0_lsb 0 -+#define r_reg_r_fccid_cci3_start_tone_12_8 0xF641 -+#define reg_r_fccid_cci3_start_tone_12_8_pos 0 -+#define reg_r_fccid_cci3_start_tone_12_8_len 5 -+#define reg_r_fccid_cci3_start_tone_12_8_lsb 8 -+#define r_reg_r_fccid_cci3_end_tone_7_0 0xF642 -+#define reg_r_fccid_cci3_end_tone_7_0_pos 0 -+#define reg_r_fccid_cci3_end_tone_7_0_len 8 -+#define reg_r_fccid_cci3_end_tone_7_0_lsb 0 -+#define r_reg_r_fccid_cci3_end_tone_12_8 0xF643 -+#define reg_r_fccid_cci3_end_tone_12_8_pos 0 -+#define reg_r_fccid_cci3_end_tone_12_8_len 5 -+#define reg_r_fccid_cci3_end_tone_12_8_lsb 8 -+#define r_reg_r_fccid_cci3_peak_7_0 0xF644 -+#define reg_r_fccid_cci3_peak_7_0_pos 0 -+#define reg_r_fccid_cci3_peak_7_0_len 8 -+#define reg_r_fccid_cci3_peak_7_0_lsb 0 -+#define r_reg_r_fccid_cci3_peak_15_8 0xF645 -+#define reg_r_fccid_cci3_peak_15_8_pos 0 -+#define reg_r_fccid_cci3_peak_15_8_len 8 -+#define reg_r_fccid_cci3_peak_15_8_lsb 8 -+#define r_reg_r_fccid_cci4_start_tone_7_0 0xF646 -+#define reg_r_fccid_cci4_start_tone_7_0_pos 0 -+#define reg_r_fccid_cci4_start_tone_7_0_len 8 -+#define reg_r_fccid_cci4_start_tone_7_0_lsb 0 -+#define r_reg_r_fccid_cci4_start_tone_12_8 0xF647 -+#define reg_r_fccid_cci4_start_tone_12_8_pos 0 -+#define reg_r_fccid_cci4_start_tone_12_8_len 5 -+#define reg_r_fccid_cci4_start_tone_12_8_lsb 8 -+#define r_reg_r_fccid_cci4_end_tone_7_0 0xF648 -+#define reg_r_fccid_cci4_end_tone_7_0_pos 0 -+#define reg_r_fccid_cci4_end_tone_7_0_len 8 -+#define reg_r_fccid_cci4_end_tone_7_0_lsb 0 -+#define r_reg_r_fccid_cci4_end_tone_12_8 0xF649 -+#define reg_r_fccid_cci4_end_tone_12_8_pos 0 -+#define reg_r_fccid_cci4_end_tone_12_8_len 5 -+#define reg_r_fccid_cci4_end_tone_12_8_lsb 8 -+#define r_reg_r_fccid_cci4_peak_7_0 0xF64A -+#define reg_r_fccid_cci4_peak_7_0_pos 0 -+#define reg_r_fccid_cci4_peak_7_0_len 8 -+#define reg_r_fccid_cci4_peak_7_0_lsb 0 -+#define r_reg_r_fccid_cci4_peak_15_8 0xF64B -+#define reg_r_fccid_cci4_peak_15_8_pos 0 -+#define reg_r_fccid_cci4_peak_15_8_len 8 -+#define reg_r_fccid_cci4_peak_15_8_lsb 8 -+#define r_reg_r_fccid_cci1_rank 0xF64C -+#define reg_r_fccid_cci1_rank_pos 0 -+#define reg_r_fccid_cci1_rank_len 3 -+#define reg_r_fccid_cci1_rank_lsb 0 -+#define r_reg_r_fccid_cci2_rank 0xF64D -+#define reg_r_fccid_cci2_rank_pos 0 -+#define reg_r_fccid_cci2_rank_len 3 -+#define reg_r_fccid_cci2_rank_lsb 0 -+#define r_reg_r_fccid_cci3_rank 0xF64E -+#define reg_r_fccid_cci3_rank_pos 0 -+#define reg_r_fccid_cci3_rank_len 3 -+#define reg_r_fccid_cci3_rank_lsb 0 -+#define r_reg_r_fccid_cci4_rank 0xF64F -+#define reg_r_fccid_cci4_rank_pos 0 -+#define reg_r_fccid_cci4_rank_len 3 -+#define reg_r_fccid_cci4_rank_lsb 0 -+#define p_reg_p_csi_shift3 0xF650 -+#define reg_p_csi_shift3_pos 0 -+#define reg_p_csi_shift3_len 4 -+#define reg_p_csi_shift3_lsb 0 -+#define p_reg_p_csi_mul3 0xF651 -+#define reg_p_csi_mul3_pos 0 -+#define reg_p_csi_mul3_len 8 -+#define reg_p_csi_mul3_lsb 0 -+#define p_reg_p_csi_level3_7_0 0xF652 -+#define reg_p_csi_level3_7_0_pos 0 -+#define reg_p_csi_level3_7_0_len 8 -+#define reg_p_csi_level3_7_0_lsb 0 -+#define p_reg_p_csi_level3_8 0xF653 -+#define reg_p_csi_level3_8_pos 0 -+#define reg_p_csi_level3_8_len 1 -+#define reg_p_csi_level3_8_lsb 8 -+#define p_reg_p_csi_fftout_shift_fix_value 0xF654 -+#define reg_p_csi_fftout_shift_fix_value_pos 0 -+#define reg_p_csi_fftout_shift_fix_value_len 4 -+#define reg_p_csi_fftout_shift_fix_value_lsb 0 -+#define p_reg_p_feq_scale_pow 0xF655 -+#define reg_p_feq_scale_pow_pos 0 -+#define reg_p_feq_scale_pow_len 6 -+#define reg_p_feq_scale_pow_lsb 0 -+#define p_reg_p_csi_cp_idx 0xF656 -+#define reg_p_csi_cp_idx_pos 0 -+#define reg_p_csi_cp_idx_len 8 -+#define reg_p_csi_cp_idx_lsb 0 -+#define p_reg_p_csi_outsh_zero_th_7_0 0xF657 -+#define reg_p_csi_outsh_zero_th_7_0_pos 0 -+#define reg_p_csi_outsh_zero_th_7_0_len 8 -+#define reg_p_csi_outsh_zero_th_7_0_lsb 0 -+#define p_reg_p_csi_outsh_zero_th_10_8 0xF658 -+#define reg_p_csi_outsh_zero_th_10_8_pos 0 -+#define reg_p_csi_outsh_zero_th_10_8_len 3 -+#define reg_p_csi_outsh_zero_th_10_8_lsb 8 -+#define p_reg_p_csi_ar_ratio 0xF659 -+#define reg_p_csi_ar_ratio_pos 0 -+#define reg_p_csi_ar_ratio_len 8 -+#define reg_p_csi_ar_ratio_lsb 0 -+#define p_reg_r_csi_cp_vld 0xF65A -+#define reg_r_csi_cp_vld_pos 0 -+#define reg_r_csi_cp_vld_len 1 -+#define reg_r_csi_cp_vld_lsb 0 -+#define p_reg_r_csi_sp_vld 0xF65B -+#define reg_r_csi_sp_vld_pos 0 -+#define reg_r_csi_sp_vld_len 1 -+#define reg_r_csi_sp_vld_lsb 0 -+#define p_reg_p_csi_fft_out_shift_en 0xF65C -+#define reg_p_csi_fft_out_shift_en_pos 0 -+#define reg_p_csi_fft_out_shift_en_len 1 -+#define reg_p_csi_fft_out_shift_en_lsb 0 -+#define p_reg_p_csi_feq_out_shift_en 0xF65D -+#define reg_p_csi_feq_out_shift_en_pos 0 -+#define reg_p_csi_feq_out_shift_en_len 1 -+#define reg_p_csi_feq_out_shift_en_lsb 0 -+#define p_reg_r_csi_cp_fft_out 0xF65E -+#define reg_r_csi_cp_fft_out_pos 0 -+#define reg_r_csi_cp_fft_out_len 1 -+#define reg_r_csi_cp_fft_out_lsb 0 -+#define p_reg_r_csi_sp_feq_log2_out 0xF65F -+#define reg_r_csi_sp_feq_log2_out_pos 0 -+#define reg_r_csi_sp_feq_log2_out_len 8 -+#define reg_r_csi_sp_feq_log2_out_lsb 0 -+#define p_reg_r_csi_sp_fft_out 0xF660 -+#define reg_r_csi_sp_fft_out_pos 0 -+#define reg_r_csi_sp_fft_out_len 1 -+#define reg_r_csi_sp_fft_out_lsb 0 -+#define p_reg_p_feq_eh2_from_fpcc_en 0xF661 -+#define reg_p_feq_eh2_from_fpcc_en_pos 0 -+#define reg_p_feq_eh2_from_fpcc_en_len 1 -+#define reg_p_feq_eh2_from_fpcc_en_lsb 0 -+#define r_reg_r_fccid_fft_ave_peak_7_0 0xF662 -+#define reg_r_fccid_fft_ave_peak_7_0_pos 0 -+#define reg_r_fccid_fft_ave_peak_7_0_len 8 -+#define reg_r_fccid_fft_ave_peak_7_0_lsb 0 -+#define r_reg_r_fccid_fft_ave_peak_15_8 0xF663 -+#define reg_r_fccid_fft_ave_peak_15_8_pos 0 -+#define reg_r_fccid_fft_ave_peak_15_8_len 8 -+#define reg_r_fccid_fft_ave_peak_15_8_lsb 8 -+#define r_reg_r_fccid_fft_ave_peak_23_16 0xF664 -+#define reg_r_fccid_fft_ave_peak_23_16_pos 0 -+#define reg_r_fccid_fft_ave_peak_23_16_len 8 -+#define reg_r_fccid_fft_ave_peak_23_16_lsb 16 -+#define r_reg_r_fccid_fft_ave_peak_26_24 0xF665 -+#define reg_r_fccid_fft_ave_peak_26_24_pos 0 -+#define reg_r_fccid_fft_ave_peak_26_24_len 3 -+#define reg_r_fccid_fft_ave_peak_26_24_lsb 24 -+#define p_reg_p_fccid_fft_ave_read_rdy 0xF666 -+#define reg_p_fccid_fft_ave_read_rdy_pos 0 -+#define reg_p_fccid_fft_ave_read_rdy_len 1 -+#define reg_p_fccid_fft_ave_read_rdy_lsb 0 -+#define p_reg_p_fccid_fft_ave_read_index_7_0 0xF667 -+#define reg_p_fccid_fft_ave_read_index_7_0_pos 0 -+#define reg_p_fccid_fft_ave_read_index_7_0_len 8 -+#define reg_p_fccid_fft_ave_read_index_7_0_lsb 0 -+#define p_reg_p_fccid_fft_ave_read_index_12_8 0xF668 -+#define reg_p_fccid_fft_ave_read_index_12_8_pos 0 -+#define reg_p_fccid_fft_ave_read_index_12_8_len 5 -+#define reg_p_fccid_fft_ave_read_index_12_8_lsb 8 -+#define p_reg_cdpf_candidate_rw 0xF669 -+#define reg_cdpf_candidate_rw_pos 0 -+#define reg_cdpf_candidate_rw_len 1 -+#define reg_cdpf_candidate_rw_lsb 0 -+#define p_reg_cdpf_candidate_prog_7_0 0xF66A -+#define reg_cdpf_candidate_prog_7_0_pos 0 -+#define reg_cdpf_candidate_prog_7_0_len 8 -+#define reg_cdpf_candidate_prog_7_0_lsb 0 -+#define p_reg_cdpf_candidate_prog_15_8 0xF66B -+#define reg_cdpf_candidate_prog_15_8_pos 0 -+#define reg_cdpf_candidate_prog_15_8_len 8 -+#define reg_cdpf_candidate_prog_15_8_lsb 8 -+#define p_reg_cdpf_candidateno_prog 0xF66C -+#define reg_cdpf_candidateno_prog_pos 0 -+#define reg_cdpf_candidateno_prog_len 6 -+#define reg_cdpf_candidateno_prog_lsb 0 -+#define p_reg_cdpf_candidateno_switch 0xF66D -+#define reg_cdpf_candidateno_switch_pos 0 -+#define reg_cdpf_candidateno_switch_len 1 -+#define reg_cdpf_candidateno_switch_lsb 0 -+#define g_reg_tpsd_txmod 0xF900 -+#define reg_tpsd_txmod_pos 0 -+#define reg_tpsd_txmod_len 2 -+#define reg_tpsd_txmod_lsb 0 -+#define g_reg_tpsd_gi 0xF901 -+#define reg_tpsd_gi_pos 0 -+#define reg_tpsd_gi_len 2 -+#define reg_tpsd_gi_lsb 0 -+#define g_reg_tpsd_hier 0xF902 -+#define reg_tpsd_hier_pos 0 -+#define reg_tpsd_hier_len 3 -+#define reg_tpsd_hier_lsb 0 -+#define g_reg_tpsd_const 0xF903 -+#define reg_tpsd_const_pos 0 -+#define reg_tpsd_const_len 2 -+#define reg_tpsd_const_lsb 0 -+#define g_reg_bw 0xF904 -+#define reg_bw_pos 0 -+#define reg_bw_len 2 -+#define reg_bw_lsb 0 -+#define g_reg_dec_pri 0xF905 -+#define reg_dec_pri_pos 0 -+#define reg_dec_pri_len 1 -+#define reg_dec_pri_lsb 0 -+#define g_reg_tpsd_hpcr 0xF906 -+#define reg_tpsd_hpcr_pos 0 -+#define reg_tpsd_hpcr_len 3 -+#define reg_tpsd_hpcr_lsb 0 -+#define g_reg_tpsd_lpcr 0xF907 -+#define reg_tpsd_lpcr_pos 0 -+#define reg_tpsd_lpcr_len 3 -+#define reg_tpsd_lpcr_lsb 0 -+#define g_reg_tpsd_indep 0xF908 -+#define reg_tpsd_indep_pos 0 -+#define reg_tpsd_indep_len 1 -+#define reg_tpsd_indep_lsb 0 -+#define g_reg_tpsd_tslice 0xF909 -+#define reg_tpsd_tslice_pos 0 -+#define reg_tpsd_tslice_len 1 -+#define reg_tpsd_tslice_lsb 0 -+#define g_reg_tpsd_mpefec 0xF90A -+#define reg_tpsd_mpefec_pos 0 -+#define reg_tpsd_mpefec_len 1 -+#define reg_tpsd_mpefec_lsb 0 -+#define g_reg_sntc_en 0xF90B -+#define reg_sntc_en_pos 0 -+#define reg_sntc_en_len 1 -+#define reg_sntc_en_lsb 0 -+#define g_reg_intp_sys_div 0xF90C -+#define reg_intp_sys_div_pos 0 -+#define reg_intp_sys_div_len 1 -+#define reg_intp_sys_div_lsb 0 -+#define g_reg_clk_sntc_sel 0xF90D -+#define reg_clk_sntc_sel_pos 0 -+#define reg_clk_sntc_sel_len 3 -+#define reg_clk_sntc_sel_lsb 0 -+#define p_reg_ce_gs_force 0xFD00 -+#define reg_ce_gs_force_pos 0 -+#define reg_ce_gs_force_len 1 -+#define reg_ce_gs_force_lsb 0 -+#define p_reg_ce_dagcgain_delay 0xFD01 -+#define reg_ce_dagcgain_delay_pos 0 -+#define reg_ce_dagcgain_delay_len 2 -+#define reg_ce_dagcgain_delay_lsb 0 -+#define p_reg_ce_derot_en 0xFD02 -+#define reg_ce_derot_en_pos 0 -+#define reg_ce_derot_en_len 1 -+#define reg_ce_derot_en_lsb 0 -+#define p_reg_ce_fctrl_en 0xFD05 -+#define reg_ce_fctrl_en_pos 0 -+#define reg_ce_fctrl_en_len 1 -+#define reg_ce_fctrl_en_lsb 0 -+#define p_reg_ce_en 0xFD06 -+#define reg_ce_en_pos 0 -+#define reg_ce_en_len 1 -+#define reg_ce_en_lsb 0 -+#define p_reg_ce_sat_wes 0xFD07 -+#define reg_ce_sat_wes_pos 0 -+#define reg_ce_sat_wes_len 1 -+#define reg_ce_sat_wes_lsb 0 -+#define p_reg_ce_sat_sigma2 0xFD08 -+#define reg_ce_sat_sigma2_pos 0 -+#define reg_ce_sat_sigma2_len 1 -+#define reg_ce_sat_sigma2_lsb 0 -+#define p_reg_ce_sat_tdi_br_re 0xFD09 -+#define reg_ce_sat_tdi_br_re_pos 0 -+#define reg_ce_sat_tdi_br_re_len 1 -+#define reg_ce_sat_tdi_br_re_lsb 0 -+#define p_reg_ce_sat_tdi_br_im 0xFD0A -+#define reg_ce_sat_tdi_br_im_pos 0 -+#define reg_ce_sat_tdi_br_im_len 1 -+#define reg_ce_sat_tdi_br_im_lsb 0 -+#define p_reg_ce_sat_tdi_ar_re 0xFD0B -+#define reg_ce_sat_tdi_ar_re_pos 0 -+#define reg_ce_sat_tdi_ar_re_len 1 -+#define reg_ce_sat_tdi_ar_re_lsb 0 -+#define p_reg_ce_sat_tdi_ar_im 0xFD0C -+#define reg_ce_sat_tdi_ar_im_pos 0 -+#define reg_ce_sat_tdi_ar_im_len 1 -+#define reg_ce_sat_tdi_ar_im_lsb 0 -+#define p_reg_ce_sat_fdi_br_re 0xFD0D -+#define reg_ce_sat_fdi_br_re_pos 0 -+#define reg_ce_sat_fdi_br_re_len 1 -+#define reg_ce_sat_fdi_br_re_lsb 0 -+#define p_reg_ce_sat_fdi_br_im 0xFD0E -+#define reg_ce_sat_fdi_br_im_pos 0 -+#define reg_ce_sat_fdi_br_im_len 1 -+#define reg_ce_sat_fdi_br_im_lsb 0 -+#define p_reg_ce_var_forced_value 0xFD0F -+#define reg_ce_var_forced_value_pos 0 -+#define reg_ce_var_forced_value_len 3 -+#define reg_ce_var_forced_value_lsb 0 -+#define p_reg_ce_s1 0xFD10 -+#define reg_ce_s1_pos 0 -+#define reg_ce_s1_len 5 -+#define reg_ce_s1_lsb 0 -+#define r_reg_ce_tdi_flatness_7_0 0xFD11 -+#define reg_ce_tdi_flatness_7_0_pos 0 -+#define reg_ce_tdi_flatness_7_0_len 8 -+#define reg_ce_tdi_flatness_7_0_lsb 0 -+#define r_reg_ce_tdi_flatness_8 0xFD12 -+#define reg_ce_tdi_flatness_8_pos 0 -+#define reg_ce_tdi_flatness_8_len 1 -+#define reg_ce_tdi_flatness_8_lsb 8 -+#define r_reg_ce_tone_7_0 0xFD13 -+#define reg_ce_tone_7_0_pos 0 -+#define reg_ce_tone_7_0_len 8 -+#define reg_ce_tone_7_0_lsb 0 -+#define r_reg_ce_tone_12_8 0xFD14 -+#define reg_ce_tone_12_8_pos 0 -+#define reg_ce_tone_12_8_len 5 -+#define reg_ce_tone_12_8_lsb 8 -+#define p_reg_ce_centroid_drift_th 0xFD15 -+#define reg_ce_centroid_drift_th_pos 0 -+#define reg_ce_centroid_drift_th_len 8 -+#define reg_ce_centroid_drift_th_lsb 0 -+#define p_reg_ce_centroid_bias_inc_7_0 0xFD16 -+#define reg_ce_centroid_bias_inc_7_0_pos 0 -+#define reg_ce_centroid_bias_inc_7_0_len 8 -+#define reg_ce_centroid_bias_inc_7_0_lsb 0 -+#define p_reg_ce_centroid_bias_inc_8 0xFD17 -+#define reg_ce_centroid_bias_inc_8_pos 0 -+#define reg_ce_centroid_bias_inc_8_len 1 -+#define reg_ce_centroid_bias_inc_8_lsb 8 -+#define p_reg_ce_centroid_count_max 0xFD18 -+#define reg_ce_centroid_count_max_pos 0 -+#define reg_ce_centroid_count_max_len 4 -+#define reg_ce_centroid_count_max_lsb 0 -+#define p_reg_ce_var_th0_7_0 0xFD19 -+#define reg_ce_var_th0_7_0_pos 0 -+#define reg_ce_var_th0_7_0_len 8 -+#define reg_ce_var_th0_7_0_lsb 0 -+#define p_reg_ce_var_th0_15_8 0xFD1A -+#define reg_ce_var_th0_15_8_pos 0 -+#define reg_ce_var_th0_15_8_len 8 -+#define reg_ce_var_th0_15_8_lsb 8 -+#define p_reg_ce_var_th1_7_0 0xFD1B -+#define reg_ce_var_th1_7_0_pos 0 -+#define reg_ce_var_th1_7_0_len 8 -+#define reg_ce_var_th1_7_0_lsb 0 -+#define p_reg_ce_var_th1_15_8 0xFD1C -+#define reg_ce_var_th1_15_8_pos 0 -+#define reg_ce_var_th1_15_8_len 8 -+#define reg_ce_var_th1_15_8_lsb 8 -+#define p_reg_ce_var_th2_7_0 0xFD1D -+#define reg_ce_var_th2_7_0_pos 0 -+#define reg_ce_var_th2_7_0_len 8 -+#define reg_ce_var_th2_7_0_lsb 0 -+#define p_reg_ce_var_th2_15_8 0xFD1E -+#define reg_ce_var_th2_15_8_pos 0 -+#define reg_ce_var_th2_15_8_len 8 -+#define reg_ce_var_th2_15_8_lsb 8 -+#define p_reg_ce_var_th3_7_0 0xFD1F -+#define reg_ce_var_th3_7_0_pos 0 -+#define reg_ce_var_th3_7_0_len 8 -+#define reg_ce_var_th3_7_0_lsb 0 -+#define p_reg_ce_var_th3_15_8 0xFD20 -+#define reg_ce_var_th3_15_8_pos 0 -+#define reg_ce_var_th3_15_8_len 8 -+#define reg_ce_var_th3_15_8_lsb 8 -+#define p_reg_ce_var_th4_7_0 0xFD21 -+#define reg_ce_var_th4_7_0_pos 0 -+#define reg_ce_var_th4_7_0_len 8 -+#define reg_ce_var_th4_7_0_lsb 0 -+#define p_reg_ce_var_th4_15_8 0xFD22 -+#define reg_ce_var_th4_15_8_pos 0 -+#define reg_ce_var_th4_15_8_len 8 -+#define reg_ce_var_th4_15_8_lsb 8 -+#define p_reg_ce_var_th5_7_0 0xFD23 -+#define reg_ce_var_th5_7_0_pos 0 -+#define reg_ce_var_th5_7_0_len 8 -+#define reg_ce_var_th5_7_0_lsb 0 -+#define p_reg_ce_var_th5_15_8 0xFD24 -+#define reg_ce_var_th5_15_8_pos 0 -+#define reg_ce_var_th5_15_8_len 8 -+#define reg_ce_var_th5_15_8_lsb 8 -+#define p_reg_ce_var_th6_7_0 0xFD25 -+#define reg_ce_var_th6_7_0_pos 0 -+#define reg_ce_var_th6_7_0_len 8 -+#define reg_ce_var_th6_7_0_lsb 0 -+#define p_reg_ce_var_th6_15_8 0xFD26 -+#define reg_ce_var_th6_15_8_pos 0 -+#define reg_ce_var_th6_15_8_len 8 -+#define reg_ce_var_th6_15_8_lsb 8 -+#define p_reg_ce_var_max 0xFD27 -+#define reg_ce_var_max_pos 0 -+#define reg_ce_var_max_len 3 -+#define reg_ce_var_max_lsb 0 -+#define p_reg_ce_cent_forced_en 0xFD28 -+#define reg_ce_cent_forced_en_pos 0 -+#define reg_ce_cent_forced_en_len 1 -+#define reg_ce_cent_forced_en_lsb 0 -+#define p_reg_ce_var_forced_en 0xFD29 -+#define reg_ce_var_forced_en_pos 0 -+#define reg_ce_var_forced_en_len 1 -+#define reg_ce_var_forced_en_lsb 0 -+#define p_reg_ce_fctrl_auto_reset_en 0xFD2A -+#define reg_ce_fctrl_auto_reset_en_pos 0 -+#define reg_ce_fctrl_auto_reset_en_len 1 -+#define reg_ce_fctrl_auto_reset_en_lsb 0 -+#define p_reg_ce_cent_auto_clr_en 0xFD2B -+#define reg_ce_cent_auto_clr_en_pos 0 -+#define reg_ce_cent_auto_clr_en_len 1 -+#define reg_ce_cent_auto_clr_en_lsb 0 -+#define p_reg_ce_fctrl_reset 0xFD2C -+#define reg_ce_fctrl_reset_pos 0 -+#define reg_ce_fctrl_reset_len 1 -+#define reg_ce_fctrl_reset_lsb 0 -+#define p_reg_ce_cent_forced_value_7_0 0xFD2D -+#define reg_ce_cent_forced_value_7_0_pos 0 -+#define reg_ce_cent_forced_value_7_0_len 8 -+#define reg_ce_cent_forced_value_7_0_lsb 0 -+#define p_reg_ce_cent_forced_value_11_8 0xFD2E -+#define reg_ce_cent_forced_value_11_8_pos 0 -+#define reg_ce_cent_forced_value_11_8_len 4 -+#define reg_ce_cent_forced_value_11_8_lsb 8 -+#define p_reg_ce_cent_auto_clr_value_7_0 0xFD2F -+#define reg_ce_cent_auto_clr_value_7_0_pos 0 -+#define reg_ce_cent_auto_clr_value_7_0_len 8 -+#define reg_ce_cent_auto_clr_value_7_0_lsb 0 -+#define p_reg_ce_cent_auto_clr_value_11_8 0xFD30 -+#define reg_ce_cent_auto_clr_value_11_8_pos 0 -+#define reg_ce_cent_auto_clr_value_11_8_len 4 -+#define reg_ce_cent_auto_clr_value_11_8_lsb 8 -+#define p_reg_ce_centroid_max_7_0 0xFD31 -+#define reg_ce_centroid_max_7_0_pos 0 -+#define reg_ce_centroid_max_7_0_len 8 -+#define reg_ce_centroid_max_7_0_lsb 0 -+#define p_reg_ce_centroid_max_11_8 0xFD32 -+#define reg_ce_centroid_max_11_8_pos 0 -+#define reg_ce_centroid_max_11_8_len 4 -+#define reg_ce_centroid_max_11_8_lsb 8 -+#define p_reg_ce_fctrl_rd 0xFD33 -+#define reg_ce_fctrl_rd_pos 0 -+#define reg_ce_fctrl_rd_len 1 -+#define reg_ce_fctrl_rd_lsb 0 -+#define r_reg_ce_centroid_out_7_0 0xFD34 -+#define reg_ce_centroid_out_7_0_pos 0 -+#define reg_ce_centroid_out_7_0_len 8 -+#define reg_ce_centroid_out_7_0_lsb 0 -+#define r_reg_ce_centroid_out_11_8 0xFD35 -+#define reg_ce_centroid_out_11_8_pos 0 -+#define reg_ce_centroid_out_11_8_len 4 -+#define reg_ce_centroid_out_11_8_lsb 8 -+#define r_reg_ce_fctrl_rdy 0xFD36 -+#define reg_ce_fctrl_rdy_pos 0 -+#define reg_ce_fctrl_rdy_len 1 -+#define reg_ce_fctrl_rdy_lsb 0 -+#define r_reg_ce_var 0xFD37 -+#define reg_ce_var_pos 0 -+#define reg_ce_var_len 3 -+#define reg_ce_var_lsb 0 -+#define r_reg_ce_bias_7_0 0xFD38 -+#define reg_ce_bias_7_0_pos 0 -+#define reg_ce_bias_7_0_len 8 -+#define reg_ce_bias_7_0_lsb 0 -+#define r_reg_ce_bias_11_8 0xFD39 -+#define reg_ce_bias_11_8_pos 0 -+#define reg_ce_bias_11_8_len 4 -+#define reg_ce_bias_11_8_lsb 8 -+#define r_reg_ce_m1_7_0 0xFD3A -+#define reg_ce_m1_7_0_pos 0 -+#define reg_ce_m1_7_0_len 8 -+#define reg_ce_m1_7_0_lsb 0 -+#define r_reg_ce_m1_11_8 0xFD3B -+#define reg_ce_m1_11_8_pos 0 -+#define reg_ce_m1_11_8_len 4 -+#define reg_ce_m1_11_8_lsb 8 -+#define r_reg_ce_rh0_7_0 0xFD3C -+#define reg_ce_rh0_7_0_pos 0 -+#define reg_ce_rh0_7_0_len 8 -+#define reg_ce_rh0_7_0_lsb 0 -+#define r_reg_ce_rh0_15_8 0xFD3D -+#define reg_ce_rh0_15_8_pos 0 -+#define reg_ce_rh0_15_8_len 8 -+#define reg_ce_rh0_15_8_lsb 8 -+#define r_reg_ce_rh0_23_16 0xFD3E -+#define reg_ce_rh0_23_16_pos 0 -+#define reg_ce_rh0_23_16_len 8 -+#define reg_ce_rh0_23_16_lsb 16 -+#define r_reg_ce_rh0_31_24 0xFD3F -+#define reg_ce_rh0_31_24_pos 0 -+#define reg_ce_rh0_31_24_len 8 -+#define reg_ce_rh0_31_24_lsb 24 -+#define p_reg_ce_tdi_delta 0xFD40 -+#define reg_ce_tdi_delta_pos 0 -+#define reg_ce_tdi_delta_len 3 -+#define reg_ce_tdi_delta_lsb 0 -+#define p_reg_ce_fdi_delta 0xFD41 -+#define reg_ce_fdi_delta_pos 0 -+#define reg_ce_fdi_delta_len 3 -+#define reg_ce_fdi_delta_lsb 0 -+#define p_reg_ce_fste_delta 0xFD42 -+#define reg_ce_fste_delta_pos 0 -+#define reg_ce_fste_delta_len 3 -+#define reg_ce_fste_delta_lsb 0 -+#define r_reg_ce_fft_s1 0xFD43 -+#define reg_ce_fft_s1_pos 0 -+#define reg_ce_fft_s1_len 4 -+#define reg_ce_fft_s1_lsb 0 -+#define r_reg_feq_fix_eh2_7_0 0xFD44 -+#define reg_feq_fix_eh2_7_0_pos 0 -+#define reg_feq_fix_eh2_7_0_len 8 -+#define reg_feq_fix_eh2_7_0_lsb 0 -+#define r_reg_feq_fix_eh2_15_8 0xFD45 -+#define reg_feq_fix_eh2_15_8_pos 0 -+#define reg_feq_fix_eh2_15_8_len 8 -+#define reg_feq_fix_eh2_15_8_lsb 8 -+#define r_reg_feq_fix_eh2_23_16 0xFD46 -+#define reg_feq_fix_eh2_23_16_pos 0 -+#define reg_feq_fix_eh2_23_16_len 8 -+#define reg_feq_fix_eh2_23_16_lsb 16 -+#define r_reg_feq_fix_eh2_31_24 0xFD47 -+#define reg_feq_fix_eh2_31_24_pos 0 -+#define reg_feq_fix_eh2_31_24_len 8 -+#define reg_feq_fix_eh2_31_24_lsb 24 -+#define r_reg_ce_m2_central_7_0 0xFD48 -+#define reg_ce_m2_central_7_0_pos 0 -+#define reg_ce_m2_central_7_0_len 8 -+#define reg_ce_m2_central_7_0_lsb 0 -+#define r_reg_ce_m2_central_15_8 0xFD49 -+#define reg_ce_m2_central_15_8_pos 0 -+#define reg_ce_m2_central_15_8_len 8 -+#define reg_ce_m2_central_15_8_lsb 8 -+#define r_reg_ce_sigma2_7_0 0xFD4A -+#define reg_ce_sigma2_7_0_pos 0 -+#define reg_ce_sigma2_7_0_len 8 -+#define reg_ce_sigma2_7_0_lsb 0 -+#define r_reg_ce_sigma2_15_8 0xFD4B -+#define reg_ce_sigma2_15_8_pos 0 -+#define reg_ce_sigma2_15_8_len 8 -+#define reg_ce_sigma2_15_8_lsb 8 -+#define r_reg_ce_sigma2_19_16 0xFD4C -+#define reg_ce_sigma2_19_16_pos 0 -+#define reg_ce_sigma2_19_16_len 4 -+#define reg_ce_sigma2_19_16_lsb 16 -+#define r_reg_ce_data_im_7_0 0xFD4D -+#define reg_ce_data_im_7_0_pos 0 -+#define reg_ce_data_im_7_0_len 8 -+#define reg_ce_data_im_7_0_lsb 0 -+#define r_reg_ce_data_im_14_8 0xFD4E -+#define reg_ce_data_im_14_8_pos 0 -+#define reg_ce_data_im_14_8_len 7 -+#define reg_ce_data_im_14_8_lsb 8 -+#define r_reg_ce_data_re_7_0 0xFD4F -+#define reg_ce_data_re_7_0_pos 0 -+#define reg_ce_data_re_7_0_len 8 -+#define reg_ce_data_re_7_0_lsb 0 -+#define r_reg_ce_data_re_14_8 0xFD50 -+#define reg_ce_data_re_14_8_pos 0 -+#define reg_ce_data_re_14_8_len 7 -+#define reg_ce_data_re_14_8_lsb 8 -+#define p_reg_ce_var_default_value 0xFD51 -+#define reg_ce_var_default_value_pos 0 -+#define reg_ce_var_default_value_len 3 -+#define reg_ce_var_default_value_lsb 0 -+#define p_reg_ce_cent_default_value_7_0 0xFD52 -+#define reg_ce_cent_default_value_7_0_pos 0 -+#define reg_ce_cent_default_value_7_0_len 8 -+#define reg_ce_cent_default_value_7_0_lsb 0 -+#define p_reg_ce_cent_default_value_11_8 0xFD53 -+#define reg_ce_cent_default_value_11_8_pos 0 -+#define reg_ce_cent_default_value_11_8_len 4 -+#define reg_ce_cent_default_value_11_8_lsb 8 -+#define r_reg_ce_var_hw 0xFD54 -+#define reg_ce_var_hw_pos 0 -+#define reg_ce_var_hw_len 3 -+#define reg_ce_var_hw_lsb 0 -+#define r_reg_ce_cent_hw_7_0 0xFD55 -+#define reg_ce_cent_hw_7_0_pos 0 -+#define reg_ce_cent_hw_7_0_len 8 -+#define reg_ce_cent_hw_7_0_lsb 0 -+#define r_reg_ce_cent_hw_11_8 0xFD56 -+#define reg_ce_cent_hw_11_8_pos 0 -+#define reg_ce_cent_hw_11_8_len 4 -+#define reg_ce_cent_hw_11_8_lsb 8 -+#define p_reg_ce_fdi_cp_test_en 0xFD57 -+#define reg_ce_fdi_cp_test_en_pos 0 -+#define reg_ce_fdi_cp_test_en_len 1 -+#define reg_ce_fdi_cp_test_en_lsb 0 -+#define p_reg_ce_cptestindex0_7_0 0xFD58 -+#define reg_ce_cptestindex0_7_0_pos 0 -+#define reg_ce_cptestindex0_7_0_len 8 -+#define reg_ce_cptestindex0_7_0_lsb 0 -+#define p_reg_ce_cptestindex0_12_8 0xFD59 -+#define reg_ce_cptestindex0_12_8_pos 0 -+#define reg_ce_cptestindex0_12_8_len 5 -+#define reg_ce_cptestindex0_12_8_lsb 8 -+#define p_reg_ce_cptestfdi0 0xFD5A -+#define reg_ce_cptestfdi0_pos 0 -+#define reg_ce_cptestfdi0_len 3 -+#define reg_ce_cptestfdi0_lsb 0 -+#define p_reg_ce_cptestindex1_7_0 0xFD5B -+#define reg_ce_cptestindex1_7_0_pos 0 -+#define reg_ce_cptestindex1_7_0_len 8 -+#define reg_ce_cptestindex1_7_0_lsb 0 -+#define p_reg_ce_cptestindex1_12_8 0xFD5C -+#define reg_ce_cptestindex1_12_8_pos 0 -+#define reg_ce_cptestindex1_12_8_len 5 -+#define reg_ce_cptestindex1_12_8_lsb 8 -+#define p_reg_ce_cptestfdi1 0xFD5D -+#define reg_ce_cptestfdi1_pos 0 -+#define reg_ce_cptestfdi1_len 3 -+#define reg_ce_cptestfdi1_lsb 0 -+#define p_reg_ce_cptestindex2_7_0 0xFD5E -+#define reg_ce_cptestindex2_7_0_pos 0 -+#define reg_ce_cptestindex2_7_0_len 8 -+#define reg_ce_cptestindex2_7_0_lsb 0 -+#define p_reg_ce_cptestindex2_12_8 0xFD5F -+#define reg_ce_cptestindex2_12_8_pos 0 -+#define reg_ce_cptestindex2_12_8_len 5 -+#define reg_ce_cptestindex2_12_8_lsb 8 -+#define p_reg_ce_cptestfdi2 0xFD60 -+#define reg_ce_cptestfdi2_pos 0 -+#define reg_ce_cptestfdi2_len 3 -+#define reg_ce_cptestfdi2_lsb 0 -+#define p_reg_ce_cptestindex3_7_0 0xFD61 -+#define reg_ce_cptestindex3_7_0_pos 0 -+#define reg_ce_cptestindex3_7_0_len 8 -+#define reg_ce_cptestindex3_7_0_lsb 0 -+#define p_reg_ce_cptestindex3_12_8 0xFD62 -+#define reg_ce_cptestindex3_12_8_pos 0 -+#define reg_ce_cptestindex3_12_8_len 5 -+#define reg_ce_cptestindex3_12_8_lsb 8 -+#define p_reg_ce_cptestfdi3 0xFD63 -+#define reg_ce_cptestfdi3_pos 0 -+#define reg_ce_cptestfdi3_len 3 -+#define reg_ce_cptestfdi3_lsb 0 -+#define p_reg_ce_cptestindex4_7_0 0xFD64 -+#define reg_ce_cptestindex4_7_0_pos 0 -+#define reg_ce_cptestindex4_7_0_len 8 -+#define reg_ce_cptestindex4_7_0_lsb 0 -+#define p_reg_ce_cptestindex4_12_8 0xFD65 -+#define reg_ce_cptestindex4_12_8_pos 0 -+#define reg_ce_cptestindex4_12_8_len 5 -+#define reg_ce_cptestindex4_12_8_lsb 8 -+#define p_reg_ce_cptestfdi4 0xFD66 -+#define reg_ce_cptestfdi4_pos 0 -+#define reg_ce_cptestfdi4_len 3 -+#define reg_ce_cptestfdi4_lsb 0 -+#define p_reg_ce_cptestindex5_7_0 0xFD67 -+#define reg_ce_cptestindex5_7_0_pos 0 -+#define reg_ce_cptestindex5_7_0_len 8 -+#define reg_ce_cptestindex5_7_0_lsb 0 -+#define p_reg_ce_cptestindex5_12_8 0xFD68 -+#define reg_ce_cptestindex5_12_8_pos 0 -+#define reg_ce_cptestindex5_12_8_len 5 -+#define reg_ce_cptestindex5_12_8_lsb 8 -+#define p_reg_ce_cptestfdi5 0xFD69 -+#define reg_ce_cptestfdi5_pos 0 -+#define reg_ce_cptestfdi5_len 3 -+#define reg_ce_cptestfdi5_lsb 0 -+#define p_reg_ce_cptestindex6_7_0 0xFD6A -+#define reg_ce_cptestindex6_7_0_pos 0 -+#define reg_ce_cptestindex6_7_0_len 8 -+#define reg_ce_cptestindex6_7_0_lsb 0 -+#define p_reg_ce_cptestindex6_12_8 0xFD6B -+#define reg_ce_cptestindex6_12_8_pos 0 -+#define reg_ce_cptestindex6_12_8_len 5 -+#define reg_ce_cptestindex6_12_8_lsb 8 -+#define p_reg_ce_cptestfdi6 0xFD6C -+#define reg_ce_cptestfdi6_pos 0 -+#define reg_ce_cptestfdi6_len 3 -+#define reg_ce_cptestfdi6_lsb 0 -+#define p_reg_ce_cptestindex7_7_0 0xFD6D -+#define reg_ce_cptestindex7_7_0_pos 0 -+#define reg_ce_cptestindex7_7_0_len 8 -+#define reg_ce_cptestindex7_7_0_lsb 0 -+#define p_reg_ce_cptestindex7_12_8 0xFD6E -+#define reg_ce_cptestindex7_12_8_pos 0 -+#define reg_ce_cptestindex7_12_8_len 5 -+#define reg_ce_cptestindex7_12_8_lsb 8 -+#define p_reg_ce_cptestfdi7 0xFD6F -+#define reg_ce_cptestfdi7_pos 0 -+#define reg_ce_cptestfdi7_len 3 -+#define reg_ce_cptestfdi7_lsb 0 -+#define p_reg_ce_cp_replace_tdiout_en 0xFD74 -+#define reg_ce_cp_replace_tdiout_en_pos 0 -+#define reg_ce_cp_replace_tdiout_en_len 1 -+#define reg_ce_cp_replace_tdiout_en_lsb 0 -+#define p_reg_ce_tdi_mask0_en 0xFD7D -+#define reg_ce_tdi_mask0_en_pos 0 -+#define reg_ce_tdi_mask0_en_len 1 -+#define reg_ce_tdi_mask0_en_lsb 0 -+#define p_reg_ce_tdi_mask_from0_7_0 0xFD7E -+#define reg_ce_tdi_mask_from0_7_0_pos 0 -+#define reg_ce_tdi_mask_from0_7_0_len 8 -+#define reg_ce_tdi_mask_from0_7_0_lsb 0 -+#define p_reg_ce_tdi_mask_from0_12_8 0xFD7F -+#define reg_ce_tdi_mask_from0_12_8_pos 0 -+#define reg_ce_tdi_mask_from0_12_8_len 5 -+#define reg_ce_tdi_mask_from0_12_8_lsb 8 -+#define p_reg_ce_tdi_mask_to0_7_0 0xFD80 -+#define reg_ce_tdi_mask_to0_7_0_pos 0 -+#define reg_ce_tdi_mask_to0_7_0_len 8 -+#define reg_ce_tdi_mask_to0_7_0_lsb 0 -+#define p_reg_ce_tdi_mask_to0_12_8 0xFD81 -+#define reg_ce_tdi_mask_to0_12_8_pos 0 -+#define reg_ce_tdi_mask_to0_12_8_len 5 -+#define reg_ce_tdi_mask_to0_12_8_lsb 8 -+#define p_reg_ce_tdi_mask1_en 0xFD82 -+#define reg_ce_tdi_mask1_en_pos 0 -+#define reg_ce_tdi_mask1_en_len 1 -+#define reg_ce_tdi_mask1_en_lsb 0 -+#define p_reg_ce_tdi_mask_from1_7_0 0xFD83 -+#define reg_ce_tdi_mask_from1_7_0_pos 0 -+#define reg_ce_tdi_mask_from1_7_0_len 8 -+#define reg_ce_tdi_mask_from1_7_0_lsb 0 -+#define p_reg_ce_tdi_mask_from1_12_8 0xFD84 -+#define reg_ce_tdi_mask_from1_12_8_pos 0 -+#define reg_ce_tdi_mask_from1_12_8_len 5 -+#define reg_ce_tdi_mask_from1_12_8_lsb 8 -+#define p_reg_ce_tdi_mask_to1_7_0 0xFD85 -+#define reg_ce_tdi_mask_to1_7_0_pos 0 -+#define reg_ce_tdi_mask_to1_7_0_len 8 -+#define reg_ce_tdi_mask_to1_7_0_lsb 0 -+#define p_reg_ce_tdi_mask_to1_12_8 0xFD86 -+#define reg_ce_tdi_mask_to1_12_8_pos 0 -+#define reg_ce_tdi_mask_to1_12_8_len 5 -+#define reg_ce_tdi_mask_to1_12_8_lsb 8 -+#define p_reg_ce_2nd_var_max 0xFD87 -+#define reg_ce_2nd_var_max_pos 0 -+#define reg_ce_2nd_var_max_len 3 -+#define reg_ce_2nd_var_max_lsb 0 -+#define p_reg_ce_2nd_cent_forced_en 0xFD88 -+#define reg_ce_2nd_cent_forced_en_pos 0 -+#define reg_ce_2nd_cent_forced_en_len 1 -+#define reg_ce_2nd_cent_forced_en_lsb 0 -+#define p_reg_ce_2nd_var_forced_en 0xFD89 -+#define reg_ce_2nd_var_forced_en_pos 0 -+#define reg_ce_2nd_var_forced_en_len 1 -+#define reg_ce_2nd_var_forced_en_lsb 0 -+#define p_reg_ce_2nd_fctrl_auto_reset_en 0xFD8A -+#define reg_ce_2nd_fctrl_auto_reset_en_pos 0 -+#define reg_ce_2nd_fctrl_auto_reset_en_len 1 -+#define reg_ce_2nd_fctrl_auto_reset_en_lsb 0 -+#define p_reg_ce_2nd_cent_auto_clr_en 0xFD8B -+#define reg_ce_2nd_cent_auto_clr_en_pos 0 -+#define reg_ce_2nd_cent_auto_clr_en_len 1 -+#define reg_ce_2nd_cent_auto_clr_en_lsb 0 -+#define p_reg_ce_2nd_cent_forced_value_7_0 0xFD8C -+#define reg_ce_2nd_cent_forced_value_7_0_pos 0 -+#define reg_ce_2nd_cent_forced_value_7_0_len 8 -+#define reg_ce_2nd_cent_forced_value_7_0_lsb 0 -+#define p_reg_ce_2nd_cent_forced_value_11_8 0xFD8D -+#define reg_ce_2nd_cent_forced_value_11_8_pos 0 -+#define reg_ce_2nd_cent_forced_value_11_8_len 4 -+#define reg_ce_2nd_cent_forced_value_11_8_lsb 8 -+#define p_reg_ce_2nd_cent_auto_clr_value_7_0 0xFD8E -+#define reg_ce_2nd_cent_auto_clr_value_7_0_pos 0 -+#define reg_ce_2nd_cent_auto_clr_value_7_0_len 8 -+#define reg_ce_2nd_cent_auto_clr_value_7_0_lsb 0 -+#define p_reg_ce_2nd_cent_auto_clr_value_11_8 0xFD8F -+#define reg_ce_2nd_cent_auto_clr_value_11_8_pos 0 -+#define reg_ce_2nd_cent_auto_clr_value_11_8_len 4 -+#define reg_ce_2nd_cent_auto_clr_value_11_8_lsb 8 -+#define p_reg_ce_gs_s1_var 0xFD90 -+#define reg_ce_gs_s1_var_pos 0 -+#define reg_ce_gs_s1_var_len 4 -+#define reg_ce_gs_s1_var_lsb 0 -+#define p_reg_ce_2nd_centroid_max_7_0 0xFD91 -+#define reg_ce_2nd_centroid_max_7_0_pos 0 -+#define reg_ce_2nd_centroid_max_7_0_len 8 -+#define reg_ce_2nd_centroid_max_7_0_lsb 0 -+#define p_reg_ce_2nd_centroid_max_11_8 0xFD92 -+#define reg_ce_2nd_centroid_max_11_8_pos 0 -+#define reg_ce_2nd_centroid_max_11_8_len 4 -+#define reg_ce_2nd_centroid_max_11_8_lsb 8 -+#define r_reg_ce_2nd_centroid_out_7_0 0xFD93 -+#define reg_ce_2nd_centroid_out_7_0_pos 0 -+#define reg_ce_2nd_centroid_out_7_0_len 8 -+#define reg_ce_2nd_centroid_out_7_0_lsb 0 -+#define r_reg_ce_2nd_centroid_out_11_8 0xFD94 -+#define reg_ce_2nd_centroid_out_11_8_pos 0 -+#define reg_ce_2nd_centroid_out_11_8_len 4 -+#define reg_ce_2nd_centroid_out_11_8_lsb 8 -+#define r_reg_ce_2nd_fctrl_rdy 0xFD95 -+#define reg_ce_2nd_fctrl_rdy_pos 0 -+#define reg_ce_2nd_fctrl_rdy_len 1 -+#define reg_ce_2nd_fctrl_rdy_lsb 0 -+#define r_reg_ce_2nd_var 0xFD96 -+#define reg_ce_2nd_var_pos 0 -+#define reg_ce_2nd_var_len 3 -+#define reg_ce_2nd_var_lsb 0 -+#define r_reg_ce_2nd_bias_7_0 0xFD97 -+#define reg_ce_2nd_bias_7_0_pos 0 -+#define reg_ce_2nd_bias_7_0_len 8 -+#define reg_ce_2nd_bias_7_0_lsb 0 -+#define r_reg_ce_2nd_bias_11_8 0xFD98 -+#define reg_ce_2nd_bias_11_8_pos 0 -+#define reg_ce_2nd_bias_11_8_len 4 -+#define reg_ce_2nd_bias_11_8_lsb 8 -+#define r_reg_ce_2nd_m1_7_0 0xFD99 -+#define reg_ce_2nd_m1_7_0_pos 0 -+#define reg_ce_2nd_m1_7_0_len 8 -+#define reg_ce_2nd_m1_7_0_lsb 0 -+#define r_reg_ce_2nd_m1_11_8 0xFD9A -+#define reg_ce_2nd_m1_11_8_pos 0 -+#define reg_ce_2nd_m1_11_8_len 4 -+#define reg_ce_2nd_m1_11_8_lsb 8 -+#define p_reg_ce_2nd_var_forced_value 0xFD9B -+#define reg_ce_2nd_var_forced_value_pos 0 -+#define reg_ce_2nd_var_forced_value_len 3 -+#define reg_ce_2nd_var_forced_value_lsb 0 -+#define r_reg_ce_2nd_m2_central_7_0 0xFD9C -+#define reg_ce_2nd_m2_central_7_0_pos 0 -+#define reg_ce_2nd_m2_central_7_0_len 8 -+#define reg_ce_2nd_m2_central_7_0_lsb 0 -+#define r_reg_ce_2nd_m2_central_15_8 0xFD9D -+#define reg_ce_2nd_m2_central_15_8_pos 0 -+#define reg_ce_2nd_m2_central_15_8_len 8 -+#define reg_ce_2nd_m2_central_15_8_lsb 8 -+#define p_reg_ce_2nd_var_default_value 0xFD9E -+#define reg_ce_2nd_var_default_value_pos 0 -+#define reg_ce_2nd_var_default_value_len 3 -+#define reg_ce_2nd_var_default_value_lsb 0 -+#define p_reg_ce_2nd_cent_default_value_7_0 0xFD9F -+#define reg_ce_2nd_cent_default_value_7_0_pos 0 -+#define reg_ce_2nd_cent_default_value_7_0_len 8 -+#define reg_ce_2nd_cent_default_value_7_0_lsb 0 -+#define p_reg_ce_2nd_cent_default_value_11_8 0xFDA0 -+#define reg_ce_2nd_cent_default_value_11_8_pos 0 -+#define reg_ce_2nd_cent_default_value_11_8_len 4 -+#define reg_ce_2nd_cent_default_value_11_8_lsb 8 -+#define p_reg_ce_use_fdi_long 0xFDA1 -+#define reg_ce_use_fdi_long_pos 0 -+#define reg_ce_use_fdi_long_len 1 -+#define reg_ce_use_fdi_long_lsb 0 -+#define p_reg_p_ce_tdi_lms_en 0xFDA2 -+#define reg_p_ce_tdi_lms_en_pos 0 -+#define reg_p_ce_tdi_lms_en_len 1 -+#define reg_p_ce_tdi_lms_en_lsb 0 -+#define p_reg_p_ce_tdi_lms_bufshift 0xFDA3 -+#define reg_p_ce_tdi_lms_bufshift_pos 0 -+#define reg_p_ce_tdi_lms_bufshift_len 2 -+#define reg_p_ce_tdi_lms_bufshift_lsb 0 -+#define p_reg_p_ce_tdi_lms_ave_ratio 0xFDA4 -+#define reg_p_ce_tdi_lms_ave_ratio_pos 0 -+#define reg_p_ce_tdi_lms_ave_ratio_len 5 -+#define reg_p_ce_tdi_lms_ave_ratio_lsb 0 -+#define p_reg_p_ce_conf2_in_con0_en 0xFDA5 -+#define reg_p_ce_conf2_in_con0_en_pos 0 -+#define reg_p_ce_conf2_in_con0_en_len 1 -+#define reg_p_ce_conf2_in_con0_en_lsb 0 -+#define p_fec_rsd_packet_unit_7_0 0xF700 -+#define fec_rsd_packet_unit_7_0_pos 0 -+#define fec_rsd_packet_unit_7_0_len 8 -+#define fec_rsd_packet_unit_7_0_lsb 0 -+#define p_fec_rsd_packet_unit_15_8 0xF701 -+#define fec_rsd_packet_unit_15_8_pos 0 -+#define fec_rsd_packet_unit_15_8_len 8 -+#define fec_rsd_packet_unit_15_8_lsb 8 -+#define r_reg_rsd_bit_err_cnt_7_0 0xF702 -+#define reg_rsd_bit_err_cnt_7_0_pos 0 -+#define reg_rsd_bit_err_cnt_7_0_len 8 -+#define reg_rsd_bit_err_cnt_7_0_lsb 0 -+#define r_reg_rsd_bit_err_cnt_15_8 0xF703 -+#define reg_rsd_bit_err_cnt_15_8_pos 0 -+#define reg_rsd_bit_err_cnt_15_8_len 8 -+#define reg_rsd_bit_err_cnt_15_8_lsb 8 -+#define r_reg_rsd_bit_err_cnt_23_16 0xF704 -+#define reg_rsd_bit_err_cnt_23_16_pos 0 -+#define reg_rsd_bit_err_cnt_23_16_len 8 -+#define reg_rsd_bit_err_cnt_23_16_lsb 16 -+#define r_reg_rsd_abort_packet_cnt_7_0 0xF705 -+#define reg_rsd_abort_packet_cnt_7_0_pos 0 -+#define reg_rsd_abort_packet_cnt_7_0_len 8 -+#define reg_rsd_abort_packet_cnt_7_0_lsb 0 -+#define r_reg_rsd_abort_packet_cnt_15_8 0xF706 -+#define reg_rsd_abort_packet_cnt_15_8_pos 0 -+#define reg_rsd_abort_packet_cnt_15_8_len 8 -+#define reg_rsd_abort_packet_cnt_15_8_lsb 8 -+#define p_fec_RSD_PKT_NUM_PER_UNIT_7_0 0xF707 -+#define fec_RSD_PKT_NUM_PER_UNIT_7_0_pos 0 -+#define fec_RSD_PKT_NUM_PER_UNIT_7_0_len 8 -+#define fec_RSD_PKT_NUM_PER_UNIT_7_0_lsb 0 -+#define p_fec_RSD_PKT_NUM_PER_UNIT_15_8 0xF708 -+#define fec_RSD_PKT_NUM_PER_UNIT_15_8_pos 0 -+#define fec_RSD_PKT_NUM_PER_UNIT_15_8_len 8 -+#define fec_RSD_PKT_NUM_PER_UNIT_15_8_lsb 8 -+#define p_fec_RS_TH_1_7_0 0xF709 -+#define fec_RS_TH_1_7_0_pos 0 -+#define fec_RS_TH_1_7_0_len 8 -+#define fec_RS_TH_1_7_0_lsb 0 -+#define p_fec_RS_TH_1_15_8 0xF70A -+#define fec_RS_TH_1_15_8_pos 0 -+#define fec_RS_TH_1_15_8_len 8 -+#define fec_RS_TH_1_15_8_lsb 8 -+#define p_fec_RS_TH_2 0xF70B -+#define fec_RS_TH_2_pos 0 -+#define fec_RS_TH_2_len 8 -+#define fec_RS_TH_2_lsb 0 -+#define p_fec_rsd_ber_rst 0xF70C -+#define fec_rsd_ber_rst_pos 0 -+#define fec_rsd_ber_rst_len 1 -+#define fec_rsd_ber_rst_lsb 0 -+#define p_reg_rsd_ber_rdy 0xF70D -+#define reg_rsd_ber_rdy_pos 0 -+#define reg_rsd_ber_rdy_len 1 -+#define reg_rsd_ber_rdy_lsb 0 -+#define p_reg_rsd_trigger_retrain 0xF70E -+#define reg_rsd_trigger_retrain_pos 0 -+#define reg_rsd_trigger_retrain_len 1 -+#define reg_rsd_trigger_retrain_lsb 0 -+#define p_reg_sync_recover 0xF70F -+#define reg_sync_recover_pos 0 -+#define reg_sync_recover_len 1 -+#define reg_sync_recover_lsb 0 -+#define p_fec_crc_en 0xF710 -+#define fec_crc_en_pos 0 -+#define fec_crc_en_len 1 -+#define fec_crc_en_lsb 0 -+#define p_fec_mon_en 0xF711 -+#define fec_mon_en_pos 0 -+#define fec_mon_en_len 1 -+#define fec_mon_en_lsb 0 -+#define p_reg_sync_chk 0xF712 -+#define reg_sync_chk_pos 0 -+#define reg_sync_chk_len 1 -+#define reg_sync_chk_lsb 0 -+#define p_fec_dummy_reg_2 0xF713 -+#define fec_dummy_reg_2_pos 0 -+#define fec_dummy_reg_2_len 3 -+#define fec_dummy_reg_2_lsb 0 -+#define p_reg_fec_data_en 0xF714 -+#define reg_fec_data_en_pos 0 -+#define reg_fec_data_en_len 1 -+#define reg_fec_data_en_lsb 0 -+#define p_fec_vtb_rsd_mon_en 0xF715 -+#define fec_vtb_rsd_mon_en_pos 0 -+#define fec_vtb_rsd_mon_en_len 1 -+#define fec_vtb_rsd_mon_en_lsb 0 -+#define p_reg_fec_sw_rst 0xF716 -+#define reg_fec_sw_rst_pos 0 -+#define reg_fec_sw_rst_len 1 -+#define reg_fec_sw_rst_lsb 0 -+#define r_fec_vtb_pm_crc 0xF717 -+#define fec_vtb_pm_crc_pos 0 -+#define fec_vtb_pm_crc_len 8 -+#define fec_vtb_pm_crc_lsb 0 -+#define r_fec_vtb_tb_7_crc 0xF718 -+#define fec_vtb_tb_7_crc_pos 0 -+#define fec_vtb_tb_7_crc_len 8 -+#define fec_vtb_tb_7_crc_lsb 0 -+#define r_fec_vtb_tb_6_crc 0xF719 -+#define fec_vtb_tb_6_crc_pos 0 -+#define fec_vtb_tb_6_crc_len 8 -+#define fec_vtb_tb_6_crc_lsb 0 -+#define r_fec_vtb_tb_5_crc 0xF71A -+#define fec_vtb_tb_5_crc_pos 0 -+#define fec_vtb_tb_5_crc_len 8 -+#define fec_vtb_tb_5_crc_lsb 0 -+#define r_fec_vtb_tb_4_crc 0xF71B -+#define fec_vtb_tb_4_crc_pos 0 -+#define fec_vtb_tb_4_crc_len 8 -+#define fec_vtb_tb_4_crc_lsb 0 -+#define r_fec_vtb_tb_3_crc 0xF71C -+#define fec_vtb_tb_3_crc_pos 0 -+#define fec_vtb_tb_3_crc_len 8 -+#define fec_vtb_tb_3_crc_lsb 0 -+#define r_fec_vtb_tb_2_crc 0xF71D -+#define fec_vtb_tb_2_crc_pos 0 -+#define fec_vtb_tb_2_crc_len 8 -+#define fec_vtb_tb_2_crc_lsb 0 -+#define r_fec_vtb_tb_1_crc 0xF71E -+#define fec_vtb_tb_1_crc_pos 0 -+#define fec_vtb_tb_1_crc_len 8 -+#define fec_vtb_tb_1_crc_lsb 0 -+#define r_fec_vtb_tb_0_crc 0xF71F -+#define fec_vtb_tb_0_crc_pos 0 -+#define fec_vtb_tb_0_crc_len 8 -+#define fec_vtb_tb_0_crc_lsb 0 -+#define r_fec_rsd_bank0_crc 0xF720 -+#define fec_rsd_bank0_crc_pos 0 -+#define fec_rsd_bank0_crc_len 8 -+#define fec_rsd_bank0_crc_lsb 0 -+#define r_fec_rsd_bank1_crc 0xF721 -+#define fec_rsd_bank1_crc_pos 0 -+#define fec_rsd_bank1_crc_len 8 -+#define fec_rsd_bank1_crc_lsb 0 -+#define r_fec_idi_vtb_crc 0xF722 -+#define fec_idi_vtb_crc_pos 0 -+#define fec_idi_vtb_crc_len 8 -+#define fec_idi_vtb_crc_lsb 0 -+#define p_reg_fec_rsd_packet_unit_exp 0xF723 -+#define reg_fec_rsd_packet_unit_exp_pos 0 -+#define reg_fec_rsd_packet_unit_exp_len 4 -+#define reg_fec_rsd_packet_unit_exp_lsb 0 -+#define p_reg_rsd_bit_err_exp_rdy 0xF724 -+#define reg_rsd_bit_err_exp_rdy_pos 0 -+#define reg_rsd_bit_err_exp_rdy_len 1 -+#define reg_rsd_bit_err_exp_rdy_lsb 0 -+#define r_reg_rsd_bit_err_exp 0xF725 -+#define reg_rsd_bit_err_exp_pos 0 -+#define reg_rsd_bit_err_exp_len 5 -+#define reg_rsd_bit_err_exp_lsb 0 -+#define p_fec_rsd_packet_unit1_7_0 0xF726 -+#define fec_rsd_packet_unit1_7_0_pos 0 -+#define fec_rsd_packet_unit1_7_0_len 8 -+#define fec_rsd_packet_unit1_7_0_lsb 0 -+#define p_fec_rsd_packet_unit1_15_8 0xF727 -+#define fec_rsd_packet_unit1_15_8_pos 0 -+#define fec_rsd_packet_unit1_15_8_len 8 -+#define fec_rsd_packet_unit1_15_8_lsb 8 -+#define r_reg_rsd_bit_err_cnt1_7_0 0xF728 -+#define reg_rsd_bit_err_cnt1_7_0_pos 0 -+#define reg_rsd_bit_err_cnt1_7_0_len 8 -+#define reg_rsd_bit_err_cnt1_7_0_lsb 0 -+#define r_reg_rsd_bit_err_cnt1_15_8 0xF729 -+#define reg_rsd_bit_err_cnt1_15_8_pos 0 -+#define reg_rsd_bit_err_cnt1_15_8_len 8 -+#define reg_rsd_bit_err_cnt1_15_8_lsb 8 -+#define r_reg_rsd_bit_err_cnt1_23_16 0xF72A -+#define reg_rsd_bit_err_cnt1_23_16_pos 0 -+#define reg_rsd_bit_err_cnt1_23_16_len 8 -+#define reg_rsd_bit_err_cnt1_23_16_lsb 16 -+#define r_reg_rsd_abort_packet_cnt1_7_0 0xF72B -+#define reg_rsd_abort_packet_cnt1_7_0_pos 0 -+#define reg_rsd_abort_packet_cnt1_7_0_len 8 -+#define reg_rsd_abort_packet_cnt1_7_0_lsb 0 -+#define r_reg_rsd_abort_packet_cnt1_15_8 0xF72C -+#define reg_rsd_abort_packet_cnt1_15_8_pos 0 -+#define reg_rsd_abort_packet_cnt1_15_8_len 8 -+#define reg_rsd_abort_packet_cnt1_15_8_lsb 8 -+#define p_fec_rsd_ber_rst1 0xF72D -+#define fec_rsd_ber_rst1_pos 0 -+#define fec_rsd_ber_rst1_len 1 -+#define fec_rsd_ber_rst1_lsb 0 -+#define p_reg_rsd_ber_rdy1 0xF72E -+#define reg_rsd_ber_rdy1_pos 0 -+#define reg_rsd_ber_rdy1_len 1 -+#define reg_rsd_ber_rdy1_lsb 0 -+#define p_reg_dca_txmod_sel 0xF72F -+#define reg_dca_txmod_sel_pos 0 -+#define reg_dca_txmod_sel_len 1 -+#define reg_dca_txmod_sel_lsb 0 -+#define p_reg_dca_platch 0xF730 -+#define reg_dca_platch_pos 0 -+#define reg_dca_platch_len 1 -+#define reg_dca_platch_lsb 0 -+#define p_reg_dca_upper_chip 0xF731 -+#define reg_dca_upper_chip_pos 0 -+#define reg_dca_upper_chip_len 1 -+#define reg_dca_upper_chip_lsb 0 -+#define p_reg_dca_lower_chip 0xF732 -+#define reg_dca_lower_chip_pos 0 -+#define reg_dca_lower_chip_len 1 -+#define reg_dca_lower_chip_lsb 0 -+#define p_reg_dca_enl 0xF733 -+#define reg_dca_enl_pos 0 -+#define reg_dca_enl_len 1 -+#define reg_dca_enl_lsb 0 -+#define p_reg_dca_enu 0xF734 -+#define reg_dca_enu_pos 0 -+#define reg_dca_enu_len 1 -+#define reg_dca_enu_lsb 0 -+#define p_reg_dca_th 0xF735 -+#define reg_dca_th_pos 0 -+#define reg_dca_th_len 5 -+#define reg_dca_th_lsb 0 -+#define p_reg_dca_scale 0xF736 -+#define reg_dca_scale_pos 0 -+#define reg_dca_scale_len 4 -+#define reg_dca_scale_lsb 0 -+#define p_reg_dca_tone_7_0 0xF737 -+#define reg_dca_tone_7_0_pos 0 -+#define reg_dca_tone_7_0_len 8 -+#define reg_dca_tone_7_0_lsb 0 -+#define p_reg_dca_tone_12_8 0xF738 -+#define reg_dca_tone_12_8_pos 0 -+#define reg_dca_tone_12_8_len 5 -+#define reg_dca_tone_12_8_lsb 8 -+#define p_reg_dca_time_7_0 0xF739 -+#define reg_dca_time_7_0_pos 0 -+#define reg_dca_time_7_0_len 8 -+#define reg_dca_time_7_0_lsb 0 -+#define p_reg_dca_time_15_8 0xF73A -+#define reg_dca_time_15_8_pos 0 -+#define reg_dca_time_15_8_len 8 -+#define reg_dca_time_15_8_lsb 8 -+#define r_fec_dcasm 0xF73B -+#define fec_dcasm_pos 0 -+#define fec_dcasm_len 3 -+#define fec_dcasm_lsb 0 -+#define p_reg_dca_stand_alone 0xF73C -+#define reg_dca_stand_alone_pos 0 -+#define reg_dca_stand_alone_len 1 -+#define reg_dca_stand_alone_lsb 0 -+#define p_reg_dca_upper_out_en 0xF73D -+#define reg_dca_upper_out_en_pos 0 -+#define reg_dca_upper_out_en_len 1 -+#define reg_dca_upper_out_en_lsb 0 -+#define p_reg_dca_rc_en 0xF73E -+#define reg_dca_rc_en_pos 0 -+#define reg_dca_rc_en_len 1 -+#define reg_dca_rc_en_lsb 0 -+#define p_reg_dca_retrain_send 0xF73F -+#define reg_dca_retrain_send_pos 0 -+#define reg_dca_retrain_send_len 1 -+#define reg_dca_retrain_send_lsb 0 -+#define p_reg_dca_retrain_rec 0xF740 -+#define reg_dca_retrain_rec_pos 0 -+#define reg_dca_retrain_rec_len 1 -+#define reg_dca_retrain_rec_lsb 0 -+#define p_reg_dca_gi_gap 0xF741 -+#define reg_dca_gi_gap_pos 0 -+#define reg_dca_gi_gap_len 8 -+#define reg_dca_gi_gap_lsb 0 -+#define r_reg_dca_rec_up_tpsd_txmod 0xF742 -+#define reg_dca_rec_up_tpsd_txmod_pos 0 -+#define reg_dca_rec_up_tpsd_txmod_len 2 -+#define reg_dca_rec_up_tpsd_txmod_lsb 0 -+#define r_reg_dca_rec_up_tpsd_const 0xF743 -+#define reg_dca_rec_up_tpsd_const_pos 0 -+#define reg_dca_rec_up_tpsd_const_len 2 -+#define reg_dca_rec_up_tpsd_const_lsb 0 -+#define r_reg_dca_rec_up_tpsd_indep 0xF744 -+#define reg_dca_rec_up_tpsd_indep_pos 0 -+#define reg_dca_rec_up_tpsd_indep_len 1 -+#define reg_dca_rec_up_tpsd_indep_lsb 0 -+#define r_reg_dca_rec_up_tpsd_hier 0xF745 -+#define reg_dca_rec_up_tpsd_hier_pos 0 -+#define reg_dca_rec_up_tpsd_hier_len 2 -+#define reg_dca_rec_up_tpsd_hier_lsb 0 -+#define r_reg_dca_rec_up_tpsd_hpcr 0xF746 -+#define reg_dca_rec_up_tpsd_hpcr_pos 0 -+#define reg_dca_rec_up_tpsd_hpcr_len 3 -+#define reg_dca_rec_up_tpsd_hpcr_lsb 0 -+#define r_reg_dca_rec_up_tpsd_lpcr 0xF747 -+#define reg_dca_rec_up_tpsd_lpcr_pos 0 -+#define reg_dca_rec_up_tpsd_lpcr_len 3 -+#define reg_dca_rec_up_tpsd_lpcr_lsb 0 -+#define r_reg_dca_rec_up_tpsd_lock 0xF748 -+#define reg_dca_rec_up_tpsd_lock_pos 0 -+#define reg_dca_rec_up_tpsd_lock_len 1 -+#define reg_dca_rec_up_tpsd_lock_lsb 0 -+#define r_reg_dca_rec_lo_tpsd_txmod 0xF749 -+#define reg_dca_rec_lo_tpsd_txmod_pos 0 -+#define reg_dca_rec_lo_tpsd_txmod_len 2 -+#define reg_dca_rec_lo_tpsd_txmod_lsb 0 -+#define r_reg_dca_rec_lo_tpsd_const 0xF74A -+#define reg_dca_rec_lo_tpsd_const_pos 0 -+#define reg_dca_rec_lo_tpsd_const_len 2 -+#define reg_dca_rec_lo_tpsd_const_lsb 0 -+#define r_reg_dca_rec_lo_tpsd_indep 0xF74B -+#define reg_dca_rec_lo_tpsd_indep_pos 0 -+#define reg_dca_rec_lo_tpsd_indep_len 1 -+#define reg_dca_rec_lo_tpsd_indep_lsb 0 -+#define r_reg_dca_rec_lo_tpsd_hier 0xF74C -+#define reg_dca_rec_lo_tpsd_hier_pos 0 -+#define reg_dca_rec_lo_tpsd_hier_len 2 -+#define reg_dca_rec_lo_tpsd_hier_lsb 0 -+#define r_reg_dca_rec_lo_tpsd_hpcr 0xF74D -+#define reg_dca_rec_lo_tpsd_hpcr_pos 0 -+#define reg_dca_rec_lo_tpsd_hpcr_len 3 -+#define reg_dca_rec_lo_tpsd_hpcr_lsb 0 -+#define r_reg_dca_rec_lo_tpsd_lpcr 0xF74E -+#define reg_dca_rec_lo_tpsd_lpcr_pos 0 -+#define reg_dca_rec_lo_tpsd_lpcr_len 3 -+#define reg_dca_rec_lo_tpsd_lpcr_lsb 0 -+#define r_reg_dca_rec_lo_tpsd_lock 0xF74F -+#define reg_dca_rec_lo_tpsd_lock_pos 0 -+#define reg_dca_rec_lo_tpsd_lock_len 1 -+#define reg_dca_rec_lo_tpsd_lock_lsb 0 -+#define p_reg_dca_gpr_ctr_up_send 0xF750 -+#define reg_dca_gpr_ctr_up_send_pos 0 -+#define reg_dca_gpr_ctr_up_send_len 8 -+#define reg_dca_gpr_ctr_up_send_lsb 0 -+#define p_reg_dca_gpr_dat_up_send_0 0xF751 -+#define reg_dca_gpr_dat_up_send_0_pos 0 -+#define reg_dca_gpr_dat_up_send_0_len 8 -+#define reg_dca_gpr_dat_up_send_0_lsb 0 -+#define p_reg_dca_gpr_dat_up_send_1 0xF752 -+#define reg_dca_gpr_dat_up_send_1_pos 0 -+#define reg_dca_gpr_dat_up_send_1_len 8 -+#define reg_dca_gpr_dat_up_send_1_lsb 0 -+#define p_reg_dca_gpr_dat_up_send_2 0xF753 -+#define reg_dca_gpr_dat_up_send_2_pos 0 -+#define reg_dca_gpr_dat_up_send_2_len 8 -+#define reg_dca_gpr_dat_up_send_2_lsb 0 -+#define p_reg_dca_gpr_dat_up_send_3 0xF754 -+#define reg_dca_gpr_dat_up_send_3_pos 0 -+#define reg_dca_gpr_dat_up_send_3_len 8 -+#define reg_dca_gpr_dat_up_send_3_lsb 0 -+#define p_reg_dca_gpr_dat_up_send_4 0xF755 -+#define reg_dca_gpr_dat_up_send_4_pos 0 -+#define reg_dca_gpr_dat_up_send_4_len 8 -+#define reg_dca_gpr_dat_up_send_4_lsb 0 -+#define p_reg_dca_gpr_dat_up_send_5 0xF756 -+#define reg_dca_gpr_dat_up_send_5_pos 0 -+#define reg_dca_gpr_dat_up_send_5_len 8 -+#define reg_dca_gpr_dat_up_send_5_lsb 0 -+#define p_reg_dca_over_wr_up_send 0xF757 -+#define reg_dca_over_wr_up_send_pos 0 -+#define reg_dca_over_wr_up_send_len 1 -+#define reg_dca_over_wr_up_send_lsb 0 -+#define p_reg_dca_int_up_send 0xF758 -+#define reg_dca_int_up_send_pos 0 -+#define reg_dca_int_up_send_len 1 -+#define reg_dca_int_up_send_lsb 0 -+#define p_reg_dca_gpr_ctr_lo_send 0xF759 -+#define reg_dca_gpr_ctr_lo_send_pos 0 -+#define reg_dca_gpr_ctr_lo_send_len 8 -+#define reg_dca_gpr_ctr_lo_send_lsb 0 -+#define p_reg_dca_gpr_dat_lo_send_0 0xF75A -+#define reg_dca_gpr_dat_lo_send_0_pos 0 -+#define reg_dca_gpr_dat_lo_send_0_len 8 -+#define reg_dca_gpr_dat_lo_send_0_lsb 0 -+#define p_reg_dca_gpr_dat_lo_send_1 0xF75B -+#define reg_dca_gpr_dat_lo_send_1_pos 0 -+#define reg_dca_gpr_dat_lo_send_1_len 8 -+#define reg_dca_gpr_dat_lo_send_1_lsb 0 -+#define p_reg_dca_gpr_dat_lo_send_2 0xF75C -+#define reg_dca_gpr_dat_lo_send_2_pos 0 -+#define reg_dca_gpr_dat_lo_send_2_len 8 -+#define reg_dca_gpr_dat_lo_send_2_lsb 0 -+#define p_reg_dca_gpr_dat_lo_send_3 0xF75D -+#define reg_dca_gpr_dat_lo_send_3_pos 0 -+#define reg_dca_gpr_dat_lo_send_3_len 8 -+#define reg_dca_gpr_dat_lo_send_3_lsb 0 -+#define p_reg_dca_gpr_dat_lo_send_4 0xF75E -+#define reg_dca_gpr_dat_lo_send_4_pos 0 -+#define reg_dca_gpr_dat_lo_send_4_len 8 -+#define reg_dca_gpr_dat_lo_send_4_lsb 0 -+#define p_reg_dca_gpr_dat_lo_send_5 0xF75F -+#define reg_dca_gpr_dat_lo_send_5_pos 0 -+#define reg_dca_gpr_dat_lo_send_5_len 8 -+#define reg_dca_gpr_dat_lo_send_5_lsb 0 -+#define p_reg_dca_over_wr_lo_send 0xF760 -+#define reg_dca_over_wr_lo_send_pos 0 -+#define reg_dca_over_wr_lo_send_len 1 -+#define reg_dca_over_wr_lo_send_lsb 0 -+#define p_reg_dca_int_lo_send 0xF761 -+#define reg_dca_int_lo_send_pos 0 -+#define reg_dca_int_lo_send_len 1 -+#define reg_dca_int_lo_send_lsb 0 -+#define r_reg_dca_gpr_ctr_up_rec 0xF762 -+#define reg_dca_gpr_ctr_up_rec_pos 0 -+#define reg_dca_gpr_ctr_up_rec_len 8 -+#define reg_dca_gpr_ctr_up_rec_lsb 0 -+#define r_reg_dca_gpr_dat_up_rec_0 0xF763 -+#define reg_dca_gpr_dat_up_rec_0_pos 0 -+#define reg_dca_gpr_dat_up_rec_0_len 8 -+#define reg_dca_gpr_dat_up_rec_0_lsb 0 -+#define r_reg_dca_gpr_dat_up_rec_1 0xF764 -+#define reg_dca_gpr_dat_up_rec_1_pos 0 -+#define reg_dca_gpr_dat_up_rec_1_len 8 -+#define reg_dca_gpr_dat_up_rec_1_lsb 0 -+#define r_reg_dca_gpr_dat_up_rec_2 0xF765 -+#define reg_dca_gpr_dat_up_rec_2_pos 0 -+#define reg_dca_gpr_dat_up_rec_2_len 8 -+#define reg_dca_gpr_dat_up_rec_2_lsb 0 -+#define r_reg_dca_gpr_dat_up_rec_3 0xF766 -+#define reg_dca_gpr_dat_up_rec_3_pos 0 -+#define reg_dca_gpr_dat_up_rec_3_len 8 -+#define reg_dca_gpr_dat_up_rec_3_lsb 0 -+#define r_reg_dca_gpr_dat_up_rec_4 0xF767 -+#define reg_dca_gpr_dat_up_rec_4_pos 0 -+#define reg_dca_gpr_dat_up_rec_4_len 8 -+#define reg_dca_gpr_dat_up_rec_4_lsb 0 -+#define r_reg_dca_gpr_dat_up_rec_5 0xF768 -+#define reg_dca_gpr_dat_up_rec_5_pos 0 -+#define reg_dca_gpr_dat_up_rec_5_len 8 -+#define reg_dca_gpr_dat_up_rec_5_lsb 0 -+#define r_reg_dca_over_wr_up_rec 0xF769 -+#define reg_dca_over_wr_up_rec_pos 0 -+#define reg_dca_over_wr_up_rec_len 1 -+#define reg_dca_over_wr_up_rec_lsb 0 -+#define p_reg_dca_int_up_rec 0xF76A -+#define reg_dca_int_up_rec_pos 0 -+#define reg_dca_int_up_rec_len 1 -+#define reg_dca_int_up_rec_lsb 0 -+#define p_reg_dca_fw_read_yet_up 0xF76B -+#define reg_dca_fw_read_yet_up_pos 0 -+#define reg_dca_fw_read_yet_up_len 1 -+#define reg_dca_fw_read_yet_up_lsb 0 -+#define r_reg_dca_gpr_ctr_lo_rec 0xF76C -+#define reg_dca_gpr_ctr_lo_rec_pos 0 -+#define reg_dca_gpr_ctr_lo_rec_len 8 -+#define reg_dca_gpr_ctr_lo_rec_lsb 0 -+#define r_reg_dca_gpr_dat_lo_rec_0 0xF76D -+#define reg_dca_gpr_dat_lo_rec_0_pos 0 -+#define reg_dca_gpr_dat_lo_rec_0_len 8 -+#define reg_dca_gpr_dat_lo_rec_0_lsb 0 -+#define r_reg_dca_gpr_dat_lo_rec_1 0xF76E -+#define reg_dca_gpr_dat_lo_rec_1_pos 0 -+#define reg_dca_gpr_dat_lo_rec_1_len 8 -+#define reg_dca_gpr_dat_lo_rec_1_lsb 0 -+#define r_reg_dca_gpr_dat_lo_rec_2 0xF76F -+#define reg_dca_gpr_dat_lo_rec_2_pos 0 -+#define reg_dca_gpr_dat_lo_rec_2_len 8 -+#define reg_dca_gpr_dat_lo_rec_2_lsb 0 -+#define r_reg_dca_gpr_dat_lo_rec_3 0xF770 -+#define reg_dca_gpr_dat_lo_rec_3_pos 0 -+#define reg_dca_gpr_dat_lo_rec_3_len 8 -+#define reg_dca_gpr_dat_lo_rec_3_lsb 0 -+#define r_reg_dca_gpr_dat_lo_rec_4 0xF771 -+#define reg_dca_gpr_dat_lo_rec_4_pos 0 -+#define reg_dca_gpr_dat_lo_rec_4_len 8 -+#define reg_dca_gpr_dat_lo_rec_4_lsb 0 -+#define r_reg_dca_gpr_dat_lo_rec_5 0xF772 -+#define reg_dca_gpr_dat_lo_rec_5_pos 0 -+#define reg_dca_gpr_dat_lo_rec_5_len 8 -+#define reg_dca_gpr_dat_lo_rec_5_lsb 0 -+#define r_reg_dca_over_wr_lo_rec 0xF773 -+#define reg_dca_over_wr_lo_rec_pos 0 -+#define reg_dca_over_wr_lo_rec_len 1 -+#define reg_dca_over_wr_lo_rec_lsb 0 -+#define p_reg_dca_int_lo_rec 0xF774 -+#define reg_dca_int_lo_rec_pos 0 -+#define reg_dca_int_lo_rec_len 1 -+#define reg_dca_int_lo_rec_lsb 0 -+#define p_reg_dca_fw_read_yet_lo 0xF775 -+#define reg_dca_fw_read_yet_lo_pos 0 -+#define reg_dca_fw_read_yet_lo_len 1 -+#define reg_dca_fw_read_yet_lo_lsb 0 -+#define p_reg_dca_en 0xF776 -+#define reg_dca_en_pos 0 -+#define reg_dca_en_len 1 -+#define reg_dca_en_lsb 0 -+#define p_reg_dca_ulrdy_delay 0xF777 -+#define reg_dca_ulrdy_delay_pos 0 -+#define reg_dca_ulrdy_delay_len 8 -+#define reg_dca_ulrdy_delay_lsb 0 -+#define p_reg_dca_fpga_latch 0xF778 -+#define reg_dca_fpga_latch_pos 0 -+#define reg_dca_fpga_latch_len 8 -+#define reg_dca_fpga_latch_lsb 0 -+#define p_reg_dca_vldld_err 0xF779 -+#define reg_dca_vldld_err_pos 0 -+#define reg_dca_vldld_err_len 1 -+#define reg_dca_vldld_err_lsb 0 -+#define p_reg_dca_vldud_err 0xF77A -+#define reg_dca_vldud_err_pos 0 -+#define reg_dca_vldud_err_len 1 -+#define reg_dca_vldud_err_lsb 0 -+#define p_reg_dca_modeu_err 0xF77B -+#define reg_dca_modeu_err_pos 0 -+#define reg_dca_modeu_err_len 1 -+#define reg_dca_modeu_err_lsb 0 -+#define p_reg_dca_model_err 0xF77C -+#define reg_dca_model_err_pos 0 -+#define reg_dca_model_err_len 1 -+#define reg_dca_model_err_lsb 0 -+#define p_reg_dca_interrupt 0xF77D -+#define reg_dca_interrupt_pos 0 -+#define reg_dca_interrupt_len 1 -+#define reg_dca_interrupt_lsb 0 -+#define p_reg_dca_auto_reset_en 0xF77E -+#define reg_dca_auto_reset_en_pos 0 -+#define reg_dca_auto_reset_en_len 1 -+#define reg_dca_auto_reset_en_lsb 0 -+#define p_reg_qnt_valuew_7_0 0xF77F -+#define reg_qnt_valuew_7_0_pos 0 -+#define reg_qnt_valuew_7_0_len 8 -+#define reg_qnt_valuew_7_0_lsb 0 -+#define p_reg_qnt_valuew_10_8 0xF780 -+#define reg_qnt_valuew_10_8_pos 0 -+#define reg_qnt_valuew_10_8_len 3 -+#define reg_qnt_valuew_10_8_lsb 8 -+#define p_reg_qnt_nfvaluew_7_0 0xF781 -+#define reg_qnt_nfvaluew_7_0_pos 0 -+#define reg_qnt_nfvaluew_7_0_len 8 -+#define reg_qnt_nfvaluew_7_0_lsb 0 -+#define p_reg_qnt_nfvaluew_10_8 0xF782 -+#define reg_qnt_nfvaluew_10_8_pos 0 -+#define reg_qnt_nfvaluew_10_8_len 3 -+#define reg_qnt_nfvaluew_10_8_lsb 8 -+#define p_reg_qnt_flatness_thr_7_0 0xF783 -+#define reg_qnt_flatness_thr_7_0_pos 0 -+#define reg_qnt_flatness_thr_7_0_len 8 -+#define reg_qnt_flatness_thr_7_0_lsb 0 -+#define p_reg_qnt_flatness_thr_8 0xF784 -+#define reg_qnt_flatness_thr_8_pos 0 -+#define reg_qnt_flatness_thr_8_len 1 -+#define reg_qnt_flatness_thr_8_lsb 8 -+#define p_reg_llr_to_be_monitor 0xF785 -+#define reg_llr_to_be_monitor_pos 0 -+#define reg_llr_to_be_monitor_len 1 -+#define reg_llr_to_be_monitor_lsb 0 -+#define p_reg_qnt_vbc_rdy 0xF786 -+#define reg_qnt_vbc_rdy_pos 0 -+#define reg_qnt_vbc_rdy_len 1 -+#define reg_qnt_vbc_rdy_lsb 0 -+#define p_reg_qnt_noncmb_vbc_rdy 0xF787 -+#define reg_qnt_noncmb_vbc_rdy_pos 0 -+#define reg_qnt_noncmb_vbc_rdy_len 1 -+#define reg_qnt_noncmb_vbc_rdy_lsb 0 -+#define p_reg_use_eh2_mean 0xF788 -+#define reg_use_eh2_mean_pos 0 -+#define reg_use_eh2_mean_len 1 -+#define reg_use_eh2_mean_lsb 0 -+#define p_reg_qnt_vbc_ccid_mode 0xF789 -+#define reg_qnt_vbc_ccid_mode_pos 0 -+#define reg_qnt_vbc_ccid_mode_len 1 -+#define reg_qnt_vbc_ccid_mode_lsb 0 -+#define p_reg_qnt_cci_bandsize 0xF78A -+#define reg_qnt_cci_bandsize_pos 0 -+#define reg_qnt_cci_bandsize_len 4 -+#define reg_qnt_cci_bandsize_lsb 0 -+#define p_reg_qnt_vbc_sframe_num 0xF78B -+#define reg_qnt_vbc_sframe_num_pos 0 -+#define reg_qnt_vbc_sframe_num_len 8 -+#define reg_qnt_vbc_sframe_num_lsb 0 -+#define p_reg_sbx_gain_diff_7_0 0xF78C -+#define reg_sbx_gain_diff_7_0_pos 0 -+#define reg_sbx_gain_diff_7_0_len 8 -+#define reg_sbx_gain_diff_7_0_lsb 0 -+#define p_reg_sbx_gain_diff_8 0xF78D -+#define reg_sbx_gain_diff_8_pos 0 -+#define reg_sbx_gain_diff_8_len 1 -+#define reg_sbx_gain_diff_8_lsb 8 -+#define p_reg_sbx_gain_diff_rdy 0xF78E -+#define reg_sbx_gain_diff_rdy_pos 0 -+#define reg_sbx_gain_diff_rdy_len 1 -+#define reg_sbx_gain_diff_rdy_lsb 0 -+#define p_reg_sbx_noncmb_gain_diff_7_0 0xF78F -+#define reg_sbx_noncmb_gain_diff_7_0_pos 0 -+#define reg_sbx_noncmb_gain_diff_7_0_len 8 -+#define reg_sbx_noncmb_gain_diff_7_0_lsb 0 -+#define p_reg_sbx_noncmb_gain_diff_8 0xF790 -+#define reg_sbx_noncmb_gain_diff_8_pos 0 -+#define reg_sbx_noncmb_gain_diff_8_len 1 -+#define reg_sbx_noncmb_gain_diff_8_lsb 8 -+#define p_reg_sbx_noncmb_gain_diff_rdy 0xF791 -+#define reg_sbx_noncmb_gain_diff_rdy_pos 0 -+#define reg_sbx_noncmb_gain_diff_rdy_len 1 -+#define reg_sbx_noncmb_gain_diff_rdy_lsb 0 -+#define r_reg_qnt_vbc_err_7_0 0xF792 -+#define reg_qnt_vbc_err_7_0_pos 0 -+#define reg_qnt_vbc_err_7_0_len 8 -+#define reg_qnt_vbc_err_7_0_lsb 0 -+#define r_reg_qnt_vbc_err_15_8 0xF793 -+#define reg_qnt_vbc_err_15_8_pos 0 -+#define reg_qnt_vbc_err_15_8_len 8 -+#define reg_qnt_vbc_err_15_8_lsb 8 -+#define r_reg_qnt_vbc_err_23_16 0xF794 -+#define reg_qnt_vbc_err_23_16_pos 0 -+#define reg_qnt_vbc_err_23_16_len 8 -+#define reg_qnt_vbc_err_23_16_lsb 16 -+#define r_reg_qnt_noncmb_vbc_err_7_0 0xF795 -+#define reg_qnt_noncmb_vbc_err_7_0_pos 0 -+#define reg_qnt_noncmb_vbc_err_7_0_len 8 -+#define reg_qnt_noncmb_vbc_err_7_0_lsb 0 -+#define r_reg_qnt_noncmb_vbc_err_15_8 0xF796 -+#define reg_qnt_noncmb_vbc_err_15_8_pos 0 -+#define reg_qnt_noncmb_vbc_err_15_8_len 8 -+#define reg_qnt_noncmb_vbc_err_15_8_lsb 8 -+#define r_reg_qnt_noncmb_vbc_err_23_16 0xF797 -+#define reg_qnt_noncmb_vbc_err_23_16_pos 0 -+#define reg_qnt_noncmb_vbc_err_23_16_len 8 -+#define reg_qnt_noncmb_vbc_err_23_16_lsb 16 -+#define p_reg_sbx_signalquality_threshold 0xF798 -+#define reg_sbx_signalquality_threshold_pos 0 -+#define reg_sbx_signalquality_threshold_len 4 -+#define reg_sbx_signalquality_threshold_lsb 0 -+#define r_reg_sbx_signalquality_ind 0xF799 -+#define reg_sbx_signalquality_ind_pos 0 -+#define reg_sbx_signalquality_ind_len 1 -+#define reg_sbx_signalquality_ind_lsb 0 -+#define p_reg_p_sbxqnt_th1 0xF79A -+#define reg_p_sbxqnt_th1_pos 0 -+#define reg_p_sbxqnt_th1_len 8 -+#define reg_p_sbxqnt_th1_lsb 0 -+#define p_reg_p_sbxqnt_th2 0xF79B -+#define reg_p_sbxqnt_th2_pos 0 -+#define reg_p_sbxqnt_th2_len 8 -+#define reg_p_sbxqnt_th2_lsb 0 -+#define p_reg_p_sbxqnt_th3 0xF79C -+#define reg_p_sbxqnt_th3_pos 0 -+#define reg_p_sbxqnt_th3_len 8 -+#define reg_p_sbxqnt_th3_lsb 0 -+#define p_reg_p_sbxqnt_th4 0xF79D -+#define reg_p_sbxqnt_th4_pos 0 -+#define reg_p_sbxqnt_th4_len 8 -+#define reg_p_sbxqnt_th4_lsb 0 -+#define p_reg_p_sbxqnt_th5 0xF79E -+#define reg_p_sbxqnt_th5_pos 0 -+#define reg_p_sbxqnt_th5_len 8 -+#define reg_p_sbxqnt_th5_lsb 0 -+#define p_reg_p_sbxqnt_th6 0xF79F -+#define reg_p_sbxqnt_th6_pos 0 -+#define reg_p_sbxqnt_th6_len 8 -+#define reg_p_sbxqnt_th6_lsb 0 -+#define p_reg_p_sbxqnt_th7 0xF800 -+#define reg_p_sbxqnt_th7_pos 0 -+#define reg_p_sbxqnt_th7_len 8 -+#define reg_p_sbxqnt_th7_lsb 0 -+#define p_reg_p_sbxqnt_th8 0xF801 -+#define reg_p_sbxqnt_th8_pos 0 -+#define reg_p_sbxqnt_th8_len 8 -+#define reg_p_sbxqnt_th8_lsb 0 -+#define p_reg_p_sbxqnt_th9 0xF802 -+#define reg_p_sbxqnt_th9_pos 0 -+#define reg_p_sbxqnt_th9_len 8 -+#define reg_p_sbxqnt_th9_lsb 0 -+#define p_reg_p_sbxqnt_th10 0xF803 -+#define reg_p_sbxqnt_th10_pos 0 -+#define reg_p_sbxqnt_th10_len 8 -+#define reg_p_sbxqnt_th10_lsb 0 -+#define p_reg_p_sbxqnt_th11 0xF804 -+#define reg_p_sbxqnt_th11_pos 0 -+#define reg_p_sbxqnt_th11_len 8 -+#define reg_p_sbxqnt_th11_lsb 0 -+#define p_reg_p_sbxqnt_th12 0xF805 -+#define reg_p_sbxqnt_th12_pos 0 -+#define reg_p_sbxqnt_th12_len 8 -+#define reg_p_sbxqnt_th12_lsb 0 -+#define p_reg_p_sbxqnt_th13_7_0 0xF806 -+#define reg_p_sbxqnt_th13_7_0_pos 0 -+#define reg_p_sbxqnt_th13_7_0_len 8 -+#define reg_p_sbxqnt_th13_7_0_lsb 0 -+#define p_reg_p_sbxqnt_th13_9_8 0xF807 -+#define reg_p_sbxqnt_th13_9_8_pos 0 -+#define reg_p_sbxqnt_th13_9_8_len 2 -+#define reg_p_sbxqnt_th13_9_8_lsb 8 -+#define p_reg_p_sbxqnt_th14_7_0 0xF808 -+#define reg_p_sbxqnt_th14_7_0_pos 0 -+#define reg_p_sbxqnt_th14_7_0_len 8 -+#define reg_p_sbxqnt_th14_7_0_lsb 0 -+#define p_reg_p_sbxqnt_th14_9_8 0xF809 -+#define reg_p_sbxqnt_th14_9_8_pos 0 -+#define reg_p_sbxqnt_th14_9_8_len 2 -+#define reg_p_sbxqnt_th14_9_8_lsb 8 -+#define p_reg_p_sbxqnt_th15_7_0 0xF80A -+#define reg_p_sbxqnt_th15_7_0_pos 0 -+#define reg_p_sbxqnt_th15_7_0_len 8 -+#define reg_p_sbxqnt_th15_7_0_lsb 0 -+#define p_reg_p_sbxqnt_th15_9_8 0xF80B -+#define reg_p_sbxqnt_th15_9_8_pos 0 -+#define reg_p_sbxqnt_th15_9_8_len 2 -+#define reg_p_sbxqnt_th15_9_8_lsb 8 -+#define p_reg_p_sbxqnt_vzh2_th0 0xF80C -+#define reg_p_sbxqnt_vzh2_th0_pos 0 -+#define reg_p_sbxqnt_vzh2_th0_len 8 -+#define reg_p_sbxqnt_vzh2_th0_lsb 0 -+#define p_reg_p_sbxqnt_vzh2_th1 0xF80D -+#define reg_p_sbxqnt_vzh2_th1_pos 0 -+#define reg_p_sbxqnt_vzh2_th1_len 8 -+#define reg_p_sbxqnt_vzh2_th1_lsb 0 -+#define p_reg_p_sbxqnt_vzh2_th2 0xF80E -+#define reg_p_sbxqnt_vzh2_th2_pos 0 -+#define reg_p_sbxqnt_vzh2_th2_len 8 -+#define reg_p_sbxqnt_vzh2_th2_lsb 0 -+#define p_reg_p_qnt_w_comp1 0xF80F -+#define reg_p_qnt_w_comp1_pos 0 -+#define reg_p_qnt_w_comp1_len 8 -+#define reg_p_qnt_w_comp1_lsb 0 -+#define p_reg_p_qnt_w_comp2 0xF810 -+#define reg_p_qnt_w_comp2_pos 0 -+#define reg_p_qnt_w_comp2_len 8 -+#define reg_p_qnt_w_comp2_lsb 0 -+#define p_reg_p_qnt_w_comp3 0xF811 -+#define reg_p_qnt_w_comp3_pos 0 -+#define reg_p_qnt_w_comp3_len 8 -+#define reg_p_qnt_w_comp3_lsb 0 -+#define p_reg_p_vtb_in_0 0xF821 -+#define reg_p_vtb_in_0_pos 0 -+#define reg_p_vtb_in_0_len 6 -+#define reg_p_vtb_in_0_lsb 0 -+#define p_reg_p_vtb_in_1 0xF822 -+#define reg_p_vtb_in_1_pos 0 -+#define reg_p_vtb_in_1_len 6 -+#define reg_p_vtb_in_1_lsb 0 -+#define p_reg_p_vtb_in_2 0xF823 -+#define reg_p_vtb_in_2_pos 0 -+#define reg_p_vtb_in_2_len 6 -+#define reg_p_vtb_in_2_lsb 0 -+#define p_reg_p_vtb_in_3 0xF824 -+#define reg_p_vtb_in_3_pos 0 -+#define reg_p_vtb_in_3_len 6 -+#define reg_p_vtb_in_3_lsb 0 -+#define p_reg_p_vtb_in_4 0xF825 -+#define reg_p_vtb_in_4_pos 0 -+#define reg_p_vtb_in_4_len 6 -+#define reg_p_vtb_in_4_lsb 0 -+#define p_reg_p_vtb_in_5 0xF826 -+#define reg_p_vtb_in_5_pos 0 -+#define reg_p_vtb_in_5_len 6 -+#define reg_p_vtb_in_5_lsb 0 -+#define p_reg_p_vtb_in_6 0xF827 -+#define reg_p_vtb_in_6_pos 0 -+#define reg_p_vtb_in_6_len 6 -+#define reg_p_vtb_in_6_lsb 0 -+#define p_reg_p_vtb_in_7 0xF828 -+#define reg_p_vtb_in_7_pos 0 -+#define reg_p_vtb_in_7_len 6 -+#define reg_p_vtb_in_7_lsb 0 -+#define p_reg_p_vtb_in_8 0xF829 -+#define reg_p_vtb_in_8_pos 0 -+#define reg_p_vtb_in_8_len 6 -+#define reg_p_vtb_in_8_lsb 0 -+#define p_reg_p_vtb_in_9 0xF82A -+#define reg_p_vtb_in_9_pos 0 -+#define reg_p_vtb_in_9_len 6 -+#define reg_p_vtb_in_9_lsb 0 -+#define p_reg_p_vtb_in_10 0xF82B -+#define reg_p_vtb_in_10_pos 0 -+#define reg_p_vtb_in_10_len 6 -+#define reg_p_vtb_in_10_lsb 0 -+#define p_reg_p_vtb_in_11 0xF82C -+#define reg_p_vtb_in_11_pos 0 -+#define reg_p_vtb_in_11_len 6 -+#define reg_p_vtb_in_11_lsb 0 -+#define p_reg_p_vtb_in_12 0xF82D -+#define reg_p_vtb_in_12_pos 0 -+#define reg_p_vtb_in_12_len 6 -+#define reg_p_vtb_in_12_lsb 0 -+#define p_reg_p_vtb_in_13 0xF82E -+#define reg_p_vtb_in_13_pos 0 -+#define reg_p_vtb_in_13_len 6 -+#define reg_p_vtb_in_13_lsb 0 -+#define p_reg_p_vtb_in_14 0xF82F -+#define reg_p_vtb_in_14_pos 0 -+#define reg_p_vtb_in_14_len 6 -+#define reg_p_vtb_in_14_lsb 0 -+#define p_reg_p_vtb_in_15 0xF830 -+#define reg_p_vtb_in_15_pos 0 -+#define reg_p_vtb_in_15_len 6 -+#define reg_p_vtb_in_15_lsb 0 -+#define I2C_i2c_m_slave_addr 0xF940 -+#define i2c_m_slave_addr_pos 0 -+#define i2c_m_slave_addr_len 8 -+#define i2c_m_slave_addr_lsb 0 -+#define I2C_i2c_m_data1 0xF941 -+#define i2c_m_data1_pos 0 -+#define i2c_m_data1_len 8 -+#define i2c_m_data1_lsb 0 -+#define I2C_i2c_m_data2 0xF942 -+#define i2c_m_data2_pos 0 -+#define i2c_m_data2_len 8 -+#define i2c_m_data2_lsb 0 -+#define I2C_i2c_m_data3 0xF943 -+#define i2c_m_data3_pos 0 -+#define i2c_m_data3_len 8 -+#define i2c_m_data3_lsb 0 -+#define I2C_i2c_m_data4 0xF944 -+#define i2c_m_data4_pos 0 -+#define i2c_m_data4_len 8 -+#define i2c_m_data4_lsb 0 -+#define I2C_i2c_m_data5 0xF945 -+#define i2c_m_data5_pos 0 -+#define i2c_m_data5_len 8 -+#define i2c_m_data5_lsb 0 -+#define I2C_i2c_m_data6 0xF946 -+#define i2c_m_data6_pos 0 -+#define i2c_m_data6_len 8 -+#define i2c_m_data6_lsb 0 -+#define I2C_i2c_m_data7 0xF947 -+#define i2c_m_data7_pos 0 -+#define i2c_m_data7_len 8 -+#define i2c_m_data7_lsb 0 -+#define I2C_i2c_m_data8 0xF948 -+#define i2c_m_data8_pos 0 -+#define i2c_m_data8_len 8 -+#define i2c_m_data8_lsb 0 -+#define I2C_i2c_m_data9 0xF949 -+#define i2c_m_data9_pos 0 -+#define i2c_m_data9_len 8 -+#define i2c_m_data9_lsb 0 -+#define I2C_i2c_m_data10 0xF94A -+#define i2c_m_data10_pos 0 -+#define i2c_m_data10_len 8 -+#define i2c_m_data10_lsb 0 -+#define I2C_i2c_m_data11 0xF94B -+#define i2c_m_data11_pos 0 -+#define i2c_m_data11_len 8 -+#define i2c_m_data11_lsb 0 -+#define I2C_i2c_m_data12 0xF94C -+#define i2c_m_data12_pos 0 -+#define i2c_m_data12_len 8 -+#define i2c_m_data12_lsb 0 -+#define I2C_i2c_m_data13 0xF94D -+#define i2c_m_data13_pos 0 -+#define i2c_m_data13_len 8 -+#define i2c_m_data13_lsb 0 -+#define I2C_i2c_m_data14 0xF94E -+#define i2c_m_data14_pos 0 -+#define i2c_m_data14_len 8 -+#define i2c_m_data14_lsb 0 -+#define I2C_i2c_m_data15 0xF94F -+#define i2c_m_data15_pos 0 -+#define i2c_m_data15_len 8 -+#define i2c_m_data15_lsb 0 -+#define I2C_i2c_m_data16 0xF950 -+#define i2c_m_data16_pos 0 -+#define i2c_m_data16_len 8 -+#define i2c_m_data16_lsb 0 -+#define I2C_i2c_m_data17 0xF951 -+#define i2c_m_data17_pos 0 -+#define i2c_m_data17_len 8 -+#define i2c_m_data17_lsb 0 -+#define I2C_i2c_m_data18 0xF952 -+#define i2c_m_data18_pos 0 -+#define i2c_m_data18_len 8 -+#define i2c_m_data18_lsb 0 -+#define I2C_i2c_m_data19 0xF953 -+#define i2c_m_data19_pos 0 -+#define i2c_m_data19_len 8 -+#define i2c_m_data19_lsb 0 -+#define I2C_i2c_m_cmd_rw 0xF954 -+#define i2c_m_cmd_rw_pos 0 -+#define i2c_m_cmd_rw_len 1 -+#define i2c_m_cmd_rw_lsb 0 -+#define I2C_i2c_m_cmd_rwlen 0xF954 -+#define i2c_m_cmd_rwlen_pos 3 -+#define i2c_m_cmd_rwlen_len 4 -+#define i2c_m_cmd_rwlen_lsb 0 -+#define I2C_i2c_m_status_cmd_exe 0xF955 -+#define i2c_m_status_cmd_exe_pos 0 -+#define i2c_m_status_cmd_exe_len 1 -+#define i2c_m_status_cmd_exe_lsb 0 -+#define I2C_i2c_m_status_wdat_done 0xF955 -+#define i2c_m_status_wdat_done_pos 1 -+#define i2c_m_status_wdat_done_len 1 -+#define i2c_m_status_wdat_done_lsb 0 -+#define I2C_i2c_m_status_wdat_fail 0xF955 -+#define i2c_m_status_wdat_fail_pos 2 -+#define i2c_m_status_wdat_fail_len 1 -+#define i2c_m_status_wdat_fail_lsb 0 -+#define I2C_i2c_m_status_rdat_rdy 0xF955 -+#define i2c_m_status_rdat_rdy_pos 3 -+#define i2c_m_status_rdat_rdy_len 1 -+#define i2c_m_status_rdat_rdy_lsb 0 -+#define I2C_i2c_m_period 0xF956 -+#define i2c_m_period_pos 0 -+#define i2c_m_period_len 8 -+#define i2c_m_period_lsb 0 -+#define I2C_i2c_m_reg_msb_lsb 0xF957 -+#define i2c_m_reg_msb_lsb_pos 0 -+#define i2c_m_reg_msb_lsb_len 1 -+#define i2c_m_reg_msb_lsb_lsb 0 -+#define I2C_reg_ofdm_rst 0xF957 -+#define reg_ofdm_rst_pos 1 -+#define reg_ofdm_rst_len 1 -+#define reg_ofdm_rst_lsb 0 -+#define I2C_reg_sample_period_on_tuner 0xF957 -+#define reg_sample_period_on_tuner_pos 2 -+#define reg_sample_period_on_tuner_len 1 -+#define reg_sample_period_on_tuner_lsb 0 -+#define I2C_reg_sel_tuner 0xF957 -+#define reg_sel_tuner_pos 3 -+#define reg_sel_tuner_len 1 -+#define reg_sel_tuner_lsb 0 -+#define I2C_reg_ofdm_rst_en 0xF957 -+#define reg_ofdm_rst_en_pos 4 -+#define reg_ofdm_rst_en_len 1 -+#define reg_ofdm_rst_en_lsb 0 -+#define p_mp2if_psb_overflow 0xF980 -+#define mp2if_psb_overflow_pos 0 -+#define mp2if_psb_overflow_len 1 -+#define mp2if_psb_overflow_lsb 0 -+#define p_mp2if_no_modify_tei_bit 0xF981 -+#define mp2if_no_modify_tei_bit_pos 0 -+#define mp2if_no_modify_tei_bit_len 1 -+#define mp2if_no_modify_tei_bit_lsb 0 -+#define p_mp2if_keep_sf_sync_byte 0xF982 -+#define mp2if_keep_sf_sync_byte_pos 0 -+#define mp2if_keep_sf_sync_byte_len 1 -+#define mp2if_keep_sf_sync_byte_lsb 0 -+#define p_mp2if_data_access_disable 0xF983 -+#define mp2if_data_access_disable_pos 0 -+#define mp2if_data_access_disable_len 1 -+#define mp2if_data_access_disable_lsb 0 -+#define p_mp2if_mpeg_ser_do7 0xF984 -+#define mp2if_mpeg_ser_do7_pos 0 -+#define mp2if_mpeg_ser_do7_len 1 -+#define mp2if_mpeg_ser_do7_lsb 0 -+#define p_mp2if_mpeg_ser_mode 0xF985 -+#define mp2if_mpeg_ser_mode_pos 0 -+#define mp2if_mpeg_ser_mode_len 1 -+#define mp2if_mpeg_ser_mode_lsb 0 -+#define p_mp2if_mpeg_par_mode 0xF986 -+#define mp2if_mpeg_par_mode_pos 0 -+#define mp2if_mpeg_par_mode_len 1 -+#define mp2if_mpeg_par_mode_lsb 0 -+#define r_mp2if_psb_empty 0xF987 -+#define mp2if_psb_empty_pos 0 -+#define mp2if_psb_empty_len 1 -+#define mp2if_psb_empty_lsb 0 -+#define r_mp2if_ts_not_188 0xF988 -+#define mp2if_ts_not_188_pos 0 -+#define mp2if_ts_not_188_len 1 -+#define mp2if_ts_not_188_lsb 0 -+#define p_mp2if_mssync_len 0xF989 -+#define mp2if_mssync_len_pos 0 -+#define mp2if_mssync_len_len 1 -+#define mp2if_mssync_len_lsb 0 -+#define p_mp2if_msdo_msb 0xF98A -+#define mp2if_msdo_msb_pos 0 -+#define mp2if_msdo_msb_len 1 -+#define mp2if_msdo_msb_lsb 0 -+#define p_mp2if_mpeg_clk_gated 0xF98B -+#define mp2if_mpeg_clk_gated_pos 0 -+#define mp2if_mpeg_clk_gated_len 1 -+#define mp2if_mpeg_clk_gated_lsb 0 -+#define p_mp2if_mpeg_err_pol 0xF98C -+#define mp2if_mpeg_err_pol_pos 0 -+#define mp2if_mpeg_err_pol_len 1 -+#define mp2if_mpeg_err_pol_lsb 0 -+#define p_mp2if_mpeg_sync_pol 0xF98D -+#define mp2if_mpeg_sync_pol_pos 0 -+#define mp2if_mpeg_sync_pol_len 1 -+#define mp2if_mpeg_sync_pol_lsb 0 -+#define p_mp2if_mpeg_vld_pol 0xF98E -+#define mp2if_mpeg_vld_pol_pos 0 -+#define mp2if_mpeg_vld_pol_len 1 -+#define mp2if_mpeg_vld_pol_lsb 0 -+#define p_mp2if_mpeg_clk_pol 0xF98F -+#define mp2if_mpeg_clk_pol_pos 0 -+#define mp2if_mpeg_clk_pol_len 1 -+#define mp2if_mpeg_clk_pol_lsb 0 -+#define p_reg_mpeg_full_speed 0xF990 -+#define reg_mpeg_full_speed_pos 0 -+#define reg_mpeg_full_speed_len 1 -+#define reg_mpeg_full_speed_lsb 0 -+#define p_mp2if_pid_complement 0xF991 -+#define mp2if_pid_complement_pos 0 -+#define mp2if_pid_complement_len 1 -+#define mp2if_pid_complement_lsb 0 -+#define p_mp2if_pid_rst 0xF992 -+#define mp2if_pid_rst_pos 0 -+#define mp2if_pid_rst_len 1 -+#define mp2if_pid_rst_lsb 0 -+#define p_mp2if_pid_en 0xF993 -+#define mp2if_pid_en_pos 0 -+#define mp2if_pid_en_len 1 -+#define mp2if_pid_en_lsb 0 -+#define p_mp2if_pid_index_en 0xF994 -+#define mp2if_pid_index_en_pos 0 -+#define mp2if_pid_index_en_len 1 -+#define mp2if_pid_index_en_lsb 0 -+#define p_mp2if_pid_index 0xF995 -+#define mp2if_pid_index_pos 0 -+#define mp2if_pid_index_len 5 -+#define mp2if_pid_index_lsb 0 -+#define p_mp2if_pid_dat_l 0xF996 -+#define mp2if_pid_dat_l_pos 0 -+#define mp2if_pid_dat_l_len 8 -+#define mp2if_pid_dat_l_lsb 0 -+#define p_mp2if_pid_dat_h 0xF997 -+#define mp2if_pid_dat_h_pos 0 -+#define mp2if_pid_dat_h_len 5 -+#define mp2if_pid_dat_h_lsb 0 -+#define p_reg_latch_clk 0xF998 -+#define reg_latch_clk_pos 0 -+#define reg_latch_clk_len 1 -+#define reg_latch_clk_lsb 0 -+#define r_mp2if_sync_byte_locked 0xF999 -+#define mp2if_sync_byte_locked_pos 0 -+#define mp2if_sync_byte_locked_len 1 -+#define mp2if_sync_byte_locked_lsb 0 -+#define p_mp2if_ignore_sync_byte 0xF99A -+#define mp2if_ignore_sync_byte_pos 0 -+#define mp2if_ignore_sync_byte_len 1 -+#define mp2if_ignore_sync_byte_lsb 0 -+#define p_reg_mp2if_clk_en 0xF99B -+#define reg_mp2if_clk_en_pos 0 -+#define reg_mp2if_clk_en_len 1 -+#define reg_mp2if_clk_en_lsb 0 -+#define p_reg_mpeg_vld_tgl 0xF99C -+#define reg_mpeg_vld_tgl_pos 0 -+#define reg_mpeg_vld_tgl_len 1 -+#define reg_mpeg_vld_tgl_lsb 0 -+#define p_reg_mp2_sw_rst 0xF99D -+#define reg_mp2_sw_rst_pos 0 -+#define reg_mp2_sw_rst_len 1 -+#define reg_mp2_sw_rst_lsb 0 -+#define p_mp2if_psb_en 0xF99E -+#define mp2if_psb_en_pos 0 -+#define mp2if_psb_en_len 1 -+#define mp2if_psb_en_lsb 0 -+#define r_mp2if_usb20_mode 0xF99F -+#define mp2if_usb20_mode_pos 0 -+#define mp2if_usb20_mode_len 1 -+#define mp2if_usb20_mode_lsb 0 -+#define r_mp2if_strap_usb20_mode 0xF9A0 -+#define mp2if_strap_usb20_mode_pos 0 -+#define mp2if_strap_usb20_mode_len 1 -+#define mp2if_strap_usb20_mode_lsb 0 -+#define r_mp2if_lost_pkt_cnt_l 0xF9A1 -+#define mp2if_lost_pkt_cnt_l_pos 0 -+#define mp2if_lost_pkt_cnt_l_len 8 -+#define mp2if_lost_pkt_cnt_l_lsb 0 -+#define r_mp2if_lost_pkt_cnt_h 0xF9A2 -+#define mp2if_lost_pkt_cnt_h_pos 0 -+#define mp2if_lost_pkt_cnt_h_len 8 -+#define mp2if_lost_pkt_cnt_h_lsb 0 -+#define p_reg_mp2if2_en 0xF9A3 -+#define reg_mp2if2_en_pos 0 -+#define reg_mp2if2_en_len 1 -+#define reg_mp2if2_en_lsb 0 -+#define p_reg_mp2if2_sw_rst 0xF9A4 -+#define reg_mp2if2_sw_rst_pos 0 -+#define reg_mp2if2_sw_rst_len 1 -+#define reg_mp2if2_sw_rst_lsb 0 -+#define p_reg_mp2if2_half_psb 0xF9A5 -+#define reg_mp2if2_half_psb_pos 0 -+#define reg_mp2if2_half_psb_len 1 -+#define reg_mp2if2_half_psb_lsb 0 -+#define p_reg_ts_byte_endian 0xF9A6 -+#define reg_ts_byte_endian_pos 0 -+#define reg_ts_byte_endian_len 1 -+#define reg_ts_byte_endian_lsb 0 -+#define p_reg_mp2_dioif 0xF9A7 -+#define reg_mp2_dioif_pos 0 -+#define reg_mp2_dioif_len 1 -+#define reg_mp2_dioif_lsb 0 -+#define p_reg_mp2_dioif_fast 0xF9A8 -+#define reg_mp2_dioif_fast_pos 0 -+#define reg_mp2_dioif_fast_len 1 -+#define reg_mp2_dioif_fast_lsb 0 -+#define p_reg_tpsd_bw_mp2if 0xF9A9 -+#define reg_tpsd_bw_mp2if_pos 0 -+#define reg_tpsd_bw_mp2if_len 2 -+#define reg_tpsd_bw_mp2if_lsb 0 -+#define p_reg_tpsd_gi_mp2if 0xF9AA -+#define reg_tpsd_gi_mp2if_pos 0 -+#define reg_tpsd_gi_mp2if_len 2 -+#define reg_tpsd_gi_mp2if_lsb 0 -+#define p_reg_tpsd_cr_mp2if 0xF9AB -+#define reg_tpsd_cr_mp2if_pos 0 -+#define reg_tpsd_cr_mp2if_len 3 -+#define reg_tpsd_cr_mp2if_lsb 0 -+#define p_reg_tpsd_cons_mp2if 0xF9AC -+#define reg_tpsd_cons_mp2if_pos 0 -+#define reg_tpsd_cons_mp2if_len 2 -+#define reg_tpsd_cons_mp2if_lsb 0 -+#define p_reg_fw_table_en 0xF9AD -+#define reg_fw_table_en_pos 0 -+#define reg_fw_table_en_len 1 -+#define reg_fw_table_en_lsb 0 -+#define p_reg_p_aud_pk_gen_aud_pk_size 0xF9AD -+#define reg_p_aud_pk_gen_aud_pk_size_pos 1 -+#define reg_p_aud_pk_gen_aud_pk_size_len 6 -+#define reg_p_aud_pk_gen_aud_pk_size_lsb 0 -+#define p_mp2if_psb_num_blk 0xF9AE -+#define mp2if_psb_num_blk_pos 0 -+#define mp2if_psb_num_blk_len 6 -+#define mp2if_psb_num_blk_lsb 0 -+#define p_reg_fec_fake 0xF9AF -+#define reg_fec_fake_pos 0 -+#define reg_fec_fake_len 1 -+#define reg_fec_fake_lsb 0 -+#define p_reg_p_ccir_atv_en 0xF9AF -+#define reg_p_ccir_atv_en_pos 1 -+#define reg_p_ccir_atv_en_len 1 -+#define reg_p_ccir_atv_en_lsb 0 -+#define p_reg_video_stop_n 0xF9AF -+#define reg_video_stop_n_pos 2 -+#define reg_video_stop_n_len 1 -+#define reg_video_stop_n_lsb 0 -+#define p_reg_audio_stop_n 0xF9AF -+#define reg_audio_stop_n_pos 3 -+#define reg_audio_stop_n_len 1 -+#define reg_audio_stop_n_lsb 0 -+#define p_mp2if_i2smode 0xF9AF -+#define mp2if_i2smode_pos 4 -+#define mp2if_i2smode_len 2 -+#define mp2if_i2smode_lsb 0 -+#define p_mp2if_word_size 0xF9AF -+#define mp2if_word_size_pos 6 -+#define mp2if_word_size_len 2 -+#define mp2if_word_size_lsb 0 -+#define p_reg_packet_gap 0xF9B0 -+#define reg_packet_gap_pos 0 -+#define reg_packet_gap_len 8 -+#define reg_packet_gap_lsb 0 -+#define p_reg_ts_dat_inv 0xF9B2 -+#define reg_ts_dat_inv_pos 0 -+#define reg_ts_dat_inv_len 1 -+#define reg_ts_dat_inv_lsb 0 -+#define p_reg_ts_lsb_1st 0xF9B3 -+#define reg_ts_lsb_1st_pos 0 -+#define reg_ts_lsb_1st_len 1 -+#define reg_ts_lsb_1st_lsb 0 -+#define p_reg_ts_capt_bg_sel 0xF9B4 -+#define reg_ts_capt_bg_sel_pos 0 -+#define reg_ts_capt_bg_sel_len 1 -+#define reg_ts_capt_bg_sel_lsb 0 -+#define p_reg_mp2if_stop_en 0xF9B5 -+#define reg_mp2if_stop_en_pos 0 -+#define reg_mp2if_stop_en_len 1 -+#define reg_mp2if_stop_en_lsb 0 -+#define p_reg_mp2if2_pes_base 0xF9B6 -+#define reg_mp2if2_pes_base_pos 0 -+#define reg_mp2if2_pes_base_len 1 -+#define reg_mp2if2_pes_base_lsb 0 -+#define p_reg_ts_sync_inv 0xF9B7 -+#define reg_ts_sync_inv_pos 0 -+#define reg_ts_sync_inv_len 1 -+#define reg_ts_sync_inv_lsb 0 -+#define p_reg_ts_vld_inv 0xF9B8 -+#define reg_ts_vld_inv_pos 0 -+#define reg_ts_vld_inv_len 1 -+#define reg_ts_vld_inv_lsb 0 -+#define p_reg_sys_buf_overflow 0xF9B9 -+#define reg_sys_buf_overflow_pos 0 -+#define reg_sys_buf_overflow_len 1 -+#define reg_sys_buf_overflow_lsb 0 -+#define p_reg_top_dummy0 0xF9BB -+#define reg_top_dummy0_pos 0 -+#define reg_top_dummy0_len 8 -+#define reg_top_dummy0_lsb 0 -+#define p_reg_top_dummy1 0xF9BC -+#define reg_top_dummy1_pos 0 -+#define reg_top_dummy1_len 8 -+#define reg_top_dummy1_lsb 0 -+#define p_reg_top_dummy2 0xF9BD -+#define reg_top_dummy2_pos 0 -+#define reg_top_dummy2_len 8 -+#define reg_top_dummy2_lsb 0 -+#define p_reg_top_dummy3 0xF9BE -+#define reg_top_dummy3_pos 0 -+#define reg_top_dummy3_len 8 -+#define reg_top_dummy3_lsb 0 -+#define p_reg_top_dummy4 0xF9BF -+#define reg_top_dummy4_pos 0 -+#define reg_top_dummy4_len 8 -+#define reg_top_dummy4_lsb 0 -+#define p_reg_top_dummy5 0xF9C0 -+#define reg_top_dummy5_pos 0 -+#define reg_top_dummy5_len 8 -+#define reg_top_dummy5_lsb 0 -+#define p_reg_top_dummy6 0xF9C1 -+#define reg_top_dummy6_pos 0 -+#define reg_top_dummy6_len 8 -+#define reg_top_dummy6_lsb 0 -+#define p_reg_top_dummy7 0xF9C2 -+#define reg_top_dummy7_pos 0 -+#define reg_top_dummy7_len 8 -+#define reg_top_dummy7_lsb 0 -+#define p_reg_top_dummy8 0xF9C3 -+#define reg_top_dummy8_pos 0 -+#define reg_top_dummy8_len 8 -+#define reg_top_dummy8_lsb 0 -+#define p_reg_top_dummy9 0xF9C4 -+#define reg_top_dummy9_pos 0 -+#define reg_top_dummy9_len 8 -+#define reg_top_dummy9_lsb 0 -+#define p_reg_top_dummyA 0xF9C5 -+#define reg_top_dummyA_pos 0 -+#define reg_top_dummyA_len 8 -+#define reg_top_dummyA_lsb 0 -+#define p_reg_top_dummyB 0xF9C6 -+#define reg_top_dummyB_pos 0 -+#define reg_top_dummyB_len 8 -+#define reg_top_dummyB_lsb 0 -+#define p_reg_top_dummyC 0xF9C7 -+#define reg_top_dummyC_pos 0 -+#define reg_top_dummyC_len 8 -+#define reg_top_dummyC_lsb 0 -+#define p_reg_top_dummyD 0xF9C8 -+#define reg_top_dummyD_pos 0 -+#define reg_top_dummyD_len 8 -+#define reg_top_dummyD_lsb 0 -+#define p_reg_top_dummyE 0xF9C9 -+#define reg_top_dummyE_pos 0 -+#define reg_top_dummyE_len 8 -+#define reg_top_dummyE_lsb 0 -+#define p_reg_top_dummyF 0xF9CA -+#define reg_top_dummyF_pos 0 -+#define reg_top_dummyF_len 8 -+#define reg_top_dummyF_lsb 0 -+#define p_reg_mp2if_clk_coeff 0xF9CB -+#define reg_mp2if_clk_coeff_pos 0 -+#define reg_mp2if_clk_coeff_len 7 -+#define reg_mp2if_clk_coeff_lsb 0 -+#define p_reg_tsip_en 0xF9CC -+#define reg_tsip_en_pos 0 -+#define reg_tsip_en_len 1 -+#define reg_tsip_en_lsb 0 -+#define p_reg_tsis_en 0xF9CD -+#define reg_tsis_en_pos 0 -+#define reg_tsis_en_len 1 -+#define reg_tsis_en_lsb 0 -+#define p_reg_tsip_br 0xF9CE -+#define reg_tsip_br_pos 0 -+#define reg_tsip_br_len 1 -+#define reg_tsip_br_lsb 0 -+#define p_reg_tsip_frm_inv 0xF9D0 -+#define reg_tsip_frm_inv_pos 0 -+#define reg_tsip_frm_inv_len 1 -+#define reg_tsip_frm_inv_lsb 0 -+#define p_reg_tsip_str_inv 0xF9D1 -+#define reg_tsip_str_inv_pos 0 -+#define reg_tsip_str_inv_len 1 -+#define reg_tsip_str_inv_lsb 0 -+#define p_reg_tsip_fail_inv 0xF9D2 -+#define reg_tsip_fail_inv_pos 0 -+#define reg_tsip_fail_inv_len 1 -+#define reg_tsip_fail_inv_lsb 0 -+#define p_reg_tsip_frm_ignore 0xF9D3 -+#define reg_tsip_frm_ignore_pos 0 -+#define reg_tsip_frm_ignore_len 1 -+#define reg_tsip_frm_ignore_lsb 0 -+#define p_reg_tsip_str_ignore 0xF9D4 -+#define reg_tsip_str_ignore_pos 0 -+#define reg_tsip_str_ignore_len 1 -+#define reg_tsip_str_ignore_lsb 0 -+#define p_reg_tsip_fail_ignore 0xF9D5 -+#define reg_tsip_fail_ignore_pos 0 -+#define reg_tsip_fail_ignore_len 1 -+#define reg_tsip_fail_ignore_lsb 0 -+#define p_reg_tsip_endian 0xF9D6 -+#define reg_tsip_endian_pos 0 -+#define reg_tsip_endian_len 1 -+#define reg_tsip_endian_lsb 0 -+#define p_reg_tsip_overflow 0xF9D7 -+#define reg_tsip_overflow_pos 0 -+#define reg_tsip_overflow_len 1 -+#define reg_tsip_overflow_lsb 0 -+#define p_reg_ts_in_src 0xF9D8 -+#define reg_ts_in_src_pos 0 -+#define reg_ts_in_src_len 1 -+#define reg_ts_in_src_lsb 0 -+#define r_reg_clk_sel 0xF9D9 -+#define reg_clk_sel_pos 0 -+#define reg_clk_sel_len 2 -+#define reg_clk_sel_lsb 0 -+#define r_reg_tog_sel 0xF9DA -+#define reg_tog_sel_pos 0 -+#define reg_tog_sel_len 2 -+#define reg_tog_sel_lsb 0 -+#define p_reg_ts_str_ignore 0xF9DB -+#define reg_ts_str_ignore_pos 0 -+#define reg_ts_str_ignore_len 1 -+#define reg_ts_str_ignore_lsb 0 -+#define p_reg_ts_frm_ignore 0xF9DC -+#define reg_ts_frm_ignore_pos 0 -+#define reg_ts_frm_ignore_len 1 -+#define reg_ts_frm_ignore_lsb 0 -+#define p_reg_clk_sel_fix 0xF9DD -+#define reg_clk_sel_fix_pos 0 -+#define reg_clk_sel_fix_len 2 -+#define reg_clk_sel_fix_lsb 0 -+#define p_reg_tog_sel_fix 0xF9DE -+#define reg_tog_sel_fix_pos 0 -+#define reg_tog_sel_fix_len 2 -+#define reg_tog_sel_fix_lsb 0 -+#define p_reg_en_fix 0xF9DF -+#define reg_en_fix_pos 0 -+#define reg_en_fix_len 1 -+#define reg_en_fix_lsb 0 -+#define p_reg_check_tpsd_hier 0xF9E0 -+#define reg_check_tpsd_hier_pos 0 -+#define reg_check_tpsd_hier_len 1 -+#define reg_check_tpsd_hier_lsb 0 -+#define p_reg_p_i2s_master_mode 0xF9E1 -+#define reg_p_i2s_master_mode_pos 0 -+#define reg_p_i2s_master_mode_len 1 -+#define reg_p_i2s_master_mode_lsb 0 -+#define p_reg_p_sc_lr_ratio 0xF9E2 -+#define reg_p_sc_lr_ratio_pos 0 -+#define reg_p_sc_lr_ratio_len 2 -+#define reg_p_sc_lr_ratio_lsb 0 -+#define p_reg_p_i2s_fs_type 0xF9E2 -+#define reg_p_i2s_fs_type_pos 2 -+#define reg_p_i2s_fs_type_len 2 -+#define reg_p_i2s_fs_type_lsb 0 -+#define r_reg_r_pp_fullq 0xF9E3 -+#define reg_r_pp_fullq_pos 0 -+#define reg_r_pp_fullq_len 1 -+#define reg_r_pp_fullq_lsb 0 -+#define p_reg_r_ccir_rst 0xF9E3 -+#define reg_r_ccir_rst_pos 1 -+#define reg_r_ccir_rst_len 1 -+#define reg_r_ccir_rst_lsb 0 -+#define p_reg_p_full_en 0xF9E3 -+#define reg_p_full_en_pos 2 -+#define reg_p_full_en_len 1 -+#define reg_p_full_en_lsb 0 -+#define p_reg_p_vbi_dis 0xF9E3 -+#define reg_p_vbi_dis_pos 3 -+#define reg_p_vbi_dis_len 1 -+#define reg_p_vbi_dis_lsb 0 -+#define p_reg_p_ccir_all 0xF9E3 -+#define reg_p_ccir_all_pos 4 -+#define reg_p_ccir_all_len 1 -+#define reg_p_ccir_all_lsb 0 -+#define p_reg_p_ccir_vbi_raw_en 0xF9E3 -+#define reg_p_ccir_vbi_raw_en_pos 5 -+#define reg_p_ccir_vbi_raw_en_len 1 -+#define reg_p_ccir_vbi_raw_en_lsb 0 -+#define p_reg_err_byte_en 0xF9E4 -+#define reg_err_byte_en_pos 0 -+#define reg_err_byte_en_len 1 -+#define reg_err_byte_en_lsb 0 -+#define p_reg_mp2_f_adc_7_0 0xF9E5 -+#define reg_mp2_f_adc_7_0_pos 0 -+#define reg_mp2_f_adc_7_0_len 8 -+#define reg_mp2_f_adc_7_0_lsb 0 -+#define p_reg_mp2_f_adc_15_8 0xF9E6 -+#define reg_mp2_f_adc_15_8_pos 0 -+#define reg_mp2_f_adc_15_8_len 8 -+#define reg_mp2_f_adc_15_8_lsb 8 -+#define p_reg_mp2_f_adc_23_16 0xF9E7 -+#define reg_mp2_f_adc_23_16_pos 0 -+#define reg_mp2_f_adc_23_16_len 8 -+#define reg_mp2_f_adc_23_16_lsb 16 -+#define p_reg_set_util 0xF9E8 -+#define reg_set_util_pos 0 -+#define reg_set_util_len 8 -+#define reg_set_util_lsb 0 -+#define r_reg_err_byte 0xF9E9 -+#define reg_err_byte_pos 0 -+#define reg_err_byte_len 8 -+#define reg_err_byte_lsb 0 -+#define p_reg_p_ln_num1 0xF9EA -+#define reg_p_ln_num1_pos 0 -+#define reg_p_ln_num1_len 5 -+#define reg_p_ln_num1_lsb 0 -+#define p_reg_p_ln_num2_2_0 0xF9EA -+#define reg_p_ln_num2_2_0_pos 5 -+#define reg_p_ln_num2_2_0_len 3 -+#define reg_p_ln_num2_2_0_lsb 0 -+#define p_reg_p_ln_num2_4_3 0xF9EB -+#define reg_p_ln_num2_4_3_pos 0 -+#define reg_p_ln_num2_4_3_len 2 -+#define reg_p_ln_num2_4_3_lsb 3 -+#define p_reg_p_ln_num3_5_0 0xF9EB -+#define reg_p_ln_num3_5_0_pos 2 -+#define reg_p_ln_num3_5_0_len 6 -+#define reg_p_ln_num3_5_0_lsb 0 -+#define p_reg_p_ln_num3_8_6 0xF9EC -+#define reg_p_ln_num3_8_6_pos 0 -+#define reg_p_ln_num3_8_6_len 3 -+#define reg_p_ln_num3_8_6_lsb 6 -+#define p_reg_p_ln_num4_4_0 0xF9EC -+#define reg_p_ln_num4_4_0_pos 3 -+#define reg_p_ln_num4_4_0_len 5 -+#define reg_p_ln_num4_4_0_lsb 0 -+#define p_reg_p_ln_num4_8_5 0xF9ED -+#define reg_p_ln_num4_8_5_pos 0 -+#define reg_p_ln_num4_8_5_len 4 -+#define reg_p_ln_num4_8_5_lsb 5 -+#define p_reg_p_ln_num5_3_0 0xF9ED -+#define reg_p_ln_num5_3_0_pos 4 -+#define reg_p_ln_num5_3_0_len 4 -+#define reg_p_ln_num5_3_0_lsb 0 -+#define p_reg_p_ln_num5_8_4 0xF9EE -+#define reg_p_ln_num5_8_4_pos 0 -+#define reg_p_ln_num5_8_4_len 5 -+#define reg_p_ln_num5_8_4_lsb 4 -+#define p_reg_p_ln_num6_2_0 0xF9EE -+#define reg_p_ln_num6_2_0_pos 5 -+#define reg_p_ln_num6_2_0_len 3 -+#define reg_p_ln_num6_2_0_lsb 0 -+#define p_reg_p_ln_num6_8_3 0xF9EF -+#define reg_p_ln_num6_8_3_pos 0 -+#define reg_p_ln_num6_8_3_len 6 -+#define reg_p_ln_num6_8_3_lsb 3 -+#define p_reg_p_pixel_num_7_0 0xF9F0 -+#define reg_p_pixel_num_7_0_pos 0 -+#define reg_p_pixel_num_7_0_len 8 -+#define reg_p_pixel_num_7_0_lsb 0 -+#define p_reg_p_pixel_num_10_8 0xF9F1 -+#define reg_p_pixel_num_10_8_pos 0 -+#define reg_p_pixel_num_10_8_len 3 -+#define reg_p_pixel_num_10_8_lsb 8 -+#define p_reg_p_ccir_yuv_en 0xF9F1 -+#define reg_p_ccir_yuv_en_pos 3 -+#define reg_p_ccir_yuv_en_len 1 -+#define reg_p_ccir_yuv_en_lsb 0 -+#define p_reg_p_ccir_size_sft 0xF9F1 -+#define reg_p_ccir_size_sft_pos 4 -+#define reg_p_ccir_size_sft_len 2 -+#define reg_p_ccir_size_sft_lsb 0 -+#define p_reg_p_psb_cnt_sft 0xF9F1 -+#define reg_p_psb_cnt_sft_pos 6 -+#define reg_p_psb_cnt_sft_len 2 -+#define reg_p_psb_cnt_sft_lsb 0 -+#define p_reg_p_tpsd_lock_trigger 0xF9F2 -+#define reg_p_tpsd_lock_trigger_pos 0 -+#define reg_p_tpsd_lock_trigger_len 1 -+#define reg_p_tpsd_lock_trigger_lsb 0 -+#define p_reg_p_ccir_clk_sel 0xF9F3 -+#define reg_p_ccir_clk_sel_pos 0 -+#define reg_p_ccir_clk_sel_len 1 -+#define reg_p_ccir_clk_sel_lsb 0 -+#define p_reg_i2c_16_8_data_sel 0xFB00 -+#define reg_i2c_16_8_data_sel_pos 0 -+#define reg_i2c_16_8_data_sel_len 1 -+#define reg_i2c_16_8_data_sel_lsb 0 -+#define p_reg_i2c_slave_trigger_byte 0xFB01 -+#define reg_i2c_slave_trigger_byte_pos 0 -+#define reg_i2c_slave_trigger_byte_len 1 -+#define reg_i2c_slave_trigger_byte_lsb 0 -+#define p_reg_wdti_level 0xFB05 -+#define reg_wdti_level_pos 0 -+#define reg_wdti_level_len 1 -+#define reg_wdti_level_lsb 0 -+#define p_reg_rssi_avg_sel_lat 0xFB06 -+#define reg_rssi_avg_sel_lat_pos 0 -+#define reg_rssi_avg_sel_lat_len 2 -+#define reg_rssi_avg_sel_lat_lsb 0 -+#define r_ofsm_rssi_avg_7_0 0xFB07 -+#define ofsm_rssi_avg_7_0_pos 0 -+#define ofsm_rssi_avg_7_0_len 8 -+#define ofsm_rssi_avg_7_0_lsb 0 -+#define r_ofsm_rssi_avg_9_8 0xFB08 -+#define ofsm_rssi_avg_9_8_pos 0 -+#define ofsm_rssi_avg_9_8_len 2 -+#define ofsm_rssi_avg_9_8_lsb 8 -+#define r_ofsm_mbist_fail_mon51 0xFB09 -+#define ofsm_mbist_fail_mon51_pos 0 -+#define ofsm_mbist_fail_mon51_len 1 -+#define ofsm_mbist_fail_mon51_lsb 0 -+#define r_ofsm_mbist_fail_com 0xFB0A -+#define ofsm_mbist_fail_com_pos 0 -+#define ofsm_mbist_fail_com_len 1 -+#define ofsm_mbist_fail_com_lsb 0 -+#define r_ofsm_mbist_fail_fft 0xFB0B -+#define ofsm_mbist_fail_fft_pos 0 -+#define ofsm_mbist_fail_fft_len 1 -+#define ofsm_mbist_fail_fft_lsb 0 -+#define r_ofsm_mbist_fail_fd 0xFB0C -+#define ofsm_mbist_fail_fd_pos 0 -+#define ofsm_mbist_fail_fd_len 1 -+#define ofsm_mbist_fail_fd_lsb 0 -+#define r_ofsm_mbist_fail_link 0xFB0D -+#define ofsm_mbist_fail_link_pos 0 -+#define ofsm_mbist_fail_link_len 1 -+#define ofsm_mbist_fail_link_lsb 0 -+#define r_ofsm_mbist_fail_mpe 0xFB0E -+#define ofsm_mbist_fail_mpe_pos 0 -+#define ofsm_mbist_fail_mpe_len 1 -+#define ofsm_mbist_fail_mpe_lsb 0 -+#define r_ofsm_mbist_done_mpe 0xFB0F -+#define ofsm_mbist_done_mpe_pos 0 -+#define ofsm_mbist_done_mpe_len 1 -+#define ofsm_mbist_done_mpe_lsb 0 -+#define r_ofsm_mbist_mode_mpe 0xFB10 -+#define ofsm_mbist_mode_mpe_pos 0 -+#define ofsm_mbist_mode_mpe_len 1 -+#define ofsm_mbist_mode_mpe_lsb 0 -+#define p_ofsm_cmd_reg 0xFB11 -+#define ofsm_cmd_reg_pos 0 -+#define ofsm_cmd_reg_len 8 -+#define ofsm_cmd_reg_lsb 0 -+#define p_ofsm_addr_reg_h 0xFB12 -+#define ofsm_addr_reg_h_pos 0 -+#define ofsm_addr_reg_h_len 8 -+#define ofsm_addr_reg_h_lsb 0 -+#define p_ofsm_addr_reg_l 0xFB13 -+#define ofsm_addr_reg_l_pos 0 -+#define ofsm_addr_reg_l_len 8 -+#define ofsm_addr_reg_l_lsb 0 -+#define p_ofsm_data_reg_0 0xFB14 -+#define ofsm_data_reg_0_pos 0 -+#define ofsm_data_reg_0_len 8 -+#define ofsm_data_reg_0_lsb 0 -+#define p_ofsm_data_reg_1 0xFB15 -+#define ofsm_data_reg_1_pos 0 -+#define ofsm_data_reg_1_len 8 -+#define ofsm_data_reg_1_lsb 0 -+#define p_ofsm_data_reg_2 0xFB16 -+#define ofsm_data_reg_2_pos 0 -+#define ofsm_data_reg_2_len 8 -+#define ofsm_data_reg_2_lsb 0 -+#define p_ofsm_data_reg_3 0xFB17 -+#define ofsm_data_reg_3_pos 0 -+#define ofsm_data_reg_3_len 8 -+#define ofsm_data_reg_3_lsb 0 -+#define p_ofsm_data_reg_4 0xFB18 -+#define ofsm_data_reg_4_pos 0 -+#define ofsm_data_reg_4_len 8 -+#define ofsm_data_reg_4_lsb 0 -+#define p_ofsm_data_reg_5 0xFB19 -+#define ofsm_data_reg_5_pos 0 -+#define ofsm_data_reg_5_len 8 -+#define ofsm_data_reg_5_lsb 0 -+#define p_ofsm_data_reg_6 0xFB1A -+#define ofsm_data_reg_6_pos 0 -+#define ofsm_data_reg_6_len 8 -+#define ofsm_data_reg_6_lsb 0 -+#define p_ofsm_data_reg_7 0xFB1B -+#define ofsm_data_reg_7_pos 0 -+#define ofsm_data_reg_7_len 8 -+#define ofsm_data_reg_7_lsb 0 -+#define p_ofsm_data_reg_8 0xFB1C -+#define ofsm_data_reg_8_pos 0 -+#define ofsm_data_reg_8_len 8 -+#define ofsm_data_reg_8_lsb 0 -+#define p_ofsm_data_reg_9 0xFB1D -+#define ofsm_data_reg_9_pos 0 -+#define ofsm_data_reg_9_len 8 -+#define ofsm_data_reg_9_lsb 0 -+#define p_ofsm_data_reg_10 0xFB1E -+#define ofsm_data_reg_10_pos 0 -+#define ofsm_data_reg_10_len 8 -+#define ofsm_data_reg_10_lsb 0 -+#define p_ofsm_data_reg_11 0xFB1F -+#define ofsm_data_reg_11_pos 0 -+#define ofsm_data_reg_11_len 8 -+#define ofsm_data_reg_11_lsb 0 -+#define p_ofsm_data_reg_12 0xFB20 -+#define ofsm_data_reg_12_pos 0 -+#define ofsm_data_reg_12_len 8 -+#define ofsm_data_reg_12_lsb 0 -+#define p_ofsm_data_reg_13 0xFB21 -+#define ofsm_data_reg_13_pos 0 -+#define ofsm_data_reg_13_len 8 -+#define ofsm_data_reg_13_lsb 0 -+#define p_ofsm_data_reg_14 0xFB22 -+#define ofsm_data_reg_14_pos 0 -+#define ofsm_data_reg_14_len 8 -+#define ofsm_data_reg_14_lsb 0 -+#define p_ofsm_data_reg_15 0xFB23 -+#define ofsm_data_reg_15_pos 0 -+#define ofsm_data_reg_15_len 8 -+#define ofsm_data_reg_15_lsb 0 -+#define p_reg_afe_mem0 0xFB24 -+#define reg_afe_mem0_pos 0 -+#define reg_afe_mem0_len 8 -+#define reg_afe_mem0_lsb 0 -+#define p_reg_afe_mem1 0xFB25 -+#define reg_afe_mem1_pos 0 -+#define reg_afe_mem1_len 8 -+#define reg_afe_mem1_lsb 0 -+#define p_reg_afe_mem2 0xFB26 -+#define reg_afe_mem2_pos 0 -+#define reg_afe_mem2_len 8 -+#define reg_afe_mem2_lsb 0 -+#define p_reg_afe_mem3 0xFB27 -+#define reg_afe_mem3_pos 0 -+#define reg_afe_mem3_len 8 -+#define reg_afe_mem3_lsb 0 -+#define p_reg_afe_mem4 0xFB28 -+#define reg_afe_mem4_pos 0 -+#define reg_afe_mem4_len 8 -+#define reg_afe_mem4_lsb 0 -+#define p_reg_afe_mem5 0xFB29 -+#define reg_afe_mem5_pos 0 -+#define reg_afe_mem5_len 8 -+#define reg_afe_mem5_lsb 0 -+#define p_reg_afe_mem6 0xFB2A -+#define reg_afe_mem6_pos 0 -+#define reg_afe_mem6_len 8 -+#define reg_afe_mem6_lsb 0 -+#define p_reg_afe_mem7 0xFB2B -+#define reg_afe_mem7_pos 0 -+#define reg_afe_mem7_len 8 -+#define reg_afe_mem7_lsb 0 -+#define p_reg_i2cbootreq 0xFB2C -+#define reg_i2cbootreq_pos 0 -+#define reg_i2cbootreq_len 1 -+#define reg_i2cbootreq_lsb 0 -+#define p_reg_rst_i2cm 0xFB30 -+#define reg_rst_i2cm_pos 0 -+#define reg_rst_i2cm_len 1 -+#define reg_rst_i2cm_lsb 0 -+#define p_reg_rst_i2cs 0xFB31 -+#define reg_rst_i2cs_pos 0 -+#define reg_rst_i2cs_len 1 -+#define reg_rst_i2cs_lsb 0 -+#define r_reg_top_gpioscli 0xFB32 -+#define reg_top_gpioscli_pos 0 -+#define reg_top_gpioscli_len 1 -+#define reg_top_gpioscli_lsb 0 -+#define p_reg_top_gpiosclo 0xFB33 -+#define reg_top_gpiosclo_pos 0 -+#define reg_top_gpiosclo_len 1 -+#define reg_top_gpiosclo_lsb 0 -+#define p_reg_top_gpiosclen 0xFB34 -+#define reg_top_gpiosclen_pos 0 -+#define reg_top_gpiosclen_len 1 -+#define reg_top_gpiosclen_lsb 0 -+#define p_reg_top_gpiosclon 0xFB35 -+#define reg_top_gpiosclon_pos 0 -+#define reg_top_gpiosclon_len 1 -+#define reg_top_gpiosclon_lsb 0 -+#define r_reg_top_gpiosdai 0xFB36 -+#define reg_top_gpiosdai_pos 0 -+#define reg_top_gpiosdai_len 1 -+#define reg_top_gpiosdai_lsb 0 -+#define p_reg_top_gpiosdao 0xFB37 -+#define reg_top_gpiosdao_pos 0 -+#define reg_top_gpiosdao_len 1 -+#define reg_top_gpiosdao_lsb 0 -+#define p_reg_top_gpiosdaen 0xFB38 -+#define reg_top_gpiosdaen_pos 0 -+#define reg_top_gpiosdaen_len 1 -+#define reg_top_gpiosdaen_lsb 0 -+#define p_reg_top_gpiosdaon 0xFB39 -+#define reg_top_gpiosdaon_pos 0 -+#define reg_top_gpiosdaon_len 1 -+#define reg_top_gpiosdaon_lsb 0 -+#define p_reg_fix_rom_en 0xFB3A -+#define reg_fix_rom_en_pos 0 -+#define reg_fix_rom_en_len 1 -+#define reg_fix_rom_en_lsb 0 -+#define p_reg_ofsm_bug_addh_0 0xFB3B -+#define reg_ofsm_bug_addh_0_pos 0 -+#define reg_ofsm_bug_addh_0_len 8 -+#define reg_ofsm_bug_addh_0_lsb 0 -+#define p_reg_ofsm_bug_addl_0 0xFB3C -+#define reg_ofsm_bug_addl_0_pos 0 -+#define reg_ofsm_bug_addl_0_len 8 -+#define reg_ofsm_bug_addl_0_lsb 0 -+#define p_reg_ofsm_bug_addh_1 0xFB3D -+#define reg_ofsm_bug_addh_1_pos 0 -+#define reg_ofsm_bug_addh_1_len 8 -+#define reg_ofsm_bug_addh_1_lsb 0 -+#define p_reg_ofsm_bug_addl_1 0xFB3E -+#define reg_ofsm_bug_addl_1_pos 0 -+#define reg_ofsm_bug_addl_1_len 8 -+#define reg_ofsm_bug_addl_1_lsb 0 -+#define p_reg_ofsm_bug_addh_2 0xFB3F -+#define reg_ofsm_bug_addh_2_pos 0 -+#define reg_ofsm_bug_addh_2_len 8 -+#define reg_ofsm_bug_addh_2_lsb 0 -+#define p_reg_ofsm_bug_addl_2 0xFB40 -+#define reg_ofsm_bug_addl_2_pos 0 -+#define reg_ofsm_bug_addl_2_len 8 -+#define reg_ofsm_bug_addl_2_lsb 0 -+#define p_reg_ofsm_bug_addh_3 0xFB41 -+#define reg_ofsm_bug_addh_3_pos 0 -+#define reg_ofsm_bug_addh_3_len 8 -+#define reg_ofsm_bug_addh_3_lsb 0 -+#define p_reg_ofsm_bug_addl_3 0xFB42 -+#define reg_ofsm_bug_addl_3_pos 0 -+#define reg_ofsm_bug_addl_3_len 8 -+#define reg_ofsm_bug_addl_3_lsb 0 -+#define p_reg_ofsm_bug_addh_4 0xFB43 -+#define reg_ofsm_bug_addh_4_pos 0 -+#define reg_ofsm_bug_addh_4_len 8 -+#define reg_ofsm_bug_addh_4_lsb 0 -+#define p_reg_ofsm_bug_addl_4 0xFB44 -+#define reg_ofsm_bug_addl_4_pos 0 -+#define reg_ofsm_bug_addl_4_len 8 -+#define reg_ofsm_bug_addl_4_lsb 0 -+#define p_reg_ofsm_bug_addh_5 0xFB45 -+#define reg_ofsm_bug_addh_5_pos 0 -+#define reg_ofsm_bug_addh_5_len 8 -+#define reg_ofsm_bug_addh_5_lsb 0 -+#define p_reg_ofsm_bug_addl_5 0xFB46 -+#define reg_ofsm_bug_addl_5_pos 0 -+#define reg_ofsm_bug_addl_5_len 8 -+#define reg_ofsm_bug_addl_5_lsb 0 -+#define p_reg_ofsm_bug_addh_6 0xFB47 -+#define reg_ofsm_bug_addh_6_pos 0 -+#define reg_ofsm_bug_addh_6_len 8 -+#define reg_ofsm_bug_addh_6_lsb 0 -+#define p_reg_ofsm_bug_addl_6 0xFB48 -+#define reg_ofsm_bug_addl_6_pos 0 -+#define reg_ofsm_bug_addl_6_len 8 -+#define reg_ofsm_bug_addl_6_lsb 0 -+#define p_reg_ofsm_bug_addh_7 0xFB49 -+#define reg_ofsm_bug_addh_7_pos 0 -+#define reg_ofsm_bug_addh_7_len 8 -+#define reg_ofsm_bug_addh_7_lsb 0 -+#define p_reg_ofsm_bug_addl_7 0xFB4A -+#define reg_ofsm_bug_addl_7_pos 0 -+#define reg_ofsm_bug_addl_7_len 8 -+#define reg_ofsm_bug_addl_7_lsb 0 -+#define p_reg_ofsm_bug_addh_8 0xFB4B -+#define reg_ofsm_bug_addh_8_pos 0 -+#define reg_ofsm_bug_addh_8_len 8 -+#define reg_ofsm_bug_addh_8_lsb 0 -+#define p_reg_ofsm_bug_addl_8 0xFB4C -+#define reg_ofsm_bug_addl_8_pos 0 -+#define reg_ofsm_bug_addl_8_len 8 -+#define reg_ofsm_bug_addl_8_lsb 0 -+#define p_reg_ofsm_bug_addh_9 0xFB4D -+#define reg_ofsm_bug_addh_9_pos 0 -+#define reg_ofsm_bug_addh_9_len 8 -+#define reg_ofsm_bug_addh_9_lsb 0 -+#define p_reg_ofsm_bug_addl_9 0xFB4E -+#define reg_ofsm_bug_addl_9_pos 0 -+#define reg_ofsm_bug_addl_9_len 8 -+#define reg_ofsm_bug_addl_9_lsb 0 -+#define p_reg_ofsm_bug_addh_10 0xFB4F -+#define reg_ofsm_bug_addh_10_pos 0 -+#define reg_ofsm_bug_addh_10_len 8 -+#define reg_ofsm_bug_addh_10_lsb 0 -+#define p_reg_ofsm_bug_addl_10 0xFB50 -+#define reg_ofsm_bug_addl_10_pos 0 -+#define reg_ofsm_bug_addl_10_len 8 -+#define reg_ofsm_bug_addl_10_lsb 0 -+#define p_reg_ofsm_bug_addh_11 0xFB51 -+#define reg_ofsm_bug_addh_11_pos 0 -+#define reg_ofsm_bug_addh_11_len 8 -+#define reg_ofsm_bug_addh_11_lsb 0 -+#define p_reg_ofsm_bug_addl_11 0xFB52 -+#define reg_ofsm_bug_addl_11_pos 0 -+#define reg_ofsm_bug_addl_11_len 8 -+#define reg_ofsm_bug_addl_11_lsb 0 -+#define p_reg_ofsm_bug_addh_12 0xFB53 -+#define reg_ofsm_bug_addh_12_pos 0 -+#define reg_ofsm_bug_addh_12_len 8 -+#define reg_ofsm_bug_addh_12_lsb 0 -+#define p_reg_ofsm_bug_addl_12 0xFB54 -+#define reg_ofsm_bug_addl_12_pos 0 -+#define reg_ofsm_bug_addl_12_len 8 -+#define reg_ofsm_bug_addl_12_lsb 0 -+#define p_reg_ofsm_bug_addh_13 0xFB55 -+#define reg_ofsm_bug_addh_13_pos 0 -+#define reg_ofsm_bug_addh_13_len 8 -+#define reg_ofsm_bug_addh_13_lsb 0 -+#define p_reg_ofsm_bug_addl_13 0xFB56 -+#define reg_ofsm_bug_addl_13_pos 0 -+#define reg_ofsm_bug_addl_13_len 8 -+#define reg_ofsm_bug_addl_13_lsb 0 -+#define p_reg_ofsm_bug_addh_14 0xFB57 -+#define reg_ofsm_bug_addh_14_pos 0 -+#define reg_ofsm_bug_addh_14_len 8 -+#define reg_ofsm_bug_addh_14_lsb 0 -+#define p_reg_ofsm_bug_addl_14 0xFB58 -+#define reg_ofsm_bug_addl_14_pos 0 -+#define reg_ofsm_bug_addl_14_len 8 -+#define reg_ofsm_bug_addl_14_lsb 0 -+#define p_reg_ofsm_bug_addh_15 0xFB59 -+#define reg_ofsm_bug_addh_15_pos 0 -+#define reg_ofsm_bug_addh_15_len 8 -+#define reg_ofsm_bug_addh_15_lsb 0 -+#define p_reg_ofsm_bug_addl_15 0xFB5A -+#define reg_ofsm_bug_addl_15_pos 0 -+#define reg_ofsm_bug_addl_15_len 8 -+#define reg_ofsm_bug_addl_15_lsb 0 -+#define p_reg_ofsm_jmp_addh_0 0xFB5B -+#define reg_ofsm_jmp_addh_0_pos 0 -+#define reg_ofsm_jmp_addh_0_len 8 -+#define reg_ofsm_jmp_addh_0_lsb 0 -+#define p_reg_ofsm_jmp_addl_0 0xFB5C -+#define reg_ofsm_jmp_addl_0_pos 0 -+#define reg_ofsm_jmp_addl_0_len 8 -+#define reg_ofsm_jmp_addl_0_lsb 0 -+#define p_reg_ofsm_jmp_addh_1 0xFB5D -+#define reg_ofsm_jmp_addh_1_pos 0 -+#define reg_ofsm_jmp_addh_1_len 8 -+#define reg_ofsm_jmp_addh_1_lsb 0 -+#define p_reg_ofsm_jmp_addl_1 0xFB5E -+#define reg_ofsm_jmp_addl_1_pos 0 -+#define reg_ofsm_jmp_addl_1_len 8 -+#define reg_ofsm_jmp_addl_1_lsb 0 -+#define p_reg_ofsm_jmp_addh_2 0xFB5F -+#define reg_ofsm_jmp_addh_2_pos 0 -+#define reg_ofsm_jmp_addh_2_len 8 -+#define reg_ofsm_jmp_addh_2_lsb 0 -+#define p_reg_ofsm_jmp_addl_2 0xFB60 -+#define reg_ofsm_jmp_addl_2_pos 0 -+#define reg_ofsm_jmp_addl_2_len 8 -+#define reg_ofsm_jmp_addl_2_lsb 0 -+#define p_reg_ofsm_jmp_addh_3 0xFB61 -+#define reg_ofsm_jmp_addh_3_pos 0 -+#define reg_ofsm_jmp_addh_3_len 8 -+#define reg_ofsm_jmp_addh_3_lsb 0 -+#define p_reg_ofsm_jmp_addl_3 0xFB62 -+#define reg_ofsm_jmp_addl_3_pos 0 -+#define reg_ofsm_jmp_addl_3_len 8 -+#define reg_ofsm_jmp_addl_3_lsb 0 -+#define p_reg_ofsm_jmp_addh_4 0xFB63 -+#define reg_ofsm_jmp_addh_4_pos 0 -+#define reg_ofsm_jmp_addh_4_len 8 -+#define reg_ofsm_jmp_addh_4_lsb 0 -+#define p_reg_ofsm_jmp_addl_4 0xFB64 -+#define reg_ofsm_jmp_addl_4_pos 0 -+#define reg_ofsm_jmp_addl_4_len 8 -+#define reg_ofsm_jmp_addl_4_lsb 0 -+#define p_reg_ofsm_jmp_addh_5 0xFB65 -+#define reg_ofsm_jmp_addh_5_pos 0 -+#define reg_ofsm_jmp_addh_5_len 8 -+#define reg_ofsm_jmp_addh_5_lsb 0 -+#define p_reg_ofsm_jmp_addl_5 0xFB66 -+#define reg_ofsm_jmp_addl_5_pos 0 -+#define reg_ofsm_jmp_addl_5_len 8 -+#define reg_ofsm_jmp_addl_5_lsb 0 -+#define p_reg_ofsm_jmp_addh_6 0xFB67 -+#define reg_ofsm_jmp_addh_6_pos 0 -+#define reg_ofsm_jmp_addh_6_len 8 -+#define reg_ofsm_jmp_addh_6_lsb 0 -+#define p_reg_ofsm_jmp_addl_6 0xFB68 -+#define reg_ofsm_jmp_addl_6_pos 0 -+#define reg_ofsm_jmp_addl_6_len 8 -+#define reg_ofsm_jmp_addl_6_lsb 0 -+#define p_reg_ofsm_jmp_addh_7 0xFB69 -+#define reg_ofsm_jmp_addh_7_pos 0 -+#define reg_ofsm_jmp_addh_7_len 8 -+#define reg_ofsm_jmp_addh_7_lsb 0 -+#define p_reg_ofsm_jmp_addl_7 0xFB6A -+#define reg_ofsm_jmp_addl_7_pos 0 -+#define reg_ofsm_jmp_addl_7_len 8 -+#define reg_ofsm_jmp_addl_7_lsb 0 -+#define p_reg_ofsm_jmp_addh_8 0xFB6B -+#define reg_ofsm_jmp_addh_8_pos 0 -+#define reg_ofsm_jmp_addh_8_len 8 -+#define reg_ofsm_jmp_addh_8_lsb 0 -+#define p_reg_ofsm_jmp_addl_8 0xFB6C -+#define reg_ofsm_jmp_addl_8_pos 0 -+#define reg_ofsm_jmp_addl_8_len 8 -+#define reg_ofsm_jmp_addl_8_lsb 0 -+#define p_reg_ofsm_jmp_addh_9 0xFB6D -+#define reg_ofsm_jmp_addh_9_pos 0 -+#define reg_ofsm_jmp_addh_9_len 8 -+#define reg_ofsm_jmp_addh_9_lsb 0 -+#define p_reg_ofsm_jmp_addl_9 0xFB6E -+#define reg_ofsm_jmp_addl_9_pos 0 -+#define reg_ofsm_jmp_addl_9_len 8 -+#define reg_ofsm_jmp_addl_9_lsb 0 -+#define p_reg_ofsm_jmp_addh_10 0xFB6F -+#define reg_ofsm_jmp_addh_10_pos 0 -+#define reg_ofsm_jmp_addh_10_len 8 -+#define reg_ofsm_jmp_addh_10_lsb 0 -+#define p_reg_ofsm_jmp_addl_10 0xFB70 -+#define reg_ofsm_jmp_addl_10_pos 0 -+#define reg_ofsm_jmp_addl_10_len 8 -+#define reg_ofsm_jmp_addl_10_lsb 0 -+#define p_reg_ofsm_jmp_addh_11 0xFB71 -+#define reg_ofsm_jmp_addh_11_pos 0 -+#define reg_ofsm_jmp_addh_11_len 8 -+#define reg_ofsm_jmp_addh_11_lsb 0 -+#define p_reg_ofsm_jmp_addl_11 0xFB72 -+#define reg_ofsm_jmp_addl_11_pos 0 -+#define reg_ofsm_jmp_addl_11_len 8 -+#define reg_ofsm_jmp_addl_11_lsb 0 -+#define p_reg_ofsm_jmp_addh_12 0xFB73 -+#define reg_ofsm_jmp_addh_12_pos 0 -+#define reg_ofsm_jmp_addh_12_len 8 -+#define reg_ofsm_jmp_addh_12_lsb 0 -+#define p_reg_ofsm_jmp_addl_12 0xFB74 -+#define reg_ofsm_jmp_addl_12_pos 0 -+#define reg_ofsm_jmp_addl_12_len 8 -+#define reg_ofsm_jmp_addl_12_lsb 0 -+#define p_reg_ofsm_jmp_addh_13 0xFB75 -+#define reg_ofsm_jmp_addh_13_pos 0 -+#define reg_ofsm_jmp_addh_13_len 8 -+#define reg_ofsm_jmp_addh_13_lsb 0 -+#define p_reg_ofsm_jmp_addl_13 0xFB76 -+#define reg_ofsm_jmp_addl_13_pos 0 -+#define reg_ofsm_jmp_addl_13_len 8 -+#define reg_ofsm_jmp_addl_13_lsb 0 -+#define p_reg_ofsm_jmp_addh_14 0xFB77 -+#define reg_ofsm_jmp_addh_14_pos 0 -+#define reg_ofsm_jmp_addh_14_len 8 -+#define reg_ofsm_jmp_addh_14_lsb 0 -+#define p_reg_ofsm_jmp_addl_14 0xFB78 -+#define reg_ofsm_jmp_addl_14_pos 0 -+#define reg_ofsm_jmp_addl_14_len 8 -+#define reg_ofsm_jmp_addl_14_lsb 0 -+#define p_reg_ofsm_jmp_addh_15 0xFB79 -+#define reg_ofsm_jmp_addh_15_pos 0 -+#define reg_ofsm_jmp_addh_15_len 8 -+#define reg_ofsm_jmp_addh_15_lsb 0 -+#define p_reg_ofsm_jmp_addl_15 0xFB7A -+#define reg_ofsm_jmp_addl_15_pos 0 -+#define reg_ofsm_jmp_addl_15_len 8 -+#define reg_ofsm_jmp_addl_15_lsb 0 -+#define p_reg_sw_mon51 0xFB7B -+#define reg_sw_mon51_pos 0 -+#define reg_sw_mon51_len 7 -+#define reg_sw_mon51_lsb 0 -+#define p_reg_ofdm_mon51_flag 0xFB7C -+#define reg_ofdm_mon51_flag_pos 0 -+#define reg_ofdm_mon51_flag_len 1 -+#define reg_ofdm_mon51_flag_lsb 0 -+#define p_reg_ofdm_force_mon51 0xFB7D -+#define reg_ofdm_force_mon51_pos 0 -+#define reg_ofdm_force_mon51_len 1 -+#define reg_ofdm_force_mon51_lsb 0 -+#define p_reg_ofdm_which_cpu 0xFB7E -+#define reg_ofdm_which_cpu_pos 0 -+#define reg_ofdm_which_cpu_len 1 -+#define reg_ofdm_which_cpu_lsb 0 -+#define p_reg_ofdm_code_ready 0xFB7F -+#define reg_ofdm_code_ready_pos 0 -+#define reg_ofdm_code_ready_len 1 -+#define reg_ofdm_code_ready_lsb 0 -+#define p_reg_ofdm_mailbox_wend 0xFB80 -+#define reg_ofdm_mailbox_wend_pos 0 -+#define reg_ofdm_mailbox_wend_len 1 -+#define reg_ofdm_mailbox_wend_lsb 0 -+#define r_reg_fast_slow_train 0xFB81 -+#define reg_fast_slow_train_pos 0 -+#define reg_fast_slow_train_len 1 -+#define reg_fast_slow_train_lsb 0 -+#define p_reg_ofdm_mailbox_wptr 0xFB82 -+#define reg_ofdm_mailbox_wptr_pos 0 -+#define reg_ofdm_mailbox_wptr_len 8 -+#define reg_ofdm_mailbox_wptr_lsb 0 -+#define p_reg_ofdm_mailbox_int 0xFB86 -+#define reg_ofdm_mailbox_int_pos 0 -+#define reg_ofdm_mailbox_int_len 1 -+#define reg_ofdm_mailbox_int_lsb 0 -+#define p_reg_ofdm_lnk2ofdm_int 0xFB87 -+#define reg_ofdm_lnk2ofdm_int_pos 0 -+#define reg_ofdm_lnk2ofdm_int_len 1 -+#define reg_ofdm_lnk2ofdm_int_lsb 0 -+#define p_reg_ofdm_ofdm2lnk_int 0xFB88 -+#define reg_ofdm_ofdm2lnk_int_pos 0 -+#define reg_ofdm_ofdm2lnk_int_len 1 -+#define reg_ofdm_ofdm2lnk_int_lsb 0 -+#define r_reg_load_ofdm_reg 0xFB8F -+#define reg_load_ofdm_reg_pos 0 -+#define reg_load_ofdm_reg_len 1 -+#define reg_load_ofdm_reg_lsb 0 -+#define p_reg_lnk_mbx_rd_length_7_0 0xFB90 -+#define reg_lnk_mbx_rd_length_7_0_pos 0 -+#define reg_lnk_mbx_rd_length_7_0_len 8 -+#define reg_lnk_mbx_rd_length_7_0_lsb 0 -+#define p_reg_lnk_mbx_rd_length_15_8 0xFB91 -+#define reg_lnk_mbx_rd_length_15_8_pos 0 -+#define reg_lnk_mbx_rd_length_15_8_len 8 -+#define reg_lnk_mbx_rd_length_15_8_lsb 8 -+#define p_reg_lnk_mbx_rd_length_17_16 0xFB92 -+#define reg_lnk_mbx_rd_length_17_16_pos 0 -+#define reg_lnk_mbx_rd_length_17_16_len 2 -+#define reg_lnk_mbx_rd_length_17_16_lsb 16 -+#define p_reg_lnk_rd_data_sel 0xFB93 -+#define reg_lnk_rd_data_sel_pos 0 -+#define reg_lnk_rd_data_sel_len 2 -+#define reg_lnk_rd_data_sel_lsb 0 -+#define p_reg_ofdm2lnk_data_7_0 0xFB96 -+#define reg_ofdm2lnk_data_7_0_pos 0 -+#define reg_ofdm2lnk_data_7_0_len 8 -+#define reg_ofdm2lnk_data_7_0_lsb 0 -+#define p_reg_ofdm2lnk_data_15_8 0xFB97 -+#define reg_ofdm2lnk_data_15_8_pos 0 -+#define reg_ofdm2lnk_data_15_8_len 8 -+#define reg_ofdm2lnk_data_15_8_lsb 8 -+#define p_reg_ofdm2lnk_data_23_16 0xFB98 -+#define reg_ofdm2lnk_data_23_16_pos 0 -+#define reg_ofdm2lnk_data_23_16_len 8 -+#define reg_ofdm2lnk_data_23_16_lsb 16 -+#define p_reg_ofdm2lnk_data_31_24 0xFB99 -+#define reg_ofdm2lnk_data_31_24_pos 0 -+#define reg_ofdm2lnk_data_31_24_len 8 -+#define reg_ofdm2lnk_data_31_24_lsb 24 -+#define p_reg_ofdm2lnk_data_39_32 0xFB9A -+#define reg_ofdm2lnk_data_39_32_pos 0 -+#define reg_ofdm2lnk_data_39_32_len 8 -+#define reg_ofdm2lnk_data_39_32_lsb 32 -+#define p_reg_ofdm2lnk_data_47_40 0xFB9B -+#define reg_ofdm2lnk_data_47_40_pos 0 -+#define reg_ofdm2lnk_data_47_40_len 8 -+#define reg_ofdm2lnk_data_47_40_lsb 40 -+#define p_reg_ofdm2lnk_data_55_48 0xFB9C -+#define reg_ofdm2lnk_data_55_48_pos 0 -+#define reg_ofdm2lnk_data_55_48_len 8 -+#define reg_ofdm2lnk_data_55_48_lsb 48 -+#define p_reg_ofdm2lnk_data_63_56 0xFB9D -+#define reg_ofdm2lnk_data_63_56_pos 0 -+#define reg_ofdm2lnk_data_63_56_len 8 -+#define reg_ofdm2lnk_data_63_56_lsb 56 -+#define p_reg_lnktoofdm_data_7_0 0xFB9E -+#define reg_lnktoofdm_data_7_0_pos 0 -+#define reg_lnktoofdm_data_7_0_len 8 -+#define reg_lnktoofdm_data_7_0_lsb 0 -+#define p_reg_lnktoofdm_data_15_8 0xFB9F -+#define reg_lnktoofdm_data_15_8_pos 0 -+#define reg_lnktoofdm_data_15_8_len 8 -+#define reg_lnktoofdm_data_15_8_lsb 8 -+#define p_reg_lnktoofdm_data_23_16 0xFBA0 -+#define reg_lnktoofdm_data_23_16_pos 0 -+#define reg_lnktoofdm_data_23_16_len 8 -+#define reg_lnktoofdm_data_23_16_lsb 16 -+#define p_reg_lnktoofdm_data_31_24 0xFBA1 -+#define reg_lnktoofdm_data_31_24_pos 0 -+#define reg_lnktoofdm_data_31_24_len 8 -+#define reg_lnktoofdm_data_31_24_lsb 24 -+#define p_reg_lnktoofdm_data_39_32 0xFBA2 -+#define reg_lnktoofdm_data_39_32_pos 0 -+#define reg_lnktoofdm_data_39_32_len 8 -+#define reg_lnktoofdm_data_39_32_lsb 32 -+#define p_reg_lnktoofdm_data_47_40 0xFBA3 -+#define reg_lnktoofdm_data_47_40_pos 0 -+#define reg_lnktoofdm_data_47_40_len 8 -+#define reg_lnktoofdm_data_47_40_lsb 40 -+#define p_reg_lnktoofdm_data_55_48 0xFBA4 -+#define reg_lnktoofdm_data_55_48_pos 0 -+#define reg_lnktoofdm_data_55_48_len 8 -+#define reg_lnktoofdm_data_55_48_lsb 48 -+#define p_reg_lnktoofdm_data_63_56 0xFBA5 -+#define reg_lnktoofdm_data_63_56_pos 0 -+#define reg_lnktoofdm_data_63_56_len 8 -+#define reg_lnktoofdm_data_63_56_lsb 56 -+#define p_reg_dbgif32_sel 0xFBA6 -+#define reg_dbgif32_sel_pos 0 -+#define reg_dbgif32_sel_len 2 -+#define reg_dbgif32_sel_lsb 0 -+#define p_reg_dyn1_clk 0xFBA7 -+#define reg_dyn1_clk_pos 0 -+#define reg_dyn1_clk_len 1 -+#define reg_dyn1_clk_lsb 0 -+#define p_reg_dyn0_clk 0xFBA8 -+#define reg_dyn0_clk_pos 0 -+#define reg_dyn0_clk_len 1 -+#define reg_dyn0_clk_lsb 0 -+#define p_reg_free_clk 0xFBA9 -+#define reg_free_clk_pos 0 -+#define reg_free_clk_len 1 -+#define reg_free_clk_lsb 0 -+#define p_reg_ofdm_stick_mem_end_7_0 0xFBAD -+#define reg_ofdm_stick_mem_end_7_0_pos 0 -+#define reg_ofdm_stick_mem_end_7_0_len 8 -+#define reg_ofdm_stick_mem_end_7_0_lsb 0 -+#define p_reg_ofdm_stick_mem_end_15_8 0xFBAE -+#define reg_ofdm_stick_mem_end_15_8_pos 0 -+#define reg_ofdm_stick_mem_end_15_8_len 8 -+#define reg_ofdm_stick_mem_end_15_8_lsb 8 -+#define p_reg_ofdm_cpu_reset 0xFBAF -+#define reg_ofdm_cpu_reset_pos 0 -+#define reg_ofdm_cpu_reset_len 1 -+#define reg_ofdm_cpu_reset_lsb 0 -+#define p_reg_ofdm_bank_float_en 0xFBB0 -+#define reg_ofdm_bank_float_en_pos 0 -+#define reg_ofdm_bank_float_en_len 1 -+#define reg_ofdm_bank_float_en_lsb 0 -+#define p_reg_ofdm_bank_float_start 0xFBB1 -+#define reg_ofdm_bank_float_start_pos 0 -+#define reg_ofdm_bank_float_start_len 8 -+#define reg_ofdm_bank_float_start_lsb 0 -+#define p_reg_ofdm_bank_float_stop 0xFBB2 -+#define reg_ofdm_bank_float_stop_pos 0 -+#define reg_ofdm_bank_float_stop_len 8 -+#define reg_ofdm_bank_float_stop_lsb 0 -+#define r_ofsm_bond0_i 0xFBB3 -+#define ofsm_bond0_i_pos 0 -+#define ofsm_bond0_i_len 1 -+#define ofsm_bond0_i_lsb 0 -+#define r_ofsm_bond1_i 0xFBB4 -+#define ofsm_bond1_i_pos 0 -+#define ofsm_bond1_i_len 1 -+#define ofsm_bond1_i_lsb 0 -+#define r_io_mux_pwron_clk_strap 0xD800 -+#define io_mux_pwron_clk_strap_pos 0 -+#define io_mux_pwron_clk_strap_len 4 -+#define io_mux_pwron_clk_strap_lsb 0 -+#define r_io_mux_pwron_mode_strap 0xD801 -+#define io_mux_pwron_mode_strap_pos 0 -+#define io_mux_pwron_mode_strap_len 4 -+#define io_mux_pwron_mode_strap_lsb 0 -+#define r_io_mux_pwron_hosta 0xD802 -+#define io_mux_pwron_hosta_pos 0 -+#define io_mux_pwron_hosta_len 1 -+#define io_mux_pwron_hosta_lsb 0 -+#define r_reg_top_revid 0xD803 -+#define reg_top_revid_pos 0 -+#define reg_top_revid_len 4 -+#define reg_top_revid_lsb 0 -+#define r_io_mux_bond0_i 0xD804 -+#define io_mux_bond0_i_pos 0 -+#define io_mux_bond0_i_len 1 -+#define io_mux_bond0_i_lsb 0 -+#define r_io_mux_bondu0_i 0xD805 -+#define io_mux_bondu0_i_pos 0 -+#define io_mux_bondu0_i_len 1 -+#define io_mux_bondu0_i_lsb 0 -+#define p_reg_ofsm_suspend 0xD806 -+#define reg_ofsm_suspend_pos 0 -+#define reg_ofsm_suspend_len 1 -+#define reg_ofsm_suspend_lsb 0 -+#define p_reg_tslice_off 0xD807 -+#define reg_tslice_off_pos 0 -+#define reg_tslice_off_len 1 -+#define reg_tslice_off_lsb 0 -+#define p_io_mux_wake_int 0xD808 -+#define io_mux_wake_int_pos 0 -+#define io_mux_wake_int_len 1 -+#define io_mux_wake_int_lsb 0 -+#define p_reg_top_pwrdw_hwen 0xD809 -+#define reg_top_pwrdw_hwen_pos 0 -+#define reg_top_pwrdw_hwen_len 1 -+#define reg_top_pwrdw_hwen_lsb 0 -+#define p_reg_top_pwrdw_inv 0xD80A -+#define reg_top_pwrdw_inv_pos 0 -+#define reg_top_pwrdw_inv_len 1 -+#define reg_top_pwrdw_inv_lsb 0 -+#define p_reg_top_pwrdw 0xD80B -+#define reg_top_pwrdw_pos 0 -+#define reg_top_pwrdw_len 1 -+#define reg_top_pwrdw_lsb 0 -+#define p_io_mux_wake_int_en 0xD80C -+#define io_mux_wake_int_en_pos 0 -+#define io_mux_wake_int_en_len 1 -+#define io_mux_wake_int_en_lsb 0 -+#define p_io_mux_pwrdw_int 0xD80D -+#define io_mux_pwrdw_int_pos 0 -+#define io_mux_pwrdw_int_len 1 -+#define io_mux_pwrdw_int_lsb 0 -+#define p_reg_top_adcdly 0xD80E -+#define reg_top_adcdly_pos 0 -+#define reg_top_adcdly_len 2 -+#define reg_top_adcdly_lsb 0 -+#define p_reg_top_debug 0xD80F -+#define reg_top_debug_pos 0 -+#define reg_top_debug_len 1 -+#define reg_top_debug_lsb 0 -+#define p_reg_top_pcout 0xD810 -+#define reg_top_pcout_pos 0 -+#define reg_top_pcout_len 1 -+#define reg_top_pcout_lsb 0 -+#define p_reg_top_rs232 0xD811 -+#define reg_top_rs232_pos 0 -+#define reg_top_rs232_len 1 -+#define reg_top_rs232_lsb 0 -+#define p_reg_iqmode 0xD812 -+#define reg_iqmode_pos 0 -+#define reg_iqmode_len 1 -+#define reg_iqmode_lsb 0 -+#define p_reg_top_rstfd 0xD813 -+#define reg_top_rstfd_pos 0 -+#define reg_top_rstfd_len 1 -+#define reg_top_rstfd_lsb 0 -+#define p_reg_sdio_clksel 0xD814 -+#define reg_sdio_clksel_pos 0 -+#define reg_sdio_clksel_len 1 -+#define reg_sdio_clksel_lsb 0 -+#define p_reg_utmi_clksel 0xD815 -+#define reg_utmi_clksel_pos 0 -+#define reg_utmi_clksel_len 8 -+#define reg_utmi_clksel_lsb 0 -+#define p_reg_top_suscnt 0xD816 -+#define reg_top_suscnt_pos 0 -+#define reg_top_suscnt_len 2 -+#define reg_top_suscnt_lsb 0 -+#define p_reg_top_dist2f 0xD817 -+#define reg_top_dist2f_pos 0 -+#define reg_top_dist2f_len 1 -+#define reg_top_dist2f_lsb 0 -+#define p_reg_top_extusb 0xD818 -+#define reg_top_extusb_pos 0 -+#define reg_top_extusb_len 1 -+#define reg_top_extusb_lsb 0 -+#define p_reg_top_adcfifo 0xD819 -+#define reg_top_adcfifo_pos 0 -+#define reg_top_adcfifo_len 1 -+#define reg_top_adcfifo_lsb 0 -+#define p_reg_top_clkoen 0xD81A -+#define reg_top_clkoen_pos 0 -+#define reg_top_clkoen_len 1 -+#define reg_top_clkoen_lsb 0 -+#define p_reg_top_stpck 0xD81B -+#define reg_top_stpck_pos 0 -+#define reg_top_stpck_len 1 -+#define reg_top_stpck_lsb 0 -+#define p_reg_top_freeck 0xD81C -+#define reg_top_freeck_pos 0 -+#define reg_top_freeck_len 1 -+#define reg_top_freeck_lsb 0 -+#define p_reg_top_dio_sel 0xD81D -+#define reg_top_dio_sel_pos 0 -+#define reg_top_dio_sel_len 1 -+#define reg_top_dio_sel_lsb 0 -+#define p_reg_top_int_en 0xD81E -+#define reg_top_int_en_pos 0 -+#define reg_top_int_en_len 1 -+#define reg_top_int_en_lsb 0 -+#define p_reg_top_int_inv 0xD81F -+#define reg_top_int_inv_pos 0 -+#define reg_top_int_inv_len 1 -+#define reg_top_int_inv_lsb 0 -+#define p_reg_tsip_clk_inv 0xD820 -+#define reg_tsip_clk_inv_pos 0 -+#define reg_tsip_clk_inv_len 1 -+#define reg_tsip_clk_inv_lsb 0 -+#define p_reg_ts_clk_inv 0xD821 -+#define reg_ts_clk_inv_pos 0 -+#define reg_ts_clk_inv_len 1 -+#define reg_ts_clk_inv_lsb 0 -+#define p_reg_ts_hybrid 0xD822 -+#define reg_ts_hybrid_pos 0 -+#define reg_ts_hybrid_len 1 -+#define reg_ts_hybrid_lsb 0 -+#define p_reg_ccir_sel 0xD823 -+#define reg_ccir_sel_pos 0 -+#define reg_ccir_sel_len 4 -+#define reg_ccir_sel_lsb 0 -+#define p_reg_top_sys_gate 0xD824 -+#define reg_top_sys_gate_pos 0 -+#define reg_top_sys_gate_len 1 -+#define reg_top_sys_gate_lsb 0 -+#define p_reg_top_padpu 0xD825 -+#define reg_top_padpu_pos 0 -+#define reg_top_padpu_len 1 -+#define reg_top_padpu_lsb 0 -+#define p_reg_top_padpd 0xD826 -+#define reg_top_padpd_pos 0 -+#define reg_top_padpd_len 1 -+#define reg_top_padpd_lsb 0 -+#define p_reg_top_padodpu 0xD827 -+#define reg_top_padodpu_pos 0 -+#define reg_top_padodpu_len 1 -+#define reg_top_padodpu_lsb 0 -+#define p_reg_top_thirdodpu 0xD828 -+#define reg_top_thirdodpu_pos 0 -+#define reg_top_thirdodpu_len 1 -+#define reg_top_thirdodpu_lsb 0 -+#define p_reg_top_agc_od 0xD829 -+#define reg_top_agc_od_pos 0 -+#define reg_top_agc_od_len 1 -+#define reg_top_agc_od_lsb 0 -+#define p_reg_top_padmpdr2 0xD82A -+#define reg_top_padmpdr2_pos 0 -+#define reg_top_padmpdr2_len 1 -+#define reg_top_padmpdr2_lsb 0 -+#define p_reg_top_padmpdr4 0xD82B -+#define reg_top_padmpdr4_pos 0 -+#define reg_top_padmpdr4_len 1 -+#define reg_top_padmpdr4_lsb 0 -+#define p_reg_top_padmpdr8 0xD82C -+#define reg_top_padmpdr8_pos 0 -+#define reg_top_padmpdr8_len 1 -+#define reg_top_padmpdr8_lsb 0 -+#define p_reg_top_padmpdrsr 0xD82D -+#define reg_top_padmpdrsr_pos 0 -+#define reg_top_padmpdrsr_len 1 -+#define reg_top_padmpdrsr_lsb 0 -+#define p_reg_top_padmppu 0xD82E -+#define reg_top_padmppu_pos 0 -+#define reg_top_padmppu_len 1 -+#define reg_top_padmppu_lsb 0 -+#define p_reg_top_padmppd 0xD82F -+#define reg_top_padmppd_pos 0 -+#define reg_top_padmppd_len 1 -+#define reg_top_padmppd_lsb 0 -+#define p_reg_top_padmiscdr2 0xD830 -+#define reg_top_padmiscdr2_pos 0 -+#define reg_top_padmiscdr2_len 1 -+#define reg_top_padmiscdr2_lsb 0 -+#define p_reg_top_padmiscdr4 0xD831 -+#define reg_top_padmiscdr4_pos 0 -+#define reg_top_padmiscdr4_len 1 -+#define reg_top_padmiscdr4_lsb 0 -+#define p_reg_top_padmiscdr8 0xD832 -+#define reg_top_padmiscdr8_pos 0 -+#define reg_top_padmiscdr8_len 1 -+#define reg_top_padmiscdr8_lsb 0 -+#define p_reg_top_padmiscdrsr 0xD833 -+#define reg_top_padmiscdrsr_pos 0 -+#define reg_top_padmiscdrsr_len 1 -+#define reg_top_padmiscdrsr_lsb 0 -+#define p_reg_top_padmiscpu 0xD834 -+#define reg_top_padmiscpu_pos 0 -+#define reg_top_padmiscpu_len 1 -+#define reg_top_padmiscpu_lsb 0 -+#define p_reg_top_padmiscpd 0xD835 -+#define reg_top_padmiscpd_pos 0 -+#define reg_top_padmiscpd_len 1 -+#define reg_top_padmiscpd_lsb 0 -+#define p_reg_host_b0_smt 0xD836 -+#define reg_host_b0_smt_pos 0 -+#define reg_host_b0_smt_len 1 -+#define reg_host_b0_smt_lsb 0 -+#define p_reg_host_b1_smt 0xD837 -+#define reg_host_b1_smt_pos 0 -+#define reg_host_b1_smt_len 1 -+#define reg_host_b1_smt_lsb 0 -+#define p_reg_host_b2_smt 0xD838 -+#define reg_host_b2_smt_pos 0 -+#define reg_host_b2_smt_len 1 -+#define reg_host_b2_smt_lsb 0 -+#define p_reg_host_b3_smt 0xD839 -+#define reg_host_b3_smt_pos 0 -+#define reg_host_b3_smt_len 1 -+#define reg_host_b3_smt_lsb 0 -+#define p_reg_host_b4_smt 0xD83A -+#define reg_host_b4_smt_pos 0 -+#define reg_host_b4_smt_len 1 -+#define reg_host_b4_smt_lsb 0 -+#define p_reg_host_b5_smt 0xD83B -+#define reg_host_b5_smt_pos 0 -+#define reg_host_b5_smt_len 1 -+#define reg_host_b5_smt_lsb 0 -+#define p_reg_host_b6_smt 0xD83C -+#define reg_host_b6_smt_pos 0 -+#define reg_host_b6_smt_len 1 -+#define reg_host_b6_smt_lsb 0 -+#define p_reg_host_b7_smt 0xD83D -+#define reg_host_b7_smt_pos 0 -+#define reg_host_b7_smt_len 1 -+#define reg_host_b7_smt_lsb 0 -+#define p_reg_host_b8_smt 0xD83E -+#define reg_host_b8_smt_pos 0 -+#define reg_host_b8_smt_len 1 -+#define reg_host_b8_smt_lsb 0 -+#define p_reg_host_b9_smt 0xD83F -+#define reg_host_b9_smt_pos 0 -+#define reg_host_b9_smt_len 1 -+#define reg_host_b9_smt_lsb 0 -+#define p_reg_host_b10_smt 0xD840 -+#define reg_host_b10_smt_pos 0 -+#define reg_host_b10_smt_len 1 -+#define reg_host_b10_smt_lsb 0 -+#define p_reg_host_b11_smt 0xD841 -+#define reg_host_b11_smt_pos 0 -+#define reg_host_b11_smt_len 1 -+#define reg_host_b11_smt_lsb 0 -+#define p_reg_host_a0_smt 0xD842 -+#define reg_host_a0_smt_pos 0 -+#define reg_host_a0_smt_len 1 -+#define reg_host_a0_smt_lsb 0 -+#define p_reg_host_a1_smt 0xD843 -+#define reg_host_a1_smt_pos 0 -+#define reg_host_a1_smt_len 1 -+#define reg_host_a1_smt_lsb 0 -+#define p_reg_host_a2_smt 0xD844 -+#define reg_host_a2_smt_pos 0 -+#define reg_host_a2_smt_len 1 -+#define reg_host_a2_smt_lsb 0 -+#define p_reg_host_a3_smt 0xD845 -+#define reg_host_a3_smt_pos 0 -+#define reg_host_a3_smt_len 1 -+#define reg_host_a3_smt_lsb 0 -+#define p_reg_host_a4_smt 0xD846 -+#define reg_host_a4_smt_pos 0 -+#define reg_host_a4_smt_len 1 -+#define reg_host_a4_smt_lsb 0 -+#define p_reg_host_a5_smt 0xD847 -+#define reg_host_a5_smt_pos 0 -+#define reg_host_a5_smt_len 1 -+#define reg_host_a5_smt_lsb 0 -+#define p_reg_host_a6_smt 0xD848 -+#define reg_host_a6_smt_pos 0 -+#define reg_host_a6_smt_len 1 -+#define reg_host_a6_smt_lsb 0 -+#define p_reg_host_a7_smt 0xD849 -+#define reg_host_a7_smt_pos 0 -+#define reg_host_a7_smt_len 1 -+#define reg_host_a7_smt_lsb 0 -+#define p_reg_host_a8_smt 0xD84A -+#define reg_host_a8_smt_pos 0 -+#define reg_host_a8_smt_len 1 -+#define reg_host_a8_smt_lsb 0 -+#define p_reg_host_a9_smt 0xD84B -+#define reg_host_a9_smt_pos 0 -+#define reg_host_a9_smt_len 1 -+#define reg_host_a9_smt_lsb 0 -+#define p_reg_host_a10_smt 0xD84C -+#define reg_host_a10_smt_pos 0 -+#define reg_host_a10_smt_len 1 -+#define reg_host_a10_smt_lsb 0 -+#define p_reg_host_a11_smt 0xD84D -+#define reg_host_a11_smt_pos 0 -+#define reg_host_a11_smt_len 1 -+#define reg_host_a11_smt_lsb 0 -+#define p_reg_testmode_pds 0xD84E -+#define reg_testmode_pds_pos 0 -+#define reg_testmode_pds_len 3 -+#define reg_testmode_pds_lsb 0 -+#define p_reg_debug31_pds 0xD84F -+#define reg_debug31_pds_pos 0 -+#define reg_debug31_pds_len 3 -+#define reg_debug31_pds_lsb 0 -+#define p_reg_debug30_pds 0xD850 -+#define reg_debug30_pds_pos 0 -+#define reg_debug30_pds_len 3 -+#define reg_debug30_pds_lsb 0 -+#define p_reg_debug29_pds 0xD851 -+#define reg_debug29_pds_pos 0 -+#define reg_debug29_pds_len 3 -+#define reg_debug29_pds_lsb 0 -+#define p_reg_debug28_pds 0xD852 -+#define reg_debug28_pds_pos 0 -+#define reg_debug28_pds_len 3 -+#define reg_debug28_pds_lsb 0 -+#define p_reg_debug27_pds 0xD853 -+#define reg_debug27_pds_pos 0 -+#define reg_debug27_pds_len 3 -+#define reg_debug27_pds_lsb 0 -+#define p_reg_debug26_pds 0xD854 -+#define reg_debug26_pds_pos 0 -+#define reg_debug26_pds_len 3 -+#define reg_debug26_pds_lsb 0 -+#define p_reg_debug25_pds 0xD855 -+#define reg_debug25_pds_pos 0 -+#define reg_debug25_pds_len 3 -+#define reg_debug25_pds_lsb 0 -+#define p_reg_debug24_pds 0xD856 -+#define reg_debug24_pds_pos 0 -+#define reg_debug24_pds_len 3 -+#define reg_debug24_pds_lsb 0 -+#define p_reg_debug23_pds 0xD857 -+#define reg_debug23_pds_pos 0 -+#define reg_debug23_pds_len 3 -+#define reg_debug23_pds_lsb 0 -+#define p_reg_debug22_pds 0xD858 -+#define reg_debug22_pds_pos 0 -+#define reg_debug22_pds_len 3 -+#define reg_debug22_pds_lsb 0 -+#define p_reg_gpioh1_pds 0xD859 -+#define reg_gpioh1_pds_pos 0 -+#define reg_gpioh1_pds_len 3 -+#define reg_gpioh1_pds_lsb 0 -+#define p_reg_gpioh2_pds 0xD85A -+#define reg_gpioh2_pds_pos 0 -+#define reg_gpioh2_pds_len 3 -+#define reg_gpioh2_pds_lsb 0 -+#define p_reg_gpioh3_pds 0xD85B -+#define reg_gpioh3_pds_pos 0 -+#define reg_gpioh3_pds_len 3 -+#define reg_gpioh3_pds_lsb 0 -+#define p_reg_gpioh4_pds 0xD85C -+#define reg_gpioh4_pds_pos 0 -+#define reg_gpioh4_pds_len 3 -+#define reg_gpioh4_pds_lsb 0 -+#define p_reg_iosda_pds 0xD85D -+#define reg_iosda_pds_pos 0 -+#define reg_iosda_pds_len 3 -+#define reg_iosda_pds_lsb 0 -+#define p_reg_ioscl_pds 0xD85E -+#define reg_ioscl_pds_pos 0 -+#define reg_ioscl_pds_len 3 -+#define reg_ioscl_pds_lsb 0 -+#define p_reg_gpioh5_pds 0xD85F -+#define reg_gpioh5_pds_pos 0 -+#define reg_gpioh5_pds_len 3 -+#define reg_gpioh5_pds_lsb 0 -+#define p_reg_bond0_pds 0xD860 -+#define reg_bond0_pds_pos 0 -+#define reg_bond0_pds_len 3 -+#define reg_bond0_pds_lsb 0 -+#define p_reg_i2caddr6_pds 0xD861 -+#define reg_i2caddr6_pds_pos 0 -+#define reg_i2caddr6_pds_len 3 -+#define reg_i2caddr6_pds_lsb 0 -+#define p_reg_i2caddr5_pds 0xD862 -+#define reg_i2caddr5_pds_pos 0 -+#define reg_i2caddr5_pds_len 3 -+#define reg_i2caddr5_pds_lsb 0 -+#define p_reg_i2caddr4_pds 0xD863 -+#define reg_i2caddr4_pds_pos 0 -+#define reg_i2caddr4_pds_len 3 -+#define reg_i2caddr4_pds_lsb 0 -+#define p_reg_host_a0_pds 0xD864 -+#define reg_host_a0_pds_pos 0 -+#define reg_host_a0_pds_len 3 -+#define reg_host_a0_pds_lsb 0 -+#define p_reg_host_a1_pds 0xD865 -+#define reg_host_a1_pds_pos 0 -+#define reg_host_a1_pds_len 3 -+#define reg_host_a1_pds_lsb 0 -+#define p_reg_debug21_pds 0xD866 -+#define reg_debug21_pds_pos 0 -+#define reg_debug21_pds_len 3 -+#define reg_debug21_pds_lsb 0 -+#define p_reg_debug20_pds 0xD867 -+#define reg_debug20_pds_pos 0 -+#define reg_debug20_pds_len 3 -+#define reg_debug20_pds_lsb 0 -+#define p_reg_debug19_pds 0xD868 -+#define reg_debug19_pds_pos 0 -+#define reg_debug19_pds_len 3 -+#define reg_debug19_pds_lsb 0 -+#define p_reg_debug18_pds 0xD869 -+#define reg_debug18_pds_pos 0 -+#define reg_debug18_pds_len 3 -+#define reg_debug18_pds_lsb 0 -+#define p_reg_debug17_pds 0xD86A -+#define reg_debug17_pds_pos 0 -+#define reg_debug17_pds_len 3 -+#define reg_debug17_pds_lsb 0 -+#define p_reg_host_a2_pds 0xD86B -+#define reg_host_a2_pds_pos 0 -+#define reg_host_a2_pds_len 3 -+#define reg_host_a2_pds_lsb 0 -+#define p_reg_host_a3_pds 0xD86C -+#define reg_host_a3_pds_pos 0 -+#define reg_host_a3_pds_len 3 -+#define reg_host_a3_pds_lsb 0 -+#define p_reg_host_a4_pds 0xD86D -+#define reg_host_a4_pds_pos 0 -+#define reg_host_a4_pds_len 3 -+#define reg_host_a4_pds_lsb 0 -+#define p_reg_host_a5_pds 0xD86E -+#define reg_host_a5_pds_pos 0 -+#define reg_host_a5_pds_len 3 -+#define reg_host_a5_pds_lsb 0 -+#define p_reg_host_a6_pds 0xD86F -+#define reg_host_a6_pds_pos 0 -+#define reg_host_a6_pds_len 3 -+#define reg_host_a6_pds_lsb 0 -+#define p_reg_p160sel_pds 0xD870 -+#define reg_p160sel_pds_pos 0 -+#define reg_p160sel_pds_len 3 -+#define reg_p160sel_pds_lsb 0 -+#define p_reg_gpioh13_pds 0xD871 -+#define reg_gpioh13_pds_pos 0 -+#define reg_gpioh13_pds_len 3 -+#define reg_gpioh13_pds_lsb 0 -+#define p_reg_gpioh12_pds 0xD872 -+#define reg_gpioh12_pds_pos 0 -+#define reg_gpioh12_pds_len 3 -+#define reg_gpioh12_pds_lsb 0 -+#define p_reg_gpioh11_pds 0xD873 -+#define reg_gpioh11_pds_pos 0 -+#define reg_gpioh11_pds_len 3 -+#define reg_gpioh11_pds_lsb 0 -+#define p_reg_host_a7_pds 0xD874 -+#define reg_host_a7_pds_pos 0 -+#define reg_host_a7_pds_len 3 -+#define reg_host_a7_pds_lsb 0 -+#define p_reg_host_a8_pds 0xD875 -+#define reg_host_a8_pds_pos 0 -+#define reg_host_a8_pds_len 3 -+#define reg_host_a8_pds_lsb 0 -+#define p_reg_host_a9_pds 0xD876 -+#define reg_host_a9_pds_pos 0 -+#define reg_host_a9_pds_len 3 -+#define reg_host_a9_pds_lsb 0 -+#define p_reg_host_a10_pds 0xD877 -+#define reg_host_a10_pds_pos 0 -+#define reg_host_a10_pds_len 3 -+#define reg_host_a10_pds_lsb 0 -+#define p_reg_host_a11_pds 0xD878 -+#define reg_host_a11_pds_pos 0 -+#define reg_host_a11_pds_len 3 -+#define reg_host_a11_pds_lsb 0 -+#define p_reg_bondu0_pds 0xD879 -+#define reg_bondu0_pds_pos 0 -+#define reg_bondu0_pds_len 3 -+#define reg_bondu0_pds_lsb 0 -+#define p_reg_host_b0_pds 0xD87A -+#define reg_host_b0_pds_pos 0 -+#define reg_host_b0_pds_len 3 -+#define reg_host_b0_pds_lsb 0 -+#define p_reg_host_b1_pds 0xD87B -+#define reg_host_b1_pds_pos 0 -+#define reg_host_b1_pds_len 3 -+#define reg_host_b1_pds_lsb 0 -+#define p_reg_host_b2_pds 0xD87C -+#define reg_host_b2_pds_pos 0 -+#define reg_host_b2_pds_len 3 -+#define reg_host_b2_pds_lsb 0 -+#define p_reg_host_b3_pds 0xD87D -+#define reg_host_b3_pds_pos 0 -+#define reg_host_b3_pds_len 3 -+#define reg_host_b3_pds_lsb 0 -+#define p_reg_host_b4_pds 0xD87E -+#define reg_host_b4_pds_pos 0 -+#define reg_host_b4_pds_len 3 -+#define reg_host_b4_pds_lsb 0 -+#define p_reg_host_b5_pds 0xD87F -+#define reg_host_b5_pds_pos 0 -+#define reg_host_b5_pds_len 3 -+#define reg_host_b5_pds_lsb 0 -+#define p_reg_host_b6_pds 0xD880 -+#define reg_host_b6_pds_pos 0 -+#define reg_host_b6_pds_len 3 -+#define reg_host_b6_pds_lsb 0 -+#define p_reg_host_b7_pds 0xD881 -+#define reg_host_b7_pds_pos 0 -+#define reg_host_b7_pds_len 3 -+#define reg_host_b7_pds_lsb 0 -+#define p_reg_afe_f12_pds 0xD882 -+#define reg_afe_f12_pds_pos 0 -+#define reg_afe_f12_pds_len 3 -+#define reg_afe_f12_pds_lsb 0 -+#define p_reg_host_b8_pds 0xD883 -+#define reg_host_b8_pds_pos 0 -+#define reg_host_b8_pds_len 3 -+#define reg_host_b8_pds_lsb 0 -+#define p_reg_host_b9_pds 0xD884 -+#define reg_host_b9_pds_pos 0 -+#define reg_host_b9_pds_len 3 -+#define reg_host_b9_pds_lsb 0 -+#define p_reg_host_b10_pds 0xD885 -+#define reg_host_b10_pds_pos 0 -+#define reg_host_b10_pds_len 3 -+#define reg_host_b10_pds_lsb 0 -+#define p_reg_host_b11_pds 0xD886 -+#define reg_host_b11_pds_pos 0 -+#define reg_host_b11_pds_len 3 -+#define reg_host_b11_pds_lsb 0 -+#define p_reg_debug16_pds 0xD887 -+#define reg_debug16_pds_pos 0 -+#define reg_debug16_pds_len 3 -+#define reg_debug16_pds_lsb 0 -+#define p_reg_debug15_pds 0xD888 -+#define reg_debug15_pds_pos 0 -+#define reg_debug15_pds_len 3 -+#define reg_debug15_pds_lsb 0 -+#define p_reg_debug14_pds 0xD889 -+#define reg_debug14_pds_pos 0 -+#define reg_debug14_pds_len 3 -+#define reg_debug14_pds_lsb 0 -+#define p_reg_debug13_pds 0xD88A -+#define reg_debug13_pds_pos 0 -+#define reg_debug13_pds_len 3 -+#define reg_debug13_pds_lsb 0 -+#define p_reg_debug12_pds 0xD88B -+#define reg_debug12_pds_pos 0 -+#define reg_debug12_pds_len 3 -+#define reg_debug12_pds_lsb 0 -+#define p_reg_debug11_pds 0xD88C -+#define reg_debug11_pds_pos 0 -+#define reg_debug11_pds_len 3 -+#define reg_debug11_pds_lsb 0 -+#define p_reg_debug10_pds 0xD88D -+#define reg_debug10_pds_pos 0 -+#define reg_debug10_pds_len 3 -+#define reg_debug10_pds_lsb 0 -+#define p_reg_debug9_pds 0xD88E -+#define reg_debug9_pds_pos 0 -+#define reg_debug9_pds_len 3 -+#define reg_debug9_pds_lsb 0 -+#define p_reg_debug8_pds 0xD88F -+#define reg_debug8_pds_pos 0 -+#define reg_debug8_pds_len 3 -+#define reg_debug8_pds_lsb 0 -+#define p_reg_debug7_pds 0xD890 -+#define reg_debug7_pds_pos 0 -+#define reg_debug7_pds_len 3 -+#define reg_debug7_pds_lsb 0 -+#define p_reg_debug6_pds 0xD891 -+#define reg_debug6_pds_pos 0 -+#define reg_debug6_pds_len 3 -+#define reg_debug6_pds_lsb 0 -+#define p_reg_debug5_pds 0xD892 -+#define reg_debug5_pds_pos 0 -+#define reg_debug5_pds_len 3 -+#define reg_debug5_pds_lsb 0 -+#define p_reg_debug4_pds 0xD893 -+#define reg_debug4_pds_pos 0 -+#define reg_debug4_pds_len 3 -+#define reg_debug4_pds_lsb 0 -+#define p_reg_clko_pds 0xD894 -+#define reg_clko_pds_pos 0 -+#define reg_clko_pds_len 3 -+#define reg_clko_pds_lsb 0 -+#define p_reg_gpioh6_pds 0xD895 -+#define reg_gpioh6_pds_pos 0 -+#define reg_gpioh6_pds_len 3 -+#define reg_gpioh6_pds_lsb 0 -+#define p_reg_gpioh7_pds 0xD896 -+#define reg_gpioh7_pds_pos 0 -+#define reg_gpioh7_pds_len 3 -+#define reg_gpioh7_pds_lsb 0 -+#define p_reg_gpioh8_pds 0xD897 -+#define reg_gpioh8_pds_pos 0 -+#define reg_gpioh8_pds_len 3 -+#define reg_gpioh8_pds_lsb 0 -+#define p_reg_gpioh9_pds 0xD898 -+#define reg_gpioh9_pds_pos 0 -+#define reg_gpioh9_pds_len 3 -+#define reg_gpioh9_pds_lsb 0 -+#define p_reg_gpioh10_pds 0xD899 -+#define reg_gpioh10_pds_pos 0 -+#define reg_gpioh10_pds_len 3 -+#define reg_gpioh10_pds_lsb 0 -+#define p_reg_debug3_pds 0xD89A -+#define reg_debug3_pds_pos 0 -+#define reg_debug3_pds_len 3 -+#define reg_debug3_pds_lsb 0 -+#define p_reg_debug2_pds 0xD89B -+#define reg_debug2_pds_pos 0 -+#define reg_debug2_pds_len 3 -+#define reg_debug2_pds_lsb 0 -+#define p_reg_debug1_pds 0xD89C -+#define reg_debug1_pds_pos 0 -+#define reg_debug1_pds_len 3 -+#define reg_debug1_pds_lsb 0 -+#define p_reg_debug0_pds 0xD89D -+#define reg_debug0_pds_pos 0 -+#define reg_debug0_pds_len 3 -+#define reg_debug0_pds_lsb 0 -+#define p_reg_gpiot1_pds 0xD89E -+#define reg_gpiot1_pds_pos 0 -+#define reg_gpiot1_pds_len 3 -+#define reg_gpiot1_pds_lsb 0 -+#define p_reg_gpiot2_pds 0xD89F -+#define reg_gpiot2_pds_pos 0 -+#define reg_gpiot2_pds_len 3 -+#define reg_gpiot2_pds_lsb 0 -+#define p_reg_rfagc_pds 0xD8A0 -+#define reg_rfagc_pds_pos 0 -+#define reg_rfagc_pds_len 3 -+#define reg_rfagc_pds_lsb 0 -+#define p_reg_ifagc_pds 0xD8A1 -+#define reg_ifagc_pds_pos 0 -+#define reg_ifagc_pds_len 3 -+#define reg_ifagc_pds_lsb 0 -+#define p_reg_gpiot3_pds 0xD8A2 -+#define reg_gpiot3_pds_pos 0 -+#define reg_gpiot3_pds_len 3 -+#define reg_gpiot3_pds_lsb 0 -+#define p_reg_i2caddr3_pds 0xD8A3 -+#define reg_i2caddr3_pds_pos 0 -+#define reg_i2caddr3_pds_len 3 -+#define reg_i2caddr3_pds_lsb 0 -+#define p_reg_i2caddr2_pds 0xD8A4 -+#define reg_i2caddr2_pds_pos 0 -+#define reg_i2caddr2_pds_len 3 -+#define reg_i2caddr2_pds_lsb 0 -+#define p_reg_i2caddr1_pds 0xD8A5 -+#define reg_i2caddr1_pds_pos 0 -+#define reg_i2caddr1_pds_len 3 -+#define reg_i2caddr1_pds_lsb 0 -+#define p_reg_afe_sel33_pds 0xD8A6 -+#define reg_afe_sel33_pds_pos 0 -+#define reg_afe_sel33_pds_len 3 -+#define reg_afe_sel33_pds_lsb 0 -+#define p_reg_iotunscl_pds 0xD8A7 -+#define reg_iotunscl_pds_pos 0 -+#define reg_iotunscl_pds_len 3 -+#define reg_iotunscl_pds_lsb 0 -+#define p_reg_iotunsda_pds 0xD8A8 -+#define reg_iotunsda_pds_pos 0 -+#define reg_iotunsda_pds_len 3 -+#define reg_iotunsda_pds_lsb 0 -+#define p_reg_rxdofsm_pds 0xD8A9 -+#define reg_rxdofsm_pds_pos 0 -+#define reg_rxdofsm_pds_len 3 -+#define reg_rxdofsm_pds_lsb 0 -+#define p_reg_txdofsm_pds 0xD8AA -+#define reg_txdofsm_pds_pos 0 -+#define reg_txdofsm_pds_len 3 -+#define reg_txdofsm_pds_lsb 0 -+#define p_reg_rxdlink_pds 0xD8AB -+#define reg_rxdlink_pds_pos 0 -+#define reg_rxdlink_pds_len 3 -+#define reg_rxdlink_pds_lsb 0 -+#define p_reg_txdlink_pds 0xD8AC -+#define reg_txdlink_pds_pos 0 -+#define reg_txdlink_pds_len 3 -+#define reg_txdlink_pds_lsb 0 -+#define p_reg_ck_test_pds 0xD8AD -+#define reg_ck_test_pds_pos 0 -+#define reg_ck_test_pds_len 3 -+#define reg_ck_test_pds_lsb 0 -+#define r_reg_top_gpioh1_i 0xD8AE -+#define reg_top_gpioh1_i_pos 0 -+#define reg_top_gpioh1_i_len 1 -+#define reg_top_gpioh1_i_lsb 0 -+#define p_reg_top_gpioh1_o 0xD8AF -+#define reg_top_gpioh1_o_pos 0 -+#define reg_top_gpioh1_o_len 1 -+#define reg_top_gpioh1_o_lsb 0 -+#define p_reg_top_gpioh1_en 0xD8B0 -+#define reg_top_gpioh1_en_pos 0 -+#define reg_top_gpioh1_en_len 1 -+#define reg_top_gpioh1_en_lsb 0 -+#define p_reg_top_gpioh1_on 0xD8B1 -+#define reg_top_gpioh1_on_pos 0 -+#define reg_top_gpioh1_on_len 1 -+#define reg_top_gpioh1_on_lsb 0 -+#define r_reg_top_gpioh3_i 0xD8B2 -+#define reg_top_gpioh3_i_pos 0 -+#define reg_top_gpioh3_i_len 1 -+#define reg_top_gpioh3_i_lsb 0 -+#define p_reg_top_gpioh3_o 0xD8B3 -+#define reg_top_gpioh3_o_pos 0 -+#define reg_top_gpioh3_o_len 1 -+#define reg_top_gpioh3_o_lsb 0 -+#define p_reg_top_gpioh3_en 0xD8B4 -+#define reg_top_gpioh3_en_pos 0 -+#define reg_top_gpioh3_en_len 1 -+#define reg_top_gpioh3_en_lsb 0 -+#define p_reg_top_gpioh3_on 0xD8B5 -+#define reg_top_gpioh3_on_pos 0 -+#define reg_top_gpioh3_on_len 1 -+#define reg_top_gpioh3_on_lsb 0 -+#define r_reg_top_gpioh2_i 0xD8B6 -+#define reg_top_gpioh2_i_pos 0 -+#define reg_top_gpioh2_i_len 1 -+#define reg_top_gpioh2_i_lsb 0 -+#define p_reg_top_gpioh2_o 0xD8B7 -+#define reg_top_gpioh2_o_pos 0 -+#define reg_top_gpioh2_o_len 1 -+#define reg_top_gpioh2_o_lsb 0 -+#define p_reg_top_gpioh2_en 0xD8B8 -+#define reg_top_gpioh2_en_pos 0 -+#define reg_top_gpioh2_en_len 1 -+#define reg_top_gpioh2_en_lsb 0 -+#define p_reg_top_gpioh2_on 0xD8B9 -+#define reg_top_gpioh2_on_pos 0 -+#define reg_top_gpioh2_on_len 1 -+#define reg_top_gpioh2_on_lsb 0 -+#define r_reg_top_gpioh5_i 0xD8BA -+#define reg_top_gpioh5_i_pos 0 -+#define reg_top_gpioh5_i_len 1 -+#define reg_top_gpioh5_i_lsb 0 -+#define p_reg_top_gpioh5_o 0xD8BB -+#define reg_top_gpioh5_o_pos 0 -+#define reg_top_gpioh5_o_len 1 -+#define reg_top_gpioh5_o_lsb 0 -+#define p_reg_top_gpioh5_en 0xD8BC -+#define reg_top_gpioh5_en_pos 0 -+#define reg_top_gpioh5_en_len 1 -+#define reg_top_gpioh5_en_lsb 0 -+#define p_reg_top_gpioh5_on 0xD8BD -+#define reg_top_gpioh5_on_pos 0 -+#define reg_top_gpioh5_on_len 1 -+#define reg_top_gpioh5_on_lsb 0 -+#define r_reg_top_gpioh4_i 0xD8BE -+#define reg_top_gpioh4_i_pos 0 -+#define reg_top_gpioh4_i_len 1 -+#define reg_top_gpioh4_i_lsb 0 -+#define p_reg_top_gpioh4_o 0xD8BF -+#define reg_top_gpioh4_o_pos 0 -+#define reg_top_gpioh4_o_len 1 -+#define reg_top_gpioh4_o_lsb 0 -+#define p_reg_top_gpioh4_en 0xD8C0 -+#define reg_top_gpioh4_en_pos 0 -+#define reg_top_gpioh4_en_len 1 -+#define reg_top_gpioh4_en_lsb 0 -+#define p_reg_top_gpioh4_on 0xD8C1 -+#define reg_top_gpioh4_on_pos 0 -+#define reg_top_gpioh4_on_len 1 -+#define reg_top_gpioh4_on_lsb 0 -+#define r_reg_top_gpioh7_i 0xD8C2 -+#define reg_top_gpioh7_i_pos 0 -+#define reg_top_gpioh7_i_len 1 -+#define reg_top_gpioh7_i_lsb 0 -+#define p_reg_top_gpioh7_o 0xD8C3 -+#define reg_top_gpioh7_o_pos 0 -+#define reg_top_gpioh7_o_len 1 -+#define reg_top_gpioh7_o_lsb 0 -+#define p_reg_top_gpioh7_en 0xD8C4 -+#define reg_top_gpioh7_en_pos 0 -+#define reg_top_gpioh7_en_len 1 -+#define reg_top_gpioh7_en_lsb 0 -+#define p_reg_top_gpioh7_on 0xD8C5 -+#define reg_top_gpioh7_on_pos 0 -+#define reg_top_gpioh7_on_len 1 -+#define reg_top_gpioh7_on_lsb 0 -+#define r_reg_top_gpioh6_i 0xD8C6 -+#define reg_top_gpioh6_i_pos 0 -+#define reg_top_gpioh6_i_len 1 -+#define reg_top_gpioh6_i_lsb 0 -+#define p_reg_top_gpioh6_o 0xD8C7 -+#define reg_top_gpioh6_o_pos 0 -+#define reg_top_gpioh6_o_len 1 -+#define reg_top_gpioh6_o_lsb 0 -+#define p_reg_top_gpioh6_en 0xD8C8 -+#define reg_top_gpioh6_en_pos 0 -+#define reg_top_gpioh6_en_len 1 -+#define reg_top_gpioh6_en_lsb 0 -+#define p_reg_top_gpioh6_on 0xD8C9 -+#define reg_top_gpioh6_on_pos 0 -+#define reg_top_gpioh6_on_len 1 -+#define reg_top_gpioh6_on_lsb 0 -+#define r_reg_top_gpioh9_i 0xD8CA -+#define reg_top_gpioh9_i_pos 0 -+#define reg_top_gpioh9_i_len 1 -+#define reg_top_gpioh9_i_lsb 0 -+#define p_reg_top_gpioh9_o 0xD8CB -+#define reg_top_gpioh9_o_pos 0 -+#define reg_top_gpioh9_o_len 1 -+#define reg_top_gpioh9_o_lsb 0 -+#define p_reg_top_gpioh9_en 0xD8CC -+#define reg_top_gpioh9_en_pos 0 -+#define reg_top_gpioh9_en_len 1 -+#define reg_top_gpioh9_en_lsb 0 -+#define p_reg_top_gpioh9_on 0xD8CD -+#define reg_top_gpioh9_on_pos 0 -+#define reg_top_gpioh9_on_len 1 -+#define reg_top_gpioh9_on_lsb 0 -+#define r_reg_top_gpioh8_i 0xD8CE -+#define reg_top_gpioh8_i_pos 0 -+#define reg_top_gpioh8_i_len 1 -+#define reg_top_gpioh8_i_lsb 0 -+#define p_reg_top_gpioh8_o 0xD8CF -+#define reg_top_gpioh8_o_pos 0 -+#define reg_top_gpioh8_o_len 1 -+#define reg_top_gpioh8_o_lsb 0 -+#define p_reg_top_gpioh8_en 0xD8D0 -+#define reg_top_gpioh8_en_pos 0 -+#define reg_top_gpioh8_en_len 1 -+#define reg_top_gpioh8_en_lsb 0 -+#define p_reg_top_gpioh8_on 0xD8D1 -+#define reg_top_gpioh8_on_pos 0 -+#define reg_top_gpioh8_on_len 1 -+#define reg_top_gpioh8_on_lsb 0 -+#define r_reg_top_gpioh11_i 0xD8D2 -+#define reg_top_gpioh11_i_pos 0 -+#define reg_top_gpioh11_i_len 1 -+#define reg_top_gpioh11_i_lsb 0 -+#define p_reg_top_gpioh11_o 0xD8D3 -+#define reg_top_gpioh11_o_pos 0 -+#define reg_top_gpioh11_o_len 1 -+#define reg_top_gpioh11_o_lsb 0 -+#define p_reg_top_gpioh11_en 0xD8D4 -+#define reg_top_gpioh11_en_pos 0 -+#define reg_top_gpioh11_en_len 1 -+#define reg_top_gpioh11_en_lsb 0 -+#define p_reg_top_gpioh11_on 0xD8D5 -+#define reg_top_gpioh11_on_pos 0 -+#define reg_top_gpioh11_on_len 1 -+#define reg_top_gpioh11_on_lsb 0 -+#define r_reg_top_gpioh10_i 0xD8D6 -+#define reg_top_gpioh10_i_pos 0 -+#define reg_top_gpioh10_i_len 1 -+#define reg_top_gpioh10_i_lsb 0 -+#define p_reg_top_gpioh10_o 0xD8D7 -+#define reg_top_gpioh10_o_pos 0 -+#define reg_top_gpioh10_o_len 1 -+#define reg_top_gpioh10_o_lsb 0 -+#define p_reg_top_gpioh10_en 0xD8D8 -+#define reg_top_gpioh10_en_pos 0 -+#define reg_top_gpioh10_en_len 1 -+#define reg_top_gpioh10_en_lsb 0 -+#define p_reg_top_gpioh10_on 0xD8D9 -+#define reg_top_gpioh10_on_pos 0 -+#define reg_top_gpioh10_on_len 1 -+#define reg_top_gpioh10_on_lsb 0 -+#define r_reg_top_gpioh13_i 0xD8DA -+#define reg_top_gpioh13_i_pos 0 -+#define reg_top_gpioh13_i_len 1 -+#define reg_top_gpioh13_i_lsb 0 -+#define p_reg_top_gpioh13_o 0xD8DB -+#define reg_top_gpioh13_o_pos 0 -+#define reg_top_gpioh13_o_len 1 -+#define reg_top_gpioh13_o_lsb 0 -+#define p_reg_top_gpioh13_en 0xD8DC -+#define reg_top_gpioh13_en_pos 0 -+#define reg_top_gpioh13_en_len 1 -+#define reg_top_gpioh13_en_lsb 0 -+#define p_reg_top_gpioh13_on 0xD8DD -+#define reg_top_gpioh13_on_pos 0 -+#define reg_top_gpioh13_on_len 1 -+#define reg_top_gpioh13_on_lsb 0 -+#define r_reg_top_gpioh12_i 0xD8DE -+#define reg_top_gpioh12_i_pos 0 -+#define reg_top_gpioh12_i_len 1 -+#define reg_top_gpioh12_i_lsb 0 -+#define p_reg_top_gpioh12_o 0xD8DF -+#define reg_top_gpioh12_o_pos 0 -+#define reg_top_gpioh12_o_len 1 -+#define reg_top_gpioh12_o_lsb 0 -+#define p_reg_top_gpioh12_en 0xD8E0 -+#define reg_top_gpioh12_en_pos 0 -+#define reg_top_gpioh12_en_len 1 -+#define reg_top_gpioh12_en_lsb 0 -+#define p_reg_top_gpioh12_on 0xD8E1 -+#define reg_top_gpioh12_on_pos 0 -+#define reg_top_gpioh12_on_len 1 -+#define reg_top_gpioh12_on_lsb 0 -+#define r_reg_top_gpiot1_i 0xD8E2 -+#define reg_top_gpiot1_i_pos 0 -+#define reg_top_gpiot1_i_len 1 -+#define reg_top_gpiot1_i_lsb 0 -+#define p_reg_top_gpiot1_o 0xD8E3 -+#define reg_top_gpiot1_o_pos 0 -+#define reg_top_gpiot1_o_len 1 -+#define reg_top_gpiot1_o_lsb 0 -+#define p_reg_top_gpiot1_en 0xD8E4 -+#define reg_top_gpiot1_en_pos 0 -+#define reg_top_gpiot1_en_len 1 -+#define reg_top_gpiot1_en_lsb 0 -+#define p_reg_top_gpiot1_on 0xD8E5 -+#define reg_top_gpiot1_on_pos 0 -+#define reg_top_gpiot1_on_len 1 -+#define reg_top_gpiot1_on_lsb 0 -+#define r_reg_top_gpiot3_i 0xD8E6 -+#define reg_top_gpiot3_i_pos 0 -+#define reg_top_gpiot3_i_len 1 -+#define reg_top_gpiot3_i_lsb 0 -+#define p_reg_top_gpiot3_o 0xD8E7 -+#define reg_top_gpiot3_o_pos 0 -+#define reg_top_gpiot3_o_len 1 -+#define reg_top_gpiot3_o_lsb 0 -+#define p_reg_top_gpiot3_en 0xD8E8 -+#define reg_top_gpiot3_en_pos 0 -+#define reg_top_gpiot3_en_len 1 -+#define reg_top_gpiot3_en_lsb 0 -+#define p_reg_top_gpiot3_on 0xD8E9 -+#define reg_top_gpiot3_on_pos 0 -+#define reg_top_gpiot3_on_len 1 -+#define reg_top_gpiot3_on_lsb 0 -+#define r_reg_top_gpiot2_i 0xD8EA -+#define reg_top_gpiot2_i_pos 0 -+#define reg_top_gpiot2_i_len 1 -+#define reg_top_gpiot2_i_lsb 0 -+#define p_reg_top_gpiot2_o 0xD8EB -+#define reg_top_gpiot2_o_pos 0 -+#define reg_top_gpiot2_o_len 1 -+#define reg_top_gpiot2_o_lsb 0 -+#define p_reg_top_gpiot2_en 0xD8EC -+#define reg_top_gpiot2_en_pos 0 -+#define reg_top_gpiot2_en_len 1 -+#define reg_top_gpiot2_en_lsb 0 -+#define p_reg_top_gpiot2_on 0xD8ED -+#define reg_top_gpiot2_on_pos 0 -+#define reg_top_gpiot2_on_len 1 -+#define reg_top_gpiot2_on_lsb 0 -+#define p_reg_top_lock2_out 0xD8EE -+#define reg_top_lock2_out_pos 0 -+#define reg_top_lock2_out_len 1 -+#define reg_top_lock2_out_lsb 0 -+#define p_reg_top_lock2_tpsd 0xD8EF -+#define reg_top_lock2_tpsd_pos 0 -+#define reg_top_lock2_tpsd_len 1 -+#define reg_top_lock2_tpsd_lsb 0 -+#define p_reg_top_lock2_o 0xD8F0 -+#define reg_top_lock2_o_pos 0 -+#define reg_top_lock2_o_len 1 -+#define reg_top_lock2_o_lsb 0 -+#define p_reg_top_lock2_en 0xD8F1 -+#define reg_top_lock2_en_pos 0 -+#define reg_top_lock2_en_len 1 -+#define reg_top_lock2_en_lsb 0 -+#define p_reg_top_lock2_on 0xD8F2 -+#define reg_top_lock2_on_pos 0 -+#define reg_top_lock2_on_len 1 -+#define reg_top_lock2_on_lsb 0 -+#define p_reg_top_lock1_out 0xD8F3 -+#define reg_top_lock1_out_pos 0 -+#define reg_top_lock1_out_len 1 -+#define reg_top_lock1_out_lsb 0 -+#define p_reg_top_lock1_tpsd 0xD8F4 -+#define reg_top_lock1_tpsd_pos 0 -+#define reg_top_lock1_tpsd_len 1 -+#define reg_top_lock1_tpsd_lsb 0 -+#define p_reg_top_lock1_o 0xD8F5 -+#define reg_top_lock1_o_pos 0 -+#define reg_top_lock1_o_len 1 -+#define reg_top_lock1_o_lsb 0 -+#define p_reg_top_lock1_en 0xD8F6 -+#define reg_top_lock1_en_pos 0 -+#define reg_top_lock1_en_len 1 -+#define reg_top_lock1_en_lsb 0 -+#define p_reg_top_lock1_on 0xD8F7 -+#define reg_top_lock1_on_pos 0 -+#define reg_top_lock1_on_len 1 -+#define reg_top_lock1_on_lsb 0 -+#define p_reg_top_lock4_out 0xD8F8 -+#define reg_top_lock4_out_pos 0 -+#define reg_top_lock4_out_len 1 -+#define reg_top_lock4_out_lsb 0 -+#define p_reg_top_lock4_tpsd 0xD8F9 -+#define reg_top_lock4_tpsd_pos 0 -+#define reg_top_lock4_tpsd_len 1 -+#define reg_top_lock4_tpsd_lsb 0 -+#define p_reg_top_lock4_o 0xD8FA -+#define reg_top_lock4_o_pos 0 -+#define reg_top_lock4_o_len 1 -+#define reg_top_lock4_o_lsb 0 -+#define p_reg_top_lock4_en 0xD8FB -+#define reg_top_lock4_en_pos 0 -+#define reg_top_lock4_en_len 1 -+#define reg_top_lock4_en_lsb 0 -+#define p_reg_top_lock4_on 0xD8FC -+#define reg_top_lock4_on_pos 0 -+#define reg_top_lock4_on_len 1 -+#define reg_top_lock4_on_lsb 0 -+#define p_reg_top_lock3_out 0xD8FD -+#define reg_top_lock3_out_pos 0 -+#define reg_top_lock3_out_len 1 -+#define reg_top_lock3_out_lsb 0 -+#define p_reg_top_lock3_tpsd 0xD8FE -+#define reg_top_lock3_tpsd_pos 0 -+#define reg_top_lock3_tpsd_len 1 -+#define reg_top_lock3_tpsd_lsb 0 -+#define p_reg_top_lock3_o 0xD8FF -+#define reg_top_lock3_o_pos 0 -+#define reg_top_lock3_o_len 1 -+#define reg_top_lock3_o_lsb 0 -+#define p_reg_top_lock3_en 0xD900 -+#define reg_top_lock3_en_pos 0 -+#define reg_top_lock3_en_len 1 -+#define reg_top_lock3_en_lsb 0 -+#define p_reg_top_lock3_on 0xD901 -+#define reg_top_lock3_on_pos 0 -+#define reg_top_lock3_on_len 1 -+#define reg_top_lock3_on_lsb 0 -+#define p_reg_top_pwm0_en 0xD902 -+#define reg_top_pwm0_en_pos 0 -+#define reg_top_pwm0_en_len 1 -+#define reg_top_pwm0_en_lsb 0 -+#define p_reg_top_pwm1_en 0xD903 -+#define reg_top_pwm1_en_pos 0 -+#define reg_top_pwm1_en_len 1 -+#define reg_top_pwm1_en_lsb 0 -+#define p_reg_top_pwm2_en 0xD904 -+#define reg_top_pwm2_en_pos 0 -+#define reg_top_pwm2_en_len 1 -+#define reg_top_pwm2_en_lsb 0 -+#define p_reg_top_pwm3_en 0xD905 -+#define reg_top_pwm3_en_pos 0 -+#define reg_top_pwm3_en_len 1 -+#define reg_top_pwm3_en_lsb 0 -+#define p_reg_top_pwm0_gpio 0xD906 -+#define reg_top_pwm0_gpio_pos 0 -+#define reg_top_pwm0_gpio_len 1 -+#define reg_top_pwm0_gpio_lsb 0 -+#define p_reg_top_pwm0_pos 0xD907 -+#define reg_top_pwm0_pos_pos 0 -+#define reg_top_pwm0_pos_len 3 -+#define reg_top_pwm0_pos_lsb 0 -+#define p_reg_top_pwm0_width 0xD908 -+#define reg_top_pwm0_width_pos 0 -+#define reg_top_pwm0_width_len 2 -+#define reg_top_pwm0_width_lsb 0 -+#define p_reg_top_pwm0_duration 0xD909 -+#define reg_top_pwm0_duration_pos 0 -+#define reg_top_pwm0_duration_len 8 -+#define reg_top_pwm0_duration_lsb 0 -+#define p_reg_top_pwm1_gpio 0xD90A -+#define reg_top_pwm1_gpio_pos 0 -+#define reg_top_pwm1_gpio_len 1 -+#define reg_top_pwm1_gpio_lsb 0 -+#define p_reg_top_pwm1_pos 0xD90B -+#define reg_top_pwm1_pos_pos 0 -+#define reg_top_pwm1_pos_len 3 -+#define reg_top_pwm1_pos_lsb 0 -+#define p_reg_top_pwm1_width 0xD90C -+#define reg_top_pwm1_width_pos 0 -+#define reg_top_pwm1_width_len 2 -+#define reg_top_pwm1_width_lsb 0 -+#define p_reg_top_pwm1_duration 0xD90D -+#define reg_top_pwm1_duration_pos 0 -+#define reg_top_pwm1_duration_len 8 -+#define reg_top_pwm1_duration_lsb 0 -+#define p_reg_top_pwm2_gpio 0xD90E -+#define reg_top_pwm2_gpio_pos 0 -+#define reg_top_pwm2_gpio_len 1 -+#define reg_top_pwm2_gpio_lsb 0 -+#define p_reg_top_pwm2_pos 0xD90F -+#define reg_top_pwm2_pos_pos 0 -+#define reg_top_pwm2_pos_len 3 -+#define reg_top_pwm2_pos_lsb 0 -+#define p_reg_top_pwm2_width 0xD910 -+#define reg_top_pwm2_width_pos 0 -+#define reg_top_pwm2_width_len 2 -+#define reg_top_pwm2_width_lsb 0 -+#define p_reg_top_pwm2_duration 0xD911 -+#define reg_top_pwm2_duration_pos 0 -+#define reg_top_pwm2_duration_len 8 -+#define reg_top_pwm2_duration_lsb 0 -+#define p_reg_top_pwm3_gpio 0xD912 -+#define reg_top_pwm3_gpio_pos 0 -+#define reg_top_pwm3_gpio_len 1 -+#define reg_top_pwm3_gpio_lsb 0 -+#define p_reg_top_pwm3_pos 0xD913 -+#define reg_top_pwm3_pos_pos 0 -+#define reg_top_pwm3_pos_len 3 -+#define reg_top_pwm3_pos_lsb 0 -+#define p_reg_top_pwm3_width 0xD914 -+#define reg_top_pwm3_width_pos 0 -+#define reg_top_pwm3_width_len 2 -+#define reg_top_pwm3_width_lsb 0 -+#define p_reg_top_pwm3_duration 0xD915 -+#define reg_top_pwm3_duration_pos 0 -+#define reg_top_pwm3_duration_len 8 -+#define reg_top_pwm3_duration_lsb 0 -+#define p_reg_top_hosta_mpeg_par_mode 0xD916 -+#define reg_top_hosta_mpeg_par_mode_pos 0 -+#define reg_top_hosta_mpeg_par_mode_len 1 -+#define reg_top_hosta_mpeg_par_mode_lsb 0 -+#define p_reg_top_hosta_mpeg_ser_mode 0xD917 -+#define reg_top_hosta_mpeg_ser_mode_pos 0 -+#define reg_top_hosta_mpeg_ser_mode_len 1 -+#define reg_top_hosta_mpeg_ser_mode_lsb 0 -+#define p_reg_top_hosta_mpeg_ser_do7 0xD918 -+#define reg_top_hosta_mpeg_ser_do7_pos 0 -+#define reg_top_hosta_mpeg_ser_do7_len 1 -+#define reg_top_hosta_mpeg_ser_do7_lsb 0 -+#define p_reg_top_hosta_dca_upper 0xD919 -+#define reg_top_hosta_dca_upper_pos 0 -+#define reg_top_hosta_dca_upper_len 1 -+#define reg_top_hosta_dca_upper_lsb 0 -+#define p_reg_top_hosta_dca_lower 0xD91A -+#define reg_top_hosta_dca_lower_pos 0 -+#define reg_top_hosta_dca_lower_len 1 -+#define reg_top_hosta_dca_lower_lsb 0 -+#define p_reg_top_hostb_mpeg_par_mode 0xD91B -+#define reg_top_hostb_mpeg_par_mode_pos 0 -+#define reg_top_hostb_mpeg_par_mode_len 1 -+#define reg_top_hostb_mpeg_par_mode_lsb 0 -+#define p_reg_top_hostb_mpeg_ser_mode 0xD91C -+#define reg_top_hostb_mpeg_ser_mode_pos 0 -+#define reg_top_hostb_mpeg_ser_mode_len 1 -+#define reg_top_hostb_mpeg_ser_mode_lsb 0 -+#define p_reg_top_hostb_mpeg_ser_do7 0xD91D -+#define reg_top_hostb_mpeg_ser_do7_pos 0 -+#define reg_top_hostb_mpeg_ser_do7_len 1 -+#define reg_top_hostb_mpeg_ser_do7_lsb 0 -+#define p_reg_top_hostb_dca_upper 0xD91E -+#define reg_top_hostb_dca_upper_pos 0 -+#define reg_top_hostb_dca_upper_len 1 -+#define reg_top_hostb_dca_upper_lsb 0 -+#define p_reg_top_hostb_dca_lower 0xD91F -+#define reg_top_hostb_dca_lower_pos 0 -+#define reg_top_hostb_dca_lower_len 1 -+#define reg_top_hostb_dca_lower_lsb 0 -+#define p_reg_top_host_reverse 0xD920 -+#define reg_top_host_reverse_pos 0 -+#define reg_top_host_reverse_len 1 -+#define reg_top_host_reverse_lsb 0 -+#define p_reg_top_hosta_ccir 0xD921 -+#define reg_top_hosta_ccir_pos 0 -+#define reg_top_hosta_ccir_len 1 -+#define reg_top_hosta_ccir_lsb 0 -+#define p_reg_top_hostb_ccir 0xD922 -+#define reg_top_hostb_ccir_pos 0 -+#define reg_top_hostb_ccir_len 1 -+#define reg_top_hostb_ccir_lsb 0 -+#define p_reg_top_i2s_master_mode 0xD923 -+#define reg_top_i2s_master_mode_pos 0 -+#define reg_top_i2s_master_mode_len 1 -+#define reg_top_i2s_master_mode_lsb 0 -+#define p_reg_usb_cfg_speed 0xDD00 -+#define reg_usb_cfg_speed_pos 0 -+#define reg_usb_cfg_speed_len 1 -+#define reg_usb_cfg_speed_lsb 0 -+#define p_reg_usb_cfg_utmi16 0xDD00 -+#define reg_usb_cfg_utmi16_pos 1 -+#define reg_usb_cfg_utmi16_len 1 -+#define reg_usb_cfg_utmi16_lsb 0 -+#define p_reg_usb_cfg_test 0xDD00 -+#define reg_usb_cfg_test_pos 3 -+#define reg_usb_cfg_test_len 3 -+#define reg_usb_cfg_test_lsb 0 -+#define p_reg_usb_port_sim_reset 0xDD00 -+#define reg_usb_port_sim_reset_pos 6 -+#define reg_usb_port_sim_reset_len 1 -+#define reg_usb_port_sim_reset_lsb 0 -+#define p_reg_usb_port_run 0xDD00 -+#define reg_usb_port_run_pos 7 -+#define reg_usb_port_run_len 1 -+#define reg_usb_port_run_lsb 0 -+#define r_usb_line_state_0 0xDD01 -+#define usb_line_state_0_pos 0 -+#define usb_line_state_0_len 1 -+#define usb_line_state_0_lsb 0 -+#define r_usb_line_state_1 0xDD01 -+#define usb_line_state_1_pos 1 -+#define usb_line_state_1_len 1 -+#define usb_line_state_1_lsb 0 -+#define r_reg_usb_status_speed 0xDD01 -+#define reg_usb_status_speed_pos 2 -+#define reg_usb_status_speed_len 1 -+#define reg_usb_status_speed_lsb 0 -+#define r_reg_usb_status_connect 0xDD01 -+#define reg_usb_status_connect_pos 3 -+#define reg_usb_status_connect_len 1 -+#define reg_usb_status_connect_lsb 0 -+#define r_reg_usb_rx_buf 0xDD01 -+#define reg_usb_rx_buf_pos 4 -+#define reg_usb_rx_buf_len 1 -+#define reg_usb_rx_buf_lsb 0 -+#define r_reg_usb_port_reset 0xDD01 -+#define reg_usb_port_reset_pos 5 -+#define reg_usb_port_reset_len 1 -+#define reg_usb_port_reset_lsb 0 -+#define r_reg_usb_port_suspend 0xDD01 -+#define reg_usb_port_suspend_pos 6 -+#define reg_usb_port_suspend_len 1 -+#define reg_usb_port_suspend_lsb 0 -+#define p_reg_ep1_tx_type 0xDD07 -+#define reg_ep1_tx_type_pos 2 -+#define reg_ep1_tx_type_len 1 -+#define reg_ep1_tx_type_lsb 0 -+#define p_reg_ep2_rx_type 0xDD07 -+#define reg_ep2_rx_type_pos 3 -+#define reg_ep2_rx_type_len 1 -+#define reg_ep2_rx_type_lsb 0 -+#define p_reg_ep3_tx_type 0xDD07 -+#define reg_ep3_tx_type_pos 4 -+#define reg_ep3_tx_type_len 1 -+#define reg_ep3_tx_type_lsb 0 -+#define p_reg_ep4_tx_type 0xDD07 -+#define reg_ep4_tx_type_pos 5 -+#define reg_ep4_tx_type_len 1 -+#define reg_ep4_tx_type_lsb 0 -+#define p_reg_ep5_tx_type 0xDD07 -+#define reg_ep5_tx_type_pos 6 -+#define reg_ep5_tx_type_len 1 -+#define reg_ep5_tx_type_lsb 0 -+#define p_reg_ep6_tx_type 0xDD07 -+#define reg_ep6_tx_type_pos 7 -+#define reg_ep6_tx_type_len 1 -+#define reg_ep6_tx_type_lsb 0 -+#define p_reg_ep0_max_pkt 0xDD08 -+#define reg_ep0_max_pkt_pos 0 -+#define reg_ep0_max_pkt_len 8 -+#define reg_ep0_max_pkt_lsb 0 -+#define p_reg_ep2_max_pkt 0xDD0A -+#define reg_ep2_max_pkt_pos 0 -+#define reg_ep2_max_pkt_len 8 -+#define reg_ep2_max_pkt_lsb 0 -+#define p_reg_ep4_max_pkt 0xDD0C -+#define reg_ep4_max_pkt_pos 0 -+#define reg_ep4_max_pkt_len 8 -+#define reg_ep4_max_pkt_lsb 0 -+#define p_reg_ep5_max_pkt 0xDD0D -+#define reg_ep5_max_pkt_pos 0 -+#define reg_ep5_max_pkt_len 8 -+#define reg_ep5_max_pkt_lsb 0 -+#define p_reg_ep6_max_pkt_7_0 0xDD0E -+#define reg_ep6_max_pkt_7_0_pos 0 -+#define reg_ep6_max_pkt_7_0_len 8 -+#define reg_ep6_max_pkt_7_0_lsb 0 -+#define p_reg_ep6_max_pkt_15_8 0xDD0F -+#define reg_ep6_max_pkt_15_8_pos 0 -+#define reg_ep6_max_pkt_15_8_len 8 -+#define reg_ep6_max_pkt_15_8_lsb 8 -+#define p_reg_usb_addr 0xDD10 -+#define reg_usb_addr_pos 0 -+#define reg_usb_addr_len 7 -+#define reg_usb_addr_lsb 0 -+#define p_reg_usb_addr_now 0xDD10 -+#define reg_usb_addr_now_pos 7 -+#define reg_usb_addr_now_len 1 -+#define reg_usb_addr_now_lsb 0 -+#define p_reg_ep0_tx_en 0xDD11 -+#define reg_ep0_tx_en_pos 0 -+#define reg_ep0_tx_en_len 1 -+#define reg_ep0_tx_en_lsb 0 -+#define p_reg_ep0_rx_en 0xDD11 -+#define reg_ep0_rx_en_pos 1 -+#define reg_ep0_rx_en_len 1 -+#define reg_ep0_rx_en_lsb 0 -+#define p_reg_ep1_tx_en 0xDD11 -+#define reg_ep1_tx_en_pos 2 -+#define reg_ep1_tx_en_len 1 -+#define reg_ep1_tx_en_lsb 0 -+#define p_reg_ep2_rx_en 0xDD11 -+#define reg_ep2_rx_en_pos 3 -+#define reg_ep2_rx_en_len 1 -+#define reg_ep2_rx_en_lsb 0 -+#define p_reg_ep3_tx_en 0xDD11 -+#define reg_ep3_tx_en_pos 4 -+#define reg_ep3_tx_en_len 1 -+#define reg_ep3_tx_en_lsb 0 -+#define p_reg_ep4_tx_en 0xDD11 -+#define reg_ep4_tx_en_pos 5 -+#define reg_ep4_tx_en_len 1 -+#define reg_ep4_tx_en_lsb 0 -+#define p_reg_ep5_tx_en 0xDD11 -+#define reg_ep5_tx_en_pos 6 -+#define reg_ep5_tx_en_len 1 -+#define reg_ep5_tx_en_lsb 0 -+#define p_reg_ep6_tx_en 0xDD11 -+#define reg_ep6_tx_en_pos 7 -+#define reg_ep6_tx_en_len 1 -+#define reg_ep6_tx_en_lsb 0 -+#define p_reg_ep0_tx_stall 0xDD12 -+#define reg_ep0_tx_stall_pos 0 -+#define reg_ep0_tx_stall_len 1 -+#define reg_ep0_tx_stall_lsb 0 -+#define p_reg_ep0_rx_stall 0xDD12 -+#define reg_ep0_rx_stall_pos 1 -+#define reg_ep0_rx_stall_len 1 -+#define reg_ep0_rx_stall_lsb 0 -+#define p_reg_ep1_tx_stall 0xDD12 -+#define reg_ep1_tx_stall_pos 2 -+#define reg_ep1_tx_stall_len 1 -+#define reg_ep1_tx_stall_lsb 0 -+#define p_reg_ep2_rx_stall 0xDD12 -+#define reg_ep2_rx_stall_pos 3 -+#define reg_ep2_rx_stall_len 1 -+#define reg_ep2_rx_stall_lsb 0 -+#define p_reg_ep3_tx_stall 0xDD12 -+#define reg_ep3_tx_stall_pos 4 -+#define reg_ep3_tx_stall_len 1 -+#define reg_ep3_tx_stall_lsb 0 -+#define p_reg_ep4_tx_stall 0xDD12 -+#define reg_ep4_tx_stall_pos 5 -+#define reg_ep4_tx_stall_len 1 -+#define reg_ep4_tx_stall_lsb 0 -+#define p_reg_ep5_tx_stall 0xDD12 -+#define reg_ep5_tx_stall_pos 6 -+#define reg_ep5_tx_stall_len 1 -+#define reg_ep5_tx_stall_lsb 0 -+#define p_reg_ep6_tx_stall 0xDD12 -+#define reg_ep6_tx_stall_pos 7 -+#define reg_ep6_tx_stall_len 1 -+#define reg_ep6_tx_stall_lsb 0 -+#define p_reg_ep0_tx_nak 0xDD13 -+#define reg_ep0_tx_nak_pos 0 -+#define reg_ep0_tx_nak_len 1 -+#define reg_ep0_tx_nak_lsb 0 -+#define p_reg_ep0_rx_nak 0xDD13 -+#define reg_ep0_rx_nak_pos 1 -+#define reg_ep0_rx_nak_len 1 -+#define reg_ep0_rx_nak_lsb 0 -+#define p_reg_ep1_tx_nak 0xDD13 -+#define reg_ep1_tx_nak_pos 2 -+#define reg_ep1_tx_nak_len 1 -+#define reg_ep1_tx_nak_lsb 0 -+#define p_reg_ep2_rx_nak 0xDD13 -+#define reg_ep2_rx_nak_pos 3 -+#define reg_ep2_rx_nak_len 1 -+#define reg_ep2_rx_nak_lsb 0 -+#define p_reg_ep3_tx_nak 0xDD13 -+#define reg_ep3_tx_nak_pos 4 -+#define reg_ep3_tx_nak_len 1 -+#define reg_ep3_tx_nak_lsb 0 -+#define p_reg_ep4_tx_nak 0xDD13 -+#define reg_ep4_tx_nak_pos 5 -+#define reg_ep4_tx_nak_len 1 -+#define reg_ep4_tx_nak_lsb 0 -+#define p_reg_ep5_tx_nak 0xDD13 -+#define reg_ep5_tx_nak_pos 6 -+#define reg_ep5_tx_nak_len 1 -+#define reg_ep5_tx_nak_lsb 0 -+#define p_reg_ep6_tx_nak 0xDD13 -+#define reg_ep6_tx_nak_pos 7 -+#define reg_ep6_tx_nak_len 1 -+#define reg_ep6_tx_nak_lsb 0 -+#define p_reg_ep0_tx_nak_int_en 0xDD14 -+#define reg_ep0_tx_nak_int_en_pos 0 -+#define reg_ep0_tx_nak_int_en_len 1 -+#define reg_ep0_tx_nak_int_en_lsb 0 -+#define p_reg_ep0_rx_nak_int_en 0xDD14 -+#define reg_ep0_rx_nak_int_en_pos 1 -+#define reg_ep0_rx_nak_int_en_len 1 -+#define reg_ep0_rx_nak_int_en_lsb 0 -+#define p_reg_ep1_tx_nak_int_en 0xDD14 -+#define reg_ep1_tx_nak_int_en_pos 2 -+#define reg_ep1_tx_nak_int_en_len 1 -+#define reg_ep1_tx_nak_int_en_lsb 0 -+#define p_reg_ep2_rx_nak_int_en 0xDD14 -+#define reg_ep2_rx_nak_int_en_pos 3 -+#define reg_ep2_rx_nak_int_en_len 1 -+#define reg_ep2_rx_nak_int_en_lsb 0 -+#define p_reg_ep3_tx_nak_int_en 0xDD14 -+#define reg_ep3_tx_nak_int_en_pos 4 -+#define reg_ep3_tx_nak_int_en_len 1 -+#define reg_ep3_tx_nak_int_en_lsb 0 -+#define p_reg_ep4_tx_nak_int_en 0xDD14 -+#define reg_ep4_tx_nak_int_en_pos 5 -+#define reg_ep4_tx_nak_int_en_len 1 -+#define reg_ep4_tx_nak_int_en_lsb 0 -+#define p_reg_ep5_tx_nak_int_en 0xDD14 -+#define reg_ep5_tx_nak_int_en_pos 6 -+#define reg_ep5_tx_nak_int_en_len 1 -+#define reg_ep5_tx_nak_int_en_lsb 0 -+#define p_reg_ep6_tx_nak_int_en 0xDD14 -+#define reg_ep6_tx_nak_int_en_pos 7 -+#define reg_ep6_tx_nak_int_en_len 1 -+#define reg_ep6_tx_nak_int_en_lsb 0 -+#define p_reg_ep0_tx_done_int_en 0xDD15 -+#define reg_ep0_tx_done_int_en_pos 0 -+#define reg_ep0_tx_done_int_en_len 1 -+#define reg_ep0_tx_done_int_en_lsb 0 -+#define p_reg_ep0_rx_done_int_en 0xDD15 -+#define reg_ep0_rx_done_int_en_pos 1 -+#define reg_ep0_rx_done_int_en_len 1 -+#define reg_ep0_rx_done_int_en_lsb 0 -+#define p_reg_ep1_tx_done_int_en 0xDD15 -+#define reg_ep1_tx_done_int_en_pos 2 -+#define reg_ep1_tx_done_int_en_len 1 -+#define reg_ep1_tx_done_int_en_lsb 0 -+#define p_reg_ep2_rx_done_int_en 0xDD15 -+#define reg_ep2_rx_done_int_en_pos 3 -+#define reg_ep2_rx_done_int_en_len 1 -+#define reg_ep2_rx_done_int_en_lsb 0 -+#define p_reg_ep3_tx_done_int_en 0xDD15 -+#define reg_ep3_tx_done_int_en_pos 4 -+#define reg_ep3_tx_done_int_en_len 1 -+#define reg_ep3_tx_done_int_en_lsb 0 -+#define p_reg_ep4_tx_done_int_en 0xDD15 -+#define reg_ep4_tx_done_int_en_pos 5 -+#define reg_ep4_tx_done_int_en_len 1 -+#define reg_ep4_tx_done_int_en_lsb 0 -+#define p_reg_ep5_tx_done_int_en 0xDD15 -+#define reg_ep5_tx_done_int_en_pos 6 -+#define reg_ep5_tx_done_int_en_len 1 -+#define reg_ep5_tx_done_int_en_lsb 0 -+#define p_reg_ep6_tx_done_int_en 0xDD15 -+#define reg_ep6_tx_done_int_en_pos 7 -+#define reg_ep6_tx_done_int_en_len 1 -+#define reg_ep6_tx_done_int_en_lsb 0 -+#define p_reg_ep0_tx_fail_int_en 0xDD16 -+#define reg_ep0_tx_fail_int_en_pos 0 -+#define reg_ep0_tx_fail_int_en_len 1 -+#define reg_ep0_tx_fail_int_en_lsb 0 -+#define p_reg_ep0_rx_fail_int_en 0xDD16 -+#define reg_ep0_rx_fail_int_en_pos 1 -+#define reg_ep0_rx_fail_int_en_len 1 -+#define reg_ep0_rx_fail_int_en_lsb 0 -+#define p_reg_ep1_tx_fail_int_en 0xDD16 -+#define reg_ep1_tx_fail_int_en_pos 2 -+#define reg_ep1_tx_fail_int_en_len 1 -+#define reg_ep1_tx_fail_int_en_lsb 0 -+#define p_reg_ep2_rx_fail_int_en 0xDD16 -+#define reg_ep2_rx_fail_int_en_pos 3 -+#define reg_ep2_rx_fail_int_en_len 1 -+#define reg_ep2_rx_fail_int_en_lsb 0 -+#define p_reg_ep3_tx_fail_int_en 0xDD16 -+#define reg_ep3_tx_fail_int_en_pos 4 -+#define reg_ep3_tx_fail_int_en_len 1 -+#define reg_ep3_tx_fail_int_en_lsb 0 -+#define p_reg_ep4_tx_fail_int_en 0xDD16 -+#define reg_ep4_tx_fail_int_en_pos 5 -+#define reg_ep4_tx_fail_int_en_len 1 -+#define reg_ep4_tx_fail_int_en_lsb 0 -+#define p_reg_ep5_tx_fail_int_en 0xDD16 -+#define reg_ep5_tx_fail_int_en_pos 6 -+#define reg_ep5_tx_fail_int_en_len 1 -+#define reg_ep5_tx_fail_int_en_lsb 0 -+#define p_reg_ep6_tx_fail_int_en 0xDD16 -+#define reg_ep6_tx_fail_int_en_pos 7 -+#define reg_ep6_tx_fail_int_en_len 1 -+#define reg_ep6_tx_fail_int_en_lsb 0 -+#define p_reg_suspend_int_en 0xDD17 -+#define reg_suspend_int_en_pos 0 -+#define reg_suspend_int_en_len 1 -+#define reg_suspend_int_en_lsb 0 -+#define p_reg_bus_reset_int_en 0xDD17 -+#define reg_bus_reset_int_en_pos 1 -+#define reg_bus_reset_int_en_len 1 -+#define reg_bus_reset_int_en_lsb 0 -+#define p_reg_ep0_setup_int_en 0xDD17 -+#define reg_ep0_setup_int_en_pos 2 -+#define reg_ep0_setup_int_en_len 1 -+#define reg_ep0_setup_int_en_lsb 0 -+#define p_reg_ep0_tx_nak_int 0xDD18 -+#define reg_ep0_tx_nak_int_pos 0 -+#define reg_ep0_tx_nak_int_len 1 -+#define reg_ep0_tx_nak_int_lsb 0 -+#define p_reg_ep0_rx_nak_int 0xDD18 -+#define reg_ep0_rx_nak_int_pos 1 -+#define reg_ep0_rx_nak_int_len 1 -+#define reg_ep0_rx_nak_int_lsb 0 -+#define p_reg_ep1_tx_nak_int 0xDD18 -+#define reg_ep1_tx_nak_int_pos 2 -+#define reg_ep1_tx_nak_int_len 1 -+#define reg_ep1_tx_nak_int_lsb 0 -+#define p_reg_ep2_rx_nak_int 0xDD18 -+#define reg_ep2_rx_nak_int_pos 3 -+#define reg_ep2_rx_nak_int_len 1 -+#define reg_ep2_rx_nak_int_lsb 0 -+#define p_reg_ep3_tx_nak_int 0xDD18 -+#define reg_ep3_tx_nak_int_pos 4 -+#define reg_ep3_tx_nak_int_len 1 -+#define reg_ep3_tx_nak_int_lsb 0 -+#define p_reg_ep4_tx_nak_int 0xDD18 -+#define reg_ep4_tx_nak_int_pos 5 -+#define reg_ep4_tx_nak_int_len 1 -+#define reg_ep4_tx_nak_int_lsb 0 -+#define p_reg_ep5_tx_nak_int 0xDD18 -+#define reg_ep5_tx_nak_int_pos 6 -+#define reg_ep5_tx_nak_int_len 1 -+#define reg_ep5_tx_nak_int_lsb 0 -+#define p_reg_ep6_tx_nak_int 0xDD18 -+#define reg_ep6_tx_nak_int_pos 7 -+#define reg_ep6_tx_nak_int_len 1 -+#define reg_ep6_tx_nak_int_lsb 0 -+#define p_reg_ep0_tx_done_int 0xDD19 -+#define reg_ep0_tx_done_int_pos 0 -+#define reg_ep0_tx_done_int_len 1 -+#define reg_ep0_tx_done_int_lsb 0 -+#define p_reg_ep0_rx_done_int 0xDD19 -+#define reg_ep0_rx_done_int_pos 1 -+#define reg_ep0_rx_done_int_len 1 -+#define reg_ep0_rx_done_int_lsb 0 -+#define p_reg_ep1_tx_done_int 0xDD19 -+#define reg_ep1_tx_done_int_pos 2 -+#define reg_ep1_tx_done_int_len 1 -+#define reg_ep1_tx_done_int_lsb 0 -+#define p_reg_ep2_rx_done_int 0xDD19 -+#define reg_ep2_rx_done_int_pos 3 -+#define reg_ep2_rx_done_int_len 1 -+#define reg_ep2_rx_done_int_lsb 0 -+#define p_reg_ep3_tx_done_int 0xDD19 -+#define reg_ep3_tx_done_int_pos 4 -+#define reg_ep3_tx_done_int_len 1 -+#define reg_ep3_tx_done_int_lsb 0 -+#define p_reg_ep4_tx_done_int 0xDD19 -+#define reg_ep4_tx_done_int_pos 5 -+#define reg_ep4_tx_done_int_len 1 -+#define reg_ep4_tx_done_int_lsb 0 -+#define p_reg_ep5_tx_done_int 0xDD19 -+#define reg_ep5_tx_done_int_pos 6 -+#define reg_ep5_tx_done_int_len 1 -+#define reg_ep5_tx_done_int_lsb 0 -+#define p_reg_ep6_tx_done_int 0xDD19 -+#define reg_ep6_tx_done_int_pos 7 -+#define reg_ep6_tx_done_int_len 1 -+#define reg_ep6_tx_done_int_lsb 0 -+#define p_reg_ep0_tx_fail_int 0xDD1A -+#define reg_ep0_tx_fail_int_pos 0 -+#define reg_ep0_tx_fail_int_len 1 -+#define reg_ep0_tx_fail_int_lsb 0 -+#define p_reg_ep0_rx_fail_int 0xDD1A -+#define reg_ep0_rx_fail_int_pos 1 -+#define reg_ep0_rx_fail_int_len 1 -+#define reg_ep0_rx_fail_int_lsb 0 -+#define p_reg_ep1_tx_fail_int 0xDD1A -+#define reg_ep1_tx_fail_int_pos 2 -+#define reg_ep1_tx_fail_int_len 1 -+#define reg_ep1_tx_fail_int_lsb 0 -+#define p_reg_ep2_rx_fail_int 0xDD1A -+#define reg_ep2_rx_fail_int_pos 3 -+#define reg_ep2_rx_fail_int_len 1 -+#define reg_ep2_rx_fail_int_lsb 0 -+#define p_reg_ep3_tx_fail_int 0xDD1A -+#define reg_ep3_tx_fail_int_pos 4 -+#define reg_ep3_tx_fail_int_len 1 -+#define reg_ep3_tx_fail_int_lsb 0 -+#define p_reg_ep4_tx_fail_int 0xDD1A -+#define reg_ep4_tx_fail_int_pos 5 -+#define reg_ep4_tx_fail_int_len 1 -+#define reg_ep4_tx_fail_int_lsb 0 -+#define p_reg_ep5_tx_fail_int 0xDD1A -+#define reg_ep5_tx_fail_int_pos 6 -+#define reg_ep5_tx_fail_int_len 1 -+#define reg_ep5_tx_fail_int_lsb 0 -+#define p_reg_ep6_tx_fail_int 0xDD1A -+#define reg_ep6_tx_fail_int_pos 7 -+#define reg_ep6_tx_fail_int_len 1 -+#define reg_ep6_tx_fail_int_lsb 0 -+#define p_reg_suspend_int 0xDD1B -+#define reg_suspend_int_pos 0 -+#define reg_suspend_int_len 1 -+#define reg_suspend_int_lsb 0 -+#define p_reg_bus_reset_int 0xDD1B -+#define reg_bus_reset_int_pos 1 -+#define reg_bus_reset_int_len 1 -+#define reg_bus_reset_int_lsb 0 -+#define p_reg_ep0_setup_int 0xDD1B -+#define reg_ep0_setup_int_pos 2 -+#define reg_ep0_setup_int_len 1 -+#define reg_ep0_setup_int_lsb 0 -+#define r_usbc_int 0xDD1B -+#define usbc_int_pos 3 -+#define usbc_int_len 1 -+#define usbc_int_lsb 0 -+#define r_usb_ir_int 0xDD1B -+#define usb_ir_int_pos 4 -+#define usb_ir_int_len 1 -+#define usb_ir_int_lsb 0 -+#define p_reg_ep0_tx_rst 0xDD1D -+#define reg_ep0_tx_rst_pos 0 -+#define reg_ep0_tx_rst_len 1 -+#define reg_ep0_tx_rst_lsb 0 -+#define p_reg_ep0_rx_rst 0xDD1D -+#define reg_ep0_rx_rst_pos 1 -+#define reg_ep0_rx_rst_len 1 -+#define reg_ep0_rx_rst_lsb 0 -+#define p_reg_ep1_tx_rst 0xDD1D -+#define reg_ep1_tx_rst_pos 2 -+#define reg_ep1_tx_rst_len 1 -+#define reg_ep1_tx_rst_lsb 0 -+#define p_reg_ep2_rx_rst 0xDD1D -+#define reg_ep2_rx_rst_pos 3 -+#define reg_ep2_rx_rst_len 1 -+#define reg_ep2_rx_rst_lsb 0 -+#define p_reg_ep3_tx_rst 0xDD1D -+#define reg_ep3_tx_rst_pos 4 -+#define reg_ep3_tx_rst_len 1 -+#define reg_ep3_tx_rst_lsb 0 -+#define p_reg_ep4_tx_rst 0xDD1D -+#define reg_ep4_tx_rst_pos 5 -+#define reg_ep4_tx_rst_len 1 -+#define reg_ep4_tx_rst_lsb 0 -+#define p_reg_ep5_tx_rst 0xDD1D -+#define reg_ep5_tx_rst_pos 6 -+#define reg_ep5_tx_rst_len 1 -+#define reg_ep5_tx_rst_lsb 0 -+#define p_reg_ep6_tx_rst 0xDD1D -+#define reg_ep6_tx_rst_pos 7 -+#define reg_ep6_tx_rst_len 1 -+#define reg_ep6_tx_rst_lsb 0 -+#define r_reg_ep0_tx_active 0xDD1E -+#define reg_ep0_tx_active_pos 0 -+#define reg_ep0_tx_active_len 1 -+#define reg_ep0_tx_active_lsb 0 -+#define r_reg_ep0_rx_active 0xDD1E -+#define reg_ep0_rx_active_pos 1 -+#define reg_ep0_rx_active_len 1 -+#define reg_ep0_rx_active_lsb 0 -+#define r_reg_ep1_tx_active 0xDD1E -+#define reg_ep1_tx_active_pos 2 -+#define reg_ep1_tx_active_len 1 -+#define reg_ep1_tx_active_lsb 0 -+#define r_reg_ep2_rx_active 0xDD1E -+#define reg_ep2_rx_active_pos 3 -+#define reg_ep2_rx_active_len 1 -+#define reg_ep2_rx_active_lsb 0 -+#define r_reg_ep3_tx_active 0xDD1E -+#define reg_ep3_tx_active_pos 4 -+#define reg_ep3_tx_active_len 1 -+#define reg_ep3_tx_active_lsb 0 -+#define r_reg_ep4_tx_active 0xDD1E -+#define reg_ep4_tx_active_pos 5 -+#define reg_ep4_tx_active_len 1 -+#define reg_ep4_tx_active_lsb 0 -+#define r_reg_ep5_tx_active 0xDD1E -+#define reg_ep5_tx_active_pos 6 -+#define reg_ep5_tx_active_len 1 -+#define reg_ep5_tx_active_lsb 0 -+#define r_reg_ep6_tx_active 0xDD1E -+#define reg_ep6_tx_active_pos 7 -+#define reg_ep6_tx_active_len 1 -+#define reg_ep6_tx_active_lsb 0 -+#define p_reg_usb_setup_reset 0xDD1F -+#define reg_usb_setup_reset_pos 0 -+#define reg_usb_setup_reset_len 1 -+#define reg_usb_setup_reset_lsb 0 -+#define p_reg_usb_ep4_retry_new 0xDD1F -+#define reg_usb_ep4_retry_new_pos 1 -+#define reg_usb_ep4_retry_new_len 1 -+#define reg_usb_ep4_retry_new_lsb 0 -+#define p_reg_usb_ep5_retry_new 0xDD1F -+#define reg_usb_ep5_retry_new_pos 2 -+#define reg_usb_ep5_retry_new_len 1 -+#define reg_usb_ep5_retry_new_lsb 0 -+#define p_reg_usb_ep6_retry_new 0xDD1F -+#define reg_usb_ep6_retry_new_pos 3 -+#define reg_usb_ep6_retry_new_len 1 -+#define reg_usb_ep6_retry_new_lsb 0 -+#define p_reg_usb_iso_mult_cnt 0xDD20 -+#define reg_usb_iso_mult_cnt_pos 0 -+#define reg_usb_iso_mult_cnt_len 2 -+#define reg_usb_iso_mult_cnt_lsb 0 -+#define p_reg_p_iso_fix_en 0xDD21 -+#define reg_p_iso_fix_en_pos 0 -+#define reg_p_iso_fix_en_len 1 -+#define reg_p_iso_fix_en_lsb 0 -+#define p_reg_p_iso_fix_rst 0xDD22 -+#define reg_p_iso_fix_rst_pos 0 -+#define reg_p_iso_fix_rst_len 1 -+#define reg_p_iso_fix_rst_lsb 0 -+#define p_reg_p_read_point_7_0 0xDD23 -+#define reg_p_read_point_7_0_pos 0 -+#define reg_p_read_point_7_0_len 8 -+#define reg_p_read_point_7_0_lsb 0 -+#define p_reg_p_read_point_11_8 0xDD24 -+#define reg_p_read_point_11_8_pos 0 -+#define reg_p_read_point_11_8_len 4 -+#define reg_p_read_point_11_8_lsb 8 -+#define p_reg_p_dbg_ctrl 0xDD25 -+#define reg_p_dbg_ctrl_pos 0 -+#define reg_p_dbg_ctrl_len 3 -+#define reg_p_dbg_ctrl_lsb 0 -+#define p_reg_p_data_swap 0xDD26 -+#define reg_p_data_swap_pos 0 -+#define reg_p_data_swap_len 2 -+#define reg_p_data_swap_lsb 0 -+#define p_reg_ep_rx_addr 0xDD80 -+#define reg_ep_rx_addr_pos 2 -+#define reg_ep_rx_addr_len 6 -+#define reg_ep_rx_addr_lsb 0 -+#define p_reg_ep0_tx_addr 0xDD81 -+#define reg_ep0_tx_addr_pos 2 -+#define reg_ep0_tx_addr_len 6 -+#define reg_ep0_tx_addr_lsb 0 -+#define p_reg_ep1_tx_addr 0xDD82 -+#define reg_ep1_tx_addr_pos 2 -+#define reg_ep1_tx_addr_len 6 -+#define reg_ep1_tx_addr_lsb 0 -+#define p_reg_ep3_tx_addr 0xDD83 -+#define reg_ep3_tx_addr_pos 2 -+#define reg_ep3_tx_addr_len 6 -+#define reg_ep3_tx_addr_lsb 0 -+#define p_reg_ep_rx_len 0xDD84 -+#define reg_ep_rx_len_pos 0 -+#define reg_ep_rx_len_len 8 -+#define reg_ep_rx_len_lsb 0 -+#define p_reg_ep0_tx_len 0xDD85 -+#define reg_ep0_tx_len_pos 0 -+#define reg_ep0_tx_len_len 8 -+#define reg_ep0_tx_len_lsb 0 -+#define p_reg_ep1_tx_len 0xDD86 -+#define reg_ep1_tx_len_pos 0 -+#define reg_ep1_tx_len_len 8 -+#define reg_ep1_tx_len_lsb 0 -+#define p_reg_ep3_tx_len 0xDD87 -+#define reg_ep3_tx_len_pos 0 -+#define reg_ep3_tx_len_len 8 -+#define reg_ep3_tx_len_lsb 0 -+#define p_reg_ep4_tx_len_7_0 0xDD88 -+#define reg_ep4_tx_len_7_0_pos 0 -+#define reg_ep4_tx_len_7_0_len 8 -+#define reg_ep4_tx_len_7_0_lsb 0 -+#define p_reg_ep4_tx_len_15_8 0xDD89 -+#define reg_ep4_tx_len_15_8_pos 0 -+#define reg_ep4_tx_len_15_8_len 8 -+#define reg_ep4_tx_len_15_8_lsb 8 -+#define p_reg_ep5_tx_len_7_0 0xDD8A -+#define reg_ep5_tx_len_7_0_pos 0 -+#define reg_ep5_tx_len_7_0_len 8 -+#define reg_ep5_tx_len_7_0_lsb 0 -+#define p_reg_ep5_tx_len_15_8 0xDD8B -+#define reg_ep5_tx_len_15_8_pos 0 -+#define reg_ep5_tx_len_15_8_len 8 -+#define reg_ep5_tx_len_15_8_lsb 8 -+#define p_reg_usb_reset_addr 0xDD8C -+#define reg_usb_reset_addr_pos 0 -+#define reg_usb_reset_addr_len 7 -+#define reg_usb_reset_addr_lsb 0 -+#define p_reg_usb_reset 0xDD8C -+#define reg_usb_reset_pos 7 -+#define reg_usb_reset_len 1 -+#define reg_usb_reset_lsb 0 -+#define p_reg_usb_sync_in 0xDD8D -+#define reg_usb_sync_in_pos 0 -+#define reg_usb_sync_in_len 1 -+#define reg_usb_sync_in_lsb 0 -+#define p_reg_usb_sync_txready 0xDD8D -+#define reg_usb_sync_txready_pos 1 -+#define reg_usb_sync_txready_len 1 -+#define reg_usb_sync_txready_lsb 0 -+#define p_reg_utmi_phy_suspend 0xDD8D -+#define reg_utmi_phy_suspend_pos 2 -+#define reg_utmi_phy_suspend_len 1 -+#define reg_utmi_phy_suspend_lsb 0 -+#define p_reg_usb_min_len 0xDD8D -+#define reg_usb_min_len_pos 3 -+#define reg_usb_min_len_len 1 -+#define reg_usb_min_len_lsb 0 -+#define p_reg_usb_phy_clksel 0xDD8D -+#define reg_usb_phy_clksel_pos 4 -+#define reg_usb_phy_clksel_len 1 -+#define reg_usb_phy_clksel_lsb 0 -+#define p_reg_ep6_tx_len_7_0 0xDD8E -+#define reg_ep6_tx_len_7_0_pos 0 -+#define reg_ep6_tx_len_7_0_len 8 -+#define reg_ep6_tx_len_7_0_lsb 0 -+#define p_reg_ep6_tx_len_15_8 0xDD8F -+#define reg_ep6_tx_len_15_8_pos 0 -+#define reg_ep6_tx_len_15_8_len 8 -+#define reg_ep6_tx_len_15_8_lsb 8 -+#define p_reg_usb_clk_phase 0xDD93 -+#define reg_usb_clk_phase_pos 0 -+#define reg_usb_clk_phase_len 2 -+#define reg_usb_clk_phase_lsb 0 -+#define p_reg_usb_clk_sel 0xDD93 -+#define reg_usb_clk_sel_pos 4 -+#define reg_usb_clk_sel_len 4 -+#define reg_usb_clk_sel_lsb 0 -+#define p_reg_usb_fifo_ptr 0xDD94 -+#define reg_usb_fifo_ptr_pos 0 -+#define reg_usb_fifo_ptr_len 3 -+#define reg_usb_fifo_ptr_lsb 0 -+#define p_reg_usb_fifo_byte 0xDD94 -+#define reg_usb_fifo_byte_pos 3 -+#define reg_usb_fifo_byte_len 2 -+#define reg_usb_fifo_byte_lsb 0 -+#define p_reg_usb_fifo_sys 0xDD94 -+#define reg_usb_fifo_sys_pos 5 -+#define reg_usb_fifo_sys_len 1 -+#define reg_usb_fifo_sys_lsb 0 -+#define p_usbdma_utmi_d_ctl_7_0 0xDD9E -+#define usbdma_utmi_d_ctl_7_0_pos 0 -+#define usbdma_utmi_d_ctl_7_0_len 8 -+#define usbdma_utmi_d_ctl_7_0_lsb 0 -+#define p_usbdma_utmi_d_ctl_13_8 0xDD9F -+#define usbdma_utmi_d_ctl_13_8_pos 0 -+#define usbdma_utmi_d_ctl_13_8_len 6 -+#define usbdma_utmi_d_ctl_13_8_lsb 8 -+#define p_usbdma_utmi_a_ctl_7_0 0xDDA0 -+#define usbdma_utmi_a_ctl_7_0_pos 0 -+#define usbdma_utmi_a_ctl_7_0_len 8 -+#define usbdma_utmi_a_ctl_7_0_lsb 0 -+#define p_usbdma_utmi_a_ctl_15_8 0xDDA1 -+#define usbdma_utmi_a_ctl_15_8_pos 0 -+#define usbdma_utmi_a_ctl_15_8_len 8 -+#define usbdma_utmi_a_ctl_15_8_lsb 8 -+#define p_usbdma_utmi_a_ctl_23_16 0xDDA2 -+#define usbdma_utmi_a_ctl_23_16_pos 0 -+#define usbdma_utmi_a_ctl_23_16_len 8 -+#define usbdma_utmi_a_ctl_23_16_lsb 16 -+#define p_usbdma_utmi_a_ctl_31_24 0xDDA3 -+#define usbdma_utmi_a_ctl_31_24_pos 0 -+#define usbdma_utmi_a_ctl_31_24_len 8 -+#define usbdma_utmi_a_ctl_31_24_lsb 24 -+#define p_usbdma_utmi_a_ctl_39_32 0xDDA4 -+#define usbdma_utmi_a_ctl_39_32_pos 0 -+#define usbdma_utmi_a_ctl_39_32_len 8 -+#define usbdma_utmi_a_ctl_39_32_lsb 32 -+#define p_usbdma_utmi_a_ctl_47_40 0xDDA5 -+#define usbdma_utmi_a_ctl_47_40_pos 0 -+#define usbdma_utmi_a_ctl_47_40_len 8 -+#define usbdma_utmi_a_ctl_47_40_lsb 40 -+#define p_usbdma_utmi_pwrmode 0xDDA6 -+#define usbdma_utmi_pwrmode_pos 3 -+#define usbdma_utmi_pwrmode_len 1 -+#define usbdma_utmi_pwrmode_lsb 0 -+#define p_usbdma_utmi_test_out 0xDDA6 -+#define usbdma_utmi_test_out_pos 4 -+#define usbdma_utmi_test_out_len 1 -+#define usbdma_utmi_test_out_lsb 0 -+#define p_usbdma_utmi_vbus_int_en 0xDDA7 -+#define usbdma_utmi_vbus_int_en_pos 0 -+#define usbdma_utmi_vbus_int_en_len 1 -+#define usbdma_utmi_vbus_int_en_lsb 0 -+#define p_usbdma_utmi_vbus_int_pol 0xDDA7 -+#define usbdma_utmi_vbus_int_pol_pos 1 -+#define usbdma_utmi_vbus_int_pol_len 1 -+#define usbdma_utmi_vbus_int_pol_lsb 0 -+#define r_usbdma_utmi_vbus_int 0xDDA8 -+#define usbdma_utmi_vbus_int_pos 0 -+#define usbdma_utmi_vbus_int_len 1 -+#define usbdma_utmi_vbus_int_lsb 0 -+#define r_usbdma_utmi_vbus_status 0xDDA8 -+#define usbdma_utmi_vbus_status_pos 1 -+#define usbdma_utmi_vbus_status_len 1 -+#define usbdma_utmi_vbus_status_lsb 0 -+#define r_usbdma_utmi_clkrdy 0xDDA8 -+#define usbdma_utmi_clkrdy_pos 2 -+#define usbdma_utmi_clkrdy_len 1 -+#define usbdma_utmi_clkrdy_lsb 0 -+#define p_reg_p_usb_iso_ccir_rst 0xDDA9 -+#define reg_p_usb_iso_ccir_rst_pos 0 -+#define reg_p_usb_iso_ccir_rst_len 1 -+#define reg_p_usb_iso_ccir_rst_lsb 0 -+#define p_reg_p_usb_iso_ccir 0xDDA9 -+#define reg_p_usb_iso_ccir_pos 1 -+#define reg_p_usb_iso_ccir_len 1 -+#define reg_p_usb_iso_ccir_lsb 0 -+#define p_reg_p_ccir_fix_en 0xDDAA -+#define reg_p_ccir_fix_en_pos 0 -+#define reg_p_ccir_fix_en_len 1 -+#define reg_p_ccir_fix_en_lsb 0 -+#define p_ir_sys_clk 0xDF80 -+#define ir_sys_clk_pos 0 -+#define ir_sys_clk_len 8 -+#define ir_sys_clk_lsb 0 -+#define p_ir_sample_clk 0xDF81 -+#define ir_sample_clk_pos 0 -+#define ir_sample_clk_len 2 -+#define ir_sample_clk_lsb 0 -+#define p_ir_idle_polarity 0xDF81 -+#define ir_idle_polarity_pos 2 -+#define ir_idle_polarity_len 1 -+#define ir_idle_polarity_lsb 0 -+#define p_ir_fifo_ovfl 0xDF82 -+#define ir_fifo_ovfl_pos 0 -+#define ir_fifo_ovfl_len 1 -+#define ir_fifo_ovfl_lsb 0 -+#define r_ir_fifo_empty 0xDF82 -+#define ir_fifo_empty_pos 1 -+#define ir_fifo_empty_len 1 -+#define ir_fifo_empty_lsb 0 -+#define r_ir_fifo_cnt 0xDF82 -+#define ir_fifo_cnt_pos 2 -+#define ir_fifo_cnt_len 3 -+#define ir_fifo_cnt_lsb 0 -+#define p_ir_fifo_rst 0xDF82 -+#define ir_fifo_rst_pos 5 -+#define ir_fifo_rst_len 1 -+#define ir_fifo_rst_lsb 0 -+#define p_reg_ir_out_th0_7_0 0xDF84 -+#define reg_ir_out_th0_7_0_pos 0 -+#define reg_ir_out_th0_7_0_len 8 -+#define reg_ir_out_th0_7_0_lsb 0 -+#define p_reg_ir_out_th0_14_8 0xDF85 -+#define reg_ir_out_th0_14_8_pos 0 -+#define reg_ir_out_th0_14_8_len 7 -+#define reg_ir_out_th0_14_8_lsb 8 -+#define p_reg_ir_out_th1_7_0 0xDF86 -+#define reg_ir_out_th1_7_0_pos 0 -+#define reg_ir_out_th1_7_0_len 8 -+#define reg_ir_out_th1_7_0_lsb 0 -+#define p_reg_ir_out_th1_14_8 0xDF87 -+#define reg_ir_out_th1_14_8_pos 0 -+#define reg_ir_out_th1_14_8_len 7 -+#define reg_ir_out_th1_14_8_lsb 8 -+#define p_reg_ir_out_th2_7_0 0xDF88 -+#define reg_ir_out_th2_7_0_pos 0 -+#define reg_ir_out_th2_7_0_len 8 -+#define reg_ir_out_th2_7_0_lsb 0 -+#define p_reg_ir_out_th2_14_8 0xDF89 -+#define reg_ir_out_th2_14_8_pos 0 -+#define reg_ir_out_th2_14_8_len 7 -+#define reg_ir_out_th2_14_8_lsb 8 -+#define p_reg_ir_out_th3_7_0 0xDF8A -+#define reg_ir_out_th3_7_0_pos 0 -+#define reg_ir_out_th3_7_0_len 8 -+#define reg_ir_out_th3_7_0_lsb 0 -+#define p_reg_ir_out_th3_14_8 0xDF8B -+#define reg_ir_out_th3_14_8_pos 0 -+#define reg_ir_out_th3_14_8_len 7 -+#define reg_ir_out_th3_14_8_lsb 8 -+#define p_reg_ir_out_th4_7_0 0xDF8C -+#define reg_ir_out_th4_7_0_pos 0 -+#define reg_ir_out_th4_7_0_len 8 -+#define reg_ir_out_th4_7_0_lsb 0 -+#define p_reg_ir_out_th4_14_8 0xDF8D -+#define reg_ir_out_th4_14_8_pos 0 -+#define reg_ir_out_th4_14_8_len 7 -+#define reg_ir_out_th4_14_8_lsb 8 -+#define p_reg_ir_out_th5_7_0 0xDF8E -+#define reg_ir_out_th5_7_0_pos 0 -+#define reg_ir_out_th5_7_0_len 8 -+#define reg_ir_out_th5_7_0_lsb 0 -+#define p_reg_ir_out_th5_14_8 0xDF8F -+#define reg_ir_out_th5_14_8_pos 0 -+#define reg_ir_out_th5_14_8_len 7 -+#define reg_ir_out_th5_14_8_lsb 8 -+#define p_reg_ir_out_th6_7_0 0xDF90 -+#define reg_ir_out_th6_7_0_pos 0 -+#define reg_ir_out_th6_7_0_len 8 -+#define reg_ir_out_th6_7_0_lsb 0 -+#define p_reg_ir_out_th6_14_8 0xDF91 -+#define reg_ir_out_th6_14_8_pos 0 -+#define reg_ir_out_th6_14_8_len 7 -+#define reg_ir_out_th6_14_8_lsb 8 -+#define p_reg_ir_out_th7_7_0 0xDF92 -+#define reg_ir_out_th7_7_0_pos 0 -+#define reg_ir_out_th7_7_0_len 8 -+#define reg_ir_out_th7_7_0_lsb 0 -+#define p_reg_ir_out_th7_14_8 0xDF93 -+#define reg_ir_out_th7_14_8_pos 0 -+#define reg_ir_out_th7_14_8_len 7 -+#define reg_ir_out_th7_14_8_lsb 8 -+#define p_reg_ir_out_th8_7_0 0xDF94 -+#define reg_ir_out_th8_7_0_pos 0 -+#define reg_ir_out_th8_7_0_len 8 -+#define reg_ir_out_th8_7_0_lsb 0 -+#define p_reg_ir_out_th8_14_8 0xDF95 -+#define reg_ir_out_th8_14_8_pos 0 -+#define reg_ir_out_th8_14_8_len 7 -+#define reg_ir_out_th8_14_8_lsb 8 -+#define p_reg_ir_out_th9_7_0 0xDF96 -+#define reg_ir_out_th9_7_0_pos 0 -+#define reg_ir_out_th9_7_0_len 8 -+#define reg_ir_out_th9_7_0_lsb 0 -+#define p_reg_ir_out_th9_14_8 0xDF97 -+#define reg_ir_out_th9_14_8_pos 0 -+#define reg_ir_out_th9_14_8_len 7 -+#define reg_ir_out_th9_14_8_lsb 8 -+#define p_reg_ir_out_th10_7_0 0xDF98 -+#define reg_ir_out_th10_7_0_pos 0 -+#define reg_ir_out_th10_7_0_len 8 -+#define reg_ir_out_th10_7_0_lsb 0 -+#define p_reg_ir_out_th10_14_8 0xDF99 -+#define reg_ir_out_th10_14_8_pos 0 -+#define reg_ir_out_th10_14_8_len 7 -+#define reg_ir_out_th10_14_8_lsb 8 -+#define p_reg_ir_out_th11_7_0 0xDF9A -+#define reg_ir_out_th11_7_0_pos 0 -+#define reg_ir_out_th11_7_0_len 8 -+#define reg_ir_out_th11_7_0_lsb 0 -+#define p_reg_ir_out_th11_14_8 0xDF9B -+#define reg_ir_out_th11_14_8_pos 0 -+#define reg_ir_out_th11_14_8_len 7 -+#define reg_ir_out_th11_14_8_lsb 8 -+#define p_reg_ir_out_th12_7_0 0xDF9C -+#define reg_ir_out_th12_7_0_pos 0 -+#define reg_ir_out_th12_7_0_len 8 -+#define reg_ir_out_th12_7_0_lsb 0 -+#define p_reg_ir_out_th12_14_8 0xDF9D -+#define reg_ir_out_th12_14_8_pos 0 -+#define reg_ir_out_th12_14_8_len 7 -+#define reg_ir_out_th12_14_8_lsb 8 -+#define p_reg_ir_out_th13_7_0 0xDF9E -+#define reg_ir_out_th13_7_0_pos 0 -+#define reg_ir_out_th13_7_0_len 8 -+#define reg_ir_out_th13_7_0_lsb 0 -+#define p_reg_ir_out_th13_14_8 0xDF9F -+#define reg_ir_out_th13_14_8_pos 0 -+#define reg_ir_out_th13_14_8_len 7 -+#define reg_ir_out_th13_14_8_lsb 8 -+#define p_reg_ir_out_th14_7_0 0xDFA0 -+#define reg_ir_out_th14_7_0_pos 0 -+#define reg_ir_out_th14_7_0_len 8 -+#define reg_ir_out_th14_7_0_lsb 0 -+#define p_reg_ir_out_th14_14_8 0xDFA1 -+#define reg_ir_out_th14_14_8_pos 0 -+#define reg_ir_out_th14_14_8_len 7 -+#define reg_ir_out_th14_14_8_lsb 8 -+#define p_reg_tuner_data_7_0 0xF000 -+#define reg_tuner_data_7_0_pos 0 -+#define reg_tuner_data_7_0_len 8 -+#define reg_tuner_data_7_0_lsb 0 -+#define p_reg_tuner_data_15_8 0xF001 -+#define reg_tuner_data_15_8_pos 0 -+#define reg_tuner_data_15_8_len 8 -+#define reg_tuner_data_15_8_lsb 8 -+#define p_reg_tuner_data_23_16 0xF002 -+#define reg_tuner_data_23_16_pos 0 -+#define reg_tuner_data_23_16_len 8 -+#define reg_tuner_data_23_16_lsb 16 -+#define p_reg_tuner_data_31_24 0xF003 -+#define reg_tuner_data_31_24_pos 0 -+#define reg_tuner_data_31_24_len 8 -+#define reg_tuner_data_31_24_lsb 24 -+#define p_reg_tuner_data_39_32 0xF004 -+#define reg_tuner_data_39_32_pos 0 -+#define reg_tuner_data_39_32_len 8 -+#define reg_tuner_data_39_32_lsb 32 -+#define p_reg_tuner_data_47_40 0xF005 -+#define reg_tuner_data_47_40_pos 0 -+#define reg_tuner_data_47_40_len 8 -+#define reg_tuner_data_47_40_lsb 40 -+#define p_reg_tuner_data_55_48 0xF006 -+#define reg_tuner_data_55_48_pos 0 -+#define reg_tuner_data_55_48_len 8 -+#define reg_tuner_data_55_48_lsb 48 -+#define p_reg_tuner_data_63_56 0xF007 -+#define reg_tuner_data_63_56_pos 0 -+#define reg_tuner_data_63_56_len 8 -+#define reg_tuner_data_63_56_lsb 56 -+#define p_reg_tuner_data_71_64 0xF008 -+#define reg_tuner_data_71_64_pos 0 -+#define reg_tuner_data_71_64_len 8 -+#define reg_tuner_data_71_64_lsb 64 -+#define p_reg_tuner_data_79_72 0xF009 -+#define reg_tuner_data_79_72_pos 0 -+#define reg_tuner_data_79_72_len 8 -+#define reg_tuner_data_79_72_lsb 72 -+#define p_reg_tuner_data_87_80 0xF00A -+#define reg_tuner_data_87_80_pos 0 -+#define reg_tuner_data_87_80_len 8 -+#define reg_tuner_data_87_80_lsb 80 -+#define p_reg_tuner_data_95_88 0xF00B -+#define reg_tuner_data_95_88_pos 0 -+#define reg_tuner_data_95_88_len 8 -+#define reg_tuner_data_95_88_lsb 88 -+#define p_reg_tuner_data_103_96 0xF00C -+#define reg_tuner_data_103_96_pos 0 -+#define reg_tuner_data_103_96_len 8 -+#define reg_tuner_data_103_96_lsb 96 -+#define p_reg_tuner_data_111_104 0xF00D -+#define reg_tuner_data_111_104_pos 0 -+#define reg_tuner_data_111_104_len 8 -+#define reg_tuner_data_111_104_lsb 104 -+#define p_reg_tuner_data_119_112 0xF00E -+#define reg_tuner_data_119_112_pos 0 -+#define reg_tuner_data_119_112_len 8 -+#define reg_tuner_data_119_112_lsb 112 -+#define p_reg_tuner_data_127_120 0xF00F -+#define reg_tuner_data_127_120_pos 0 -+#define reg_tuner_data_127_120_len 8 -+#define reg_tuner_data_127_120_lsb 120 -+#define p_reg_tuner_data_135_128 0xF010 -+#define reg_tuner_data_135_128_pos 0 -+#define reg_tuner_data_135_128_len 8 -+#define reg_tuner_data_135_128_lsb 128 -+#define p_reg_tuner_data_143_136 0xF011 -+#define reg_tuner_data_143_136_pos 0 -+#define reg_tuner_data_143_136_len 8 -+#define reg_tuner_data_143_136_lsb 136 -+#define p_reg_tuner_data_151_144 0xF012 -+#define reg_tuner_data_151_144_pos 0 -+#define reg_tuner_data_151_144_len 8 -+#define reg_tuner_data_151_144_lsb 144 -+#define p_reg_tuner_data_159_152 0xF013 -+#define reg_tuner_data_159_152_pos 0 -+#define reg_tuner_data_159_152_len 8 -+#define reg_tuner_data_159_152_lsb 152 -+#define p_reg_tuner_data_167_160 0xF014 -+#define reg_tuner_data_167_160_pos 0 -+#define reg_tuner_data_167_160_len 8 -+#define reg_tuner_data_167_160_lsb 160 -+#define p_reg_tuner_data_175_168 0xF015 -+#define reg_tuner_data_175_168_pos 0 -+#define reg_tuner_data_175_168_len 8 -+#define reg_tuner_data_175_168_lsb 168 -+#define p_reg_tuner_data_183_176 0xF016 -+#define reg_tuner_data_183_176_pos 0 -+#define reg_tuner_data_183_176_len 8 -+#define reg_tuner_data_183_176_lsb 176 -+#define p_reg_tuner_data_191_184 0xF017 -+#define reg_tuner_data_191_184_pos 0 -+#define reg_tuner_data_191_184_len 8 -+#define reg_tuner_data_191_184_lsb 184 -+#define p_reg_tuner_data_199_192 0xF018 -+#define reg_tuner_data_199_192_pos 0 -+#define reg_tuner_data_199_192_len 8 -+#define reg_tuner_data_199_192_lsb 192 -+#define p_reg_tuner_data_207_200 0xF019 -+#define reg_tuner_data_207_200_pos 0 -+#define reg_tuner_data_207_200_len 8 -+#define reg_tuner_data_207_200_lsb 200 -+#define p_reg_tuner_data_215_208 0xF01A -+#define reg_tuner_data_215_208_pos 0 -+#define reg_tuner_data_215_208_len 8 -+#define reg_tuner_data_215_208_lsb 208 -+#define p_reg_tuner_data_223_216 0xF01B -+#define reg_tuner_data_223_216_pos 0 -+#define reg_tuner_data_223_216_len 8 -+#define reg_tuner_data_223_216_lsb 216 -+#define p_reg_tuner_data_231_224 0xF01C -+#define reg_tuner_data_231_224_pos 0 -+#define reg_tuner_data_231_224_len 8 -+#define reg_tuner_data_231_224_lsb 224 -+#define p_reg_tuner_data_239_232 0xF01D -+#define reg_tuner_data_239_232_pos 0 -+#define reg_tuner_data_239_232_len 8 -+#define reg_tuner_data_239_232_lsb 232 -+#define p_reg_tuner_data_247_240 0xF01E -+#define reg_tuner_data_247_240_pos 0 -+#define reg_tuner_data_247_240_len 8 -+#define reg_tuner_data_247_240_lsb 240 -+#define p_reg_tuner_data_255_248 0xF01F -+#define reg_tuner_data_255_248_pos 0 -+#define reg_tuner_data_255_248_len 8 -+#define reg_tuner_data_255_248_lsb 248 -+#define p_reg_tuner_data_263_256 0xF020 -+#define reg_tuner_data_263_256_pos 0 -+#define reg_tuner_data_263_256_len 8 -+#define reg_tuner_data_263_256_lsb 256 -+#define p_reg_tuner_data_271_264 0xF021 -+#define reg_tuner_data_271_264_pos 0 -+#define reg_tuner_data_271_264_len 8 -+#define reg_tuner_data_271_264_lsb 264 -+#define p_reg_tuner_data_279_272 0xF022 -+#define reg_tuner_data_279_272_pos 0 -+#define reg_tuner_data_279_272_len 8 -+#define reg_tuner_data_279_272_lsb 272 -+#define p_reg_tuner_data_287_280 0xF023 -+#define reg_tuner_data_287_280_pos 0 -+#define reg_tuner_data_287_280_len 8 -+#define reg_tuner_data_287_280_lsb 280 -+#define p_reg_tuner_data_295_288 0xF024 -+#define reg_tuner_data_295_288_pos 0 -+#define reg_tuner_data_295_288_len 8 -+#define reg_tuner_data_295_288_lsb 288 -+#define p_reg_tuner_data_303_296 0xF025 -+#define reg_tuner_data_303_296_pos 0 -+#define reg_tuner_data_303_296_len 8 -+#define reg_tuner_data_303_296_lsb 296 -+#define p_reg_tuner_data_311_304 0xF026 -+#define reg_tuner_data_311_304_pos 0 -+#define reg_tuner_data_311_304_len 8 -+#define reg_tuner_data_311_304_lsb 304 -+#define p_reg_tuner_data_319_312 0xF027 -+#define reg_tuner_data_319_312_pos 0 -+#define reg_tuner_data_319_312_len 8 -+#define reg_tuner_data_319_312_lsb 312 -+#define p_reg_tuner_data_327_320 0xF028 -+#define reg_tuner_data_327_320_pos 0 -+#define reg_tuner_data_327_320_len 8 -+#define reg_tuner_data_327_320_lsb 320 -+#define p_reg_tuner_data_335_328 0xF029 -+#define reg_tuner_data_335_328_pos 0 -+#define reg_tuner_data_335_328_len 8 -+#define reg_tuner_data_335_328_lsb 328 -+#define p_reg_tuner_data_343_336 0xF02A -+#define reg_tuner_data_343_336_pos 0 -+#define reg_tuner_data_343_336_len 8 -+#define reg_tuner_data_343_336_lsb 336 -+#define p_reg_tuner_data_351_344 0xF02B -+#define reg_tuner_data_351_344_pos 0 -+#define reg_tuner_data_351_344_len 8 -+#define reg_tuner_data_351_344_lsb 344 -+#define p_reg_tuner_data_359_352 0xF02C -+#define reg_tuner_data_359_352_pos 0 -+#define reg_tuner_data_359_352_len 8 -+#define reg_tuner_data_359_352_lsb 352 -+#define p_reg_tuner_data_367_360 0xF02D -+#define reg_tuner_data_367_360_pos 0 -+#define reg_tuner_data_367_360_len 8 -+#define reg_tuner_data_367_360_lsb 360 -+#define p_reg_tuner_data_375_368 0xF02E -+#define reg_tuner_data_375_368_pos 0 -+#define reg_tuner_data_375_368_len 8 -+#define reg_tuner_data_375_368_lsb 368 -+#define p_reg_tuner_data_383_376 0xF02F -+#define reg_tuner_data_383_376_pos 0 -+#define reg_tuner_data_383_376_len 8 -+#define reg_tuner_data_383_376_lsb 376 -+#define p_reg_tuner_data_391_384 0xF030 -+#define reg_tuner_data_391_384_pos 0 -+#define reg_tuner_data_391_384_len 8 -+#define reg_tuner_data_391_384_lsb 384 -+#define p_reg_tuner_data_399_392 0xF031 -+#define reg_tuner_data_399_392_pos 0 -+#define reg_tuner_data_399_392_len 8 -+#define reg_tuner_data_399_392_lsb 392 -+#define p_reg_tuner_data_407_400 0xF032 -+#define reg_tuner_data_407_400_pos 0 -+#define reg_tuner_data_407_400_len 8 -+#define reg_tuner_data_407_400_lsb 400 -+#define p_reg_tuner_data_415_408 0xF033 -+#define reg_tuner_data_415_408_pos 0 -+#define reg_tuner_data_415_408_len 8 -+#define reg_tuner_data_415_408_lsb 408 -+#define p_reg_tuner_data_423_416 0xF034 -+#define reg_tuner_data_423_416_pos 0 -+#define reg_tuner_data_423_416_len 8 -+#define reg_tuner_data_423_416_lsb 416 -+#define p_reg_tuner_data_431_424 0xF035 -+#define reg_tuner_data_431_424_pos 0 -+#define reg_tuner_data_431_424_len 8 -+#define reg_tuner_data_431_424_lsb 424 -+#define p_reg_tuner_data_439_432 0xF036 -+#define reg_tuner_data_439_432_pos 0 -+#define reg_tuner_data_439_432_len 8 -+#define reg_tuner_data_439_432_lsb 432 -+#define p_reg_tuner_data_447_440 0xF037 -+#define reg_tuner_data_447_440_pos 0 -+#define reg_tuner_data_447_440_len 8 -+#define reg_tuner_data_447_440_lsb 440 -+#define p_reg_tuner_data_455_448 0xF038 -+#define reg_tuner_data_455_448_pos 0 -+#define reg_tuner_data_455_448_len 8 -+#define reg_tuner_data_455_448_lsb 448 -+#define p_reg_tuner_data_463_456 0xF039 -+#define reg_tuner_data_463_456_pos 0 -+#define reg_tuner_data_463_456_len 8 -+#define reg_tuner_data_463_456_lsb 456 -+#define p_reg_tuner_data_471_464 0xF03A -+#define reg_tuner_data_471_464_pos 0 -+#define reg_tuner_data_471_464_len 8 -+#define reg_tuner_data_471_464_lsb 464 -+#define p_reg_tuner_data_479_472 0xF03B -+#define reg_tuner_data_479_472_pos 0 -+#define reg_tuner_data_479_472_len 8 -+#define reg_tuner_data_479_472_lsb 472 -+#define p_reg_tuner_data_487_480 0xF03C -+#define reg_tuner_data_487_480_pos 0 -+#define reg_tuner_data_487_480_len 8 -+#define reg_tuner_data_487_480_lsb 480 -+#define p_reg_tuner_data_495_488 0xF03D -+#define reg_tuner_data_495_488_pos 0 -+#define reg_tuner_data_495_488_len 8 -+#define reg_tuner_data_495_488_lsb 488 -+#define p_reg_tuner_data_503_496 0xF03E -+#define reg_tuner_data_503_496_pos 0 -+#define reg_tuner_data_503_496_len 8 -+#define reg_tuner_data_503_496_lsb 496 -+#define p_reg_tuner_data_511_504 0xF03F -+#define reg_tuner_data_511_504_pos 0 -+#define reg_tuner_data_511_504_len 8 -+#define reg_tuner_data_511_504_lsb 504 -+#define p_reg_tuner_data_519_512 0xF040 -+#define reg_tuner_data_519_512_pos 0 -+#define reg_tuner_data_519_512_len 8 -+#define reg_tuner_data_519_512_lsb 512 -+#define p_reg_tuner_data_527_520 0xF041 -+#define reg_tuner_data_527_520_pos 0 -+#define reg_tuner_data_527_520_len 8 -+#define reg_tuner_data_527_520_lsb 520 -+#define p_reg_tuner_data_535_528 0xF042 -+#define reg_tuner_data_535_528_pos 0 -+#define reg_tuner_data_535_528_len 8 -+#define reg_tuner_data_535_528_lsb 528 -+#define p_reg_tuner_data_543_536 0xF043 -+#define reg_tuner_data_543_536_pos 0 -+#define reg_tuner_data_543_536_len 8 -+#define reg_tuner_data_543_536_lsb 536 -+#define p_reg_tuner_data_551_544 0xF044 -+#define reg_tuner_data_551_544_pos 0 -+#define reg_tuner_data_551_544_len 8 -+#define reg_tuner_data_551_544_lsb 544 -+#define p_reg_tuner_data_559_552 0xF045 -+#define reg_tuner_data_559_552_pos 0 -+#define reg_tuner_data_559_552_len 8 -+#define reg_tuner_data_559_552_lsb 552 -+#define p_reg_tuner_data_567_560 0xF046 -+#define reg_tuner_data_567_560_pos 0 -+#define reg_tuner_data_567_560_len 8 -+#define reg_tuner_data_567_560_lsb 560 -+#define p_reg_tuner_data_575_568 0xF047 -+#define reg_tuner_data_575_568_pos 0 -+#define reg_tuner_data_575_568_len 8 -+#define reg_tuner_data_575_568_lsb 568 -+#define p_reg_tuner_data_583_576 0xF048 -+#define reg_tuner_data_583_576_pos 0 -+#define reg_tuner_data_583_576_len 8 -+#define reg_tuner_data_583_576_lsb 576 -+#define p_reg_tuner_data_591_584 0xF049 -+#define reg_tuner_data_591_584_pos 0 -+#define reg_tuner_data_591_584_len 8 -+#define reg_tuner_data_591_584_lsb 584 -+#define p_reg_tuner_data_599_592 0xF04A -+#define reg_tuner_data_599_592_pos 0 -+#define reg_tuner_data_599_592_len 8 -+#define reg_tuner_data_599_592_lsb 592 -+#define p_reg_tuner_data_607_600 0xF04B -+#define reg_tuner_data_607_600_pos 0 -+#define reg_tuner_data_607_600_len 8 -+#define reg_tuner_data_607_600_lsb 600 -+#define p_reg_tuner_data_615_608 0xF04C -+#define reg_tuner_data_615_608_pos 0 -+#define reg_tuner_data_615_608_len 8 -+#define reg_tuner_data_615_608_lsb 608 -+#define p_reg_tuner_data_623_616 0xF04D -+#define reg_tuner_data_623_616_pos 0 -+#define reg_tuner_data_623_616_len 8 -+#define reg_tuner_data_623_616_lsb 616 -+#define p_reg_tuner_data_631_624 0xF04E -+#define reg_tuner_data_631_624_pos 0 -+#define reg_tuner_data_631_624_len 8 -+#define reg_tuner_data_631_624_lsb 624 -+#define p_reg_tuner_data_639_632 0xF04F -+#define reg_tuner_data_639_632_pos 0 -+#define reg_tuner_data_639_632_len 8 -+#define reg_tuner_data_639_632_lsb 632 -+#define p_reg_tuner_data_647_640 0xF050 -+#define reg_tuner_data_647_640_pos 0 -+#define reg_tuner_data_647_640_len 8 -+#define reg_tuner_data_647_640_lsb 640 -+#define p_reg_tuner_data_655_648 0xF051 -+#define reg_tuner_data_655_648_pos 0 -+#define reg_tuner_data_655_648_len 8 -+#define reg_tuner_data_655_648_lsb 648 -+#define p_reg_tuner_data_663_656 0xF052 -+#define reg_tuner_data_663_656_pos 0 -+#define reg_tuner_data_663_656_len 8 -+#define reg_tuner_data_663_656_lsb 656 -+#define p_reg_tuner_data_671_664 0xF053 -+#define reg_tuner_data_671_664_pos 0 -+#define reg_tuner_data_671_664_len 8 -+#define reg_tuner_data_671_664_lsb 664 -+#define p_reg_tuner_data_679_672 0xF054 -+#define reg_tuner_data_679_672_pos 0 -+#define reg_tuner_data_679_672_len 8 -+#define reg_tuner_data_679_672_lsb 672 -+#define p_reg_tuner_data_687_680 0xF055 -+#define reg_tuner_data_687_680_pos 0 -+#define reg_tuner_data_687_680_len 8 -+#define reg_tuner_data_687_680_lsb 680 -+#define p_reg_tuner_data_695_688 0xF056 -+#define reg_tuner_data_695_688_pos 0 -+#define reg_tuner_data_695_688_len 8 -+#define reg_tuner_data_695_688_lsb 688 -+#define p_reg_tuner_data_703_696 0xF057 -+#define reg_tuner_data_703_696_pos 0 -+#define reg_tuner_data_703_696_len 8 -+#define reg_tuner_data_703_696_lsb 696 -+#define p_reg_tuner_data_711_704 0xF058 -+#define reg_tuner_data_711_704_pos 0 -+#define reg_tuner_data_711_704_len 8 -+#define reg_tuner_data_711_704_lsb 704 -+#define p_reg_tuner_data_719_712 0xF059 -+#define reg_tuner_data_719_712_pos 0 -+#define reg_tuner_data_719_712_len 8 -+#define reg_tuner_data_719_712_lsb 712 -+#define p_reg_tuner_data_727_720 0xF05A -+#define reg_tuner_data_727_720_pos 0 -+#define reg_tuner_data_727_720_len 8 -+#define reg_tuner_data_727_720_lsb 720 -+#define p_reg_tuner_data_735_728 0xF05B -+#define reg_tuner_data_735_728_pos 0 -+#define reg_tuner_data_735_728_len 8 -+#define reg_tuner_data_735_728_lsb 728 -+#define p_reg_tuner_data_743_736 0xF05C -+#define reg_tuner_data_743_736_pos 0 -+#define reg_tuner_data_743_736_len 8 -+#define reg_tuner_data_743_736_lsb 736 -+#define p_reg_tuner_data_751_744 0xF05D -+#define reg_tuner_data_751_744_pos 0 -+#define reg_tuner_data_751_744_len 8 -+#define reg_tuner_data_751_744_lsb 744 -+#define p_reg_tuner_data_759_752 0xF05E -+#define reg_tuner_data_759_752_pos 0 -+#define reg_tuner_data_759_752_len 8 -+#define reg_tuner_data_759_752_lsb 752 -+#define p_reg_tuner_data_767_760 0xF05F -+#define reg_tuner_data_767_760_pos 0 -+#define reg_tuner_data_767_760_len 8 -+#define reg_tuner_data_767_760_lsb 760 -+#define p_reg_tuner_data_775_768 0xF060 -+#define reg_tuner_data_775_768_pos 0 -+#define reg_tuner_data_775_768_len 8 -+#define reg_tuner_data_775_768_lsb 768 -+#define p_reg_tuner_data_783_776 0xF061 -+#define reg_tuner_data_783_776_pos 0 -+#define reg_tuner_data_783_776_len 8 -+#define reg_tuner_data_783_776_lsb 776 -+#define p_reg_tuner_data_791_784 0xF062 -+#define reg_tuner_data_791_784_pos 0 -+#define reg_tuner_data_791_784_len 8 -+#define reg_tuner_data_791_784_lsb 784 -+#define p_reg_tuner_data_799_792 0xF063 -+#define reg_tuner_data_799_792_pos 0 -+#define reg_tuner_data_799_792_len 8 -+#define reg_tuner_data_799_792_lsb 792 -+#define p_reg_tuner_data_807_800 0xF064 -+#define reg_tuner_data_807_800_pos 0 -+#define reg_tuner_data_807_800_len 8 -+#define reg_tuner_data_807_800_lsb 800 -+#define p_reg_tuner_data_815_808 0xF065 -+#define reg_tuner_data_815_808_pos 0 -+#define reg_tuner_data_815_808_len 8 -+#define reg_tuner_data_815_808_lsb 808 -+#define p_reg_tuner_data_823_816 0xF066 -+#define reg_tuner_data_823_816_pos 0 -+#define reg_tuner_data_823_816_len 8 -+#define reg_tuner_data_823_816_lsb 816 -+#define p_reg_tuner_data_831_824 0xF067 -+#define reg_tuner_data_831_824_pos 0 -+#define reg_tuner_data_831_824_len 8 -+#define reg_tuner_data_831_824_lsb 824 -+#define p_reg_tuner_data_839_832 0xF068 -+#define reg_tuner_data_839_832_pos 0 -+#define reg_tuner_data_839_832_len 8 -+#define reg_tuner_data_839_832_lsb 832 -+#define p_reg_tuner_data_847_840 0xF069 -+#define reg_tuner_data_847_840_pos 0 -+#define reg_tuner_data_847_840_len 8 -+#define reg_tuner_data_847_840_lsb 840 -+#define p_reg_tuner_data_855_848 0xF06A -+#define reg_tuner_data_855_848_pos 0 -+#define reg_tuner_data_855_848_len 8 -+#define reg_tuner_data_855_848_lsb 848 -+#define p_reg_tuner_data_863_856 0xF06B -+#define reg_tuner_data_863_856_pos 0 -+#define reg_tuner_data_863_856_len 8 -+#define reg_tuner_data_863_856_lsb 856 -+#define p_reg_tuner_data_871_864 0xF06C -+#define reg_tuner_data_871_864_pos 0 -+#define reg_tuner_data_871_864_len 8 -+#define reg_tuner_data_871_864_lsb 864 -+#define p_reg_tuner_data_879_872 0xF06D -+#define reg_tuner_data_879_872_pos 0 -+#define reg_tuner_data_879_872_len 8 -+#define reg_tuner_data_879_872_lsb 872 -+#define p_reg_tuner_data_887_880 0xF06E -+#define reg_tuner_data_887_880_pos 0 -+#define reg_tuner_data_887_880_len 8 -+#define reg_tuner_data_887_880_lsb 880 -+#define p_reg_tuner_data_895_888 0xF06F -+#define reg_tuner_data_895_888_pos 0 -+#define reg_tuner_data_895_888_len 8 -+#define reg_tuner_data_895_888_lsb 888 -+#define p_reg_tuner_data_903_896 0xF070 -+#define reg_tuner_data_903_896_pos 0 -+#define reg_tuner_data_903_896_len 8 -+#define reg_tuner_data_903_896_lsb 896 -+#define p_reg_tuner_data_911_904 0xF071 -+#define reg_tuner_data_911_904_pos 0 -+#define reg_tuner_data_911_904_len 8 -+#define reg_tuner_data_911_904_lsb 904 -+#define p_reg_tuner_data_919_912 0xF072 -+#define reg_tuner_data_919_912_pos 0 -+#define reg_tuner_data_919_912_len 8 -+#define reg_tuner_data_919_912_lsb 912 -+#define p_reg_tuner_data_927_920 0xF073 -+#define reg_tuner_data_927_920_pos 0 -+#define reg_tuner_data_927_920_len 8 -+#define reg_tuner_data_927_920_lsb 920 -+#define p_reg_tuner_data_935_928 0xF074 -+#define reg_tuner_data_935_928_pos 0 -+#define reg_tuner_data_935_928_len 8 -+#define reg_tuner_data_935_928_lsb 928 -+#define p_reg_tuner_data_943_936 0xF075 -+#define reg_tuner_data_943_936_pos 0 -+#define reg_tuner_data_943_936_len 8 -+#define reg_tuner_data_943_936_lsb 936 -+#define p_reg_tuner_data_951_944 0xF076 -+#define reg_tuner_data_951_944_pos 0 -+#define reg_tuner_data_951_944_len 8 -+#define reg_tuner_data_951_944_lsb 944 -+#define p_reg_tuner_data_959_952 0xF077 -+#define reg_tuner_data_959_952_pos 0 -+#define reg_tuner_data_959_952_len 8 -+#define reg_tuner_data_959_952_lsb 952 -+#define p_reg_tuner_data_967_960 0xF078 -+#define reg_tuner_data_967_960_pos 0 -+#define reg_tuner_data_967_960_len 8 -+#define reg_tuner_data_967_960_lsb 960 -+#define p_reg_tuner_data_975_968 0xF079 -+#define reg_tuner_data_975_968_pos 0 -+#define reg_tuner_data_975_968_len 8 -+#define reg_tuner_data_975_968_lsb 968 -+#define p_reg_tuner_data_983_976 0xF07A -+#define reg_tuner_data_983_976_pos 0 -+#define reg_tuner_data_983_976_len 8 -+#define reg_tuner_data_983_976_lsb 976 -+#define p_reg_tuner_data_991_984 0xF07B -+#define reg_tuner_data_991_984_pos 0 -+#define reg_tuner_data_991_984_len 8 -+#define reg_tuner_data_991_984_lsb 984 -+#define p_reg_tuner_data_999_992 0xF07C -+#define reg_tuner_data_999_992_pos 0 -+#define reg_tuner_data_999_992_len 8 -+#define reg_tuner_data_999_992_lsb 992 -+#define p_reg_tuner_data_1007_1000 0xF07D -+#define reg_tuner_data_1007_1000_pos 0 -+#define reg_tuner_data_1007_1000_len 8 -+#define reg_tuner_data_1007_1000_lsb 1000 -+#define p_reg_tuner_data_1015_1008 0xF07E -+#define reg_tuner_data_1015_1008_pos 0 -+#define reg_tuner_data_1015_1008_len 8 -+#define reg_tuner_data_1015_1008_lsb 1008 -+#define p_reg_tuner_data_1023_1016 0xF07F -+#define reg_tuner_data_1023_1016_pos 0 -+#define reg_tuner_data_1023_1016_len 8 -+#define reg_tuner_data_1023_1016_lsb 1016 -+#define p_reg_tuner_data_1031_1024 0xF080 -+#define reg_tuner_data_1031_1024_pos 0 -+#define reg_tuner_data_1031_1024_len 8 -+#define reg_tuner_data_1031_1024_lsb 1024 -+#define p_reg_tuner_data_1039_1032 0xF081 -+#define reg_tuner_data_1039_1032_pos 0 -+#define reg_tuner_data_1039_1032_len 8 -+#define reg_tuner_data_1039_1032_lsb 1032 -+#define p_reg_tuner_data_1047_1040 0xF082 -+#define reg_tuner_data_1047_1040_pos 0 -+#define reg_tuner_data_1047_1040_len 8 -+#define reg_tuner_data_1047_1040_lsb 1040 -+#define p_reg_tuner_data_1055_1048 0xF083 -+#define reg_tuner_data_1055_1048_pos 0 -+#define reg_tuner_data_1055_1048_len 8 -+#define reg_tuner_data_1055_1048_lsb 1048 -+#define p_reg_tuner_data_1063_1056 0xF084 -+#define reg_tuner_data_1063_1056_pos 0 -+#define reg_tuner_data_1063_1056_len 8 -+#define reg_tuner_data_1063_1056_lsb 1056 -+#define p_reg_tuner_data_1071_1064 0xF085 -+#define reg_tuner_data_1071_1064_pos 0 -+#define reg_tuner_data_1071_1064_len 8 -+#define reg_tuner_data_1071_1064_lsb 1064 -+#define p_reg_tuner_data_1079_1072 0xF086 -+#define reg_tuner_data_1079_1072_pos 0 -+#define reg_tuner_data_1079_1072_len 8 -+#define reg_tuner_data_1079_1072_lsb 1072 -+#define p_reg_tuner_data_1087_1080 0xF087 -+#define reg_tuner_data_1087_1080_pos 0 -+#define reg_tuner_data_1087_1080_len 8 -+#define reg_tuner_data_1087_1080_lsb 1080 -+#define p_reg_tuner_data_1095_1088 0xF088 -+#define reg_tuner_data_1095_1088_pos 0 -+#define reg_tuner_data_1095_1088_len 8 -+#define reg_tuner_data_1095_1088_lsb 1088 -+#define p_reg_tuner_data_1103_1096 0xF089 -+#define reg_tuner_data_1103_1096_pos 0 -+#define reg_tuner_data_1103_1096_len 8 -+#define reg_tuner_data_1103_1096_lsb 1096 -+#define p_reg_tuner_data_1111_1104 0xF08A -+#define reg_tuner_data_1111_1104_pos 0 -+#define reg_tuner_data_1111_1104_len 8 -+#define reg_tuner_data_1111_1104_lsb 1104 -+#define p_reg_tuner_data_1119_1112 0xF08B -+#define reg_tuner_data_1119_1112_pos 0 -+#define reg_tuner_data_1119_1112_len 8 -+#define reg_tuner_data_1119_1112_lsb 1112 -+#define p_reg_tuner_data_1127_1120 0xF08C -+#define reg_tuner_data_1127_1120_pos 0 -+#define reg_tuner_data_1127_1120_len 8 -+#define reg_tuner_data_1127_1120_lsb 1120 -+#define p_reg_tuner_data_1135_1128 0xF08D -+#define reg_tuner_data_1135_1128_pos 0 -+#define reg_tuner_data_1135_1128_len 8 -+#define reg_tuner_data_1135_1128_lsb 1128 -+#define p_reg_tuner_data_1143_1136 0xF08E -+#define reg_tuner_data_1143_1136_pos 0 -+#define reg_tuner_data_1143_1136_len 8 -+#define reg_tuner_data_1143_1136_lsb 1136 -+#define p_reg_tuner_data_1151_1144 0xF08F -+#define reg_tuner_data_1151_1144_pos 0 -+#define reg_tuner_data_1151_1144_len 8 -+#define reg_tuner_data_1151_1144_lsb 1144 -+#define p_reg_tuner_data_1159_1152 0xF090 -+#define reg_tuner_data_1159_1152_pos 0 -+#define reg_tuner_data_1159_1152_len 8 -+#define reg_tuner_data_1159_1152_lsb 1152 -+#define p_reg_tuner_data_1167_1160 0xF091 -+#define reg_tuner_data_1167_1160_pos 0 -+#define reg_tuner_data_1167_1160_len 8 -+#define reg_tuner_data_1167_1160_lsb 1160 -+#define p_reg_tuner_data_1175_1168 0xF092 -+#define reg_tuner_data_1175_1168_pos 0 -+#define reg_tuner_data_1175_1168_len 8 -+#define reg_tuner_data_1175_1168_lsb 1168 -+#define p_reg_tuner_data_1183_1176 0xF093 -+#define reg_tuner_data_1183_1176_pos 0 -+#define reg_tuner_data_1183_1176_len 8 -+#define reg_tuner_data_1183_1176_lsb 1176 -+#define p_reg_tuner_data_1191_1184 0xF094 -+#define reg_tuner_data_1191_1184_pos 0 -+#define reg_tuner_data_1191_1184_len 8 -+#define reg_tuner_data_1191_1184_lsb 1184 -+#define p_reg_tuner_data_1199_1192 0xF095 -+#define reg_tuner_data_1199_1192_pos 0 -+#define reg_tuner_data_1199_1192_len 8 -+#define reg_tuner_data_1199_1192_lsb 1192 -+#define p_reg_tuner_data_1207_1200 0xF096 -+#define reg_tuner_data_1207_1200_pos 0 -+#define reg_tuner_data_1207_1200_len 8 -+#define reg_tuner_data_1207_1200_lsb 1200 -+#define p_reg_tuner_data_1215_1208 0xF097 -+#define reg_tuner_data_1215_1208_pos 0 -+#define reg_tuner_data_1215_1208_len 8 -+#define reg_tuner_data_1215_1208_lsb 1208 -+#define p_reg_tuner_data_1223_1216 0xF098 -+#define reg_tuner_data_1223_1216_pos 0 -+#define reg_tuner_data_1223_1216_len 8 -+#define reg_tuner_data_1223_1216_lsb 1216 -+#define p_reg_tuner_data_1231_1224 0xF099 -+#define reg_tuner_data_1231_1224_pos 0 -+#define reg_tuner_data_1231_1224_len 8 -+#define reg_tuner_data_1231_1224_lsb 1224 -+#define p_reg_tuner_data_1239_1232 0xF09A -+#define reg_tuner_data_1239_1232_pos 0 -+#define reg_tuner_data_1239_1232_len 8 -+#define reg_tuner_data_1239_1232_lsb 1232 -+#define p_reg_tuner_data_1247_1240 0xF09B -+#define reg_tuner_data_1247_1240_pos 0 -+#define reg_tuner_data_1247_1240_len 8 -+#define reg_tuner_data_1247_1240_lsb 1240 -+#define p_reg_tuner_data_1255_1248 0xF09C -+#define reg_tuner_data_1255_1248_pos 0 -+#define reg_tuner_data_1255_1248_len 8 -+#define reg_tuner_data_1255_1248_lsb 1248 -+#define p_reg_tuner_data_1263_1256 0xF09D -+#define reg_tuner_data_1263_1256_pos 0 -+#define reg_tuner_data_1263_1256_len 8 -+#define reg_tuner_data_1263_1256_lsb 1256 -+#define p_reg_tuner_data_1271_1264 0xF09E -+#define reg_tuner_data_1271_1264_pos 0 -+#define reg_tuner_data_1271_1264_len 8 -+#define reg_tuner_data_1271_1264_lsb 1264 -+#define p_reg_tuner_data_1279_1272 0xF09F -+#define reg_tuner_data_1279_1272_pos 0 -+#define reg_tuner_data_1279_1272_len 8 -+#define reg_tuner_data_1279_1272_lsb 1272 -+#define p_reg_tuner_data_1287_1280 0xF0A0 -+#define reg_tuner_data_1287_1280_pos 0 -+#define reg_tuner_data_1287_1280_len 8 -+#define reg_tuner_data_1287_1280_lsb 1280 -+#define p_reg_tuner_data_1295_1288 0xF0A1 -+#define reg_tuner_data_1295_1288_pos 0 -+#define reg_tuner_data_1295_1288_len 8 -+#define reg_tuner_data_1295_1288_lsb 1288 -+#define p_reg_tuner_data_1303_1296 0xF0A2 -+#define reg_tuner_data_1303_1296_pos 0 -+#define reg_tuner_data_1303_1296_len 8 -+#define reg_tuner_data_1303_1296_lsb 1296 -+#define p_reg_tuner_data_1311_1304 0xF0A3 -+#define reg_tuner_data_1311_1304_pos 0 -+#define reg_tuner_data_1311_1304_len 8 -+#define reg_tuner_data_1311_1304_lsb 1304 -+#define p_reg_tuner_data_1319_1312 0xF0A4 -+#define reg_tuner_data_1319_1312_pos 0 -+#define reg_tuner_data_1319_1312_len 8 -+#define reg_tuner_data_1319_1312_lsb 1312 -+#define p_reg_tuner_data_1327_1320 0xF0A5 -+#define reg_tuner_data_1327_1320_pos 0 -+#define reg_tuner_data_1327_1320_len 8 -+#define reg_tuner_data_1327_1320_lsb 1320 -+#define p_reg_tuner_data_1335_1328 0xF0A6 -+#define reg_tuner_data_1335_1328_pos 0 -+#define reg_tuner_data_1335_1328_len 8 -+#define reg_tuner_data_1335_1328_lsb 1328 -+#define p_reg_tuner_data_1343_1336 0xF0A7 -+#define reg_tuner_data_1343_1336_pos 0 -+#define reg_tuner_data_1343_1336_len 8 -+#define reg_tuner_data_1343_1336_lsb 1336 -+#define p_reg_tuner_data_1351_1344 0xF0A8 -+#define reg_tuner_data_1351_1344_pos 0 -+#define reg_tuner_data_1351_1344_len 8 -+#define reg_tuner_data_1351_1344_lsb 1344 -+#define p_reg_tuner_data_1359_1352 0xF0A9 -+#define reg_tuner_data_1359_1352_pos 0 -+#define reg_tuner_data_1359_1352_len 8 -+#define reg_tuner_data_1359_1352_lsb 1352 -+#define p_reg_tuner_data_1367_1360 0xF0AA -+#define reg_tuner_data_1367_1360_pos 0 -+#define reg_tuner_data_1367_1360_len 8 -+#define reg_tuner_data_1367_1360_lsb 1360 -+#define p_reg_tuner_data_1375_1368 0xF0AB -+#define reg_tuner_data_1375_1368_pos 0 -+#define reg_tuner_data_1375_1368_len 8 -+#define reg_tuner_data_1375_1368_lsb 1368 -+#define p_reg_tuner_data_1383_1376 0xF0AC -+#define reg_tuner_data_1383_1376_pos 0 -+#define reg_tuner_data_1383_1376_len 8 -+#define reg_tuner_data_1383_1376_lsb 1376 -+#define p_reg_tuner_data_1391_1384 0xF0AD -+#define reg_tuner_data_1391_1384_pos 0 -+#define reg_tuner_data_1391_1384_len 8 -+#define reg_tuner_data_1391_1384_lsb 1384 -+#define p_reg_tuner_data_1399_1392 0xF0AE -+#define reg_tuner_data_1399_1392_pos 0 -+#define reg_tuner_data_1399_1392_len 8 -+#define reg_tuner_data_1399_1392_lsb 1392 -+#define p_reg_tuner_data_1407_1400 0xF0AF -+#define reg_tuner_data_1407_1400_pos 0 -+#define reg_tuner_data_1407_1400_len 8 -+#define reg_tuner_data_1407_1400_lsb 1400 -+#define p_reg_tuner_data_1415_1408 0xF0B0 -+#define reg_tuner_data_1415_1408_pos 0 -+#define reg_tuner_data_1415_1408_len 8 -+#define reg_tuner_data_1415_1408_lsb 1408 -+#define p_reg_tuner_data_1423_1416 0xF0B1 -+#define reg_tuner_data_1423_1416_pos 0 -+#define reg_tuner_data_1423_1416_len 8 -+#define reg_tuner_data_1423_1416_lsb 1416 -+#define p_reg_tuner_data_1431_1424 0xF0B2 -+#define reg_tuner_data_1431_1424_pos 0 -+#define reg_tuner_data_1431_1424_len 8 -+#define reg_tuner_data_1431_1424_lsb 1424 -+#define p_reg_tuner_data_1439_1432 0xF0B3 -+#define reg_tuner_data_1439_1432_pos 0 -+#define reg_tuner_data_1439_1432_len 8 -+#define reg_tuner_data_1439_1432_lsb 1432 -+#define p_reg_tuner_data_1447_1440 0xF0B4 -+#define reg_tuner_data_1447_1440_pos 0 -+#define reg_tuner_data_1447_1440_len 8 -+#define reg_tuner_data_1447_1440_lsb 1440 -+#define p_reg_tuner_data_1455_1448 0xF0B5 -+#define reg_tuner_data_1455_1448_pos 0 -+#define reg_tuner_data_1455_1448_len 8 -+#define reg_tuner_data_1455_1448_lsb 1448 -+#define p_reg_tuner_data_1463_1456 0xF0B6 -+#define reg_tuner_data_1463_1456_pos 0 -+#define reg_tuner_data_1463_1456_len 8 -+#define reg_tuner_data_1463_1456_lsb 1456 -+#define p_reg_tuner_data_1471_1464 0xF0B7 -+#define reg_tuner_data_1471_1464_pos 0 -+#define reg_tuner_data_1471_1464_len 8 -+#define reg_tuner_data_1471_1464_lsb 1464 -+#define p_reg_tuner_data_1479_1472 0xF0B8 -+#define reg_tuner_data_1479_1472_pos 0 -+#define reg_tuner_data_1479_1472_len 8 -+#define reg_tuner_data_1479_1472_lsb 1472 -+#define p_reg_tuner_data_1487_1480 0xF0B9 -+#define reg_tuner_data_1487_1480_pos 0 -+#define reg_tuner_data_1487_1480_len 8 -+#define reg_tuner_data_1487_1480_lsb 1480 -+#define p_reg_tuner_data_1495_1488 0xF0BA -+#define reg_tuner_data_1495_1488_pos 0 -+#define reg_tuner_data_1495_1488_len 8 -+#define reg_tuner_data_1495_1488_lsb 1488 -+#define p_reg_tuner_data_1503_1496 0xF0BB -+#define reg_tuner_data_1503_1496_pos 0 -+#define reg_tuner_data_1503_1496_len 8 -+#define reg_tuner_data_1503_1496_lsb 1496 -+#define p_reg_tuner_data_1511_1504 0xF0BC -+#define reg_tuner_data_1511_1504_pos 0 -+#define reg_tuner_data_1511_1504_len 8 -+#define reg_tuner_data_1511_1504_lsb 1504 -+#define p_reg_tuner_data_1519_1512 0xF0BD -+#define reg_tuner_data_1519_1512_pos 0 -+#define reg_tuner_data_1519_1512_len 8 -+#define reg_tuner_data_1519_1512_lsb 1512 -+#define p_reg_tuner_data_1527_1520 0xF0BE -+#define reg_tuner_data_1527_1520_pos 0 -+#define reg_tuner_data_1527_1520_len 8 -+#define reg_tuner_data_1527_1520_lsb 1520 -+#define p_reg_tuner_data_1535_1528 0xF0BF -+#define reg_tuner_data_1535_1528_pos 0 -+#define reg_tuner_data_1535_1528_len 8 -+#define reg_tuner_data_1535_1528_lsb 1528 -+#define p_reg_tuner_data_1543_1536 0xF0C0 -+#define reg_tuner_data_1543_1536_pos 0 -+#define reg_tuner_data_1543_1536_len 8 -+#define reg_tuner_data_1543_1536_lsb 1536 -+#define p_reg_tuner_data_1551_1544 0xF0C1 -+#define reg_tuner_data_1551_1544_pos 0 -+#define reg_tuner_data_1551_1544_len 8 -+#define reg_tuner_data_1551_1544_lsb 1544 -+#define p_reg_tuner_data_1559_1552 0xF0C2 -+#define reg_tuner_data_1559_1552_pos 0 -+#define reg_tuner_data_1559_1552_len 8 -+#define reg_tuner_data_1559_1552_lsb 1552 -+#define p_reg_tuner_data_1567_1560 0xF0C3 -+#define reg_tuner_data_1567_1560_pos 0 -+#define reg_tuner_data_1567_1560_len 8 -+#define reg_tuner_data_1567_1560_lsb 1560 -+#define p_reg_tuner_data_1575_1568 0xF0C4 -+#define reg_tuner_data_1575_1568_pos 0 -+#define reg_tuner_data_1575_1568_len 8 -+#define reg_tuner_data_1575_1568_lsb 1568 -+#define p_reg_tuner_data_1583_1576 0xF0C5 -+#define reg_tuner_data_1583_1576_pos 0 -+#define reg_tuner_data_1583_1576_len 8 -+#define reg_tuner_data_1583_1576_lsb 1576 -+#define p_reg_tuner_data_1591_1584 0xF0C6 -+#define reg_tuner_data_1591_1584_pos 0 -+#define reg_tuner_data_1591_1584_len 8 -+#define reg_tuner_data_1591_1584_lsb 1584 -+#define p_reg_tuner_data_1599_1592 0xF0C7 -+#define reg_tuner_data_1599_1592_pos 0 -+#define reg_tuner_data_1599_1592_len 8 -+#define reg_tuner_data_1599_1592_lsb 1592 -+#define p_reg_tuner_data_1607_1600 0xF0C8 -+#define reg_tuner_data_1607_1600_pos 0 -+#define reg_tuner_data_1607_1600_len 8 -+#define reg_tuner_data_1607_1600_lsb 1600 -+#define p_reg_tuner_data_1615_1608 0xF0C9 -+#define reg_tuner_data_1615_1608_pos 0 -+#define reg_tuner_data_1615_1608_len 8 -+#define reg_tuner_data_1615_1608_lsb 1608 -+#define p_reg_tuner_data_1623_1616 0xF0CA -+#define reg_tuner_data_1623_1616_pos 0 -+#define reg_tuner_data_1623_1616_len 8 -+#define reg_tuner_data_1623_1616_lsb 1616 -+#define p_reg_tuner_data_1631_1624 0xF0CB -+#define reg_tuner_data_1631_1624_pos 0 -+#define reg_tuner_data_1631_1624_len 8 -+#define reg_tuner_data_1631_1624_lsb 1624 -+#define p_reg_tuner_data_1639_1632 0xF0CC -+#define reg_tuner_data_1639_1632_pos 0 -+#define reg_tuner_data_1639_1632_len 8 -+#define reg_tuner_data_1639_1632_lsb 1632 -+#define p_reg_tuner_data_1647_1640 0xF0CD -+#define reg_tuner_data_1647_1640_pos 0 -+#define reg_tuner_data_1647_1640_len 8 -+#define reg_tuner_data_1647_1640_lsb 1640 -+#define p_reg_tuner_data_1655_1648 0xF0CE -+#define reg_tuner_data_1655_1648_pos 0 -+#define reg_tuner_data_1655_1648_len 8 -+#define reg_tuner_data_1655_1648_lsb 1648 -+#define p_reg_tuner_data_1663_1656 0xF0CF -+#define reg_tuner_data_1663_1656_pos 0 -+#define reg_tuner_data_1663_1656_len 8 -+#define reg_tuner_data_1663_1656_lsb 1656 -+#define p_reg_tuner_data_1671_1664 0xF0D0 -+#define reg_tuner_data_1671_1664_pos 0 -+#define reg_tuner_data_1671_1664_len 8 -+#define reg_tuner_data_1671_1664_lsb 1664 -+#define p_reg_tuner_data_1679_1672 0xF0D1 -+#define reg_tuner_data_1679_1672_pos 0 -+#define reg_tuner_data_1679_1672_len 8 -+#define reg_tuner_data_1679_1672_lsb 1672 -+#define p_reg_tuner_data_1687_1680 0xF0D2 -+#define reg_tuner_data_1687_1680_pos 0 -+#define reg_tuner_data_1687_1680_len 8 -+#define reg_tuner_data_1687_1680_lsb 1680 -+#define p_reg_tuner_data_1695_1688 0xF0D3 -+#define reg_tuner_data_1695_1688_pos 0 -+#define reg_tuner_data_1695_1688_len 8 -+#define reg_tuner_data_1695_1688_lsb 1688 -+#define p_reg_tuner_data_1703_1696 0xF0D4 -+#define reg_tuner_data_1703_1696_pos 0 -+#define reg_tuner_data_1703_1696_len 8 -+#define reg_tuner_data_1703_1696_lsb 1696 -+#define p_reg_tuner_data_1711_1704 0xF0D5 -+#define reg_tuner_data_1711_1704_pos 0 -+#define reg_tuner_data_1711_1704_len 8 -+#define reg_tuner_data_1711_1704_lsb 1704 -+#define p_reg_tuner_data_1719_1712 0xF0D6 -+#define reg_tuner_data_1719_1712_pos 0 -+#define reg_tuner_data_1719_1712_len 8 -+#define reg_tuner_data_1719_1712_lsb 1712 -+#define p_reg_tuner_data_1727_1720 0xF0D7 -+#define reg_tuner_data_1727_1720_pos 0 -+#define reg_tuner_data_1727_1720_len 8 -+#define reg_tuner_data_1727_1720_lsb 1720 -+#define p_reg_tuner_data_1735_1728 0xF0D8 -+#define reg_tuner_data_1735_1728_pos 0 -+#define reg_tuner_data_1735_1728_len 8 -+#define reg_tuner_data_1735_1728_lsb 1728 -+#define p_reg_tuner_data_1743_1736 0xF0D9 -+#define reg_tuner_data_1743_1736_pos 0 -+#define reg_tuner_data_1743_1736_len 8 -+#define reg_tuner_data_1743_1736_lsb 1736 -+#define p_reg_tuner_data_1751_1744 0xF0DA -+#define reg_tuner_data_1751_1744_pos 0 -+#define reg_tuner_data_1751_1744_len 8 -+#define reg_tuner_data_1751_1744_lsb 1744 -+#define p_reg_tuner_data_1759_1752 0xF0DB -+#define reg_tuner_data_1759_1752_pos 0 -+#define reg_tuner_data_1759_1752_len 8 -+#define reg_tuner_data_1759_1752_lsb 1752 -+#define p_reg_tuner_data_1767_1760 0xF0DC -+#define reg_tuner_data_1767_1760_pos 0 -+#define reg_tuner_data_1767_1760_len 8 -+#define reg_tuner_data_1767_1760_lsb 1760 -+#define p_reg_tuner_data_1775_1768 0xF0DD -+#define reg_tuner_data_1775_1768_pos 0 -+#define reg_tuner_data_1775_1768_len 8 -+#define reg_tuner_data_1775_1768_lsb 1768 -+#define p_reg_tuner_data_1783_1776 0xF0DE -+#define reg_tuner_data_1783_1776_pos 0 -+#define reg_tuner_data_1783_1776_len 8 -+#define reg_tuner_data_1783_1776_lsb 1776 -+#define p_reg_tuner_data_1791_1784 0xF0DF -+#define reg_tuner_data_1791_1784_pos 0 -+#define reg_tuner_data_1791_1784_len 8 -+#define reg_tuner_data_1791_1784_lsb 1784 -+#define p_reg_tuner_data_1799_1792 0xF0E0 -+#define reg_tuner_data_1799_1792_pos 0 -+#define reg_tuner_data_1799_1792_len 8 -+#define reg_tuner_data_1799_1792_lsb 1792 -+#define p_reg_tuner_data_1807_1800 0xF0E1 -+#define reg_tuner_data_1807_1800_pos 0 -+#define reg_tuner_data_1807_1800_len 8 -+#define reg_tuner_data_1807_1800_lsb 1800 -+#define p_reg_tuner_data_1815_1808 0xF0E2 -+#define reg_tuner_data_1815_1808_pos 0 -+#define reg_tuner_data_1815_1808_len 8 -+#define reg_tuner_data_1815_1808_lsb 1808 -+#define p_reg_tuner_data_1823_1816 0xF0E3 -+#define reg_tuner_data_1823_1816_pos 0 -+#define reg_tuner_data_1823_1816_len 8 -+#define reg_tuner_data_1823_1816_lsb 1816 -+#define p_reg_tuner_data_1831_1824 0xF0E4 -+#define reg_tuner_data_1831_1824_pos 0 -+#define reg_tuner_data_1831_1824_len 8 -+#define reg_tuner_data_1831_1824_lsb 1824 -+#define p_reg_tuner_data_1839_1832 0xF0E5 -+#define reg_tuner_data_1839_1832_pos 0 -+#define reg_tuner_data_1839_1832_len 8 -+#define reg_tuner_data_1839_1832_lsb 1832 -+#define p_reg_tuner_data_1847_1840 0xF0E6 -+#define reg_tuner_data_1847_1840_pos 0 -+#define reg_tuner_data_1847_1840_len 8 -+#define reg_tuner_data_1847_1840_lsb 1840 -+#define p_reg_tuner_data_1855_1848 0xF0E7 -+#define reg_tuner_data_1855_1848_pos 0 -+#define reg_tuner_data_1855_1848_len 8 -+#define reg_tuner_data_1855_1848_lsb 1848 -+#define p_reg_tuner_data_1863_1856 0xF0E8 -+#define reg_tuner_data_1863_1856_pos 0 -+#define reg_tuner_data_1863_1856_len 8 -+#define reg_tuner_data_1863_1856_lsb 1856 -+#define p_reg_tuner_data_1871_1864 0xF0E9 -+#define reg_tuner_data_1871_1864_pos 0 -+#define reg_tuner_data_1871_1864_len 8 -+#define reg_tuner_data_1871_1864_lsb 1864 -+#define p_reg_tuner_data_1879_1872 0xF0EA -+#define reg_tuner_data_1879_1872_pos 0 -+#define reg_tuner_data_1879_1872_len 8 -+#define reg_tuner_data_1879_1872_lsb 1872 -+#define p_reg_tuner_data_1887_1880 0xF0EB -+#define reg_tuner_data_1887_1880_pos 0 -+#define reg_tuner_data_1887_1880_len 8 -+#define reg_tuner_data_1887_1880_lsb 1880 -+#define p_reg_tuner_data_1895_1888 0xF0EC -+#define reg_tuner_data_1895_1888_pos 0 -+#define reg_tuner_data_1895_1888_len 8 -+#define reg_tuner_data_1895_1888_lsb 1888 -+#define p_reg_tuner_data_1903_1896 0xF0ED -+#define reg_tuner_data_1903_1896_pos 0 -+#define reg_tuner_data_1903_1896_len 8 -+#define reg_tuner_data_1903_1896_lsb 1896 -+#define p_reg_tuner_data_1911_1904 0xF0EE -+#define reg_tuner_data_1911_1904_pos 0 -+#define reg_tuner_data_1911_1904_len 8 -+#define reg_tuner_data_1911_1904_lsb 1904 -+#define p_reg_tuner_data_1919_1912 0xF0EF -+#define reg_tuner_data_1919_1912_pos 0 -+#define reg_tuner_data_1919_1912_len 8 -+#define reg_tuner_data_1919_1912_lsb 1912 -+#define p_reg_tuner_data_1927_1920 0xF0F0 -+#define reg_tuner_data_1927_1920_pos 0 -+#define reg_tuner_data_1927_1920_len 8 -+#define reg_tuner_data_1927_1920_lsb 1920 -+#define p_reg_tuner_data_1935_1928 0xF0F1 -+#define reg_tuner_data_1935_1928_pos 0 -+#define reg_tuner_data_1935_1928_len 8 -+#define reg_tuner_data_1935_1928_lsb 1928 -+#define p_reg_tuner_data_1943_1936 0xF0F2 -+#define reg_tuner_data_1943_1936_pos 0 -+#define reg_tuner_data_1943_1936_len 8 -+#define reg_tuner_data_1943_1936_lsb 1936 -+#define p_reg_tuner_data_1951_1944 0xF0F3 -+#define reg_tuner_data_1951_1944_pos 0 -+#define reg_tuner_data_1951_1944_len 8 -+#define reg_tuner_data_1951_1944_lsb 1944 -+#define p_reg_tuner_data_1959_1952 0xF0F4 -+#define reg_tuner_data_1959_1952_pos 0 -+#define reg_tuner_data_1959_1952_len 8 -+#define reg_tuner_data_1959_1952_lsb 1952 -+#define p_reg_tuner_data_1967_1960 0xF0F5 -+#define reg_tuner_data_1967_1960_pos 0 -+#define reg_tuner_data_1967_1960_len 8 -+#define reg_tuner_data_1967_1960_lsb 1960 -+#define p_reg_tuner_data_1975_1968 0xF0F6 -+#define reg_tuner_data_1975_1968_pos 0 -+#define reg_tuner_data_1975_1968_len 8 -+#define reg_tuner_data_1975_1968_lsb 1968 -+#define p_reg_tuner_data_1983_1976 0xF0F7 -+#define reg_tuner_data_1983_1976_pos 0 -+#define reg_tuner_data_1983_1976_len 8 -+#define reg_tuner_data_1983_1976_lsb 1976 -+#define p_reg_tuner_data_1991_1984 0xF0F8 -+#define reg_tuner_data_1991_1984_pos 0 -+#define reg_tuner_data_1991_1984_len 8 -+#define reg_tuner_data_1991_1984_lsb 1984 -+#define p_reg_tuner_data_1999_1992 0xF0F9 -+#define reg_tuner_data_1999_1992_pos 0 -+#define reg_tuner_data_1999_1992_len 8 -+#define reg_tuner_data_1999_1992_lsb 1992 -+#define p_reg_tuner_data_2007_2000 0xF0FA -+#define reg_tuner_data_2007_2000_pos 0 -+#define reg_tuner_data_2007_2000_len 8 -+#define reg_tuner_data_2007_2000_lsb 2000 -+#define p_reg_tuner_data_2015_2008 0xF0FB -+#define reg_tuner_data_2015_2008_pos 0 -+#define reg_tuner_data_2015_2008_len 8 -+#define reg_tuner_data_2015_2008_lsb 2008 -+#define p_reg_tuner_data_2023_2016 0xF0FC -+#define reg_tuner_data_2023_2016_pos 0 -+#define reg_tuner_data_2023_2016_len 8 -+#define reg_tuner_data_2023_2016_lsb 2016 -+#define p_reg_tuner_data_2031_2024 0xF0FD -+#define reg_tuner_data_2031_2024_pos 0 -+#define reg_tuner_data_2031_2024_len 8 -+#define reg_tuner_data_2031_2024_lsb 2024 -+#define p_reg_tuner_data_2039_2032 0xF0FE -+#define reg_tuner_data_2039_2032_pos 0 -+#define reg_tuner_data_2039_2032_len 8 -+#define reg_tuner_data_2039_2032_lsb 2032 -+#define p_reg_tuner_data_2047_2040 0xF0FF -+#define reg_tuner_data_2047_2040_pos 0 -+#define reg_tuner_data_2047_2040_len 8 -+#define reg_tuner_data_2047_2040_lsb 2040 -+#define p_reg_tuner_master_rd_wr 0xF100 -+#define reg_tuner_master_rd_wr_pos 0 -+#define reg_tuner_master_rd_wr_len 1 -+#define reg_tuner_master_rd_wr_lsb 0 -+#define p_reg_tuner_master_length 0xF101 -+#define reg_tuner_master_length_pos 0 -+#define reg_tuner_master_length_len 8 -+#define reg_tuner_master_length_lsb 0 -+#define p_reg_tuner_cmd_exe 0xF102 -+#define reg_tuner_cmd_exe_pos 0 -+#define reg_tuner_cmd_exe_len 1 -+#define reg_tuner_cmd_exe_lsb 0 -+#define p_reg_tuner_wdat_done 0xF102 -+#define reg_tuner_wdat_done_pos 1 -+#define reg_tuner_wdat_done_len 1 -+#define reg_tuner_wdat_done_lsb 0 -+#define p_reg_tuner_wdat_fail 0xF102 -+#define reg_tuner_wdat_fail_pos 2 -+#define reg_tuner_wdat_fail_len 1 -+#define reg_tuner_wdat_fail_lsb 0 -+#define p_reg_tuner_ofsm_i2cm_rdat_rdy 0xF102 -+#define reg_tuner_ofsm_i2cm_rdat_rdy_pos 3 -+#define reg_tuner_ofsm_i2cm_rdat_rdy_len 1 -+#define reg_tuner_ofsm_i2cm_rdat_rdy_lsb 0 -+#define p_reg_tuner_current_state 0xF102 -+#define reg_tuner_current_state_pos 4 -+#define reg_tuner_current_state_len 3 -+#define reg_tuner_current_state_lsb 0 -+#define p_reg_one_cycle_counter_tuner 0xF103 -+#define reg_one_cycle_counter_tuner_pos 0 -+#define reg_one_cycle_counter_tuner_len 8 -+#define reg_one_cycle_counter_tuner_lsb 0 -+#define p_reg_msb_lsb 0xF104 -+#define reg_msb_lsb_pos 0 -+#define reg_msb_lsb_len 1 -+#define reg_msb_lsb_lsb 0 -+#define p_reg_ofdm_rst 0xF104 -+#define p_reg_sel_thirdi2c 0xF104 -+#define reg_sel_thirdi2c_pos 2 -+#define reg_sel_thirdi2c_len 1 -+#define reg_sel_thirdi2c_lsb 0 -+#define p_reg_sel_tuner 0xF104 -+#define p_reg_ofdm_rst_en 0xF104 -+#define p_reg_sdio_cccr_v 0xF140 -+#define reg_sdio_cccr_v_pos 0 -+#define reg_sdio_cccr_v_len 4 -+#define reg_sdio_cccr_v_lsb 0 -+#define p_reg_sdio_sdio_v 0xF140 -+#define reg_sdio_sdio_v_pos 4 -+#define reg_sdio_sdio_v_len 4 -+#define reg_sdio_sdio_v_lsb 0 -+#define p_reg_sdioc_sd_v 0xF141 -+#define reg_sdioc_sd_v_pos 0 -+#define reg_sdioc_sd_v_len 4 -+#define reg_sdioc_sd_v_lsb 0 -+#define p_reg_sdioc_ior1 0xF143 -+#define reg_sdioc_ior1_pos 1 -+#define reg_sdioc_ior1_len 1 -+#define reg_sdioc_ior1_lsb 0 -+#define p_reg_sdioc_int1 0xF145 -+#define reg_sdioc_int1_pos 1 -+#define reg_sdioc_int1_len 1 -+#define reg_sdioc_int1_lsb 0 -+#define p_reg_sdioc_scsi 0xF147 -+#define reg_sdioc_scsi_pos 6 -+#define reg_sdioc_scsi_len 1 -+#define reg_sdioc_scsi_lsb 0 -+#define p_reg_sdioc_sdc 0xF148 -+#define reg_sdioc_sdc_pos 0 -+#define reg_sdioc_sdc_len 1 -+#define reg_sdioc_sdc_lsb 0 -+#define p_reg_sdioc_smb 0xF148 -+#define reg_sdioc_smb_pos 1 -+#define reg_sdioc_smb_len 1 -+#define reg_sdioc_smb_lsb 0 -+#define p_reg_sdioc_srw 0xF148 -+#define reg_sdioc_srw_pos 2 -+#define reg_sdioc_srw_len 1 -+#define reg_sdioc_srw_lsb 0 -+#define p_reg_sdioc_sbs 0xF148 -+#define reg_sdioc_sbs_pos 3 -+#define reg_sdioc_sbs_len 1 -+#define reg_sdioc_sbs_lsb 0 -+#define p_reg_sdioc_s4mi 0xF148 -+#define reg_sdioc_s4mi_pos 4 -+#define reg_sdioc_s4mi_len 1 -+#define reg_sdioc_s4mi_lsb 0 -+#define p_reg_sdioc_lsc 0xF148 -+#define reg_sdioc_lsc_pos 6 -+#define reg_sdioc_lsc_len 1 -+#define reg_sdioc_lsc_lsb 0 -+#define p_reg_sdioc_4bls 0xF148 -+#define reg_sdioc_4bls_pos 7 -+#define reg_sdioc_4bls_len 1 -+#define reg_sdioc_4bls_lsb 0 -+#define p_reg_sdioc_cis_7_0 0xF149 -+#define reg_sdioc_cis_7_0_pos 0 -+#define reg_sdioc_cis_7_0_len 8 -+#define reg_sdioc_cis_7_0_lsb 0 -+#define p_reg_sdioc_cis_15_8 0xF14A -+#define reg_sdioc_cis_15_8_pos 0 -+#define reg_sdioc_cis_15_8_len 8 -+#define reg_sdioc_cis_15_8_lsb 8 -+#define p_reg_sdioc_cis_23_16 0xF14B -+#define reg_sdioc_cis_23_16_pos 0 -+#define reg_sdioc_cis_23_16_len 8 -+#define reg_sdioc_cis_23_16_lsb 16 -+#define p_reg_sdioc_fs 0xF14D -+#define reg_sdioc_fs_pos 0 -+#define reg_sdioc_fs_len 4 -+#define reg_sdioc_fs_lsb 0 -+#define p_reg_sdioc_df 0xF14D -+#define reg_sdioc_df_pos 7 -+#define reg_sdioc_df_len 1 -+#define reg_sdioc_df_lsb 0 -+#define p_reg_sdioc_ex1 0xF14E -+#define reg_sdioc_ex1_pos 1 -+#define reg_sdioc_ex1_len 1 -+#define reg_sdioc_ex1_lsb 0 -+#define p_reg_sdioc_rf1 0xF14F -+#define reg_sdioc_rf1_pos 1 -+#define reg_sdioc_rf1_len 1 -+#define reg_sdioc_rf1_lsb 0 -+#define p_reg_sdioc_smpc 0xF152 -+#define reg_sdioc_smpc_pos 0 -+#define reg_sdioc_smpc_len 1 -+#define reg_sdioc_smpc_lsb 0 -+#define p_reg_sdioc_f1_code 0xF160 -+#define reg_sdioc_f1_code_pos 0 -+#define reg_sdioc_f1_code_len 4 -+#define reg_sdioc_f1_code_lsb 0 -+#define p_reg_sdioc_scsa 0xF160 -+#define reg_sdioc_scsa_pos 6 -+#define reg_sdioc_scsa_len 1 -+#define reg_sdioc_scsa_lsb 0 -+#define p_reg_sdioc_csa_en 0xF160 -+#define reg_sdioc_csa_en_pos 7 -+#define reg_sdioc_csa_en_len 1 -+#define reg_sdioc_csa_en_lsb 0 -+#define p_reg_sdioc_f1_ext_code 0xF161 -+#define reg_sdioc_f1_ext_code_pos 0 -+#define reg_sdioc_f1_ext_code_len 8 -+#define reg_sdioc_f1_ext_code_lsb 0 -+#define p_reg_sdioc_sps 0xF162 -+#define reg_sdioc_sps_pos 0 -+#define reg_sdioc_sps_len 1 -+#define reg_sdioc_sps_lsb 0 -+#define p_reg_sdioc_func1_cis_ptr_7_0 0xF169 -+#define reg_sdioc_func1_cis_ptr_7_0_pos 0 -+#define reg_sdioc_func1_cis_ptr_7_0_len 8 -+#define reg_sdioc_func1_cis_ptr_7_0_lsb 0 -+#define p_reg_sdioc_func1_cis_ptr_15_8 0xF16A -+#define reg_sdioc_func1_cis_ptr_15_8_pos 0 -+#define reg_sdioc_func1_cis_ptr_15_8_len 8 -+#define reg_sdioc_func1_cis_ptr_15_8_lsb 8 -+#define p_reg_sdioc_func1_cis_ptr_23_16 0xF16B -+#define reg_sdioc_func1_cis_ptr_23_16_pos 0 -+#define reg_sdioc_func1_cis_ptr_23_16_len 8 -+#define reg_sdioc_func1_cis_ptr_23_16_lsb 16 -+#define p_reg_sdio_FUNCID0_0 0xF180 -+#define reg_sdio_FUNCID0_0_pos 0 -+#define reg_sdio_FUNCID0_0_len 8 -+#define reg_sdio_FUNCID0_0_lsb 0 -+#define p_reg_sdio_FUNCID0_1 0xF181 -+#define reg_sdio_FUNCID0_1_pos 0 -+#define reg_sdio_FUNCID0_1_len 8 -+#define reg_sdio_FUNCID0_1_lsb 0 -+#define p_reg_sdio_FUNCID0_2 0xF182 -+#define reg_sdio_FUNCID0_2_pos 0 -+#define reg_sdio_FUNCID0_2_len 8 -+#define reg_sdio_FUNCID0_2_lsb 0 -+#define p_reg_sdio_FUNCID0_3 0xF183 -+#define reg_sdio_FUNCID0_3_pos 0 -+#define reg_sdio_FUNCID0_3_len 8 -+#define reg_sdio_FUNCID0_3_lsb 0 -+#define p_reg_sdio_MANFID0_0 0xF184 -+#define reg_sdio_MANFID0_0_pos 0 -+#define reg_sdio_MANFID0_0_len 8 -+#define reg_sdio_MANFID0_0_lsb 0 -+#define p_reg_sdio_MANFID0_1 0xF185 -+#define reg_sdio_MANFID0_1_pos 0 -+#define reg_sdio_MANFID0_1_len 8 -+#define reg_sdio_MANFID0_1_lsb 0 -+#define p_reg_sdio_MANFID0_2_7_0 0xF186 -+#define reg_sdio_MANFID0_2_7_0_pos 0 -+#define reg_sdio_MANFID0_2_7_0_len 8 -+#define reg_sdio_MANFID0_2_7_0_lsb 0 -+#define p_reg_sdio_MANFID0_2_15_8 0xF187 -+#define reg_sdio_MANFID0_2_15_8_pos 0 -+#define reg_sdio_MANFID0_2_15_8_len 8 -+#define reg_sdio_MANFID0_2_15_8_lsb 8 -+#define p_reg_sdio_MANFID0_4_7_0 0xF188 -+#define reg_sdio_MANFID0_4_7_0_pos 0 -+#define reg_sdio_MANFID0_4_7_0_len 8 -+#define reg_sdio_MANFID0_4_7_0_lsb 0 -+#define p_reg_sdio_MANFID0_4_15_8 0xF189 -+#define reg_sdio_MANFID0_4_15_8_pos 0 -+#define reg_sdio_MANFID0_4_15_8_len 8 -+#define reg_sdio_MANFID0_4_15_8_lsb 8 -+#define p_reg_sdio_FUNCE0_0 0xF18A -+#define reg_sdio_FUNCE0_0_pos 0 -+#define reg_sdio_FUNCE0_0_len 8 -+#define reg_sdio_FUNCE0_0_lsb 0 -+#define p_reg_sdio_FUNCE0_1 0xF18B -+#define reg_sdio_FUNCE0_1_pos 0 -+#define reg_sdio_FUNCE0_1_len 8 -+#define reg_sdio_FUNCE0_1_lsb 0 -+#define p_reg_sdio_FUNCE0_2 0xF18C -+#define reg_sdio_FUNCE0_2_pos 0 -+#define reg_sdio_FUNCE0_2_len 8 -+#define reg_sdio_FUNCE0_2_lsb 0 -+#define p_reg_sdio_FUNCE0_3_7_0 0xF18D -+#define reg_sdio_FUNCE0_3_7_0_pos 0 -+#define reg_sdio_FUNCE0_3_7_0_len 8 -+#define reg_sdio_FUNCE0_3_7_0_lsb 0 -+#define p_reg_sdio_FUNCE0_3_15_8 0xF18E -+#define reg_sdio_FUNCE0_3_15_8_pos 0 -+#define reg_sdio_FUNCE0_3_15_8_len 8 -+#define reg_sdio_FUNCE0_3_15_8_lsb 8 -+#define p_reg_sdio_FUNCE0_5 0xF18F -+#define reg_sdio_FUNCE0_5_pos 0 -+#define reg_sdio_FUNCE0_5_len 8 -+#define reg_sdio_FUNCE0_5_lsb 0 -+#define p_reg_sdio_VERS_10_0 0xF190 -+#define reg_sdio_VERS_10_0_pos 0 -+#define reg_sdio_VERS_10_0_len 8 -+#define reg_sdio_VERS_10_0_lsb 0 -+#define p_reg_sdio_VERS_10_1 0xF191 -+#define reg_sdio_VERS_10_1_pos 0 -+#define reg_sdio_VERS_10_1_len 8 -+#define reg_sdio_VERS_10_1_lsb 0 -+#define p_reg_sdio_VERS_10_2 0xF192 -+#define reg_sdio_VERS_10_2_pos 0 -+#define reg_sdio_VERS_10_2_len 8 -+#define reg_sdio_VERS_10_2_lsb 0 -+#define p_reg_sdio_VERS_10_3 0xF193 -+#define reg_sdio_VERS_10_3_pos 0 -+#define reg_sdio_VERS_10_3_len 8 -+#define reg_sdio_VERS_10_3_lsb 0 -+#define p_reg_sdio_VERS_10_4 0xF194 -+#define reg_sdio_VERS_10_4_pos 0 -+#define reg_sdio_VERS_10_4_len 8 -+#define reg_sdio_VERS_10_4_lsb 0 -+#define p_reg_sdio_VERS_10_5 0xF195 -+#define reg_sdio_VERS_10_5_pos 0 -+#define reg_sdio_VERS_10_5_len 8 -+#define reg_sdio_VERS_10_5_lsb 0 -+#define p_reg_sdio_VERS_10_6 0xF196 -+#define reg_sdio_VERS_10_6_pos 0 -+#define reg_sdio_VERS_10_6_len 8 -+#define reg_sdio_VERS_10_6_lsb 0 -+#define p_reg_sdio_VERS_10_7 0xF197 -+#define reg_sdio_VERS_10_7_pos 0 -+#define reg_sdio_VERS_10_7_len 8 -+#define reg_sdio_VERS_10_7_lsb 0 -+#define p_reg_sdio_VERS_10_8 0xF198 -+#define reg_sdio_VERS_10_8_pos 0 -+#define reg_sdio_VERS_10_8_len 8 -+#define reg_sdio_VERS_10_8_lsb 0 -+#define p_reg_sdio_VERS_10_9 0xF199 -+#define reg_sdio_VERS_10_9_pos 0 -+#define reg_sdio_VERS_10_9_len 8 -+#define reg_sdio_VERS_10_9_lsb 0 -+#define p_reg_sdio_VERS_10_A 0xF19A -+#define reg_sdio_VERS_10_A_pos 0 -+#define reg_sdio_VERS_10_A_len 8 -+#define reg_sdio_VERS_10_A_lsb 0 -+#define p_reg_sdio_VERS_10_B 0xF19B -+#define reg_sdio_VERS_10_B_pos 0 -+#define reg_sdio_VERS_10_B_len 8 -+#define reg_sdio_VERS_10_B_lsb 0 -+#define p_reg_sdio_VERS_10_C 0xF19C -+#define reg_sdio_VERS_10_C_pos 0 -+#define reg_sdio_VERS_10_C_len 8 -+#define reg_sdio_VERS_10_C_lsb 0 -+#define p_reg_sdio_VERS_10_D 0xF19D -+#define reg_sdio_VERS_10_D_pos 0 -+#define reg_sdio_VERS_10_D_len 8 -+#define reg_sdio_VERS_10_D_lsb 0 -+#define p_reg_sdio_VERS_10_E 0xF19E -+#define reg_sdio_VERS_10_E_pos 0 -+#define reg_sdio_VERS_10_E_len 8 -+#define reg_sdio_VERS_10_E_lsb 0 -+#define p_reg_sdio_VERS_10_F 0xF19F -+#define reg_sdio_VERS_10_F_pos 0 -+#define reg_sdio_VERS_10_F_len 8 -+#define reg_sdio_VERS_10_F_lsb 0 -+#define p_reg_sdio_VERS_10_10 0xF1A0 -+#define reg_sdio_VERS_10_10_pos 0 -+#define reg_sdio_VERS_10_10_len 8 -+#define reg_sdio_VERS_10_10_lsb 0 -+#define p_reg_sdio_VERS_10_11 0xF1A1 -+#define reg_sdio_VERS_10_11_pos 0 -+#define reg_sdio_VERS_10_11_len 8 -+#define reg_sdio_VERS_10_11_lsb 0 -+#define p_reg_sdio_VERS_10_12 0xF1A2 -+#define reg_sdio_VERS_10_12_pos 0 -+#define reg_sdio_VERS_10_12_len 8 -+#define reg_sdio_VERS_10_12_lsb 0 -+#define p_reg_sdio_VERS_10_13 0xF1A3 -+#define reg_sdio_VERS_10_13_pos 0 -+#define reg_sdio_VERS_10_13_len 8 -+#define reg_sdio_VERS_10_13_lsb 0 -+#define p_reg_sdio_VERS_10_14 0xF1A4 -+#define reg_sdio_VERS_10_14_pos 0 -+#define reg_sdio_VERS_10_14_len 8 -+#define reg_sdio_VERS_10_14_lsb 0 -+#define p_reg_sdio_VERS_10_15 0xF1A5 -+#define reg_sdio_VERS_10_15_pos 0 -+#define reg_sdio_VERS_10_15_len 8 -+#define reg_sdio_VERS_10_15_lsb 0 -+#define p_reg_sdio_VERS_10_16 0xF1A6 -+#define reg_sdio_VERS_10_16_pos 0 -+#define reg_sdio_VERS_10_16_len 8 -+#define reg_sdio_VERS_10_16_lsb 0 -+#define p_reg_sdio_VERS_10_17 0xF1A7 -+#define reg_sdio_VERS_10_17_pos 0 -+#define reg_sdio_VERS_10_17_len 8 -+#define reg_sdio_VERS_10_17_lsb 0 -+#define p_reg_sdio_VERS_10_18 0xF1A8 -+#define reg_sdio_VERS_10_18_pos 0 -+#define reg_sdio_VERS_10_18_len 8 -+#define reg_sdio_VERS_10_18_lsb 0 -+#define p_reg_sdio_VERS_10_19 0xF1A9 -+#define reg_sdio_VERS_10_19_pos 0 -+#define reg_sdio_VERS_10_19_len 8 -+#define reg_sdio_VERS_10_19_lsb 0 -+#define p_reg_sdio_VERS_10_1A 0xF1AA -+#define reg_sdio_VERS_10_1A_pos 0 -+#define reg_sdio_VERS_10_1A_len 8 -+#define reg_sdio_VERS_10_1A_lsb 0 -+#define p_reg_sdio_VERS_10_1B 0xF1AB -+#define reg_sdio_VERS_10_1B_pos 0 -+#define reg_sdio_VERS_10_1B_len 8 -+#define reg_sdio_VERS_10_1B_lsb 0 -+#define p_reg_sdio_VERS_10_1C 0xF1AC -+#define reg_sdio_VERS_10_1C_pos 0 -+#define reg_sdio_VERS_10_1C_len 8 -+#define reg_sdio_VERS_10_1C_lsb 0 -+#define p_reg_sdio_VERS_10_1D 0xF1AD -+#define reg_sdio_VERS_10_1D_pos 0 -+#define reg_sdio_VERS_10_1D_len 8 -+#define reg_sdio_VERS_10_1D_lsb 0 -+#define p_reg_sdio_VERS_10_1E 0xF1AE -+#define reg_sdio_VERS_10_1E_pos 0 -+#define reg_sdio_VERS_10_1E_len 8 -+#define reg_sdio_VERS_10_1E_lsb 0 -+#define p_reg_sdio_VERS_10_1F 0xF1AF -+#define reg_sdio_VERS_10_1F_pos 0 -+#define reg_sdio_VERS_10_1F_len 8 -+#define reg_sdio_VERS_10_1F_lsb 0 -+#define p_reg_sdio_VERS_10_20 0xF1B0 -+#define reg_sdio_VERS_10_20_pos 0 -+#define reg_sdio_VERS_10_20_len 8 -+#define reg_sdio_VERS_10_20_lsb 0 -+#define p_reg_sdio_VERS_10_21 0xF1B1 -+#define reg_sdio_VERS_10_21_pos 0 -+#define reg_sdio_VERS_10_21_len 8 -+#define reg_sdio_VERS_10_21_lsb 0 -+#define p_reg_sdio_VERS_10_22 0xF1B2 -+#define reg_sdio_VERS_10_22_pos 0 -+#define reg_sdio_VERS_10_22_len 8 -+#define reg_sdio_VERS_10_22_lsb 0 -+#define p_reg_sdio_VERS_10_23 0xF1B3 -+#define reg_sdio_VERS_10_23_pos 0 -+#define reg_sdio_VERS_10_23_len 8 -+#define reg_sdio_VERS_10_23_lsb 0 -+#define p_reg_sdio_VERS_10_24 0xF1B4 -+#define reg_sdio_VERS_10_24_pos 0 -+#define reg_sdio_VERS_10_24_len 8 -+#define reg_sdio_VERS_10_24_lsb 0 -+#define p_reg_sdio_VERS_10_25 0xF1B5 -+#define reg_sdio_VERS_10_25_pos 0 -+#define reg_sdio_VERS_10_25_len 8 -+#define reg_sdio_VERS_10_25_lsb 0 -+#define p_reg_sdio_VERS_10_26 0xF1B6 -+#define reg_sdio_VERS_10_26_pos 0 -+#define reg_sdio_VERS_10_26_len 8 -+#define reg_sdio_VERS_10_26_lsb 0 -+#define p_reg_sdio_VERS_10_27 0xF1B7 -+#define reg_sdio_VERS_10_27_pos 0 -+#define reg_sdio_VERS_10_27_len 8 -+#define reg_sdio_VERS_10_27_lsb 0 -+#define p_reg_sdio_END0 0xF1B8 -+#define reg_sdio_END0_pos 0 -+#define reg_sdio_END0_len 8 -+#define reg_sdio_END0_lsb 0 -+#define p_reg_sdio_FUNCID1_0 0xF1C0 -+#define reg_sdio_FUNCID1_0_pos 0 -+#define reg_sdio_FUNCID1_0_len 8 -+#define reg_sdio_FUNCID1_0_lsb 0 -+#define p_reg_sdio_FUNCID1_1 0xF1C1 -+#define reg_sdio_FUNCID1_1_pos 0 -+#define reg_sdio_FUNCID1_1_len 8 -+#define reg_sdio_FUNCID1_1_lsb 0 -+#define p_reg_sdio_FUNCID1_2 0xF1C2 -+#define reg_sdio_FUNCID1_2_pos 0 -+#define reg_sdio_FUNCID1_2_len 8 -+#define reg_sdio_FUNCID1_2_lsb 0 -+#define p_reg_sdio_FUNCID1_3 0xF1C3 -+#define reg_sdio_FUNCID1_3_pos 0 -+#define reg_sdio_FUNCID1_3_len 8 -+#define reg_sdio_FUNCID1_3_lsb 0 -+#define p_reg_sdio_FUNCE1_0 0xF1C4 -+#define reg_sdio_FUNCE1_0_pos 0 -+#define reg_sdio_FUNCE1_0_len 8 -+#define reg_sdio_FUNCE1_0_lsb 0 -+#define p_reg_sdio_FUNCE1_1 0xF1C5 -+#define reg_sdio_FUNCE1_1_pos 0 -+#define reg_sdio_FUNCE1_1_len 8 -+#define reg_sdio_FUNCE1_1_lsb 0 -+#define p_reg_sdio_FUNCE1_2 0xF1C6 -+#define reg_sdio_FUNCE1_2_pos 0 -+#define reg_sdio_FUNCE1_2_len 8 -+#define reg_sdio_FUNCE1_2_lsb 0 -+#define p_reg_sdio_FUNCE1_3 0xF1C7 -+#define reg_sdio_FUNCE1_3_pos 0 -+#define reg_sdio_FUNCE1_3_len 8 -+#define reg_sdio_FUNCE1_3_lsb 0 -+#define p_reg_sdio_FUNCE1_4 0xF1C8 -+#define reg_sdio_FUNCE1_4_pos 0 -+#define reg_sdio_FUNCE1_4_len 8 -+#define reg_sdio_FUNCE1_4_lsb 0 -+#define p_reg_sdio_FUNCE1_5_7_0 0xF1C9 -+#define reg_sdio_FUNCE1_5_7_0_pos 0 -+#define reg_sdio_FUNCE1_5_7_0_len 8 -+#define reg_sdio_FUNCE1_5_7_0_lsb 0 -+#define p_reg_sdio_FUNCE1_5_15_8 0xF1CA -+#define reg_sdio_FUNCE1_5_15_8_pos 0 -+#define reg_sdio_FUNCE1_5_15_8_len 8 -+#define reg_sdio_FUNCE1_5_15_8_lsb 8 -+#define p_reg_sdio_FUNCE1_5_23_16 0xF1CB -+#define reg_sdio_FUNCE1_5_23_16_pos 0 -+#define reg_sdio_FUNCE1_5_23_16_len 8 -+#define reg_sdio_FUNCE1_5_23_16_lsb 16 -+#define p_reg_sdio_FUNCE1_5_31_24 0xF1CC -+#define reg_sdio_FUNCE1_5_31_24_pos 0 -+#define reg_sdio_FUNCE1_5_31_24_len 8 -+#define reg_sdio_FUNCE1_5_31_24_lsb 24 -+#define p_reg_sdio_FUNCE1_9_7_0 0xF1CD -+#define reg_sdio_FUNCE1_9_7_0_pos 0 -+#define reg_sdio_FUNCE1_9_7_0_len 8 -+#define reg_sdio_FUNCE1_9_7_0_lsb 0 -+#define p_reg_sdio_FUNCE1_9_15_8 0xF1CE -+#define reg_sdio_FUNCE1_9_15_8_pos 0 -+#define reg_sdio_FUNCE1_9_15_8_len 8 -+#define reg_sdio_FUNCE1_9_15_8_lsb 8 -+#define p_reg_sdio_FUNCE1_9_23_16 0xF1CF -+#define reg_sdio_FUNCE1_9_23_16_pos 0 -+#define reg_sdio_FUNCE1_9_23_16_len 8 -+#define reg_sdio_FUNCE1_9_23_16_lsb 16 -+#define p_reg_sdio_FUNCE1_9_31_24 0xF1D0 -+#define reg_sdio_FUNCE1_9_31_24_pos 0 -+#define reg_sdio_FUNCE1_9_31_24_len 8 -+#define reg_sdio_FUNCE1_9_31_24_lsb 24 -+#define p_reg_sdio_FUNCE1_D 0xF1D1 -+#define reg_sdio_FUNCE1_D_pos 0 -+#define reg_sdio_FUNCE1_D_len 8 -+#define reg_sdio_FUNCE1_D_lsb 0 -+#define p_reg_sdio_FUNCE1_E_7_0 0xF1D2 -+#define reg_sdio_FUNCE1_E_7_0_pos 0 -+#define reg_sdio_FUNCE1_E_7_0_len 8 -+#define reg_sdio_FUNCE1_E_7_0_lsb 0 -+#define p_reg_sdio_FUNCE1_E_15_8 0xF1D3 -+#define reg_sdio_FUNCE1_E_15_8_pos 0 -+#define reg_sdio_FUNCE1_E_15_8_len 8 -+#define reg_sdio_FUNCE1_E_15_8_lsb 8 -+#define p_reg_sdio_FUNCE1_10_7_0 0xF1D4 -+#define reg_sdio_FUNCE1_10_7_0_pos 0 -+#define reg_sdio_FUNCE1_10_7_0_len 8 -+#define reg_sdio_FUNCE1_10_7_0_lsb 0 -+#define p_reg_sdio_FUNCE1_10_15_8 0xF1D5 -+#define reg_sdio_FUNCE1_10_15_8_pos 0 -+#define reg_sdio_FUNCE1_10_15_8_len 8 -+#define reg_sdio_FUNCE1_10_15_8_lsb 8 -+#define p_reg_sdio_FUNCE1_10_23_16 0xF1D6 -+#define reg_sdio_FUNCE1_10_23_16_pos 0 -+#define reg_sdio_FUNCE1_10_23_16_len 8 -+#define reg_sdio_FUNCE1_10_23_16_lsb 16 -+#define p_reg_sdio_FUNCE1_10_31_24 0xF1D7 -+#define reg_sdio_FUNCE1_10_31_24_pos 0 -+#define reg_sdio_FUNCE1_10_31_24_len 8 -+#define reg_sdio_FUNCE1_10_31_24_lsb 24 -+#define p_reg_sdio_FUNCE1_14 0xF1D8 -+#define reg_sdio_FUNCE1_14_pos 0 -+#define reg_sdio_FUNCE1_14_len 8 -+#define reg_sdio_FUNCE1_14_lsb 0 -+#define p_reg_sdio_FUNCE1_15 0xF1D9 -+#define reg_sdio_FUNCE1_15_pos 0 -+#define reg_sdio_FUNCE1_15_len 8 -+#define reg_sdio_FUNCE1_15_lsb 0 -+#define p_reg_sdio_FUNCE1_16 0xF1DA -+#define reg_sdio_FUNCE1_16_pos 0 -+#define reg_sdio_FUNCE1_16_len 8 -+#define reg_sdio_FUNCE1_16_lsb 0 -+#define p_reg_sdio_FUNCE1_17 0xF1DB -+#define reg_sdio_FUNCE1_17_pos 0 -+#define reg_sdio_FUNCE1_17_len 8 -+#define reg_sdio_FUNCE1_17_lsb 0 -+#define p_reg_sdio_FUNCE1_18 0xF1DC -+#define reg_sdio_FUNCE1_18_pos 0 -+#define reg_sdio_FUNCE1_18_len 8 -+#define reg_sdio_FUNCE1_18_lsb 0 -+#define p_reg_sdio_FUNCE1_19 0xF1DD -+#define reg_sdio_FUNCE1_19_pos 0 -+#define reg_sdio_FUNCE1_19_len 8 -+#define reg_sdio_FUNCE1_19_lsb 0 -+#define p_reg_sdio_FUNCE1_1A_7_0 0xF1DE -+#define reg_sdio_FUNCE1_1A_7_0_pos 0 -+#define reg_sdio_FUNCE1_1A_7_0_len 8 -+#define reg_sdio_FUNCE1_1A_7_0_lsb 0 -+#define p_reg_sdio_FUNCE1_1A_15_8 0xF1DF -+#define reg_sdio_FUNCE1_1A_15_8_pos 0 -+#define reg_sdio_FUNCE1_1A_15_8_len 8 -+#define reg_sdio_FUNCE1_1A_15_8_lsb 8 -+#define p_reg_sdio_FUNCE1_1C_7_0 0xF1E0 -+#define reg_sdio_FUNCE1_1C_7_0_pos 0 -+#define reg_sdio_FUNCE1_1C_7_0_len 8 -+#define reg_sdio_FUNCE1_1C_7_0_lsb 0 -+#define p_reg_sdio_FUNCE1_1C_15_8 0xF1E1 -+#define reg_sdio_FUNCE1_1C_15_8_pos 0 -+#define reg_sdio_FUNCE1_1C_15_8_len 8 -+#define reg_sdio_FUNCE1_1C_15_8_lsb 8 -+#define p_reg_sdio_FUNCE1_1E_7_0 0xF1E2 -+#define reg_sdio_FUNCE1_1E_7_0_pos 0 -+#define reg_sdio_FUNCE1_1E_7_0_len 8 -+#define reg_sdio_FUNCE1_1E_7_0_lsb 0 -+#define p_reg_sdio_FUNCE1_1E_15_8 0xF1E3 -+#define reg_sdio_FUNCE1_1E_15_8_pos 0 -+#define reg_sdio_FUNCE1_1E_15_8_len 8 -+#define reg_sdio_FUNCE1_1E_15_8_lsb 8 -+#define p_reg_sdio_FUNCE1_20_7_0 0xF1E4 -+#define reg_sdio_FUNCE1_20_7_0_pos 0 -+#define reg_sdio_FUNCE1_20_7_0_len 8 -+#define reg_sdio_FUNCE1_20_7_0_lsb 0 -+#define p_reg_sdio_FUNCE1_20_15_8 0xF1E5 -+#define reg_sdio_FUNCE1_20_15_8_pos 0 -+#define reg_sdio_FUNCE1_20_15_8_len 8 -+#define reg_sdio_FUNCE1_20_15_8_lsb 8 -+#define p_reg_sdio_FUNCE1_22_7_0 0xF1E6 -+#define reg_sdio_FUNCE1_22_7_0_pos 0 -+#define reg_sdio_FUNCE1_22_7_0_len 8 -+#define reg_sdio_FUNCE1_22_7_0_lsb 0 -+#define p_reg_sdio_FUNCE1_22_15_8 0xF1E7 -+#define reg_sdio_FUNCE1_22_15_8_pos 0 -+#define reg_sdio_FUNCE1_22_15_8_len 8 -+#define reg_sdio_FUNCE1_22_15_8_lsb 8 -+#define p_reg_sdio_FUNCE1_24_7_0 0xF1E8 -+#define reg_sdio_FUNCE1_24_7_0_pos 0 -+#define reg_sdio_FUNCE1_24_7_0_len 8 -+#define reg_sdio_FUNCE1_24_7_0_lsb 0 -+#define p_reg_sdio_FUNCE1_24_15_8 0xF1E9 -+#define reg_sdio_FUNCE1_24_15_8_pos 0 -+#define reg_sdio_FUNCE1_24_15_8_len 8 -+#define reg_sdio_FUNCE1_24_15_8_lsb 8 -+#define p_reg_sdio_FUNCE1_26_7_0 0xF1EA -+#define reg_sdio_FUNCE1_26_7_0_pos 0 -+#define reg_sdio_FUNCE1_26_7_0_len 8 -+#define reg_sdio_FUNCE1_26_7_0_lsb 0 -+#define p_reg_sdio_FUNCE1_26_15_8 0xF1EB -+#define reg_sdio_FUNCE1_26_15_8_pos 0 -+#define reg_sdio_FUNCE1_26_15_8_len 8 -+#define reg_sdio_FUNCE1_26_15_8_lsb 8 -+#define p_reg_sdio_FUNCE1_28_7_0 0xF1EC -+#define reg_sdio_FUNCE1_28_7_0_pos 0 -+#define reg_sdio_FUNCE1_28_7_0_len 8 -+#define reg_sdio_FUNCE1_28_7_0_lsb 0 -+#define p_reg_sdio_FUNCE1_28_15_8 0xF1ED -+#define reg_sdio_FUNCE1_28_15_8_pos 0 -+#define reg_sdio_FUNCE1_28_15_8_len 8 -+#define reg_sdio_FUNCE1_28_15_8_lsb 8 -+#define p_reg_sdio_FUNCE1_2A_7_0 0xF1EE -+#define reg_sdio_FUNCE1_2A_7_0_pos 0 -+#define reg_sdio_FUNCE1_2A_7_0_len 8 -+#define reg_sdio_FUNCE1_2A_7_0_lsb 0 -+#define p_reg_sdio_FUNCE1_2A_15_8 0xF1EF -+#define reg_sdio_FUNCE1_2A_15_8_pos 0 -+#define reg_sdio_FUNCE1_2A_15_8_len 8 -+#define reg_sdio_FUNCE1_2A_15_8_lsb 8 -+#define p_reg_sdio_END1 0xF1F0 -+#define reg_sdio_END1_pos 0 -+#define reg_sdio_END1_len 8 -+#define reg_sdio_END1_lsb 0 -+#define r_sdioc_tx_fifo_empty 0xF210 -+#define sdioc_tx_fifo_empty_pos 0 -+#define sdioc_tx_fifo_empty_len 1 -+#define sdioc_tx_fifo_empty_lsb 0 -+#define p_reg_sdio_53ra 0xF210 -+#define reg_sdio_53ra_pos 1 -+#define reg_sdio_53ra_len 1 -+#define reg_sdio_53ra_lsb 0 -+#define p_reg_sdioc_rd_wait_dly 0xF210 -+#define reg_sdioc_rd_wait_dly_pos 4 -+#define reg_sdioc_rd_wait_dly_len 2 -+#define reg_sdioc_rd_wait_dly_lsb 0 -+#define p_reg_write_mbx_complete 0xF211 -+#define reg_write_mbx_complete_pos 0 -+#define reg_write_mbx_complete_len 1 -+#define reg_write_mbx_complete_lsb 0 -+#define p_reg_sdioc_sw_err 0xF211 -+#define reg_sdioc_sw_err_pos 1 -+#define reg_sdioc_sw_err_len 1 -+#define reg_sdioc_sw_err_lsb 0 -+#define p_reg_sdioc_tran_dat_dly 0xF211 -+#define reg_sdioc_tran_dat_dly_pos 4 -+#define reg_sdioc_tran_dat_dly_len 3 -+#define reg_sdioc_tran_dat_dly_lsb 0 -+#define p_reg_sdioc_external_int_en 0xF212 -+#define reg_sdioc_external_int_en_pos 1 -+#define reg_sdioc_external_int_en_len 1 -+#define reg_sdioc_external_int_en_lsb 0 -+#define r_reg_sdioc_external_int 0xF212 -+#define reg_sdioc_external_int_pos 2 -+#define reg_sdioc_external_int_len 1 -+#define reg_sdioc_external_int_lsb 0 -+#define p_reg_auto_clrWB_en 0xF213 -+#define reg_auto_clrWB_en_pos 0 -+#define reg_auto_clrWB_en_len 1 -+#define reg_auto_clrWB_en_lsb 0 -+#define p_reg_sdioc_crc_s_dly 0xF213 -+#define reg_sdioc_crc_s_dly_pos 1 -+#define reg_sdioc_crc_s_dly_len 1 -+#define reg_sdioc_crc_s_dly_lsb 0 -+#define p_reg_sdioc_neg_out_sel 0xF213 -+#define reg_sdioc_neg_out_sel_pos 2 -+#define reg_sdioc_neg_out_sel_len 1 -+#define reg_sdioc_neg_out_sel_lsb 0 -+#define p_reg_sdioc_tx_fifo_rst 0xF213 -+#define reg_sdioc_tx_fifo_rst_pos 4 -+#define reg_sdioc_tx_fifo_rst_len 1 -+#define reg_sdioc_tx_fifo_rst_lsb 0 -+#define p_reg_sdioc_rx_fifo_rst 0xF213 -+#define reg_sdioc_rx_fifo_rst_pos 5 -+#define reg_sdioc_rx_fifo_rst_len 1 -+#define reg_sdioc_rx_fifo_rst_lsb 0 -+#define p_reg_sdioc_auto_rst_sm_en 0xF213 -+#define reg_sdioc_auto_rst_sm_en_pos 6 -+#define reg_sdioc_auto_rst_sm_en_len 1 -+#define reg_sdioc_auto_rst_sm_en_lsb 0 -+#define p_sdio_link_clr_Wbusy_en 0xF214 -+#define sdio_link_clr_Wbusy_en_pos 0 -+#define sdio_link_clr_Wbusy_en_len 1 -+#define sdio_link_clr_Wbusy_en_lsb 0 -+#define p_sdio_link_clr_Wbusy 0xF214 -+#define sdio_link_clr_Wbusy_pos 1 -+#define sdio_link_clr_Wbusy_len 1 -+#define sdio_link_clr_Wbusy_lsb 0 -+#define p_reg_sdioc_dbg_sel 0xF214 -+#define reg_sdioc_dbg_sel_pos 4 -+#define reg_sdioc_dbg_sel_len 4 -+#define reg_sdioc_dbg_sel_lsb 0 -+#define p_reg_sdioc_skip_ocr 0xF215 -+#define reg_sdioc_skip_ocr_pos 0 -+#define reg_sdioc_skip_ocr_len 1 -+#define reg_sdioc_skip_ocr_lsb 0 -+#define p_reg_sdioc_spi_ns 0xF215 -+#define reg_sdioc_spi_ns_pos 1 -+#define reg_sdioc_spi_ns_len 1 -+#define reg_sdioc_spi_ns_lsb 0 -+#define r_sdio_spi_mode 0xF215 -+#define sdio_spi_mode_pos 7 -+#define sdio_spi_mode_len 1 -+#define sdio_spi_mode_lsb 0 -+#define r_link_ofsm_mailbox_int 0xF402 -+#define link_ofsm_mailbox_int_pos 4 -+#define link_ofsm_mailbox_int_len 1 -+#define link_ofsm_mailbox_int_lsb 0 -+#define r_link_ofsm_dvbt_int 0xF403 -+#define link_ofsm_dvbt_int_pos 2 -+#define link_ofsm_dvbt_int_len 1 -+#define link_ofsm_dvbt_int_lsb 0 -+#define p_reg_dvbt_intsts 0xF404 -+#define reg_dvbt_intsts_pos 2 -+#define reg_dvbt_intsts_len 1 -+#define reg_dvbt_intsts_lsb 0 -+#define p_reg_link_mailbox_int 0xF405 -+#define reg_link_mailbox_int_pos 5 -+#define reg_link_mailbox_int_len 1 -+#define reg_link_mailbox_int_lsb 0 -+#define p_reg_mailbox_wptr_rst 0xF408 -+#define reg_mailbox_wptr_rst_pos 0 -+#define reg_mailbox_wptr_rst_len 1 -+#define reg_mailbox_wptr_rst_lsb 0 -+#define p_reg_link_mailbox_wptr 0xF409 -+#define reg_link_mailbox_wptr_pos 0 -+#define reg_link_mailbox_wptr_len 8 -+#define reg_link_mailbox_wptr_lsb 0 -+#define p_reg_link_mailbox_wend 0xF410 -+#define reg_link_mailbox_wend_pos 0 -+#define reg_link_mailbox_wend_len 1 -+#define reg_link_mailbox_wend_lsb 0 -+#define p_reg_rd_data_sel 0xF411 -+#define reg_rd_data_sel_pos 0 -+#define reg_rd_data_sel_len 2 -+#define reg_rd_data_sel_lsb 0 -+#define p_reg_fifo_rd_length_7_0 0xF412 -+#define reg_fifo_rd_length_7_0_pos 0 -+#define reg_fifo_rd_length_7_0_len 8 -+#define reg_fifo_rd_length_7_0_lsb 0 -+#define p_reg_fifo_rd_length_15_8 0xF413 -+#define reg_fifo_rd_length_15_8_pos 0 -+#define reg_fifo_rd_length_15_8_len 8 -+#define reg_fifo_rd_length_15_8_lsb 8 -+#define p_reg_fifo_rd_length_17_16 0xF414 -+#define reg_fifo_rd_length_17_16_pos 0 -+#define reg_fifo_rd_length_17_16_len 2 -+#define reg_fifo_rd_length_17_16_lsb 16 -+#define p_reg_rst_fifo_rptr 0xF414 -+#define reg_rst_fifo_rptr_pos 6 -+#define reg_rst_fifo_rptr_len 1 -+#define reg_rst_fifo_rptr_lsb 0 -+#define p_reg_force_sel 0xF414 -+#define reg_force_sel_pos 7 -+#define reg_force_sel_len 1 -+#define reg_force_sel_lsb 0 -+#define p_reg_fifo_rptr_7_0 0xF415 -+#define reg_fifo_rptr_7_0_pos 0 -+#define reg_fifo_rptr_7_0_len 8 -+#define reg_fifo_rptr_7_0_lsb 0 -+#define p_reg_fifo_rptr_15_8 0xF416 -+#define reg_fifo_rptr_15_8_pos 0 -+#define reg_fifo_rptr_15_8_len 8 -+#define reg_fifo_rptr_15_8_lsb 8 -+#define p_reg_fifo_rptr_17_16 0xF417 -+#define reg_fifo_rptr_17_16_pos 0 -+#define reg_fifo_rptr_17_16_len 2 -+#define reg_fifo_rptr_17_16_lsb 16 -+#define p_reg_max_package_size_7_0 0xF418 -+#define reg_max_package_size_7_0_pos 0 -+#define reg_max_package_size_7_0_len 8 -+#define reg_max_package_size_7_0_lsb 0 -+#define p_reg_max_package_size_11_8 0xF419 -+#define reg_max_package_size_11_8_pos 0 -+#define reg_max_package_size_11_8_len 4 -+#define reg_max_package_size_11_8_lsb 8 -+#define p_reg_dvbt_en 0xF41A -+#define reg_dvbt_en_pos 0 -+#define reg_dvbt_en_len 1 -+#define reg_dvbt_en_lsb 0 -+#define p_reg_dvbt_bufsize 0xF41A -+#define reg_dvbt_bufsize_pos 1 -+#define reg_dvbt_bufsize_len 1 -+#define reg_dvbt_bufsize_lsb 0 -+#define p_reg_dvbt_path 0xF41A -+#define reg_dvbt_path_pos 2 -+#define reg_dvbt_path_len 1 -+#define reg_dvbt_path_lsb 0 -+#define p_reg_dvbt_r5 0xF41A -+#define reg_dvbt_r5_pos 3 -+#define reg_dvbt_r5_len 1 -+#define reg_dvbt_r5_lsb 0 -+#define p_reg_mailbox_inten 0xF41E -+#define reg_mailbox_inten_pos 4 -+#define reg_mailbox_inten_len 1 -+#define reg_mailbox_inten_lsb 0 -+#define p_reg_dvbt_inten 0xF41F -+#define reg_dvbt_inten_pos 2 -+#define reg_dvbt_inten_len 1 -+#define reg_dvbt_inten_lsb 0 -+#define r_link_ofsm_ip_length_7_0 0xF447 -+#define link_ofsm_ip_length_7_0_pos 0 -+#define link_ofsm_ip_length_7_0_len 8 -+#define link_ofsm_ip_length_7_0_lsb 0 -+#define r_link_ofsm_ip_length_11_8 0xF448 -+#define link_ofsm_ip_length_11_8_pos 0 -+#define link_ofsm_ip_length_11_8_len 4 -+#define link_ofsm_ip_length_11_8_lsb 8 -+#define r_link_ofsm_ip_valid 0xF448 -+#define link_ofsm_ip_valid_pos 7 -+#define link_ofsm_ip_valid_len 1 -+#define link_ofsm_ip_valid_lsb 0 -+#define p_reg_spi_master 0xF600 -+#define reg_spi_master_pos 0 -+#define reg_spi_master_len 1 -+#define reg_spi_master_lsb 0 -+#define p_reg_spi_bit 0xF601 -+#define reg_spi_bit_pos 0 -+#define reg_spi_bit_len 2 -+#define reg_spi_bit_lsb 0 -+#define p_reg_spi_cs 0xF602 -+#define reg_spi_cs_pos 0 -+#define reg_spi_cs_len 1 -+#define reg_spi_cs_lsb 0 -+#define p_reg_spi_polarity 0xF602 -+#define reg_spi_polarity_pos 1 -+#define reg_spi_polarity_len 1 -+#define reg_spi_polarity_lsb 0 -+#define p_reg_spi_phase 0xF602 -+#define reg_spi_phase_pos 2 -+#define reg_spi_phase_len 1 -+#define reg_spi_phase_lsb 0 -+#define p_reg_spi_1st_byte 0xF603 -+#define reg_spi_1st_byte_pos 0 -+#define reg_spi_1st_byte_len 4 -+#define reg_spi_1st_byte_lsb 0 -+#define p_reg_spi_clk_div 0xF603 -+#define reg_spi_clk_div_pos 4 -+#define reg_spi_clk_div_len 4 -+#define reg_spi_clk_div_lsb 0 -+#define p_reg_spi_rst 0xF604 -+#define reg_spi_rst_pos 0 -+#define reg_spi_rst_len 1 -+#define reg_spi_rst_lsb 0 -+#define r_reg_spi_tx_done 0xF604 -+#define reg_spi_tx_done_pos 1 -+#define reg_spi_tx_done_len 1 -+#define reg_spi_tx_done_lsb 0 -+#define r_reg_spi_rx_done 0xF604 -+#define reg_spi_rx_done_pos 2 -+#define reg_spi_rx_done_len 1 -+#define reg_spi_rx_done_lsb 0 -+#define p_reg_spi_dbg_sel 0xF604 -+#define reg_spi_dbg_sel_pos 3 -+#define reg_spi_dbg_sel_len 1 -+#define reg_spi_dbg_sel_lsb 0 -+#define r_reg_spi_crc_err 0xF604 -+#define reg_spi_crc_err_pos 4 -+#define reg_spi_crc_err_len 4 -+#define reg_spi_crc_err_lsb 0 -+#define r_link_ofsm_usb20_mode 0xF613 -+#define link_ofsm_usb20_mode_pos 0 -+#define link_ofsm_usb20_mode_len 1 -+#define link_ofsm_usb20_mode_lsb 0 -+#define r_link_ofsm_strap_usb20_mode 0xF613 -+#define link_ofsm_strap_usb20_mode_pos 1 -+#define link_ofsm_strap_usb20_mode_len 1 -+#define link_ofsm_strap_usb20_mode_lsb 0 -+#define p_reg_link_stick_mem_end_7_0 0xF618 -+#define reg_link_stick_mem_end_7_0_pos 0 -+#define reg_link_stick_mem_end_7_0_len 8 -+#define reg_link_stick_mem_end_7_0_lsb 0 -+#define p_reg_link_stick_mem_end_15_8 0xF619 -+#define reg_link_stick_mem_end_15_8_pos 0 -+#define reg_link_stick_mem_end_15_8_len 8 -+#define reg_link_stick_mem_end_15_8_lsb 8 -+#define p_reg_ofdm_auto_write_addr_l 0xF61A -+#define reg_ofdm_auto_write_addr_l_pos 0 -+#define reg_ofdm_auto_write_addr_l_len 8 -+#define reg_ofdm_auto_write_addr_l_lsb 0 -+#define p_reg_ofdm_auto_write_addr_h 0xF61B -+#define reg_ofdm_auto_write_addr_h_pos 0 -+#define reg_ofdm_auto_write_addr_h_len 8 -+#define reg_ofdm_auto_write_addr_h_lsb 0 -+#define p_reg_link_auto_write_addr_l 0xF61C -+#define reg_link_auto_write_addr_l_pos 0 -+#define reg_link_auto_write_addr_l_len 8 -+#define reg_link_auto_write_addr_l_lsb 0 -+#define p_reg_link_auto_write_addr_h 0xF61D -+#define reg_link_auto_write_addr_h_pos 0 -+#define reg_link_auto_write_addr_h_len 8 -+#define reg_link_auto_write_addr_h_lsb 0 -+#define p_reg_mailbox_auto_write_addr 0xF61E -+#define reg_mailbox_auto_write_addr_pos 0 -+#define reg_mailbox_auto_write_addr_len 8 -+#define reg_mailbox_auto_write_addr_lsb 0 -+#define p_reg_usbmem_auto_write_addr 0xF61F -+#define reg_usbmem_auto_write_addr_pos 0 -+#define reg_usbmem_auto_write_addr_len 8 -+#define reg_usbmem_auto_write_addr_lsb 0 -+#define p_reg_mailbox_auto_read_addr 0xF620 -+#define reg_mailbox_auto_read_addr_pos 0 -+#define reg_mailbox_auto_read_addr_len 8 -+#define reg_mailbox_auto_read_addr_lsb 0 -+#define p_reg_usbmem_auto_read_addr 0xF621 -+#define reg_usbmem_auto_read_addr_pos 0 -+#define reg_usbmem_auto_read_addr_len 8 -+#define reg_usbmem_auto_read_addr_lsb 0 -+#define p_reg_auto_write_ofdm 0xF622 -+#define reg_auto_write_ofdm_pos 0 -+#define reg_auto_write_ofdm_len 1 -+#define reg_auto_write_ofdm_lsb 0 -+#define p_reg_auto_write_link 0xF622 -+#define reg_auto_write_link_pos 1 -+#define reg_auto_write_link_len 1 -+#define reg_auto_write_link_lsb 0 -+#define p_reg_auto_write_mailbox 0xF622 -+#define reg_auto_write_mailbox_pos 2 -+#define reg_auto_write_mailbox_len 1 -+#define reg_auto_write_mailbox_lsb 0 -+#define p_reg_auto_write_usbmem 0xF622 -+#define reg_auto_write_usbmem_pos 3 -+#define reg_auto_write_usbmem_len 1 -+#define reg_auto_write_usbmem_lsb 0 -+#define p_reg_auto_write_i2cm 0xF622 -+#define reg_auto_write_i2cm_pos 4 -+#define reg_auto_write_i2cm_len 1 -+#define reg_auto_write_i2cm_lsb 0 -+#define p_reg_auto_read_mailbox 0xF623 -+#define reg_auto_read_mailbox_pos 0 -+#define reg_auto_read_mailbox_len 1 -+#define reg_auto_read_mailbox_lsb 0 -+#define p_reg_auto_read_rom 0xF623 -+#define reg_auto_read_rom_pos 1 -+#define reg_auto_read_rom_len 1 -+#define reg_auto_read_rom_lsb 0 -+#define p_reg_auto_sum_l 0xF624 -+#define reg_auto_sum_l_pos 0 -+#define reg_auto_sum_l_len 8 -+#define reg_auto_sum_l_lsb 0 -+#define p_reg_auto_sum_h 0xF625 -+#define reg_auto_sum_h_pos 0 -+#define reg_auto_sum_h_len 8 -+#define reg_auto_sum_h_lsb 0 -+#define p_reg_auto_sum_to_h 0xF626 -+#define reg_auto_sum_to_h_pos 0 -+#define reg_auto_sum_to_h_len 1 -+#define reg_auto_sum_to_h_lsb 0 -+#define p_reg_auto_sum_en 0xF627 -+#define reg_auto_sum_en_pos 0 -+#define reg_auto_sum_en_len 1 -+#define reg_auto_sum_en_lsb 0 -+#define p_reg_rom_remap_begin_7_0 0xF628 -+#define reg_rom_remap_begin_7_0_pos 0 -+#define reg_rom_remap_begin_7_0_len 8 -+#define reg_rom_remap_begin_7_0_lsb 0 -+#define p_reg_rom_remap_begin_15_8 0xF629 -+#define reg_rom_remap_begin_15_8_pos 0 -+#define reg_rom_remap_begin_15_8_len 8 -+#define reg_rom_remap_begin_15_8_lsb 8 -+#define p_reg_rom_remap_end_7_0 0xF62A -+#define reg_rom_remap_end_7_0_pos 0 -+#define reg_rom_remap_end_7_0_len 8 -+#define reg_rom_remap_end_7_0_lsb 0 -+#define p_reg_rom_remap_end_15_8 0xF62B -+#define reg_rom_remap_end_15_8_pos 0 -+#define reg_rom_remap_end_15_8_len 8 -+#define reg_rom_remap_end_15_8_lsb 8 -+#define p_reg_rom_remap_delta_7_0 0xF62C -+#define reg_rom_remap_delta_7_0_pos 0 -+#define reg_rom_remap_delta_7_0_len 8 -+#define reg_rom_remap_delta_7_0_lsb 0 -+#define p_reg_rom_remap_delta_15_8 0xF62D -+#define reg_rom_remap_delta_15_8_pos 0 -+#define reg_rom_remap_delta_15_8_len 8 -+#define reg_rom_remap_delta_15_8_lsb 8 -+#define p_reg_rom_remap_en 0xF62E -+#define reg_rom_remap_en_pos 0 -+#define reg_rom_remap_en_len 1 -+#define reg_rom_remap_en_lsb 0 -+#define p_reg_rom_remap_ofdm 0xF62E -+#define reg_rom_remap_ofdm_pos 1 -+#define reg_rom_remap_ofdm_len 1 -+#define reg_rom_remap_ofdm_lsb 0 -+#define p_reg_link_cpu_reset 0xF62F -+#define reg_link_cpu_reset_pos 0 -+#define reg_link_cpu_reset_len 1 -+#define reg_link_cpu_reset_lsb 0 -+#define p_reg_i2cm_auto_write_addr 0xF630 -+#define reg_i2cm_auto_write_addr_pos 0 -+#define reg_i2cm_auto_write_addr_len 8 -+#define reg_i2cm_auto_write_addr_lsb 0 -+#define p_reg_link_bank_float_en 0xF631 -+#define reg_link_bank_float_en_pos 0 -+#define reg_link_bank_float_en_len 1 -+#define reg_link_bank_float_en_lsb 0 -+#define p_reg_link_bank_float_start 0xF632 -+#define reg_link_bank_float_start_pos 0 -+#define reg_link_bank_float_start_len 8 -+#define reg_link_bank_float_start_lsb 0 -+#define p_reg_link_bank_float_stop 0xF633 -+#define reg_link_bank_float_stop_pos 0 -+#define reg_link_bank_float_stop_len 8 -+#define reg_link_bank_float_stop_lsb 0 -+#define p_reg_rom_auto_read_addr_7_0 0xF638 -+#define reg_rom_auto_read_addr_7_0_pos 0 -+#define reg_rom_auto_read_addr_7_0_len 8 -+#define reg_rom_auto_read_addr_7_0_lsb 0 -+#define p_reg_rom_auto_read_addr_15_8 0xF639 -+#define reg_rom_auto_read_addr_15_8_pos 0 -+#define reg_rom_auto_read_addr_15_8_len 8 -+#define reg_rom_auto_read_addr_15_8_lsb 8 -+#define p_reg_link_ofsm_dummy_7_0 0xF640 -+#define reg_link_ofsm_dummy_7_0_pos 0 -+#define reg_link_ofsm_dummy_7_0_len 8 -+#define reg_link_ofsm_dummy_7_0_lsb 0 -+#define p_reg_link_ofsm_dummy_15_8 0xF641 -+#define reg_link_ofsm_dummy_15_8_pos 0 -+#define reg_link_ofsm_dummy_15_8_len 8 -+#define reg_link_ofsm_dummy_15_8_lsb 8 -+#define p_reg_link_ofsm_dummy_23_16 0xF642 -+#define reg_link_ofsm_dummy_23_16_pos 0 -+#define reg_link_ofsm_dummy_23_16_len 8 -+#define reg_link_ofsm_dummy_23_16_lsb 16 -+#define p_reg_link_ofsm_dummy_31_24 0xF643 -+#define reg_link_ofsm_dummy_31_24_pos 0 -+#define reg_link_ofsm_dummy_31_24_len 8 -+#define reg_link_ofsm_dummy_31_24_lsb 24 -+#define p_reg_link_ofsm_dummy_39_32 0xF644 -+#define reg_link_ofsm_dummy_39_32_pos 0 -+#define reg_link_ofsm_dummy_39_32_len 8 -+#define reg_link_ofsm_dummy_39_32_lsb 32 -+#define p_reg_link_ofsm_dummy_47_40 0xF645 -+#define reg_link_ofsm_dummy_47_40_pos 0 -+#define reg_link_ofsm_dummy_47_40_len 8 -+#define reg_link_ofsm_dummy_47_40_lsb 40 -+#define p_reg_link_ofsm_dummy_55_48 0xF646 -+#define reg_link_ofsm_dummy_55_48_pos 0 -+#define reg_link_ofsm_dummy_55_48_len 8 -+#define reg_link_ofsm_dummy_55_48_lsb 48 -+#define p_reg_link_ofsm_dummy_63_56 0xF647 -+#define reg_link_ofsm_dummy_63_56_pos 0 -+#define reg_link_ofsm_dummy_63_56_len 8 -+#define reg_link_ofsm_dummy_63_56_lsb 56 -+#define p_reg_link_ofsm_dummy_71_64 0xF648 -+#define reg_link_ofsm_dummy_71_64_pos 0 -+#define reg_link_ofsm_dummy_71_64_len 8 -+#define reg_link_ofsm_dummy_71_64_lsb 64 -+#define p_reg_link_ofsm_dummy_79_72 0xF649 -+#define reg_link_ofsm_dummy_79_72_pos 0 -+#define reg_link_ofsm_dummy_79_72_len 8 -+#define reg_link_ofsm_dummy_79_72_lsb 72 -+#define p_reg_sdio_mode 0xF66F -+#define reg_sdio_mode_pos 0 -+#define reg_sdio_mode_len 1 -+#define reg_sdio_mode_lsb 0 -+#define p_reg_lnk2ofdm_data_7_0 0xF6A0 -+#define reg_lnk2ofdm_data_7_0_pos 0 -+#define reg_lnk2ofdm_data_7_0_len 8 -+#define reg_lnk2ofdm_data_7_0_lsb 0 -+#define p_reg_lnk2ofdm_data_15_8 0xF6A1 -+#define reg_lnk2ofdm_data_15_8_pos 0 -+#define reg_lnk2ofdm_data_15_8_len 8 -+#define reg_lnk2ofdm_data_15_8_lsb 8 -+#define p_reg_lnk2ofdm_data_23_16 0xF6A2 -+#define reg_lnk2ofdm_data_23_16_pos 0 -+#define reg_lnk2ofdm_data_23_16_len 8 -+#define reg_lnk2ofdm_data_23_16_lsb 16 -+#define p_reg_lnk2ofdm_data_31_24 0xF6A3 -+#define reg_lnk2ofdm_data_31_24_pos 0 -+#define reg_lnk2ofdm_data_31_24_len 8 -+#define reg_lnk2ofdm_data_31_24_lsb 24 -+#define p_reg_lnk2ofdm_data_39_32 0xF6A4 -+#define reg_lnk2ofdm_data_39_32_pos 0 -+#define reg_lnk2ofdm_data_39_32_len 8 -+#define reg_lnk2ofdm_data_39_32_lsb 32 -+#define p_reg_lnk2ofdm_data_47_40 0xF6A5 -+#define reg_lnk2ofdm_data_47_40_pos 0 -+#define reg_lnk2ofdm_data_47_40_len 8 -+#define reg_lnk2ofdm_data_47_40_lsb 40 -+#define p_reg_lnk2ofdm_data_55_48 0xF6A6 -+#define reg_lnk2ofdm_data_55_48_pos 0 -+#define reg_lnk2ofdm_data_55_48_len 8 -+#define reg_lnk2ofdm_data_55_48_lsb 48 -+#define p_reg_lnk2ofdm_data_63_56 0xF6A7 -+#define reg_lnk2ofdm_data_63_56_pos 0 -+#define reg_lnk2ofdm_data_63_56_len 8 -+#define reg_lnk2ofdm_data_63_56_lsb 56 -+#define p_reg_ofdmtolnk_data_7_0 0xF6A8 -+#define reg_ofdmtolnk_data_7_0_pos 0 -+#define reg_ofdmtolnk_data_7_0_len 8 -+#define reg_ofdmtolnk_data_7_0_lsb 0 -+#define p_reg_ofdmtolnk_data_15_8 0xF6A9 -+#define reg_ofdmtolnk_data_15_8_pos 0 -+#define reg_ofdmtolnk_data_15_8_len 8 -+#define reg_ofdmtolnk_data_15_8_lsb 8 -+#define p_reg_ofdmtolnk_data_23_16 0xF6AA -+#define reg_ofdmtolnk_data_23_16_pos 0 -+#define reg_ofdmtolnk_data_23_16_len 8 -+#define reg_ofdmtolnk_data_23_16_lsb 16 -+#define p_reg_ofdmtolnk_data_31_24 0xF6AB -+#define reg_ofdmtolnk_data_31_24_pos 0 -+#define reg_ofdmtolnk_data_31_24_len 8 -+#define reg_ofdmtolnk_data_31_24_lsb 24 -+#define p_reg_ofdmtolnk_data_39_32 0xF6AC -+#define reg_ofdmtolnk_data_39_32_pos 0 -+#define reg_ofdmtolnk_data_39_32_len 8 -+#define reg_ofdmtolnk_data_39_32_lsb 32 -+#define p_reg_ofdmtolnk_data_47_40 0xF6AD -+#define reg_ofdmtolnk_data_47_40_pos 0 -+#define reg_ofdmtolnk_data_47_40_len 8 -+#define reg_ofdmtolnk_data_47_40_lsb 40 -+#define p_reg_ofdmtolnk_data_55_48 0xF6AE -+#define reg_ofdmtolnk_data_55_48_pos 0 -+#define reg_ofdmtolnk_data_55_48_len 8 -+#define reg_ofdmtolnk_data_55_48_lsb 48 -+#define p_reg_ofdmtolnk_data_63_56 0xF6AF -+#define reg_ofdmtolnk_data_63_56_pos 0 -+#define reg_ofdmtolnk_data_63_56_len 8 -+#define reg_ofdmtolnk_data_63_56_lsb 56 -+#define p_reg_mon51_flag 0xF6B0 -+#define reg_mon51_flag_pos 0 -+#define reg_mon51_flag_len 1 -+#define reg_mon51_flag_lsb 0 -+#define p_reg_force_mon51 0xF6B1 -+#define reg_force_mon51_pos 0 -+#define reg_force_mon51_len 1 -+#define reg_force_mon51_lsb 0 -+#define p_reg_which_cpu 0xF6B2 -+#define reg_which_cpu_pos 0 -+#define reg_which_cpu_len 1 -+#define reg_which_cpu_lsb 0 -+#define p_reg_program_ofdm_code_ready 0xF6B3 -+#define reg_program_ofdm_code_ready_pos 0 -+#define reg_program_ofdm_code_ready_len 1 -+#define reg_program_ofdm_code_ready_lsb 0 -+#define p_reg_link_wr_ofdm_en 0xF6B3 -+#define reg_link_wr_ofdm_en_pos 1 -+#define reg_link_wr_ofdm_en_len 1 -+#define reg_link_wr_ofdm_en_lsb 0 -+#define p_reg_i2c_mode 0xF6B4 -+#define reg_i2c_mode_pos 0 -+#define reg_i2c_mode_len 1 -+#define reg_i2c_mode_lsb 0 -+#define p_reg_sw_reset_sdio 0xF6B4 -+#define reg_sw_reset_sdio_pos 1 -+#define reg_sw_reset_sdio_len 1 -+#define reg_sw_reset_sdio_lsb 0 -+#define p_reg_debug_mpefec_sel 0xF6B4 -+#define reg_debug_mpefec_sel_pos 2 -+#define reg_debug_mpefec_sel_len 1 -+#define reg_debug_mpefec_sel_lsb 0 -+#define p_reg_lnk_dynamic_clk 0xF6B4 -+#define reg_lnk_dynamic_clk_pos 3 -+#define reg_lnk_dynamic_clk_len 1 -+#define reg_lnk_dynamic_clk_lsb 0 -+#define p_reg_lnk_free_clk 0xF6B4 -+#define reg_lnk_free_clk_pos 4 -+#define reg_lnk_free_clk_len 1 -+#define reg_lnk_free_clk_lsb 0 -+#define p_reg_i2c_sample_rate_up_en 0xF6B4 -+#define reg_i2c_sample_rate_up_en_pos 5 -+#define reg_i2c_sample_rate_up_en_len 1 -+#define reg_i2c_sample_rate_up_en_lsb 0 -+#define p_reg_i2c_start_patch 0xF6B4 -+#define reg_i2c_start_patch_pos 6 -+#define reg_i2c_start_patch_len 1 -+#define reg_i2c_start_patch_lsb 0 -+#define p_reg_link_i2cs_msb 0xF6B5 -+#define reg_link_i2cs_msb_pos 1 -+#define reg_link_i2cs_msb_len 1 -+#define reg_link_i2cs_msb_lsb 0 -+#define p_reg_link_ofsm_dbg_en 0xF6B5 -+#define reg_link_ofsm_dbg_en_pos 4 -+#define reg_link_ofsm_dbg_en_len 1 -+#define reg_link_ofsm_dbg_en_lsb 0 -+#define p_reg_link_i2c_dbg_sel 0xF6B5 -+#define reg_link_i2c_dbg_sel_pos 5 -+#define reg_link_i2c_dbg_sel_len 1 -+#define reg_link_i2c_dbg_sel_lsb 0 -+#define p_reg_fast_slow_train 0xF6DD -+#define p_reg_lnk2ofdm_int 0xF6DE -+#define reg_lnk2ofdm_int_pos 0 -+#define reg_lnk2ofdm_int_len 1 -+#define reg_lnk2ofdm_int_lsb 0 -+#define p_reg_ofdm2lnk_int 0xF6DF -+#define reg_ofdm2lnk_int_pos 0 -+#define reg_ofdm2lnk_int_len 1 -+#define reg_ofdm2lnk_int_lsb 0 -+#define p_reg_load_ofdm_reg 0xF6E4 -+#define p_link_ofsm_cmd_reg 0xF6EA -+#define link_ofsm_cmd_reg_pos 0 -+#define link_ofsm_cmd_reg_len 8 -+#define link_ofsm_cmd_reg_lsb 0 -+#define p_link_ofsm_addr_reg_h 0xF6EB -+#define link_ofsm_addr_reg_h_pos 0 -+#define link_ofsm_addr_reg_h_len 8 -+#define link_ofsm_addr_reg_h_lsb 0 -+#define p_link_ofsm_addr_reg_l 0xF6EC -+#define link_ofsm_addr_reg_l_pos 0 -+#define link_ofsm_addr_reg_l_len 8 -+#define link_ofsm_addr_reg_l_lsb 0 -+#define p_link_ofsm_data_reg_0 0xF6ED -+#define link_ofsm_data_reg_0_pos 0 -+#define link_ofsm_data_reg_0_len 8 -+#define link_ofsm_data_reg_0_lsb 0 -+#define p_link_ofsm_data_reg_1 0xF6EE -+#define link_ofsm_data_reg_1_pos 0 -+#define link_ofsm_data_reg_1_len 8 -+#define link_ofsm_data_reg_1_lsb 0 -+#define p_link_ofsm_data_reg_2 0xF6EF -+#define link_ofsm_data_reg_2_pos 0 -+#define link_ofsm_data_reg_2_len 8 -+#define link_ofsm_data_reg_2_lsb 0 -+#define p_link_ofsm_data_reg_3 0xF6F0 -+#define link_ofsm_data_reg_3_pos 0 -+#define link_ofsm_data_reg_3_len 8 -+#define link_ofsm_data_reg_3_lsb 0 -+#define p_link_ofsm_data_reg_4 0xF6F1 -+#define link_ofsm_data_reg_4_pos 0 -+#define link_ofsm_data_reg_4_len 8 -+#define link_ofsm_data_reg_4_lsb 0 -+#define p_link_ofsm_data_reg_5 0xF6F2 -+#define link_ofsm_data_reg_5_pos 0 -+#define link_ofsm_data_reg_5_len 8 -+#define link_ofsm_data_reg_5_lsb 0 -+#define p_link_ofsm_data_reg_6 0xF6F3 -+#define link_ofsm_data_reg_6_pos 0 -+#define link_ofsm_data_reg_6_len 8 -+#define link_ofsm_data_reg_6_lsb 0 -+#define p_link_ofsm_data_reg_7 0xF6F4 -+#define link_ofsm_data_reg_7_pos 0 -+#define link_ofsm_data_reg_7_len 8 -+#define link_ofsm_data_reg_7_lsb 0 -+#define p_link_ofsm_data_reg_8 0xF6F5 -+#define link_ofsm_data_reg_8_pos 0 -+#define link_ofsm_data_reg_8_len 8 -+#define link_ofsm_data_reg_8_lsb 0 -+#define p_link_ofsm_data_reg_9 0xF6F6 -+#define link_ofsm_data_reg_9_pos 0 -+#define link_ofsm_data_reg_9_len 8 -+#define link_ofsm_data_reg_9_lsb 0 -+#define p_link_ofsm_data_reg_10 0xF6F7 -+#define link_ofsm_data_reg_10_pos 0 -+#define link_ofsm_data_reg_10_len 8 -+#define link_ofsm_data_reg_10_lsb 0 -+#define p_link_ofsm_data_reg_11 0xF6F8 -+#define link_ofsm_data_reg_11_pos 0 -+#define link_ofsm_data_reg_11_len 8 -+#define link_ofsm_data_reg_11_lsb 0 -+#define p_link_ofsm_data_reg_12 0xF6F9 -+#define link_ofsm_data_reg_12_pos 0 -+#define link_ofsm_data_reg_12_len 8 -+#define link_ofsm_data_reg_12_lsb 0 -+#define p_link_ofsm_data_reg_13 0xF6FA -+#define link_ofsm_data_reg_13_pos 0 -+#define link_ofsm_data_reg_13_len 8 -+#define link_ofsm_data_reg_13_lsb 0 -+#define p_link_ofsm_data_reg_14 0xF6FB -+#define link_ofsm_data_reg_14_pos 0 -+#define link_ofsm_data_reg_14_len 8 -+#define link_ofsm_data_reg_14_lsb 0 -+#define p_link_ofsm_data_reg_15 0xF6FC -+#define link_ofsm_data_reg_15_pos 0 -+#define link_ofsm_data_reg_15_len 8 -+#define link_ofsm_data_reg_15_lsb 0 -+#define p_reg_debug_mux 0xF6FE -+#define reg_debug_mux_pos 3 -+#define reg_debug_mux_len 1 -+#define reg_debug_mux_lsb 0 -+#define p_reg_top_gpioon0 0xF6FF -+#define reg_top_gpioon0_pos 0 -+#define reg_top_gpioon0_len 1 -+#define reg_top_gpioon0_lsb 0 -+#define p_reg_p_dmb_phy_is_dvb 0xDC31 -+#define reg_p_dmb_phy_is_dvb_pos 0 -+#define reg_p_dmb_phy_is_dvb_len 1 -+#define reg_p_dmb_phy_is_dvb_lsb 0 -+#define p_reg_p_dmb_xt_reset 0xDC32 -+#define reg_p_dmb_xt_reset_pos 0 -+#define reg_p_dmb_xt_reset_len 1 -+#define reg_p_dmb_xt_reset_lsb 0 -+#define p_reg_p_dmb_sw_reset 0xDC33 -+#define reg_p_dmb_sw_reset_pos 0 -+#define reg_p_dmb_sw_reset_len 1 -+#define reg_p_dmb_sw_reset_lsb 0 -+ -+#endif --- -1.7.5.4 - diff --git a/meta-openpli/recipes-linux/linux/linux-etxx00/em28xx-dvb-stop-URBs-when-stopping-the-streaming.patch b/meta-openpli/recipes-linux/linux/linux-etxx00/em28xx-dvb-stop-URBs-when-stopping-the-streaming.patch deleted file mode 100644 index eac9d080d0..0000000000 --- a/meta-openpli/recipes-linux/linux/linux-etxx00/em28xx-dvb-stop-URBs-when-stopping-the-streaming.patch +++ /dev/null @@ -1,87 +0,0 @@ -em28xx-dvb: stop URBs when stopping the streaming - -Stop the URBs in em28xx_stop_streaming(), so that em28xx_irq_callback() -cannot be called after the streaming has stopped. - -This should eliminate the crashes reported by Antti Palosaari and the warnings -reported by Andy Furniss. - -Signed-off-by: Gianluca Gennari ---- - drivers/media/video/em28xx/em28xx-core.c | 26 +++++++++++++++++++++++++- - drivers/media/video/em28xx/em28xx-dvb.c | 2 +- - drivers/media/video/em28xx/em28xx.h | 1 + - 3 files changed, 27 insertions(+), 2 deletions(-) - -diff --git a/drivers/media/video/em28xx/em28xx-core.c b/drivers/media/video/em28xx/em28xx-core.c -index 53a9fb9..cbbe399 100644 ---- a/drivers/media/video/em28xx/em28xx-core.c -+++ b/drivers/media/video/em28xx/em28xx-core.c -@@ -666,7 +666,6 @@ int em28xx_capture_start(struct em28xx *dev, int start) - - return rc; - } --EXPORT_SYMBOL_GPL(em28xx_capture_start); - - int em28xx_vbi_supported(struct em28xx *dev) - { -@@ -1008,6 +1007,31 @@ void em28xx_uninit_isoc(struct em28xx *dev, enum em28xx_mode mode) - EXPORT_SYMBOL_GPL(em28xx_uninit_isoc); - - /* -+ * Stop URBs -+ */ -+void em28xx_stop_urbs(struct em28xx *dev) -+{ -+ int i; -+ struct urb *urb; -+ struct em28xx_usb_isoc_bufs *isoc_bufs = &dev->isoc_ctl.digital_bufs; -+ -+ em28xx_isocdbg("em28xx: called em28xx_stop_urbs\n"); -+ -+ for (i = 0; i < isoc_bufs->num_bufs; i++) { -+ urb = isoc_bufs->urb[i]; -+ if (urb) { -+ if (!irqs_disabled()) -+ usb_kill_urb(urb); -+ else -+ usb_unlink_urb(urb); -+ } -+ } -+ -+ em28xx_capture_start(dev, 0); -+} -+EXPORT_SYMBOL_GPL(em28xx_stop_urbs); -+ -+/* - * Allocate URBs - */ - int em28xx_alloc_isoc(struct em28xx *dev, enum em28xx_mode mode, -diff --git a/drivers/media/video/em28xx/em28xx-dvb.c b/drivers/media/video/em28xx/em28xx-dvb.c -index 21f3e55..ea3810f 100644 ---- a/drivers/media/video/em28xx/em28xx-dvb.c -+++ b/drivers/media/video/em28xx/em28xx-dvb.c -@@ -183,7 +183,7 @@ static int em28xx_stop_streaming(struct em28xx_dvb *dvb) - { - struct em28xx *dev = dvb->adapter.priv; - -- em28xx_capture_start(dev, 0); -+ em28xx_stop_urbs(dev); - - em28xx_set_mode(dev, EM28XX_SUSPEND); - -diff --git a/drivers/media/video/em28xx/em28xx.h b/drivers/media/video/em28xx/em28xx.h -index 2868b19..286b9f8 100644 ---- a/drivers/media/video/em28xx/em28xx.h -+++ b/drivers/media/video/em28xx/em28xx.h -@@ -695,6 +695,7 @@ int em28xx_init_isoc(struct em28xx *dev, enum em28xx_mode mode, - int max_packets, int num_bufs, int max_pkt_size, - int (*isoc_copy) (struct em28xx *dev, struct urb *urb)); - void em28xx_uninit_isoc(struct em28xx *dev, enum em28xx_mode mode); -+void em28xx_stop_urbs(struct em28xx *dev); - int em28xx_isoc_dvb_max_packetsize(struct em28xx *dev); - int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode); - int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio); --- -1.7.5.4 - diff --git a/meta-openpli/recipes-linux/linux/linux-etxx00/et4x00/defconfig b/meta-openpli/recipes-linux/linux/linux-etxx00/et4x00/defconfig index 3f54251dc2..61f3b30d60 100644 --- a/meta-openpli/recipes-linux/linux/linux-etxx00/et4x00/defconfig +++ b/meta-openpli/recipes-linux/linux/linux-etxx00/et4x00/defconfig @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/mips 3.4.3 Kernel Configuration +# Linux/mips 3.6.0 Kernel Configuration # CONFIG_MIPS=y @@ -20,6 +20,7 @@ CONFIG_BRCMSTB=y # CONFIG_LANTIQ is not set # CONFIG_LASAT is not set # CONFIG_MACH_LOONGSON is not set +# CONFIG_MACH_LOONGSON1 is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SIM is not set # CONFIG_NEC_MARKEINS is not set @@ -152,8 +153,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_BOOT_RAW=y CONFIG_CEVT_R4K_LIB=y @@ -214,12 +213,10 @@ CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_CROSS_MEMORY_ATTACH is not set CONFIG_NEED_PER_CPU_KM=y # CONFIG_CLEANCACHE is not set -CONFIG_TICK_ONESHOT=y -# CONFIG_NO_HZ is not set -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_FRONTSWAP is not set # CONFIG_HZ_48 is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_128 is not set @@ -239,6 +236,7 @@ CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" CONFIG_HAVE_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y # # General setup @@ -266,7 +264,18 @@ CONFIG_HAVE_GENERIC_HARDIRQS=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_FORCED_THREADING=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_CMOS_UPDATE=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y # # RCU Subsystem @@ -311,7 +320,6 @@ CONFIG_PERF_USE_VMALLOC=y # Kernel Performance Events And Counters # # CONFIG_PERF_EVENTS is not set -# CONFIG_PERF_COUNTERS is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_COMPAT_BRK=y CONFIG_SLAB=y @@ -324,8 +332,11 @@ CONFIG_HAVE_OPROFILE=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_DMA_ATTRS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_HAVE_CLK=y CONFIG_HAVE_DMA_API_DEBUG=y CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y # # GCOV-based kernel profiling @@ -435,9 +446,12 @@ CONFIG_HIBERNATE_CALLBACKS=y CONFIG_HIBERNATION=y CONFIG_PM_STD_PARTITION="" CONFIG_PM_SLEEP=y +# CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_WAKELOCKS is not set CONFIG_PM_RUNTIME=y CONFIG_PM=y # CONFIG_PM_DEBUG is not set +CONFIG_PM_CLK=y CONFIG_NET=y # @@ -447,6 +461,7 @@ CONFIG_PACKET=y CONFIG_UNIX=y # CONFIG_UNIX_DIAG is not set CONFIG_XFRM=y +CONFIG_XFRM_ALGO=m # CONFIG_XFRM_USER is not set # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set @@ -528,6 +543,7 @@ CONFIG_NETFILTER_XTABLES=m # Xtables targets # # CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_HMARK is not set # CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set # CONFIG_NETFILTER_XT_TARGET_LED is not set # CONFIG_NETFILTER_XT_TARGET_LOG is not set @@ -594,7 +610,6 @@ CONFIG_IP_NF_TARGET_REJECT=m # IPv6: Netfilter Configuration # # CONFIG_NF_DEFRAG_IPV6 is not set -# CONFIG_IP6_NF_QUEUE is not set CONFIG_IP6_NF_IPTABLES=m # CONFIG_IP6_NF_MATCH_AH is not set # CONFIG_IP6_NF_MATCH_EUI64 is not set @@ -624,12 +639,12 @@ CONFIG_IP6_NF_TARGET_REJECT=m # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set -# CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set # CONFIG_PHONET is not set # CONFIG_IEEE802154 is not set # CONFIG_NET_SCHED is not set # CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y # CONFIG_BATMAN_ADV is not set # CONFIG_OPENVSWITCH is not set CONFIG_BQL=y @@ -658,6 +673,7 @@ CONFIG_BT_HCIUART_H4=y CONFIG_BT_HCIUART_BCSP=y # CONFIG_BT_HCIUART_ATH3K is not set CONFIG_BT_HCIUART_LL=y +# CONFIG_BT_HCIUART_3WIRE is not set CONFIG_BT_HCIBCM203X=m CONFIG_BT_HCIBPA10X=m CONFIG_BT_HCIBFUSB=m @@ -675,10 +691,10 @@ CONFIG_CFG80211=y # CONFIG_NL80211_TESTMODE is not set # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set # CONFIG_CFG80211_REG_DEBUG is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set CONFIG_CFG80211_DEFAULT_PS=y # CONFIG_CFG80211_INTERNAL_REGDB is not set CONFIG_CFG80211_WEXT=y -CONFIG_WIRELESS_EXT_SYSFS=y CONFIG_LIB80211=y CONFIG_LIB80211_CRYPT_WEP=m CONFIG_LIB80211_CRYPT_CCMP=m @@ -693,6 +709,7 @@ CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" # CONFIG_MAC80211_MESH is not set CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_MESSAGE_TRACING is not set # CONFIG_MAC80211_DEBUG_MENU is not set # CONFIG_WIMAX is not set CONFIG_RFKILL=y @@ -782,8 +799,7 @@ CONFIG_MTD_PHYSMAP=y # Self-contained MTD device drivers # # CONFIG_MTD_DATAFLASH is not set -CONFIG_MTD_M25P80=y -CONFIG_M25PXX_USE_FAST_READ=y +# CONFIG_MTD_M25P80 is not set # CONFIG_MTD_SST25L is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set @@ -820,7 +836,6 @@ CONFIG_MTD_UBI=y CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MTD_UBI_BEB_RESERVE=1 # CONFIG_MTD_UBI_GLUEBI is not set -# CONFIG_MTD_UBI_DEBUG is not set # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set @@ -847,6 +862,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # # CONFIG_SENSORS_LIS3LV02D is not set # CONFIG_AD525X_DPOT is not set +# CONFIG_ATMEL_PWM is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_APDS9802ALS is not set @@ -859,7 +875,8 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_HMC6352 is not set # CONFIG_DS1682 is not set # CONFIG_TI_DAC7512 is not set -# CONFIG_BMP085 is not set +# CONFIG_BMP085_I2C is not set +# CONFIG_BMP085_SPI is not set # CONFIG_USB_SWITCH_FSA9480 is not set # CONFIG_C2PORT is not set @@ -911,7 +928,6 @@ CONFIG_CHR_DEV_SG=y # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set # CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m # # SCSI Transports @@ -998,6 +1014,7 @@ CONFIG_NET_VENDOR_BROADCOM=y # CONFIG_NET_VENDOR_SEEQ is not set # CONFIG_NET_VENDOR_SMSC is not set # CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_PHYLIB is not set # CONFIG_MICREL_KS8995MA is not set CONFIG_PPP=m @@ -1039,7 +1056,6 @@ CONFIG_ATH9K_COMMON=m CONFIG_ATH9K_BTCOEX_SUPPORT=y CONFIG_ATH9K=m # CONFIG_ATH9K_AHB is not set -# CONFIG_ATH9K_DFS_CERTIFIED is not set CONFIG_ATH9K_RATE_CONTROL=y CONFIG_ATH9K_HTC=m CONFIG_CARL9170=m @@ -1053,7 +1069,7 @@ CONFIG_ATH6KL_USB=m # CONFIG_B43LEGACY is not set CONFIG_BRCMUTIL=m CONFIG_BRCMFMAC=m -CONFIG_BRCMFMAC_USB=y +# CONFIG_BRCMFMAC_USB is not set # CONFIG_BRCMDBG is not set CONFIG_HOSTAP=m CONFIG_HOSTAP_FIRMWARE=y @@ -1083,12 +1099,17 @@ CONFIG_RT2X00_LIB_CRYPTO=y CONFIG_RT2X00_LIB_LEDS=y # CONFIG_RT2X00_DEBUG is not set # CONFIG_RTL8192CU is not set +CONFIG_WL_TI=y CONFIG_WL1251=m # CONFIG_WL1251_SPI is not set -# CONFIG_WL12XX_MENU is not set +CONFIG_WL12XX=m +CONFIG_WL18XX=m +CONFIG_WLCORE=m +# CONFIG_WLCORE_SPI is not set CONFIG_ZD1211RW=m # CONFIG_ZD1211RW_DEBUG is not set CONFIG_MWIFIEX=y +CONFIG_MWIFIEX_USB=m # # Enable WiMAX (Networking options) to see the WiMAX drivers @@ -1103,6 +1124,7 @@ CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set CONFIG_INPUT_POLLDEV=m # CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set # # Userland interfaces @@ -1128,11 +1150,13 @@ CONFIG_INPUT_KEYBOARD=y # CONFIG_KEYBOARD_TCA6416 is not set # CONFIG_KEYBOARD_TCA8418 is not set # CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set # CONFIG_KEYBOARD_MAX7359 is not set # CONFIG_KEYBOARD_MCS is not set # CONFIG_KEYBOARD_MPR121 is not set # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set # CONFIG_KEYBOARD_STOWAWAY is not set # CONFIG_KEYBOARD_SUNKBD is not set # CONFIG_KEYBOARD_OMAP4 is not set @@ -1197,16 +1221,18 @@ CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y # CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_ATMEL is not set +# CONFIG_HW_RANDOM_EXYNOS is not set # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set -# CONFIG_RAMOOPS is not set CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=y # CONFIG_I2C_MUX is not set CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=m # # I2C Hardware Bus support @@ -1215,6 +1241,7 @@ CONFIG_I2C_HELPER_AUTO=y # # I2C system bus drivers (mostly embedded / system-on-chip) # +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set # CONFIG_I2C_OCORES is not set # CONFIG_I2C_PCA_PLATFORM is not set # CONFIG_I2C_PXA_PCI is not set @@ -1246,6 +1273,7 @@ CONFIG_SPI_MASTER=y # CONFIG_SPI_ALTERA is not set # CONFIG_SPI_BITBANG is not set # CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_XCOMM is not set # CONFIG_SPI_XILINX is not set # CONFIG_SPI_DESIGNWARE is not set @@ -1272,8 +1300,23 @@ CONFIG_SPI_MASTER=y # # Enable Device Drivers -> PPS to see the PTP clock options. # +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y # CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_POWER_AVS is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set # CONFIG_WATCHDOG is not set @@ -1293,10 +1336,13 @@ CONFIG_BCMA_POSSIBLE=y # # Multifunction device drivers # -# CONFIG_MFD_CORE is not set +CONFIG_MFD_CORE=m # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_LM3533 is not set # CONFIG_TPS6105X is not set # CONFIG_TPS6507X is not set # CONFIG_MFD_TPS65217 is not set @@ -1309,59 +1355,54 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_DA9052_SPI is not set # CONFIG_MFD_DA9052_I2C is not set # CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set # CONFIG_MFD_MAX8925 is not set # CONFIG_MFD_MAX8997 is not set # CONFIG_MFD_MAX8998 is not set -# CONFIG_MFD_S5M_CORE is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM831X_I2C is not set # CONFIG_MFD_WM831X_SPI is not set # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set # CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_MC13XXX is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set # CONFIG_ABX500_CORE is not set # CONFIG_EZX_PCAP is not set -# CONFIG_MFD_WL1273_CORE is not set +CONFIG_MFD_WL1273_CORE=m # CONFIG_MFD_TPS65090 is not set # CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_PALMAS is not set # CONFIG_REGULATOR is not set CONFIG_MEDIA_SUPPORT=y # # Multimedia core support # +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_RC_SUPPORT=y # CONFIG_MEDIA_CONTROLLER is not set -CONFIG_VIDEO_DEV=m -CONFIG_VIDEO_V4L2_COMMON=m +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y CONFIG_DVB_CORE=y CONFIG_DVB_NET=y -CONFIG_VIDEO_MEDIA=m # -# Multimedia drivers +# Media drivers # CONFIG_RC_CORE=y -CONFIG_LIRC=y CONFIG_RC_MAP=y -CONFIG_IR_NEC_DECODER=y -CONFIG_IR_RC5_DECODER=y -CONFIG_IR_RC6_DECODER=y -CONFIG_IR_JVC_DECODER=y -CONFIG_IR_SONY_DECODER=y -CONFIG_IR_RC5_SZ_DECODER=y -CONFIG_IR_SANYO_DECODER=y -CONFIG_IR_MCE_KBD_DECODER=y -CONFIG_IR_LIRC_CODEC=y -# CONFIG_RC_ATI_REMOTE is not set -# CONFIG_IR_IMON is not set -# CONFIG_IR_MCEUSB is not set -# CONFIG_IR_REDRAT3 is not set -# CONFIG_IR_STREAMZAP is not set -# CONFIG_RC_LOOPBACK is not set -# CONFIG_IR_GPIO_CIR is not set +# CONFIG_RC_DECODERS is not set +# CONFIG_RC_DEVICES is not set # CONFIG_MEDIA_ATTACH is not set -CONFIG_MEDIA_TUNER=m +CONFIG_MEDIA_TUNER=y CONFIG_MEDIA_TUNER_CUSTOMISE=y # @@ -1388,18 +1429,25 @@ CONFIG_MEDIA_TUNER_MXL5007T=m CONFIG_MEDIA_TUNER_MC44S803=m CONFIG_MEDIA_TUNER_MAX2165=m CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_FC0011=m +CONFIG_MEDIA_TUNER_FC0012=m +CONFIG_MEDIA_TUNER_FC0013=m CONFIG_MEDIA_TUNER_TDA18212=m -CONFIG_VIDEO_V4L2=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_VIDEO_V4L2=y CONFIG_VIDEOBUF_GEN=m CONFIG_VIDEOBUF_VMALLOC=m CONFIG_VIDEOBUF_DVB=m CONFIG_VIDEO_TVEEPROM=m CONFIG_VIDEO_TUNER=m +CONFIG_VIDEOBUF2_CORE=m +CONFIG_VIDEOBUF2_MEMOPS=m +CONFIG_VIDEOBUF2_VMALLOC=m CONFIG_VIDEO_CAPTURE_DRIVERS=y # CONFIG_VIDEO_ADV_DEBUG is not set # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set # CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set -CONFIG_VIDEO_IR_I2C=m +# CONFIG_VIDEO_IR_I2C is not set # # Encoders, decoders, sensors and other helper chips @@ -1413,11 +1461,11 @@ CONFIG_VIDEO_IR_I2C=m # CONFIG_VIDEO_TDA9840 is not set # CONFIG_VIDEO_TEA6415C is not set # CONFIG_VIDEO_TEA6420 is not set -# CONFIG_VIDEO_MSP3400 is not set +CONFIG_VIDEO_MSP3400=m # CONFIG_VIDEO_CS5345 is not set -# CONFIG_VIDEO_CS53L32A is not set +CONFIG_VIDEO_CS53L32A=m # CONFIG_VIDEO_TLV320AIC23B is not set -# CONFIG_VIDEO_WM8775 is not set +CONFIG_VIDEO_WM8775=m # CONFIG_VIDEO_WM8739 is not set # CONFIG_VIDEO_VP27SMPX is not set @@ -1436,7 +1484,7 @@ CONFIG_VIDEO_IR_I2C=m # CONFIG_VIDEO_BT866 is not set # CONFIG_VIDEO_KS0127 is not set # CONFIG_VIDEO_SAA7110 is not set -# CONFIG_VIDEO_SAA711X is not set +CONFIG_VIDEO_SAA711X=m # CONFIG_VIDEO_SAA7191 is not set # CONFIG_VIDEO_TVP514X is not set # CONFIG_VIDEO_TVP5150 is not set @@ -1447,12 +1495,12 @@ CONFIG_VIDEO_IR_I2C=m # Video and audio decoders # # CONFIG_VIDEO_SAA717X is not set -# CONFIG_VIDEO_CX25840 is not set +CONFIG_VIDEO_CX25840=m # # MPEG video encoders # -# CONFIG_VIDEO_CX2341X is not set +CONFIG_VIDEO_CX2341X=m # # Video encoders @@ -1462,12 +1510,13 @@ CONFIG_VIDEO_IR_I2C=m # CONFIG_VIDEO_ADV7170 is not set # CONFIG_VIDEO_ADV7175 is not set # CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set # CONFIG_VIDEO_AK881X is not set # # Camera sensor devices # -# CONFIG_VIDEO_OV7670 is not set +CONFIG_VIDEO_OV7670=m # CONFIG_VIDEO_VS6624 is not set # CONFIG_VIDEO_MT9V011 is not set # CONFIG_VIDEO_TCM825X is not set @@ -1490,85 +1539,112 @@ CONFIG_VIDEO_IR_I2C=m # CONFIG_VIDEO_M52790 is not set # CONFIG_VIDEO_VIVI is not set CONFIG_V4L_USB_DRIVERS=y -# CONFIG_USB_VIDEO_CLASS is not set + +# +# Webcam devices +# +CONFIG_USB_VIDEO_CLASS=m CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y CONFIG_USB_GSPCA=m -# CONFIG_USB_M5602 is not set -# CONFIG_USB_STV06XX is not set -# CONFIG_USB_GL860 is not set -# CONFIG_USB_GSPCA_BENQ is not set -# CONFIG_USB_GSPCA_CONEX is not set -# CONFIG_USB_GSPCA_CPIA1 is not set -# CONFIG_USB_GSPCA_ETOMS is not set -# CONFIG_USB_GSPCA_FINEPIX is not set -# CONFIG_USB_GSPCA_JEILINJ is not set -# CONFIG_USB_GSPCA_JL2005BCD is not set -# CONFIG_USB_GSPCA_KINECT is not set -# CONFIG_USB_GSPCA_KONICA is not set -# CONFIG_USB_GSPCA_MARS is not set -# CONFIG_USB_GSPCA_MR97310A is not set -# CONFIG_USB_GSPCA_NW80X is not set -# CONFIG_USB_GSPCA_OV519 is not set -# CONFIG_USB_GSPCA_OV534 is not set -# CONFIG_USB_GSPCA_OV534_9 is not set -# CONFIG_USB_GSPCA_PAC207 is not set -# CONFIG_USB_GSPCA_PAC7302 is not set -# CONFIG_USB_GSPCA_PAC7311 is not set -# CONFIG_USB_GSPCA_SE401 is not set -# CONFIG_USB_GSPCA_SN9C2028 is not set -# CONFIG_USB_GSPCA_SN9C20X is not set -# CONFIG_USB_GSPCA_SONIXB is not set -# CONFIG_USB_GSPCA_SONIXJ is not set -# CONFIG_USB_GSPCA_SPCA500 is not set -# CONFIG_USB_GSPCA_SPCA501 is not set -# CONFIG_USB_GSPCA_SPCA505 is not set -# CONFIG_USB_GSPCA_SPCA506 is not set -# CONFIG_USB_GSPCA_SPCA508 is not set -# CONFIG_USB_GSPCA_SPCA561 is not set -# CONFIG_USB_GSPCA_SPCA1528 is not set -# CONFIG_USB_GSPCA_SQ905 is not set -# CONFIG_USB_GSPCA_SQ905C is not set -# CONFIG_USB_GSPCA_SQ930X is not set -# CONFIG_USB_GSPCA_STK014 is not set -# CONFIG_USB_GSPCA_STV0680 is not set -# CONFIG_USB_GSPCA_SUNPLUS is not set -# CONFIG_USB_GSPCA_T613 is not set -# CONFIG_USB_GSPCA_TOPRO is not set -# CONFIG_USB_GSPCA_TV8532 is not set -# CONFIG_USB_GSPCA_VC032X is not set -# CONFIG_USB_GSPCA_VICAM is not set -# CONFIG_USB_GSPCA_XIRLINK_CIT is not set -# CONFIG_USB_GSPCA_ZC3XX is not set -# CONFIG_VIDEO_PVRUSB2 is not set -# CONFIG_VIDEO_HDPVR is not set +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_GL860=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_PWC=m +# CONFIG_USB_PWC_DEBUG is not set +CONFIG_USB_PWC_INPUT_EVDEV=y +CONFIG_VIDEO_CPIA2=m +CONFIG_USB_ZR364XX=m +CONFIG_USB_STKWEBCAM=m +CONFIG_USB_S2255=m +CONFIG_USB_SN9C102=m + +# +# Webcam and/or TV USB devices +# CONFIG_VIDEO_EM28XX=m CONFIG_VIDEO_EM28XX_ALSA=m CONFIG_VIDEO_EM28XX_DVB=m -CONFIG_VIDEO_EM28XX_RC=y -# CONFIG_VIDEO_TLG2300 is not set -# CONFIG_VIDEO_CX231XX is not set -# CONFIG_VIDEO_TM6000 is not set -# CONFIG_VIDEO_USBVISION is not set -# CONFIG_USB_ET61X251 is not set -# CONFIG_USB_SN9C102 is not set -# CONFIG_USB_PWC is not set -# CONFIG_VIDEO_CPIA2 is not set -# CONFIG_USB_ZR364XX is not set -# CONFIG_USB_STKWEBCAM is not set -# CONFIG_USB_S2255 is not set -# CONFIG_V4L_PLATFORM_DRIVERS is not set +CONFIG_VIDEO_EM28XX_RC=m + +# +# TV USB devices +# +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_PVRUSB2_DVB=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_TLG2300=m +CONFIG_VIDEO_CX231XX=m +# CONFIG_VIDEO_CX231XX_RC is not set +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_TM6000_DVB=m +CONFIG_VIDEO_USBVISION=m +CONFIG_V4L_PLATFORM_DRIVERS=y +# CONFIG_SOC_CAMERA is not set # CONFIG_V4L_MEM2MEM_DRIVERS is not set CONFIG_RADIO_ADAPTERS=y -# CONFIG_RADIO_SI470X is not set -# CONFIG_USB_MR800 is not set -# CONFIG_USB_DSBR is not set -# CONFIG_I2C_SI4713 is not set -# CONFIG_RADIO_SI4713 is not set -# CONFIG_USB_KEENE is not set -# CONFIG_RADIO_TEA5764 is not set -# CONFIG_RADIO_SAA7706H is not set -# CONFIG_RADIO_TEF6862 is not set -# CONFIG_RADIO_WL1273 is not set +CONFIG_RADIO_SI470X=y +CONFIG_USB_SI470X=m +CONFIG_I2C_SI470X=m +CONFIG_USB_MR800=m +CONFIG_USB_DSBR=m +# CONFIG_RADIO_SHARK is not set +# CONFIG_RADIO_SHARK2 is not set +CONFIG_I2C_SI4713=m +CONFIG_RADIO_SI4713=m +CONFIG_USB_KEENE=m +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_TEF6862=m +CONFIG_RADIO_WL1273=m # # Texas Instruments WL128x FM driver (ST based) @@ -1581,7 +1657,7 @@ CONFIG_TTPCI_EEPROM=m # # Supported USB Adapters # -CONFIG_DVB_USB=y +CONFIG_DVB_USB=m # CONFIG_DVB_USB_DEBUG is not set CONFIG_DVB_USB_A800=m CONFIG_DVB_USB_DIBUSB_MB=m @@ -1602,7 +1678,7 @@ CONFIG_DVB_USB_TTUSB2=m CONFIG_DVB_USB_DTT200U=m CONFIG_DVB_USB_OPERA1=m CONFIG_DVB_USB_AF9005=m -CONFIG_DVB_USB_AF9005_REMOTE=m +# CONFIG_DVB_USB_AF9005_REMOTE is not set CONFIG_DVB_USB_PCTV452E=m CONFIG_DVB_USB_DW2102=m CONFIG_DVB_USB_CINERGY_T2=m @@ -1619,6 +1695,7 @@ CONFIG_DVB_USB_TECHNISAT_USB2=m CONFIG_DVB_USB_IT913X=m CONFIG_DVB_USB_MXL111SF=m CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_AF9035=m CONFIG_SMS_SIANO_MDTV=m # @@ -1708,6 +1785,7 @@ CONFIG_DVB_HD29L2=m CONFIG_DVB_STV0367=m CONFIG_DVB_CXD2820R=m CONFIG_DVB_RTL2830=m +CONFIG_DVB_RTL2832=m # # DVB-C (cable) frontends @@ -1726,8 +1804,11 @@ CONFIG_DVB_OR51132=m CONFIG_DVB_BCM3510=m CONFIG_DVB_LGDT330X=m CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LG2160=m CONFIG_DVB_S5H1409=m CONFIG_DVB_AU8522=m +CONFIG_DVB_AU8522_DTV=m +CONFIG_DVB_AU8522_V4L=m CONFIG_DVB_S5H1411=m # @@ -1760,6 +1841,7 @@ CONFIG_DVB_TDA665x=m CONFIG_DVB_IX2505V=m CONFIG_DVB_IT913X_FE=m CONFIG_DVB_M88RS2000=m +CONFIG_DVB_AF9033=m # # Tools to develop new frontends @@ -1796,11 +1878,13 @@ CONFIG_FB=y # Frame buffer hardware drivers # # CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_TMIO is not set # CONFIG_FB_SMSCUFX is not set # CONFIG_FB_UDL is not set # CONFIG_FB_VIRTUAL is not set # CONFIG_FB_METRONOME is not set # CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_AUO_K190X is not set # CONFIG_EXYNOS_VIDEO is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set @@ -1857,16 +1941,15 @@ CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_USB is not set # CONFIG_SND_SOC is not set # CONFIG_SOUND_PRIME is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -CONFIG_HIDRAW=y # -# USB Input Devices +# HID support # -CONFIG_USB_HID=y -# CONFIG_HID_PID is not set -CONFIG_USB_HIDDEV=y +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +CONFIG_HIDRAW=y +# CONFIG_UHID is not set +CONFIG_HID_GENERIC=y # # Special HID drivers @@ -1874,6 +1957,7 @@ CONFIG_USB_HIDDEV=y # CONFIG_HID_A4TECH is not set # CONFIG_HID_ACRUX is not set # CONFIG_HID_APPLE is not set +# CONFIG_HID_AUREAL is not set # CONFIG_HID_BELKIN is not set # CONFIG_HID_CHERRY is not set # CONFIG_HID_CHICONY is not set @@ -1892,6 +1976,7 @@ CONFIG_USB_HIDDEV=y # CONFIG_HID_TWINHAN is not set # CONFIG_HID_KENSINGTON is not set # CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LENOVO_TPKBD is not set CONFIG_HID_LOGITECH=y CONFIG_HID_LOGITECH_DJ=y # CONFIG_LOGITECH_FF is not set @@ -1920,10 +2005,16 @@ CONFIG_HID_LOGITECH_DJ=y # CONFIG_HID_TOPSEED is not set # CONFIG_HID_THRUSTMASTER is not set CONFIG_HID_WACOM=m -# CONFIG_HID_WACOM_POWER_SUPPLY is not set # CONFIG_HID_WIIMOTE is not set # CONFIG_HID_ZEROPLUS is not set # CONFIG_HID_ZYDACRON is not set + +# +# USB HID support +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +CONFIG_USB_HIDDEV=y CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_USB_ARCH_HAS_XHCI is not set @@ -1937,8 +2028,6 @@ CONFIG_USB=y # # Miscellaneous USB options # -CONFIG_USB_DEVICEFS=y -CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_SUSPEND is not set # CONFIG_USB_OTG_WHITELIST is not set @@ -1958,6 +2047,7 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_OHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_CHIPIDEA is not set # # USB Device Class drivers @@ -2066,6 +2156,7 @@ CONFIG_USB_SERIAL_OPTION=m # CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set # CONFIG_USB_SERIAL_ZIO is not set # CONFIG_USB_SERIAL_SSU100 is not set +# CONFIG_USB_SERIAL_QT2 is not set # CONFIG_USB_SERIAL_DEBUG is not set # @@ -2090,6 +2181,11 @@ CONFIG_USB_SERIAL_OPTION=m # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set # CONFIG_USB_YUREX is not set + +# +# USB Physical Layer drivers +# +# CONFIG_USB_ISP1301 is not set # CONFIG_USB_GADGET is not set # @@ -2114,13 +2210,16 @@ CONFIG_LEDS_CLASS=y # CONFIG_LEDS_DAC124S085 is not set # CONFIG_LEDS_BD2802 is not set # CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_LM3556 is not set # CONFIG_LEDS_OT200 is not set +# CONFIG_LEDS_BLINKM is not set CONFIG_LEDS_TRIGGERS=y # # LED Triggers # # CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_ONESHOT is not set # CONFIG_LEDS_TRIGGER_HEARTBEAT is not set # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set @@ -2128,6 +2227,7 @@ CONFIG_LEDS_TRIGGERS=y # # iptables trigger is under Netfilter config (LED target) # +# CONFIG_LEDS_TRIGGER_TRANSIENT is not set # CONFIG_ACCESSIBILITY is not set CONFIG_RTC_LIB=y # CONFIG_RTC_CLASS is not set @@ -2159,10 +2259,8 @@ CONFIG_R8712U=m # CONFIG_TRANZPORT is not set # CONFIG_LINE6_USB is not set # CONFIG_USB_SERIAL_QUATECH2 is not set -# CONFIG_USB_SERIAL_QUATECH_USB2 is not set # CONFIG_VT6656 is not set -# CONFIG_IIO is not set -# CONFIG_FB_SM7XX is not set +# CONFIG_ZSMALLOC is not set # CONFIG_USB_ENESTORAGE is not set # CONFIG_BCM_WIMAX is not set # CONFIG_FT1000 is not set @@ -2174,8 +2272,8 @@ CONFIG_R8712U=m # CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set CONFIG_STAGING_MEDIA=y CONFIG_DVB_AS102=m -# CONFIG_EASYCAP is not set -# CONFIG_LIRC_STAGING is not set +CONFIG_EASYCAP=m +# CONFIG_EASYCAP_DEBUG is not set # # Android @@ -2183,6 +2281,12 @@ CONFIG_DVB_AS102=m # CONFIG_ANDROID is not set # CONFIG_PHONE is not set CONFIG_USB_WPAN_HCD=m +# CONFIG_IPACK_BUS is not set +CONFIG_WIMAX_GDM72XX=m +# CONFIG_WIMAX_GDM72XX_QOS is not set +# CONFIG_WIMAX_GDM72XX_K_MODE is not set +# CONFIG_WIMAX_GDM72XX_WIMAX2 is not set +CONFIG_WIMAX_GDM72XX_USB=y # # Hardware Spinlock drivers @@ -2197,19 +2301,11 @@ CONFIG_USB_WPAN_HCD=m # Rpmsg drivers (EXPERIMENTAL) # # CONFIG_VIRT_DRIVERS is not set -CONFIG_PM_DEVFREQ=y - -# -# DEVFREQ Governors -# -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -CONFIG_DEVFREQ_GOV_PERFORMANCE=y -CONFIG_DEVFREQ_GOV_POWERSAVE=y -CONFIG_DEVFREQ_GOV_USERSPACE=y - -# -# DEVFREQ Drivers -# +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +# CONFIG_PWM is not set # # File systems @@ -2290,6 +2386,7 @@ CONFIG_TMPFS=y CONFIG_MISC_FILESYSTEMS=y # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set CONFIG_HFS_FS=y CONFIG_HFSPLUS_FS=y # CONFIG_BEFS_FS is not set @@ -2311,11 +2408,9 @@ CONFIG_JFFS2_RUBIN=y # CONFIG_JFFS2_CMODE_SIZE is not set CONFIG_JFFS2_CMODE_FAVOURLZO=y CONFIG_UBIFS_FS=y -# CONFIG_UBIFS_FS_XATTR is not set # CONFIG_UBIFS_FS_ADVANCED_COMPR is not set CONFIG_UBIFS_FS_LZO=y CONFIG_UBIFS_FS_ZLIB=y -# CONFIG_UBIFS_FS_DEBUG is not set # CONFIG_LOGFS is not set # CONFIG_CRAMFS is not set CONFIG_SQUASHFS=m @@ -2339,10 +2434,17 @@ CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_UFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y +CONFIG_NFS_V2=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set -# CONFIG_NFS_V4 is not set +CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y +CONFIG_NFS_V4_1=y +CONFIG_PNFS_FILE_LAYOUT=m +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" CONFIG_ROOT_NFS=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y CONFIG_NFSD=m CONFIG_NFSD_V3=y # CONFIG_NFSD_V3_ACL is not set @@ -2351,13 +2453,18 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_SUNRPC_BACKCHANNEL=y +CONFIG_SUNRPC_SWAP=y # CONFIG_SUNRPC_DEBUG is not set # CONFIG_CEPH_FS is not set CONFIG_CIFS=y # CONFIG_CIFS_STATS is not set # CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_UPCALL is not set # CONFIG_CIFS_XATTR is not set # CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DFS_UPCALL is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set @@ -2400,6 +2507,17 @@ CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=y CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set CONFIG_NLS_UTF8=y # @@ -2413,6 +2531,7 @@ CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 CONFIG_FRAME_WARN=0 # CONFIG_MAGIC_SYSRQ is not set # CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set @@ -2421,6 +2540,8 @@ CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set # CONFIG_LOCKUP_DETECTOR is not set # CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 # CONFIG_DETECT_HUNG_TASK is not set # CONFIG_SCHED_DEBUG is not set # CONFIG_SCHEDSTATS is not set @@ -2455,6 +2576,7 @@ CONFIG_DEBUG_KERNEL=y # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set # CONFIG_FAULT_INJECTION is not set CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y @@ -2480,7 +2602,9 @@ CONFIG_CMDLINE="ubi.mtd=rootfs rootfstype=ubifs root=ubi0:rootfs bmem=256M@512M # # Security options # -# CONFIG_KEYS is not set +CONFIG_KEYS=y +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set # CONFIG_SECURITY_DMESG_RESTRICT is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set @@ -2540,7 +2664,7 @@ CONFIG_CRYPTO_HMAC=y # # Digest # -# CONFIG_CRYPTO_CRC32C is not set +CONFIG_CRYPTO_CRC32C=y # CONFIG_CRYPTO_GHASH is not set CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y @@ -2620,5 +2744,7 @@ CONFIG_HAS_DMA=y CONFIG_DQL=y CONFIG_NLATTR=y CONFIG_GENERIC_ATOMIC64=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y CONFIG_AVERAGE=y # CONFIG_CORDIC is not set +# CONFIG_DDR is not set diff --git a/meta-openpli/recipes-linux/linux/linux-etxx00/et5x00/defconfig b/meta-openpli/recipes-linux/linux/linux-etxx00/et5x00/defconfig index 12a0ef9dde..f89b6b2c10 100644 --- a/meta-openpli/recipes-linux/linux/linux-etxx00/et5x00/defconfig +++ b/meta-openpli/recipes-linux/linux/linux-etxx00/et5x00/defconfig @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/mips 3.4.0 Kernel Configuration +# Linux/mips 3.6.0 Kernel Configuration # CONFIG_MIPS=y @@ -20,6 +20,7 @@ CONFIG_BRCMSTB=y # CONFIG_LANTIQ is not set # CONFIG_LASAT is not set # CONFIG_MACH_LOONGSON is not set +# CONFIG_MACH_LOONGSON1 is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SIM is not set # CONFIG_NEC_MARKEINS is not set @@ -134,14 +135,11 @@ CONFIG_BRCM_UPPER_256MB=y CONFIG_BRCM_HAS_1GB_MEMC0=y CONFIG_BRCM_PLATFORM_DEFAULTS=y CONFIG_BCM7405=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_BOOT_RAW=y CONFIG_CEVT_R4K_LIB=y @@ -189,6 +187,7 @@ CONFIG_MIPS_MT_DISABLED=y CONFIG_CPU_HAS_SYNC=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_SELECT_MEMORY_MODEL=y # CONFIG_FLATMEM_MANUAL is not set CONFIG_SPARSEMEM_MANUAL=y @@ -205,14 +204,12 @@ CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_CROSS_MEMORY_ATTACH is not set # CONFIG_CLEANCACHE is not set +# CONFIG_FRONTSWAP is not set CONFIG_SMP=y CONFIG_SYS_SUPPORTS_SMP=y CONFIG_NR_CPUS=2 -CONFIG_TICK_ONESHOT=y -# CONFIG_NO_HZ is not set -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_HZ_48 is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_128 is not set @@ -232,6 +229,7 @@ CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" CONFIG_HAVE_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y # # General setup @@ -258,7 +256,18 @@ CONFIG_HAVE_GENERIC_HARDIRQS=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_FORCED_THREADING=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_CMOS_UPDATE=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y # # RCU Subsystem @@ -266,6 +275,7 @@ CONFIG_IRQ_FORCED_THREADING=y CONFIG_TREE_RCU=y # CONFIG_PREEMPT_RCU is not set CONFIG_RCU_FANOUT=32 +CONFIG_RCU_FANOUT_LEAF=16 # CONFIG_RCU_FANOUT_EXACT is not set # CONFIG_TREE_RCU_TRACE is not set # CONFIG_IKCONFIG is not set @@ -305,7 +315,6 @@ CONFIG_PERF_USE_VMALLOC=y # Kernel Performance Events And Counters # # CONFIG_PERF_EVENTS is not set -# CONFIG_PERF_COUNTERS is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_PCI_QUIRKS=y CONFIG_COMPAT_BRK=y @@ -320,8 +329,11 @@ CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_DMA_ATTRS=y CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_HAVE_CLK=y CONFIG_HAVE_DMA_API_DEBUG=y CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y # # GCOV-based kernel profiling @@ -417,6 +429,7 @@ CONFIG_PCI_DOMAINS=y # CONFIG_PCI_IOV is not set # CONFIG_PCI_PRI is not set # CONFIG_PCI_PASID is not set +# CONFIG_PCIEPORTBUS is not set CONFIG_MMU=y # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -449,6 +462,7 @@ CONFIG_PACKET=y CONFIG_UNIX=y # CONFIG_UNIX_DIAG is not set CONFIG_XFRM=y +CONFIG_XFRM_ALGO=m # CONFIG_XFRM_USER is not set # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set @@ -530,6 +544,7 @@ CONFIG_NETFILTER_XTABLES=m # Xtables targets # # CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_HMARK is not set # CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set # CONFIG_NETFILTER_XT_TARGET_LED is not set # CONFIG_NETFILTER_XT_TARGET_LOG is not set @@ -596,7 +611,6 @@ CONFIG_IP_NF_TARGET_REJECT=m # IPv6: Netfilter Configuration # # CONFIG_NF_DEFRAG_IPV6 is not set -# CONFIG_IP6_NF_QUEUE is not set CONFIG_IP6_NF_IPTABLES=m # CONFIG_IP6_NF_MATCH_AH is not set # CONFIG_IP6_NF_MATCH_EUI64 is not set @@ -626,12 +640,12 @@ CONFIG_IP6_NF_TARGET_REJECT=m # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set -# CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set # CONFIG_PHONET is not set # CONFIG_IEEE802154 is not set # CONFIG_NET_SCHED is not set # CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y # CONFIG_BATMAN_ADV is not set # CONFIG_OPENVSWITCH is not set CONFIG_RPS=y @@ -663,6 +677,7 @@ CONFIG_BT_HCIUART_H4=y CONFIG_BT_HCIUART_BCSP=y # CONFIG_BT_HCIUART_ATH3K is not set CONFIG_BT_HCIUART_LL=y +# CONFIG_BT_HCIUART_3WIRE is not set CONFIG_BT_HCIBCM203X=m CONFIG_BT_HCIBPA10X=m CONFIG_BT_HCIBFUSB=m @@ -680,10 +695,10 @@ CONFIG_CFG80211=y # CONFIG_NL80211_TESTMODE is not set # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set # CONFIG_CFG80211_REG_DEBUG is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set CONFIG_CFG80211_DEFAULT_PS=y # CONFIG_CFG80211_INTERNAL_REGDB is not set CONFIG_CFG80211_WEXT=y -CONFIG_WIRELESS_EXT_SYSFS=y CONFIG_LIB80211=y CONFIG_LIB80211_CRYPT_WEP=m CONFIG_LIB80211_CRYPT_CCMP=m @@ -698,6 +713,7 @@ CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" # CONFIG_MAC80211_MESH is not set CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_MESSAGE_TRACING is not set # CONFIG_MAC80211_DEBUG_MENU is not set # CONFIG_WIMAX is not set CONFIG_RFKILL=y @@ -826,7 +842,6 @@ CONFIG_MTD_UBI=y CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MTD_UBI_BEB_RESERVE=1 # CONFIG_MTD_UBI_GLUEBI is not set -# CONFIG_MTD_UBI_DEBUG is not set # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set @@ -860,6 +875,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # # CONFIG_SENSORS_LIS3LV02D is not set # CONFIG_AD525X_DPOT is not set +# CONFIG_ATMEL_PWM is not set # CONFIG_PHANTOM is not set # CONFIG_INTEL_MID_PTI is not set # CONFIG_SGI_IOC4 is not set @@ -876,7 +892,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_SENSORS_APDS990X is not set # CONFIG_HMC6352 is not set # CONFIG_DS1682 is not set -# CONFIG_BMP085 is not set +# CONFIG_BMP085_I2C is not set # CONFIG_PCH_PHUB is not set # CONFIG_USB_SWITCH_FSA9480 is not set # CONFIG_C2PORT is not set @@ -927,7 +943,6 @@ CONFIG_CHR_DEV_SG=y # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set # CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m # # SCSI Transports @@ -1164,6 +1179,7 @@ CONFIG_NET_VENDOR_BROADCOM=y # CONFIG_NET_VENDOR_TI is not set # CONFIG_NET_VENDOR_TOSHIBA is not set # CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_PHYLIB is not set @@ -1178,7 +1194,6 @@ CONFIG_PPP_ASYNC=m CONFIG_PPP_SYNC_TTY=m # CONFIG_SLIP is not set CONFIG_SLHC=m -# CONFIG_TR is not set # # USB Network Adapters @@ -1215,7 +1230,6 @@ CONFIG_ATH9K_BTCOEX_SUPPORT=y CONFIG_ATH9K=m # CONFIG_ATH9K_PCI is not set # CONFIG_ATH9K_AHB is not set -# CONFIG_ATH9K_DFS_CERTIFIED is not set CONFIG_ATH9K_RATE_CONTROL=y CONFIG_ATH9K_HTC=m CONFIG_CARL9170=m @@ -1239,6 +1253,7 @@ CONFIG_HOSTAP_FIRMWARE=y # CONFIG_IPW2100 is not set # CONFIG_IPW2200 is not set CONFIG_IWLWIFI=m +CONFIG_IWLDVM=m # # Debugging Options @@ -1280,12 +1295,16 @@ CONFIG_RT2X00_LIB_LEDS=y # CONFIG_RTL8192SE is not set # CONFIG_RTL8192DE is not set # CONFIG_RTL8192CU is not set +CONFIG_WL_TI=y CONFIG_WL1251=m -# CONFIG_WL12XX_MENU is not set +CONFIG_WL12XX=m +CONFIG_WL18XX=m +CONFIG_WLCORE=m CONFIG_ZD1211RW=m # CONFIG_ZD1211RW_DEBUG is not set CONFIG_MWIFIEX=y # CONFIG_MWIFIEX_PCIE is not set +CONFIG_MWIFIEX_USB=m # # Enable WiMAX (Networking options) to see the WiMAX drivers @@ -1301,6 +1320,7 @@ CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set CONFIG_INPUT_POLLDEV=m # CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set # # Userland interfaces @@ -1326,11 +1346,13 @@ CONFIG_INPUT_KEYBOARD=y # CONFIG_KEYBOARD_TCA6416 is not set # CONFIG_KEYBOARD_TCA8418 is not set # CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set # CONFIG_KEYBOARD_MAX7359 is not set # CONFIG_KEYBOARD_MCS is not set # CONFIG_KEYBOARD_MPR121 is not set # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set # CONFIG_KEYBOARD_STOWAWAY is not set # CONFIG_KEYBOARD_SUNKBD is not set # CONFIG_KEYBOARD_OMAP4 is not set @@ -1397,18 +1419,20 @@ CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y # CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_ATMEL is not set +# CONFIG_HW_RANDOM_EXYNOS is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y -# CONFIG_RAMOOPS is not set CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=y # CONFIG_I2C_MUX is not set CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=m # # I2C Hardware Bus support @@ -1435,6 +1459,7 @@ CONFIG_I2C_HELPER_AUTO=y # # I2C system bus drivers (mostly embedded / system-on-chip) # +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set # CONFIG_I2C_DESIGNWARE_PCI is not set # CONFIG_I2C_EG20T is not set # CONFIG_I2C_INTEL_MID is not set @@ -1478,8 +1503,23 @@ CONFIG_I2C_HELPER_AUTO=y # # Enable Device Drivers -> PPS to see the PTP clock options. # +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y # CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_POWER_AVS is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set # CONFIG_WATCHDOG is not set @@ -1499,10 +1539,13 @@ CONFIG_BCMA_POSSIBLE=y # # Multifunction device drivers # -# CONFIG_MFD_CORE is not set +CONFIG_MFD_CORE=m # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_LM3533 is not set # CONFIG_TPS6105X is not set # CONFIG_TPS6507X is not set # CONFIG_MFD_TPS65217 is not set @@ -1514,60 +1557,57 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_PMIC_DA903X is not set # CONFIG_MFD_DA9052_I2C is not set # CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set # CONFIG_MFD_MAX8925 is not set # CONFIG_MFD_MAX8997 is not set # CONFIG_MFD_MAX8998 is not set -# CONFIG_MFD_S5M_CORE is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_ARIZONA_I2C is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM831X_I2C is not set # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set # CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13XXX_I2C is not set # CONFIG_ABX500_CORE is not set # CONFIG_LPC_SCH is not set +# CONFIG_LPC_ICH is not set # CONFIG_MFD_RDC321X is not set # CONFIG_MFD_JANZ_CMODIO is not set # CONFIG_MFD_VX855 is not set -# CONFIG_MFD_WL1273_CORE is not set +CONFIG_MFD_WL1273_CORE=m # CONFIG_MFD_TPS65090 is not set # CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_PALMAS is not set # CONFIG_REGULATOR is not set CONFIG_MEDIA_SUPPORT=y # # Multimedia core support # +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_RC_SUPPORT=y # CONFIG_MEDIA_CONTROLLER is not set -CONFIG_VIDEO_DEV=m -CONFIG_VIDEO_V4L2_COMMON=m +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y CONFIG_DVB_CORE=y CONFIG_DVB_NET=y -CONFIG_VIDEO_MEDIA=m # -# Multimedia drivers +# Media drivers # +CONFIG_VIDEO_SAA7146=m +CONFIG_VIDEO_SAA7146_VV=m CONFIG_RC_CORE=y -CONFIG_LIRC=y CONFIG_RC_MAP=y -CONFIG_IR_NEC_DECODER=y -CONFIG_IR_RC5_DECODER=y -CONFIG_IR_RC6_DECODER=y -CONFIG_IR_JVC_DECODER=y -CONFIG_IR_SONY_DECODER=y -CONFIG_IR_RC5_SZ_DECODER=y -CONFIG_IR_SANYO_DECODER=y -CONFIG_IR_MCE_KBD_DECODER=y -CONFIG_IR_LIRC_CODEC=y -# CONFIG_RC_ATI_REMOTE is not set -# CONFIG_IR_IMON is not set -# CONFIG_IR_MCEUSB is not set -# CONFIG_IR_REDRAT3 is not set -# CONFIG_IR_STREAMZAP is not set -# CONFIG_RC_LOOPBACK is not set -# CONFIG_IR_GPIO_CIR is not set +# CONFIG_RC_DECODERS is not set +# CONFIG_RC_DEVICES is not set # CONFIG_MEDIA_ATTACH is not set -CONFIG_MEDIA_TUNER=m +CONFIG_MEDIA_TUNER=y CONFIG_MEDIA_TUNER_CUSTOMISE=y # @@ -1594,18 +1634,27 @@ CONFIG_MEDIA_TUNER_MXL5007T=m CONFIG_MEDIA_TUNER_MC44S803=m CONFIG_MEDIA_TUNER_MAX2165=m CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_FC0011=m +CONFIG_MEDIA_TUNER_FC0012=m +CONFIG_MEDIA_TUNER_FC0013=m CONFIG_MEDIA_TUNER_TDA18212=m -CONFIG_VIDEO_V4L2=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_VIDEO_V4L2=y CONFIG_VIDEOBUF_GEN=m +CONFIG_VIDEOBUF_DMA_SG=m CONFIG_VIDEOBUF_VMALLOC=m CONFIG_VIDEOBUF_DVB=m CONFIG_VIDEO_TVEEPROM=m CONFIG_VIDEO_TUNER=m +CONFIG_VIDEOBUF2_CORE=m +CONFIG_VIDEOBUF2_MEMOPS=m +CONFIG_VIDEOBUF2_DMA_CONTIG=m +CONFIG_VIDEOBUF2_VMALLOC=m CONFIG_VIDEO_CAPTURE_DRIVERS=y # CONFIG_VIDEO_ADV_DEBUG is not set # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set # CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set -CONFIG_VIDEO_IR_I2C=m +# CONFIG_VIDEO_IR_I2C is not set # # Encoders, decoders, sensors and other helper chips @@ -1619,11 +1668,11 @@ CONFIG_VIDEO_IR_I2C=m # CONFIG_VIDEO_TDA9840 is not set # CONFIG_VIDEO_TEA6415C is not set # CONFIG_VIDEO_TEA6420 is not set -# CONFIG_VIDEO_MSP3400 is not set +CONFIG_VIDEO_MSP3400=m # CONFIG_VIDEO_CS5345 is not set -# CONFIG_VIDEO_CS53L32A is not set +CONFIG_VIDEO_CS53L32A=m # CONFIG_VIDEO_TLV320AIC23B is not set -# CONFIG_VIDEO_WM8775 is not set +CONFIG_VIDEO_WM8775=m # CONFIG_VIDEO_WM8739 is not set # CONFIG_VIDEO_VP27SMPX is not set @@ -1642,7 +1691,7 @@ CONFIG_VIDEO_IR_I2C=m # CONFIG_VIDEO_BT866 is not set # CONFIG_VIDEO_KS0127 is not set # CONFIG_VIDEO_SAA7110 is not set -# CONFIG_VIDEO_SAA711X is not set +CONFIG_VIDEO_SAA711X=m # CONFIG_VIDEO_SAA7191 is not set # CONFIG_VIDEO_TVP514X is not set # CONFIG_VIDEO_TVP5150 is not set @@ -1653,12 +1702,12 @@ CONFIG_VIDEO_IR_I2C=m # Video and audio decoders # # CONFIG_VIDEO_SAA717X is not set -# CONFIG_VIDEO_CX25840 is not set +CONFIG_VIDEO_CX25840=m # # MPEG video encoders # -# CONFIG_VIDEO_CX2341X is not set +CONFIG_VIDEO_CX2341X=m # # Video encoders @@ -1668,12 +1717,13 @@ CONFIG_VIDEO_IR_I2C=m # CONFIG_VIDEO_ADV7170 is not set # CONFIG_VIDEO_ADV7175 is not set # CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set # CONFIG_VIDEO_AK881X is not set # # Camera sensor devices # -# CONFIG_VIDEO_OV7670 is not set +CONFIG_VIDEO_OV7670=m # CONFIG_VIDEO_VS6624 is not set # CONFIG_VIDEO_MT9V011 is not set # CONFIG_VIDEO_TCM825X is not set @@ -1696,87 +1746,115 @@ CONFIG_VIDEO_IR_I2C=m # CONFIG_VIDEO_M52790 is not set # CONFIG_VIDEO_VIVI is not set CONFIG_V4L_USB_DRIVERS=y -# CONFIG_USB_VIDEO_CLASS is not set + +# +# Webcam devices +# +CONFIG_USB_VIDEO_CLASS=m CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y CONFIG_USB_GSPCA=m -# CONFIG_USB_M5602 is not set -# CONFIG_USB_STV06XX is not set -# CONFIG_USB_GL860 is not set -# CONFIG_USB_GSPCA_BENQ is not set -# CONFIG_USB_GSPCA_CONEX is not set -# CONFIG_USB_GSPCA_CPIA1 is not set -# CONFIG_USB_GSPCA_ETOMS is not set -# CONFIG_USB_GSPCA_FINEPIX is not set -# CONFIG_USB_GSPCA_JEILINJ is not set -# CONFIG_USB_GSPCA_JL2005BCD is not set -# CONFIG_USB_GSPCA_KINECT is not set -# CONFIG_USB_GSPCA_KONICA is not set -# CONFIG_USB_GSPCA_MARS is not set -# CONFIG_USB_GSPCA_MR97310A is not set -# CONFIG_USB_GSPCA_NW80X is not set -# CONFIG_USB_GSPCA_OV519 is not set -# CONFIG_USB_GSPCA_OV534 is not set -# CONFIG_USB_GSPCA_OV534_9 is not set -# CONFIG_USB_GSPCA_PAC207 is not set -# CONFIG_USB_GSPCA_PAC7302 is not set -# CONFIG_USB_GSPCA_PAC7311 is not set -# CONFIG_USB_GSPCA_SE401 is not set -# CONFIG_USB_GSPCA_SN9C2028 is not set -# CONFIG_USB_GSPCA_SN9C20X is not set -# CONFIG_USB_GSPCA_SONIXB is not set -# CONFIG_USB_GSPCA_SONIXJ is not set -# CONFIG_USB_GSPCA_SPCA500 is not set -# CONFIG_USB_GSPCA_SPCA501 is not set -# CONFIG_USB_GSPCA_SPCA505 is not set -# CONFIG_USB_GSPCA_SPCA506 is not set -# CONFIG_USB_GSPCA_SPCA508 is not set -# CONFIG_USB_GSPCA_SPCA561 is not set -# CONFIG_USB_GSPCA_SPCA1528 is not set -# CONFIG_USB_GSPCA_SQ905 is not set -# CONFIG_USB_GSPCA_SQ905C is not set -# CONFIG_USB_GSPCA_SQ930X is not set -# CONFIG_USB_GSPCA_STK014 is not set -# CONFIG_USB_GSPCA_STV0680 is not set -# CONFIG_USB_GSPCA_SUNPLUS is not set -# CONFIG_USB_GSPCA_T613 is not set -# CONFIG_USB_GSPCA_TOPRO is not set -# CONFIG_USB_GSPCA_TV8532 is not set -# CONFIG_USB_GSPCA_VC032X is not set -# CONFIG_USB_GSPCA_VICAM is not set -# CONFIG_USB_GSPCA_XIRLINK_CIT is not set -# CONFIG_USB_GSPCA_ZC3XX is not set -# CONFIG_VIDEO_PVRUSB2 is not set -# CONFIG_VIDEO_HDPVR is not set +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_GL860=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_PWC=m +# CONFIG_USB_PWC_DEBUG is not set +CONFIG_USB_PWC_INPUT_EVDEV=y +CONFIG_VIDEO_CPIA2=m +CONFIG_USB_ZR364XX=m +CONFIG_USB_STKWEBCAM=m +CONFIG_USB_S2255=m +CONFIG_USB_SN9C102=m + +# +# Webcam and/or TV USB devices +# CONFIG_VIDEO_EM28XX=m CONFIG_VIDEO_EM28XX_ALSA=m CONFIG_VIDEO_EM28XX_DVB=m -CONFIG_VIDEO_EM28XX_RC=y -# CONFIG_VIDEO_TLG2300 is not set -# CONFIG_VIDEO_CX231XX is not set -# CONFIG_VIDEO_TM6000 is not set -# CONFIG_VIDEO_USBVISION is not set -# CONFIG_USB_ET61X251 is not set -# CONFIG_USB_SN9C102 is not set -# CONFIG_USB_PWC is not set -# CONFIG_VIDEO_CPIA2 is not set -# CONFIG_USB_ZR364XX is not set -# CONFIG_USB_STKWEBCAM is not set -# CONFIG_USB_S2255 is not set +CONFIG_VIDEO_EM28XX_RC=m + +# +# TV USB devices +# +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_PVRUSB2_DVB=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_TLG2300=m +CONFIG_VIDEO_CX231XX=m +# CONFIG_VIDEO_CX231XX_RC is not set +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_TM6000_DVB=m +CONFIG_VIDEO_USBVISION=m # CONFIG_V4L_PCI_DRIVERS is not set -# CONFIG_V4L_PLATFORM_DRIVERS is not set +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_CAFE_CCIC=m +# CONFIG_SOC_CAMERA is not set # CONFIG_V4L_MEM2MEM_DRIVERS is not set CONFIG_RADIO_ADAPTERS=y -# CONFIG_RADIO_SI470X is not set -# CONFIG_USB_MR800 is not set -# CONFIG_USB_DSBR is not set -# CONFIG_RADIO_MAXIRADIO is not set -# CONFIG_I2C_SI4713 is not set -# CONFIG_RADIO_SI4713 is not set -# CONFIG_USB_KEENE is not set -# CONFIG_RADIO_TEA5764 is not set -# CONFIG_RADIO_SAA7706H is not set -# CONFIG_RADIO_TEF6862 is not set -# CONFIG_RADIO_WL1273 is not set +CONFIG_RADIO_SI470X=y +CONFIG_USB_SI470X=m +CONFIG_I2C_SI470X=m +CONFIG_USB_MR800=m +CONFIG_USB_DSBR=m +CONFIG_RADIO_MAXIRADIO=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_I2C_SI4713=m +CONFIG_RADIO_SI4713=m +CONFIG_USB_KEENE=m +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_TEF6862=m +CONFIG_RADIO_WL1273=m # # Texas Instruments WL128x FM driver (ST based) @@ -1789,13 +1867,14 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # Supported SAA7146 based PCI Adapters # CONFIG_TTPCI_EEPROM=m -# CONFIG_DVB_AV7110 is not set +CONFIG_DVB_AV7110=m +# CONFIG_DVB_AV7110_OSD is not set # CONFIG_DVB_BUDGET_CORE is not set # # Supported USB Adapters # -CONFIG_DVB_USB=y +CONFIG_DVB_USB=m # CONFIG_DVB_USB_DEBUG is not set CONFIG_DVB_USB_A800=m CONFIG_DVB_USB_DIBUSB_MB=m @@ -1816,7 +1895,7 @@ CONFIG_DVB_USB_TTUSB2=m CONFIG_DVB_USB_DTT200U=m CONFIG_DVB_USB_OPERA1=m CONFIG_DVB_USB_AF9005=m -CONFIG_DVB_USB_AF9005_REMOTE=m +# CONFIG_DVB_USB_AF9005_REMOTE is not set CONFIG_DVB_USB_PCTV452E=m CONFIG_DVB_USB_DW2102=m CONFIG_DVB_USB_CINERGY_T2=m @@ -1833,6 +1912,7 @@ CONFIG_DVB_USB_TECHNISAT_USB2=m CONFIG_DVB_USB_IT913X=m CONFIG_DVB_USB_MXL111SF=m CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_AF9035=m # CONFIG_DVB_TTUSB_BUDGET is not set # CONFIG_DVB_TTUSB_DEC is not set CONFIG_SMS_SIANO_MDTV=m @@ -1958,6 +2038,7 @@ CONFIG_DVB_HD29L2=m CONFIG_DVB_STV0367=m CONFIG_DVB_CXD2820R=m CONFIG_DVB_RTL2830=m +CONFIG_DVB_RTL2832=m # # DVB-C (cable) frontends @@ -1976,8 +2057,11 @@ CONFIG_DVB_OR51132=m CONFIG_DVB_BCM3510=m CONFIG_DVB_LGDT330X=m CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LG2160=m CONFIG_DVB_S5H1409=m CONFIG_DVB_AU8522=m +CONFIG_DVB_AU8522_DTV=m +CONFIG_DVB_AU8522_V4L=m CONFIG_DVB_S5H1411=m # @@ -2010,6 +2094,7 @@ CONFIG_DVB_TDA665x=m CONFIG_DVB_IX2505V=m CONFIG_DVB_IT913X_FE=m CONFIG_DVB_M88RS2000=m +CONFIG_DVB_AF9033=m # # Tools to develop new frontends @@ -2072,12 +2157,14 @@ CONFIG_FB=y # CONFIG_FB_ARK is not set # CONFIG_FB_PM3 is not set # CONFIG_FB_CARMINE is not set +# CONFIG_FB_TMIO is not set # CONFIG_FB_SMSCUFX is not set # CONFIG_FB_UDL is not set # CONFIG_FB_VIRTUAL is not set # CONFIG_FB_METRONOME is not set # CONFIG_FB_MB862XX is not set # CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_AUO_K190X is not set # CONFIG_EXYNOS_VIDEO is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set @@ -2129,21 +2216,21 @@ CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_SBAWE_SEQ is not set # CONFIG_SND_EMU10K1_SEQ is not set # CONFIG_SND_DRIVERS is not set +CONFIG_SND_TEA575X=m # CONFIG_SND_PCI is not set # CONFIG_SND_MIPS is not set # CONFIG_SND_USB is not set # CONFIG_SND_SOC is not set # CONFIG_SOUND_PRIME is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -CONFIG_HIDRAW=y # -# USB Input Devices +# HID support # -CONFIG_USB_HID=y -# CONFIG_HID_PID is not set -CONFIG_USB_HIDDEV=y +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +CONFIG_HIDRAW=y +# CONFIG_UHID is not set +CONFIG_HID_GENERIC=y # # Special HID drivers @@ -2151,6 +2238,7 @@ CONFIG_USB_HIDDEV=y # CONFIG_HID_A4TECH is not set # CONFIG_HID_ACRUX is not set # CONFIG_HID_APPLE is not set +# CONFIG_HID_AUREAL is not set # CONFIG_HID_BELKIN is not set # CONFIG_HID_CHERRY is not set # CONFIG_HID_CHICONY is not set @@ -2169,6 +2257,7 @@ CONFIG_USB_HIDDEV=y # CONFIG_HID_TWINHAN is not set # CONFIG_HID_KENSINGTON is not set # CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LENOVO_TPKBD is not set CONFIG_HID_LOGITECH=y CONFIG_HID_LOGITECH_DJ=y # CONFIG_LOGITECH_FF is not set @@ -2197,10 +2286,16 @@ CONFIG_HID_LOGITECH_DJ=y # CONFIG_HID_TOPSEED is not set # CONFIG_HID_THRUSTMASTER is not set CONFIG_HID_WACOM=m -# CONFIG_HID_WACOM_POWER_SUPPLY is not set # CONFIG_HID_WIIMOTE is not set # CONFIG_HID_ZEROPLUS is not set # CONFIG_HID_ZYDACRON is not set + +# +# USB HID support +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +CONFIG_USB_HIDDEV=y CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y CONFIG_USB_ARCH_HAS_XHCI=y @@ -2214,8 +2309,6 @@ CONFIG_USB=y # # Miscellaneous USB options # -CONFIG_USB_DEVICEFS=y -CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set @@ -2236,6 +2329,7 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_CHIPIDEA is not set # # USB Device Class drivers @@ -2301,7 +2395,7 @@ CONFIG_USB_SERIAL_FTDI_SIO=m CONFIG_USB_SERIAL_F81232=m # CONFIG_USB_SERIAL_GARMIN is not set # CONFIG_USB_SERIAL_IPW is not set -CONFIG_USB_SERIAL_IUU=m +# CONFIG_USB_SERIAL_IUU is not set # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set CONFIG_USB_SERIAL_KEYSPAN=m # CONFIG_USB_SERIAL_KEYSPAN_MPR is not set @@ -2344,6 +2438,7 @@ CONFIG_USB_SERIAL_OPTION=m # CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set # CONFIG_USB_SERIAL_ZIO is not set # CONFIG_USB_SERIAL_SSU100 is not set +# CONFIG_USB_SERIAL_QT2 is not set # CONFIG_USB_SERIAL_DEBUG is not set # @@ -2368,6 +2463,11 @@ CONFIG_USB_SERIAL_OPTION=m # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set # CONFIG_USB_YUREX is not set + +# +# USB Physical Layer drivers +# +# CONFIG_USB_ISP1301 is not set # CONFIG_USB_GADGET is not set # @@ -2392,13 +2492,16 @@ CONFIG_LEDS_CLASS=y # CONFIG_LEDS_PCA9633 is not set # CONFIG_LEDS_BD2802 is not set # CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_LM3556 is not set # CONFIG_LEDS_OT200 is not set +# CONFIG_LEDS_BLINKM is not set CONFIG_LEDS_TRIGGERS=y # # LED Triggers # # CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_ONESHOT is not set # CONFIG_LEDS_TRIGGER_HEARTBEAT is not set # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set @@ -2406,6 +2509,7 @@ CONFIG_LEDS_TRIGGERS=y # # iptables trigger is under Netfilter config (LED target) # +# CONFIG_LEDS_TRIGGER_TRANSIENT is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_RTC_LIB=y @@ -2445,12 +2549,10 @@ CONFIG_R8712U=m # CONFIG_IDE_PHISON is not set # CONFIG_LINE6_USB is not set # CONFIG_USB_SERIAL_QUATECH2 is not set -# CONFIG_USB_SERIAL_QUATECH_USB2 is not set # CONFIG_VT6655 is not set # CONFIG_VT6656 is not set -# CONFIG_VME_BUS is not set # CONFIG_DX_SEP is not set -# CONFIG_IIO is not set +# CONFIG_ZSMALLOC is not set # CONFIG_FB_SM7XX is not set # CONFIG_CRYSTALHD is not set # CONFIG_FB_XGI is not set @@ -2466,11 +2568,22 @@ CONFIG_R8712U=m CONFIG_STAGING_MEDIA=y CONFIG_DVB_AS102=m # CONFIG_DVB_CXD2099 is not set -# CONFIG_VIDEO_DT3155 is not set -# CONFIG_EASYCAP is not set -# CONFIG_VIDEO_GO7007 is not set -# CONFIG_SOLO6X10 is not set -# CONFIG_LIRC_STAGING is not set +CONFIG_VIDEO_DT3155=m +CONFIG_DT3155_CCIR=y +CONFIG_DT3155_STREAMING=y +CONFIG_EASYCAP=m +# CONFIG_EASYCAP_DEBUG is not set +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m +CONFIG_VIDEO_GO7007_OV7640=m +CONFIG_VIDEO_GO7007_SAA7113=m +CONFIG_VIDEO_GO7007_SAA7115=m +CONFIG_VIDEO_GO7007_TW9903=m +CONFIG_VIDEO_GO7007_UDA1342=m +CONFIG_VIDEO_GO7007_SONY_TUNER=m +CONFIG_VIDEO_GO7007_TW2804=m +CONFIG_SOLO6X10=m # # Android @@ -2478,6 +2591,12 @@ CONFIG_DVB_AS102=m # CONFIG_ANDROID is not set # CONFIG_PHONE is not set CONFIG_USB_WPAN_HCD=m +# CONFIG_IPACK_BUS is not set +CONFIG_WIMAX_GDM72XX=m +# CONFIG_WIMAX_GDM72XX_QOS is not set +# CONFIG_WIMAX_GDM72XX_K_MODE is not set +# CONFIG_WIMAX_GDM72XX_WIMAX2 is not set +CONFIG_WIMAX_GDM72XX_USB=y # # Hardware Spinlock drivers @@ -2493,6 +2612,11 @@ CONFIG_USB_WPAN_HCD=m # # CONFIG_VIRT_DRIVERS is not set # CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +# CONFIG_VME_BUS is not set +# CONFIG_PWM is not set # # File systems @@ -2573,6 +2697,7 @@ CONFIG_TMPFS=y CONFIG_MISC_FILESYSTEMS=y # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set CONFIG_HFS_FS=y CONFIG_HFSPLUS_FS=y # CONFIG_BEFS_FS is not set @@ -2594,11 +2719,9 @@ CONFIG_JFFS2_RUBIN=y # CONFIG_JFFS2_CMODE_SIZE is not set CONFIG_JFFS2_CMODE_FAVOURLZO=y CONFIG_UBIFS_FS=y -# CONFIG_UBIFS_FS_XATTR is not set # CONFIG_UBIFS_FS_ADVANCED_COMPR is not set CONFIG_UBIFS_FS_LZO=y CONFIG_UBIFS_FS_ZLIB=y -# CONFIG_UBIFS_FS_DEBUG is not set # CONFIG_LOGFS is not set # CONFIG_CRAMFS is not set CONFIG_SQUASHFS=m @@ -2622,10 +2745,17 @@ CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_UFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y +CONFIG_NFS_V2=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set -# CONFIG_NFS_V4 is not set +CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y +CONFIG_NFS_V4_1=y +CONFIG_PNFS_FILE_LAYOUT=m +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" CONFIG_ROOT_NFS=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y CONFIG_NFSD=m CONFIG_NFSD_V3=y # CONFIG_NFSD_V3_ACL is not set @@ -2634,13 +2764,18 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_SUNRPC_BACKCHANNEL=y +CONFIG_SUNRPC_SWAP=y # CONFIG_SUNRPC_DEBUG is not set # CONFIG_CEPH_FS is not set CONFIG_CIFS=y # CONFIG_CIFS_STATS is not set # CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_UPCALL is not set # CONFIG_CIFS_XATTR is not set # CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DFS_UPCALL is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set @@ -2683,6 +2818,17 @@ CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=y CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set CONFIG_NLS_UTF8=y # @@ -2696,6 +2842,7 @@ CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 CONFIG_FRAME_WARN=0 # CONFIG_MAGIC_SYSRQ is not set # CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set @@ -2704,6 +2851,8 @@ CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set # CONFIG_LOCKUP_DETECTOR is not set # CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 # CONFIG_DETECT_HUNG_TASK is not set # CONFIG_SCHED_DEBUG is not set # CONFIG_SCHEDSTATS is not set @@ -2741,6 +2890,7 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=60 # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_DEBUG_PAGEALLOC is not set CONFIG_HAVE_FUNCTION_TRACER=y @@ -2767,7 +2917,9 @@ CONFIG_CMDLINE="bmem=130M ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs conso # # Security options # -# CONFIG_KEYS is not set +CONFIG_KEYS=y +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set # CONFIG_SECURITY_DMESG_RESTRICT is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set @@ -2828,7 +2980,7 @@ CONFIG_CRYPTO_HMAC=y # # Digest # -# CONFIG_CRYPTO_CRC32C is not set +CONFIG_CRYPTO_CRC32C=y # CONFIG_CRYPTO_GHASH is not set CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y @@ -2912,5 +3064,7 @@ CONFIG_CPU_RMAP=y CONFIG_DQL=y CONFIG_NLATTR=y CONFIG_GENERIC_ATOMIC64=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y CONFIG_AVERAGE=y # CONFIG_CORDIC is not set +# CONFIG_DDR is not set diff --git a/meta-openpli/recipes-linux/linux/linux-etxx00/et6x00/defconfig b/meta-openpli/recipes-linux/linux/linux-etxx00/et6x00/defconfig index c753e41cc0..5180ed680a 100644 --- a/meta-openpli/recipes-linux/linux/linux-etxx00/et6x00/defconfig +++ b/meta-openpli/recipes-linux/linux/linux-etxx00/et6x00/defconfig @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/mips 3.4.0 Kernel Configuration +# Linux/mips 3.6.0 Kernel Configuration # CONFIG_MIPS=y @@ -20,6 +20,7 @@ CONFIG_BRCMSTB=y # CONFIG_LANTIQ is not set # CONFIG_LASAT is not set # CONFIG_MACH_LOONGSON is not set +# CONFIG_MACH_LOONGSON1 is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SIM is not set # CONFIG_NEC_MARKEINS is not set @@ -134,14 +135,11 @@ CONFIG_BRCM_UPPER_256MB=y CONFIG_BRCM_HAS_1GB_MEMC0=y CONFIG_BRCM_PLATFORM_DEFAULTS=y CONFIG_BCM7405=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_BOOT_RAW=y CONFIG_CEVT_R4K_LIB=y @@ -189,6 +187,7 @@ CONFIG_MIPS_MT_DISABLED=y CONFIG_CPU_HAS_SYNC=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_SELECT_MEMORY_MODEL=y # CONFIG_FLATMEM_MANUAL is not set CONFIG_SPARSEMEM_MANUAL=y @@ -205,14 +204,12 @@ CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_CROSS_MEMORY_ATTACH is not set # CONFIG_CLEANCACHE is not set +# CONFIG_FRONTSWAP is not set CONFIG_SMP=y CONFIG_SYS_SUPPORTS_SMP=y CONFIG_NR_CPUS=2 -CONFIG_TICK_ONESHOT=y -# CONFIG_NO_HZ is not set -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_HZ_48 is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_128 is not set @@ -232,6 +229,7 @@ CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" CONFIG_HAVE_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y # # General setup @@ -258,7 +256,18 @@ CONFIG_HAVE_GENERIC_HARDIRQS=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_FORCED_THREADING=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_CMOS_UPDATE=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y # # RCU Subsystem @@ -266,6 +275,7 @@ CONFIG_IRQ_FORCED_THREADING=y CONFIG_TREE_RCU=y # CONFIG_PREEMPT_RCU is not set CONFIG_RCU_FANOUT=32 +CONFIG_RCU_FANOUT_LEAF=16 # CONFIG_RCU_FANOUT_EXACT is not set # CONFIG_TREE_RCU_TRACE is not set # CONFIG_IKCONFIG is not set @@ -305,7 +315,6 @@ CONFIG_PERF_USE_VMALLOC=y # Kernel Performance Events And Counters # # CONFIG_PERF_EVENTS is not set -# CONFIG_PERF_COUNTERS is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_PCI_QUIRKS=y CONFIG_COMPAT_BRK=y @@ -320,8 +329,11 @@ CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_DMA_ATTRS=y CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_HAVE_CLK=y CONFIG_HAVE_DMA_API_DEBUG=y CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y # # GCOV-based kernel profiling @@ -417,6 +429,7 @@ CONFIG_PCI_DOMAINS=y # CONFIG_PCI_IOV is not set # CONFIG_PCI_PRI is not set # CONFIG_PCI_PASID is not set +# CONFIG_PCIEPORTBUS is not set CONFIG_MMU=y # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -449,6 +462,7 @@ CONFIG_PACKET=y CONFIG_UNIX=y # CONFIG_UNIX_DIAG is not set CONFIG_XFRM=y +CONFIG_XFRM_ALGO=m # CONFIG_XFRM_USER is not set # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set @@ -530,6 +544,7 @@ CONFIG_NETFILTER_XTABLES=m # Xtables targets # # CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_HMARK is not set # CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set # CONFIG_NETFILTER_XT_TARGET_LED is not set # CONFIG_NETFILTER_XT_TARGET_LOG is not set @@ -596,7 +611,6 @@ CONFIG_IP_NF_TARGET_REJECT=m # IPv6: Netfilter Configuration # # CONFIG_NF_DEFRAG_IPV6 is not set -# CONFIG_IP6_NF_QUEUE is not set CONFIG_IP6_NF_IPTABLES=m # CONFIG_IP6_NF_MATCH_AH is not set # CONFIG_IP6_NF_MATCH_EUI64 is not set @@ -626,12 +640,12 @@ CONFIG_IP6_NF_TARGET_REJECT=m # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set -# CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set # CONFIG_PHONET is not set # CONFIG_IEEE802154 is not set # CONFIG_NET_SCHED is not set # CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y # CONFIG_BATMAN_ADV is not set # CONFIG_OPENVSWITCH is not set CONFIG_RPS=y @@ -663,6 +677,7 @@ CONFIG_BT_HCIUART_H4=y CONFIG_BT_HCIUART_BCSP=y # CONFIG_BT_HCIUART_ATH3K is not set CONFIG_BT_HCIUART_LL=y +# CONFIG_BT_HCIUART_3WIRE is not set CONFIG_BT_HCIBCM203X=m CONFIG_BT_HCIBPA10X=m CONFIG_BT_HCIBFUSB=m @@ -680,10 +695,10 @@ CONFIG_CFG80211=y # CONFIG_NL80211_TESTMODE is not set # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set # CONFIG_CFG80211_REG_DEBUG is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set CONFIG_CFG80211_DEFAULT_PS=y # CONFIG_CFG80211_INTERNAL_REGDB is not set CONFIG_CFG80211_WEXT=y -CONFIG_WIRELESS_EXT_SYSFS=y CONFIG_LIB80211=y CONFIG_LIB80211_CRYPT_WEP=m CONFIG_LIB80211_CRYPT_CCMP=m @@ -698,6 +713,7 @@ CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" # CONFIG_MAC80211_MESH is not set CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_MESSAGE_TRACING is not set # CONFIG_MAC80211_DEBUG_MENU is not set # CONFIG_WIMAX is not set CONFIG_RFKILL=y @@ -826,7 +842,6 @@ CONFIG_MTD_UBI=y CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MTD_UBI_BEB_RESERVE=1 # CONFIG_MTD_UBI_GLUEBI is not set -# CONFIG_MTD_UBI_DEBUG is not set # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set @@ -860,6 +875,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # # CONFIG_SENSORS_LIS3LV02D is not set # CONFIG_AD525X_DPOT is not set +# CONFIG_ATMEL_PWM is not set # CONFIG_PHANTOM is not set # CONFIG_INTEL_MID_PTI is not set # CONFIG_SGI_IOC4 is not set @@ -876,7 +892,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_SENSORS_APDS990X is not set # CONFIG_HMC6352 is not set # CONFIG_DS1682 is not set -# CONFIG_BMP085 is not set +# CONFIG_BMP085_I2C is not set # CONFIG_PCH_PHUB is not set # CONFIG_USB_SWITCH_FSA9480 is not set # CONFIG_C2PORT is not set @@ -927,7 +943,6 @@ CONFIG_CHR_DEV_SG=y # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set # CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m # # SCSI Transports @@ -1164,6 +1179,7 @@ CONFIG_NET_VENDOR_BROADCOM=y # CONFIG_NET_VENDOR_TI is not set # CONFIG_NET_VENDOR_TOSHIBA is not set # CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_PHYLIB is not set @@ -1178,7 +1194,6 @@ CONFIG_PPP_ASYNC=m CONFIG_PPP_SYNC_TTY=m # CONFIG_SLIP is not set CONFIG_SLHC=m -# CONFIG_TR is not set # # USB Network Adapters @@ -1215,7 +1230,6 @@ CONFIG_ATH9K_BTCOEX_SUPPORT=y CONFIG_ATH9K=m # CONFIG_ATH9K_PCI is not set # CONFIG_ATH9K_AHB is not set -# CONFIG_ATH9K_DFS_CERTIFIED is not set CONFIG_ATH9K_RATE_CONTROL=y CONFIG_ATH9K_HTC=m CONFIG_CARL9170=m @@ -1239,6 +1253,7 @@ CONFIG_HOSTAP_FIRMWARE=y # CONFIG_IPW2100 is not set # CONFIG_IPW2200 is not set CONFIG_IWLWIFI=m +CONFIG_IWLDVM=m # # Debugging Options @@ -1280,12 +1295,16 @@ CONFIG_RT2X00_LIB_LEDS=y # CONFIG_RTL8192SE is not set # CONFIG_RTL8192DE is not set # CONFIG_RTL8192CU is not set +CONFIG_WL_TI=y CONFIG_WL1251=m -# CONFIG_WL12XX_MENU is not set +CONFIG_WL12XX=m +CONFIG_WL18XX=m +CONFIG_WLCORE=m CONFIG_ZD1211RW=m # CONFIG_ZD1211RW_DEBUG is not set CONFIG_MWIFIEX=y # CONFIG_MWIFIEX_PCIE is not set +CONFIG_MWIFIEX_USB=m # # Enable WiMAX (Networking options) to see the WiMAX drivers @@ -1301,6 +1320,7 @@ CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set CONFIG_INPUT_POLLDEV=m # CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set # # Userland interfaces @@ -1326,11 +1346,13 @@ CONFIG_INPUT_KEYBOARD=y # CONFIG_KEYBOARD_TCA6416 is not set # CONFIG_KEYBOARD_TCA8418 is not set # CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set # CONFIG_KEYBOARD_MAX7359 is not set # CONFIG_KEYBOARD_MCS is not set # CONFIG_KEYBOARD_MPR121 is not set # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set # CONFIG_KEYBOARD_STOWAWAY is not set # CONFIG_KEYBOARD_SUNKBD is not set # CONFIG_KEYBOARD_OMAP4 is not set @@ -1397,18 +1419,20 @@ CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y # CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_ATMEL is not set +# CONFIG_HW_RANDOM_EXYNOS is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y -# CONFIG_RAMOOPS is not set CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=y # CONFIG_I2C_MUX is not set CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=m # # I2C Hardware Bus support @@ -1435,6 +1459,7 @@ CONFIG_I2C_HELPER_AUTO=y # # I2C system bus drivers (mostly embedded / system-on-chip) # +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set # CONFIG_I2C_DESIGNWARE_PCI is not set # CONFIG_I2C_EG20T is not set # CONFIG_I2C_INTEL_MID is not set @@ -1478,8 +1503,23 @@ CONFIG_I2C_HELPER_AUTO=y # # Enable Device Drivers -> PPS to see the PTP clock options. # +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y # CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_POWER_AVS is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set # CONFIG_WATCHDOG is not set @@ -1499,10 +1539,13 @@ CONFIG_BCMA_POSSIBLE=y # # Multifunction device drivers # -# CONFIG_MFD_CORE is not set +CONFIG_MFD_CORE=m # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_LM3533 is not set # CONFIG_TPS6105X is not set # CONFIG_TPS6507X is not set # CONFIG_MFD_TPS65217 is not set @@ -1514,60 +1557,57 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_PMIC_DA903X is not set # CONFIG_MFD_DA9052_I2C is not set # CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set # CONFIG_MFD_MAX8925 is not set # CONFIG_MFD_MAX8997 is not set # CONFIG_MFD_MAX8998 is not set -# CONFIG_MFD_S5M_CORE is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_ARIZONA_I2C is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM831X_I2C is not set # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set # CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13XXX_I2C is not set # CONFIG_ABX500_CORE is not set # CONFIG_LPC_SCH is not set +# CONFIG_LPC_ICH is not set # CONFIG_MFD_RDC321X is not set # CONFIG_MFD_JANZ_CMODIO is not set # CONFIG_MFD_VX855 is not set -# CONFIG_MFD_WL1273_CORE is not set +CONFIG_MFD_WL1273_CORE=m # CONFIG_MFD_TPS65090 is not set # CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_PALMAS is not set # CONFIG_REGULATOR is not set CONFIG_MEDIA_SUPPORT=y # # Multimedia core support # +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_RC_SUPPORT=y # CONFIG_MEDIA_CONTROLLER is not set -CONFIG_VIDEO_DEV=m -CONFIG_VIDEO_V4L2_COMMON=m +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y CONFIG_DVB_CORE=y CONFIG_DVB_NET=y -CONFIG_VIDEO_MEDIA=m # -# Multimedia drivers +# Media drivers # +CONFIG_VIDEO_SAA7146=m +CONFIG_VIDEO_SAA7146_VV=m CONFIG_RC_CORE=y -CONFIG_LIRC=y CONFIG_RC_MAP=y -CONFIG_IR_NEC_DECODER=y -CONFIG_IR_RC5_DECODER=y -CONFIG_IR_RC6_DECODER=y -CONFIG_IR_JVC_DECODER=y -CONFIG_IR_SONY_DECODER=y -CONFIG_IR_RC5_SZ_DECODER=y -CONFIG_IR_SANYO_DECODER=y -CONFIG_IR_MCE_KBD_DECODER=y -CONFIG_IR_LIRC_CODEC=y -# CONFIG_RC_ATI_REMOTE is not set -# CONFIG_IR_IMON is not set -# CONFIG_IR_MCEUSB is not set -# CONFIG_IR_REDRAT3 is not set -# CONFIG_IR_STREAMZAP is not set -# CONFIG_RC_LOOPBACK is not set -# CONFIG_IR_GPIO_CIR is not set +# CONFIG_RC_DECODERS is not set +# CONFIG_RC_DEVICES is not set # CONFIG_MEDIA_ATTACH is not set -CONFIG_MEDIA_TUNER=m +CONFIG_MEDIA_TUNER=y CONFIG_MEDIA_TUNER_CUSTOMISE=y # @@ -1594,18 +1634,27 @@ CONFIG_MEDIA_TUNER_MXL5007T=m CONFIG_MEDIA_TUNER_MC44S803=m CONFIG_MEDIA_TUNER_MAX2165=m CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_FC0011=m +CONFIG_MEDIA_TUNER_FC0012=m +CONFIG_MEDIA_TUNER_FC0013=m CONFIG_MEDIA_TUNER_TDA18212=m -CONFIG_VIDEO_V4L2=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_VIDEO_V4L2=y CONFIG_VIDEOBUF_GEN=m +CONFIG_VIDEOBUF_DMA_SG=m CONFIG_VIDEOBUF_VMALLOC=m CONFIG_VIDEOBUF_DVB=m CONFIG_VIDEO_TVEEPROM=m CONFIG_VIDEO_TUNER=m +CONFIG_VIDEOBUF2_CORE=m +CONFIG_VIDEOBUF2_MEMOPS=m +CONFIG_VIDEOBUF2_DMA_CONTIG=m +CONFIG_VIDEOBUF2_VMALLOC=m CONFIG_VIDEO_CAPTURE_DRIVERS=y # CONFIG_VIDEO_ADV_DEBUG is not set # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set # CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set -CONFIG_VIDEO_IR_I2C=m +# CONFIG_VIDEO_IR_I2C is not set # # Encoders, decoders, sensors and other helper chips @@ -1619,11 +1668,11 @@ CONFIG_VIDEO_IR_I2C=m # CONFIG_VIDEO_TDA9840 is not set # CONFIG_VIDEO_TEA6415C is not set # CONFIG_VIDEO_TEA6420 is not set -# CONFIG_VIDEO_MSP3400 is not set +CONFIG_VIDEO_MSP3400=m # CONFIG_VIDEO_CS5345 is not set -# CONFIG_VIDEO_CS53L32A is not set +CONFIG_VIDEO_CS53L32A=m # CONFIG_VIDEO_TLV320AIC23B is not set -# CONFIG_VIDEO_WM8775 is not set +CONFIG_VIDEO_WM8775=m # CONFIG_VIDEO_WM8739 is not set # CONFIG_VIDEO_VP27SMPX is not set @@ -1642,7 +1691,7 @@ CONFIG_VIDEO_IR_I2C=m # CONFIG_VIDEO_BT866 is not set # CONFIG_VIDEO_KS0127 is not set # CONFIG_VIDEO_SAA7110 is not set -# CONFIG_VIDEO_SAA711X is not set +CONFIG_VIDEO_SAA711X=m # CONFIG_VIDEO_SAA7191 is not set # CONFIG_VIDEO_TVP514X is not set # CONFIG_VIDEO_TVP5150 is not set @@ -1653,12 +1702,12 @@ CONFIG_VIDEO_IR_I2C=m # Video and audio decoders # # CONFIG_VIDEO_SAA717X is not set -# CONFIG_VIDEO_CX25840 is not set +CONFIG_VIDEO_CX25840=m # # MPEG video encoders # -# CONFIG_VIDEO_CX2341X is not set +CONFIG_VIDEO_CX2341X=m # # Video encoders @@ -1668,12 +1717,13 @@ CONFIG_VIDEO_IR_I2C=m # CONFIG_VIDEO_ADV7170 is not set # CONFIG_VIDEO_ADV7175 is not set # CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set # CONFIG_VIDEO_AK881X is not set # # Camera sensor devices # -# CONFIG_VIDEO_OV7670 is not set +CONFIG_VIDEO_OV7670=m # CONFIG_VIDEO_VS6624 is not set # CONFIG_VIDEO_MT9V011 is not set # CONFIG_VIDEO_TCM825X is not set @@ -1696,87 +1746,115 @@ CONFIG_VIDEO_IR_I2C=m # CONFIG_VIDEO_M52790 is not set # CONFIG_VIDEO_VIVI is not set CONFIG_V4L_USB_DRIVERS=y -# CONFIG_USB_VIDEO_CLASS is not set + +# +# Webcam devices +# +CONFIG_USB_VIDEO_CLASS=m CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y CONFIG_USB_GSPCA=m -# CONFIG_USB_M5602 is not set -# CONFIG_USB_STV06XX is not set -# CONFIG_USB_GL860 is not set -# CONFIG_USB_GSPCA_BENQ is not set -# CONFIG_USB_GSPCA_CONEX is not set -# CONFIG_USB_GSPCA_CPIA1 is not set -# CONFIG_USB_GSPCA_ETOMS is not set -# CONFIG_USB_GSPCA_FINEPIX is not set -# CONFIG_USB_GSPCA_JEILINJ is not set -# CONFIG_USB_GSPCA_JL2005BCD is not set -# CONFIG_USB_GSPCA_KINECT is not set -# CONFIG_USB_GSPCA_KONICA is not set -# CONFIG_USB_GSPCA_MARS is not set -# CONFIG_USB_GSPCA_MR97310A is not set -# CONFIG_USB_GSPCA_NW80X is not set -# CONFIG_USB_GSPCA_OV519 is not set -# CONFIG_USB_GSPCA_OV534 is not set -# CONFIG_USB_GSPCA_OV534_9 is not set -# CONFIG_USB_GSPCA_PAC207 is not set -# CONFIG_USB_GSPCA_PAC7302 is not set -# CONFIG_USB_GSPCA_PAC7311 is not set -# CONFIG_USB_GSPCA_SE401 is not set -# CONFIG_USB_GSPCA_SN9C2028 is not set -# CONFIG_USB_GSPCA_SN9C20X is not set -# CONFIG_USB_GSPCA_SONIXB is not set -# CONFIG_USB_GSPCA_SONIXJ is not set -# CONFIG_USB_GSPCA_SPCA500 is not set -# CONFIG_USB_GSPCA_SPCA501 is not set -# CONFIG_USB_GSPCA_SPCA505 is not set -# CONFIG_USB_GSPCA_SPCA506 is not set -# CONFIG_USB_GSPCA_SPCA508 is not set -# CONFIG_USB_GSPCA_SPCA561 is not set -# CONFIG_USB_GSPCA_SPCA1528 is not set -# CONFIG_USB_GSPCA_SQ905 is not set -# CONFIG_USB_GSPCA_SQ905C is not set -# CONFIG_USB_GSPCA_SQ930X is not set -# CONFIG_USB_GSPCA_STK014 is not set -# CONFIG_USB_GSPCA_STV0680 is not set -# CONFIG_USB_GSPCA_SUNPLUS is not set -# CONFIG_USB_GSPCA_T613 is not set -# CONFIG_USB_GSPCA_TOPRO is not set -# CONFIG_USB_GSPCA_TV8532 is not set -# CONFIG_USB_GSPCA_VC032X is not set -# CONFIG_USB_GSPCA_VICAM is not set -# CONFIG_USB_GSPCA_XIRLINK_CIT is not set -# CONFIG_USB_GSPCA_ZC3XX is not set -# CONFIG_VIDEO_PVRUSB2 is not set -# CONFIG_VIDEO_HDPVR is not set +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_GL860=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_PWC=m +# CONFIG_USB_PWC_DEBUG is not set +CONFIG_USB_PWC_INPUT_EVDEV=y +CONFIG_VIDEO_CPIA2=m +CONFIG_USB_ZR364XX=m +CONFIG_USB_STKWEBCAM=m +CONFIG_USB_S2255=m +CONFIG_USB_SN9C102=m + +# +# Webcam and/or TV USB devices +# CONFIG_VIDEO_EM28XX=m CONFIG_VIDEO_EM28XX_ALSA=m CONFIG_VIDEO_EM28XX_DVB=m -CONFIG_VIDEO_EM28XX_RC=y -# CONFIG_VIDEO_TLG2300 is not set -# CONFIG_VIDEO_CX231XX is not set -# CONFIG_VIDEO_TM6000 is not set -# CONFIG_VIDEO_USBVISION is not set -# CONFIG_USB_ET61X251 is not set -# CONFIG_USB_SN9C102 is not set -# CONFIG_USB_PWC is not set -# CONFIG_VIDEO_CPIA2 is not set -# CONFIG_USB_ZR364XX is not set -# CONFIG_USB_STKWEBCAM is not set -# CONFIG_USB_S2255 is not set +CONFIG_VIDEO_EM28XX_RC=m + +# +# TV USB devices +# +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_PVRUSB2_DVB=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_TLG2300=m +CONFIG_VIDEO_CX231XX=m +# CONFIG_VIDEO_CX231XX_RC is not set +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_TM6000_DVB=m +CONFIG_VIDEO_USBVISION=m # CONFIG_V4L_PCI_DRIVERS is not set -# CONFIG_V4L_PLATFORM_DRIVERS is not set +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_CAFE_CCIC=m +# CONFIG_SOC_CAMERA is not set # CONFIG_V4L_MEM2MEM_DRIVERS is not set CONFIG_RADIO_ADAPTERS=y -# CONFIG_RADIO_SI470X is not set -# CONFIG_USB_MR800 is not set -# CONFIG_USB_DSBR is not set -# CONFIG_RADIO_MAXIRADIO is not set -# CONFIG_I2C_SI4713 is not set -# CONFIG_RADIO_SI4713 is not set -# CONFIG_USB_KEENE is not set -# CONFIG_RADIO_TEA5764 is not set -# CONFIG_RADIO_SAA7706H is not set -# CONFIG_RADIO_TEF6862 is not set -# CONFIG_RADIO_WL1273 is not set +CONFIG_RADIO_SI470X=y +CONFIG_USB_SI470X=m +CONFIG_I2C_SI470X=m +CONFIG_USB_MR800=m +CONFIG_USB_DSBR=m +CONFIG_RADIO_MAXIRADIO=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_I2C_SI4713=m +CONFIG_RADIO_SI4713=m +CONFIG_USB_KEENE=m +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_TEF6862=m +CONFIG_RADIO_WL1273=m # # Texas Instruments WL128x FM driver (ST based) @@ -1789,13 +1867,14 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # Supported SAA7146 based PCI Adapters # CONFIG_TTPCI_EEPROM=m -# CONFIG_DVB_AV7110 is not set +CONFIG_DVB_AV7110=m +# CONFIG_DVB_AV7110_OSD is not set # CONFIG_DVB_BUDGET_CORE is not set # # Supported USB Adapters # -CONFIG_DVB_USB=y +CONFIG_DVB_USB=m # CONFIG_DVB_USB_DEBUG is not set CONFIG_DVB_USB_A800=m CONFIG_DVB_USB_DIBUSB_MB=m @@ -1816,7 +1895,7 @@ CONFIG_DVB_USB_TTUSB2=m CONFIG_DVB_USB_DTT200U=m CONFIG_DVB_USB_OPERA1=m CONFIG_DVB_USB_AF9005=m -CONFIG_DVB_USB_AF9005_REMOTE=m +# CONFIG_DVB_USB_AF9005_REMOTE is not set CONFIG_DVB_USB_PCTV452E=m CONFIG_DVB_USB_DW2102=m CONFIG_DVB_USB_CINERGY_T2=m @@ -1833,6 +1912,7 @@ CONFIG_DVB_USB_TECHNISAT_USB2=m CONFIG_DVB_USB_IT913X=m CONFIG_DVB_USB_MXL111SF=m CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_AF9035=m # CONFIG_DVB_TTUSB_BUDGET is not set # CONFIG_DVB_TTUSB_DEC is not set CONFIG_SMS_SIANO_MDTV=m @@ -1958,6 +2038,7 @@ CONFIG_DVB_HD29L2=m CONFIG_DVB_STV0367=m CONFIG_DVB_CXD2820R=m CONFIG_DVB_RTL2830=m +CONFIG_DVB_RTL2832=m # # DVB-C (cable) frontends @@ -1976,8 +2057,11 @@ CONFIG_DVB_OR51132=m CONFIG_DVB_BCM3510=m CONFIG_DVB_LGDT330X=m CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LG2160=m CONFIG_DVB_S5H1409=m CONFIG_DVB_AU8522=m +CONFIG_DVB_AU8522_DTV=m +CONFIG_DVB_AU8522_V4L=m CONFIG_DVB_S5H1411=m # @@ -2010,6 +2094,7 @@ CONFIG_DVB_TDA665x=m CONFIG_DVB_IX2505V=m CONFIG_DVB_IT913X_FE=m CONFIG_DVB_M88RS2000=m +CONFIG_DVB_AF9033=m # # Tools to develop new frontends @@ -2072,12 +2157,14 @@ CONFIG_FB=y # CONFIG_FB_ARK is not set # CONFIG_FB_PM3 is not set # CONFIG_FB_CARMINE is not set +# CONFIG_FB_TMIO is not set # CONFIG_FB_SMSCUFX is not set # CONFIG_FB_UDL is not set # CONFIG_FB_VIRTUAL is not set # CONFIG_FB_METRONOME is not set # CONFIG_FB_MB862XX is not set # CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_AUO_K190X is not set # CONFIG_EXYNOS_VIDEO is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set @@ -2129,21 +2216,21 @@ CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_SBAWE_SEQ is not set # CONFIG_SND_EMU10K1_SEQ is not set # CONFIG_SND_DRIVERS is not set +CONFIG_SND_TEA575X=m # CONFIG_SND_PCI is not set # CONFIG_SND_MIPS is not set # CONFIG_SND_USB is not set # CONFIG_SND_SOC is not set # CONFIG_SOUND_PRIME is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -CONFIG_HIDRAW=y # -# USB Input Devices +# HID support # -CONFIG_USB_HID=y -# CONFIG_HID_PID is not set -CONFIG_USB_HIDDEV=y +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +CONFIG_HIDRAW=y +# CONFIG_UHID is not set +CONFIG_HID_GENERIC=y # # Special HID drivers @@ -2151,6 +2238,7 @@ CONFIG_USB_HIDDEV=y # CONFIG_HID_A4TECH is not set # CONFIG_HID_ACRUX is not set # CONFIG_HID_APPLE is not set +# CONFIG_HID_AUREAL is not set # CONFIG_HID_BELKIN is not set # CONFIG_HID_CHERRY is not set # CONFIG_HID_CHICONY is not set @@ -2169,6 +2257,7 @@ CONFIG_USB_HIDDEV=y # CONFIG_HID_TWINHAN is not set # CONFIG_HID_KENSINGTON is not set # CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LENOVO_TPKBD is not set CONFIG_HID_LOGITECH=y CONFIG_HID_LOGITECH_DJ=y # CONFIG_LOGITECH_FF is not set @@ -2197,10 +2286,16 @@ CONFIG_HID_LOGITECH_DJ=y # CONFIG_HID_TOPSEED is not set # CONFIG_HID_THRUSTMASTER is not set CONFIG_HID_WACOM=m -# CONFIG_HID_WACOM_POWER_SUPPLY is not set # CONFIG_HID_WIIMOTE is not set # CONFIG_HID_ZEROPLUS is not set # CONFIG_HID_ZYDACRON is not set + +# +# USB HID support +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +CONFIG_USB_HIDDEV=y CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y CONFIG_USB_ARCH_HAS_XHCI=y @@ -2214,8 +2309,6 @@ CONFIG_USB=y # # Miscellaneous USB options # -CONFIG_USB_DEVICEFS=y -CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set @@ -2236,6 +2329,7 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_CHIPIDEA is not set # # USB Device Class drivers @@ -2301,7 +2395,7 @@ CONFIG_USB_SERIAL_FTDI_SIO=m CONFIG_USB_SERIAL_F81232=m # CONFIG_USB_SERIAL_GARMIN is not set # CONFIG_USB_SERIAL_IPW is not set -CONFIG_USB_SERIAL_IUU=m +# CONFIG_USB_SERIAL_IUU is not set # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set CONFIG_USB_SERIAL_KEYSPAN=m # CONFIG_USB_SERIAL_KEYSPAN_MPR is not set @@ -2344,6 +2438,7 @@ CONFIG_USB_SERIAL_OPTION=m # CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set # CONFIG_USB_SERIAL_ZIO is not set # CONFIG_USB_SERIAL_SSU100 is not set +# CONFIG_USB_SERIAL_QT2 is not set # CONFIG_USB_SERIAL_DEBUG is not set # @@ -2368,6 +2463,11 @@ CONFIG_USB_SERIAL_OPTION=m # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set # CONFIG_USB_YUREX is not set + +# +# USB Physical Layer drivers +# +# CONFIG_USB_ISP1301 is not set # CONFIG_USB_GADGET is not set # @@ -2392,13 +2492,16 @@ CONFIG_LEDS_CLASS=y # CONFIG_LEDS_PCA9633 is not set # CONFIG_LEDS_BD2802 is not set # CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_LM3556 is not set # CONFIG_LEDS_OT200 is not set +# CONFIG_LEDS_BLINKM is not set CONFIG_LEDS_TRIGGERS=y # # LED Triggers # # CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_ONESHOT is not set # CONFIG_LEDS_TRIGGER_HEARTBEAT is not set # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set @@ -2406,6 +2509,7 @@ CONFIG_LEDS_TRIGGERS=y # # iptables trigger is under Netfilter config (LED target) # +# CONFIG_LEDS_TRIGGER_TRANSIENT is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_RTC_LIB=y @@ -2445,12 +2549,10 @@ CONFIG_R8712U=m # CONFIG_IDE_PHISON is not set # CONFIG_LINE6_USB is not set # CONFIG_USB_SERIAL_QUATECH2 is not set -# CONFIG_USB_SERIAL_QUATECH_USB2 is not set # CONFIG_VT6655 is not set # CONFIG_VT6656 is not set -# CONFIG_VME_BUS is not set # CONFIG_DX_SEP is not set -# CONFIG_IIO is not set +# CONFIG_ZSMALLOC is not set # CONFIG_FB_SM7XX is not set # CONFIG_CRYSTALHD is not set # CONFIG_FB_XGI is not set @@ -2466,11 +2568,22 @@ CONFIG_R8712U=m CONFIG_STAGING_MEDIA=y CONFIG_DVB_AS102=m # CONFIG_DVB_CXD2099 is not set -# CONFIG_VIDEO_DT3155 is not set -# CONFIG_EASYCAP is not set -# CONFIG_VIDEO_GO7007 is not set -# CONFIG_SOLO6X10 is not set -# CONFIG_LIRC_STAGING is not set +CONFIG_VIDEO_DT3155=m +CONFIG_DT3155_CCIR=y +CONFIG_DT3155_STREAMING=y +CONFIG_EASYCAP=m +# CONFIG_EASYCAP_DEBUG is not set +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m +CONFIG_VIDEO_GO7007_OV7640=m +CONFIG_VIDEO_GO7007_SAA7113=m +CONFIG_VIDEO_GO7007_SAA7115=m +CONFIG_VIDEO_GO7007_TW9903=m +CONFIG_VIDEO_GO7007_UDA1342=m +CONFIG_VIDEO_GO7007_SONY_TUNER=m +CONFIG_VIDEO_GO7007_TW2804=m +CONFIG_SOLO6X10=m # # Android @@ -2478,6 +2591,12 @@ CONFIG_DVB_AS102=m # CONFIG_ANDROID is not set # CONFIG_PHONE is not set CONFIG_USB_WPAN_HCD=m +# CONFIG_IPACK_BUS is not set +CONFIG_WIMAX_GDM72XX=m +# CONFIG_WIMAX_GDM72XX_QOS is not set +# CONFIG_WIMAX_GDM72XX_K_MODE is not set +# CONFIG_WIMAX_GDM72XX_WIMAX2 is not set +CONFIG_WIMAX_GDM72XX_USB=y # # Hardware Spinlock drivers @@ -2493,6 +2612,11 @@ CONFIG_USB_WPAN_HCD=m # # CONFIG_VIRT_DRIVERS is not set # CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +# CONFIG_VME_BUS is not set +# CONFIG_PWM is not set # # File systems @@ -2573,6 +2697,7 @@ CONFIG_TMPFS=y CONFIG_MISC_FILESYSTEMS=y # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set CONFIG_HFS_FS=y CONFIG_HFSPLUS_FS=y # CONFIG_BEFS_FS is not set @@ -2594,11 +2719,9 @@ CONFIG_JFFS2_RUBIN=y # CONFIG_JFFS2_CMODE_SIZE is not set CONFIG_JFFS2_CMODE_FAVOURLZO=y CONFIG_UBIFS_FS=y -# CONFIG_UBIFS_FS_XATTR is not set # CONFIG_UBIFS_FS_ADVANCED_COMPR is not set CONFIG_UBIFS_FS_LZO=y CONFIG_UBIFS_FS_ZLIB=y -# CONFIG_UBIFS_FS_DEBUG is not set # CONFIG_LOGFS is not set # CONFIG_CRAMFS is not set CONFIG_SQUASHFS=m @@ -2622,10 +2745,17 @@ CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_UFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y +CONFIG_NFS_V2=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set -# CONFIG_NFS_V4 is not set +CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y +CONFIG_NFS_V4_1=y +CONFIG_PNFS_FILE_LAYOUT=m +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" CONFIG_ROOT_NFS=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y CONFIG_NFSD=m CONFIG_NFSD_V3=y # CONFIG_NFSD_V3_ACL is not set @@ -2634,13 +2764,18 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_SUNRPC_BACKCHANNEL=y +CONFIG_SUNRPC_SWAP=y # CONFIG_SUNRPC_DEBUG is not set # CONFIG_CEPH_FS is not set CONFIG_CIFS=y # CONFIG_CIFS_STATS is not set # CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_UPCALL is not set # CONFIG_CIFS_XATTR is not set # CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DFS_UPCALL is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set @@ -2683,6 +2818,17 @@ CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=y CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set CONFIG_NLS_UTF8=y # @@ -2696,6 +2842,7 @@ CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 CONFIG_FRAME_WARN=0 # CONFIG_MAGIC_SYSRQ is not set # CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set @@ -2704,6 +2851,8 @@ CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set # CONFIG_LOCKUP_DETECTOR is not set # CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 # CONFIG_DETECT_HUNG_TASK is not set # CONFIG_SCHED_DEBUG is not set # CONFIG_SCHEDSTATS is not set @@ -2741,6 +2890,7 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=60 # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_DEBUG_PAGEALLOC is not set CONFIG_HAVE_FUNCTION_TRACER=y @@ -2767,7 +2917,9 @@ CONFIG_CMDLINE="bmem=216M ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs conso # # Security options # -# CONFIG_KEYS is not set +CONFIG_KEYS=y +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set # CONFIG_SECURITY_DMESG_RESTRICT is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set @@ -2828,7 +2980,7 @@ CONFIG_CRYPTO_HMAC=y # # Digest # -# CONFIG_CRYPTO_CRC32C is not set +CONFIG_CRYPTO_CRC32C=y # CONFIG_CRYPTO_GHASH is not set CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y @@ -2912,5 +3064,7 @@ CONFIG_CPU_RMAP=y CONFIG_DQL=y CONFIG_NLATTR=y CONFIG_GENERIC_ATOMIC64=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y CONFIG_AVERAGE=y # CONFIG_CORDIC is not set +# CONFIG_DDR is not set diff --git a/meta-openpli/recipes-linux/linux/linux-etxx00/et9x00/defconfig b/meta-openpli/recipes-linux/linux/linux-etxx00/et9x00/defconfig index 34001dc049..5180ed680a 100644 --- a/meta-openpli/recipes-linux/linux/linux-etxx00/et9x00/defconfig +++ b/meta-openpli/recipes-linux/linux/linux-etxx00/et9x00/defconfig @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/mips 3.4.3 Kernel Configuration +# Linux/mips 3.6.0 Kernel Configuration # CONFIG_MIPS=y @@ -20,6 +20,7 @@ CONFIG_BRCMSTB=y # CONFIG_LANTIQ is not set # CONFIG_LASAT is not set # CONFIG_MACH_LOONGSON is not set +# CONFIG_MACH_LOONGSON1 is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SIM is not set # CONFIG_NEC_MARKEINS is not set @@ -134,14 +135,11 @@ CONFIG_BRCM_UPPER_256MB=y CONFIG_BRCM_HAS_1GB_MEMC0=y CONFIG_BRCM_PLATFORM_DEFAULTS=y CONFIG_BCM7405=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_BOOT_RAW=y CONFIG_CEVT_R4K_LIB=y @@ -189,6 +187,7 @@ CONFIG_MIPS_MT_DISABLED=y CONFIG_CPU_HAS_SYNC=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_SELECT_MEMORY_MODEL=y # CONFIG_FLATMEM_MANUAL is not set CONFIG_SPARSEMEM_MANUAL=y @@ -205,14 +204,12 @@ CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_CROSS_MEMORY_ATTACH is not set # CONFIG_CLEANCACHE is not set +# CONFIG_FRONTSWAP is not set CONFIG_SMP=y CONFIG_SYS_SUPPORTS_SMP=y CONFIG_NR_CPUS=2 -CONFIG_TICK_ONESHOT=y -# CONFIG_NO_HZ is not set -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_HZ_48 is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_128 is not set @@ -232,6 +229,7 @@ CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" CONFIG_HAVE_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y # # General setup @@ -258,7 +256,18 @@ CONFIG_HAVE_GENERIC_HARDIRQS=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_FORCED_THREADING=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_CMOS_UPDATE=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y # # RCU Subsystem @@ -266,6 +275,7 @@ CONFIG_IRQ_FORCED_THREADING=y CONFIG_TREE_RCU=y # CONFIG_PREEMPT_RCU is not set CONFIG_RCU_FANOUT=32 +CONFIG_RCU_FANOUT_LEAF=16 # CONFIG_RCU_FANOUT_EXACT is not set # CONFIG_TREE_RCU_TRACE is not set # CONFIG_IKCONFIG is not set @@ -305,7 +315,6 @@ CONFIG_PERF_USE_VMALLOC=y # Kernel Performance Events And Counters # # CONFIG_PERF_EVENTS is not set -# CONFIG_PERF_COUNTERS is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_PCI_QUIRKS=y CONFIG_COMPAT_BRK=y @@ -320,8 +329,11 @@ CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_DMA_ATTRS=y CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_HAVE_CLK=y CONFIG_HAVE_DMA_API_DEBUG=y CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y # # GCOV-based kernel profiling @@ -417,6 +429,7 @@ CONFIG_PCI_DOMAINS=y # CONFIG_PCI_IOV is not set # CONFIG_PCI_PRI is not set # CONFIG_PCI_PASID is not set +# CONFIG_PCIEPORTBUS is not set CONFIG_MMU=y # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -449,6 +462,7 @@ CONFIG_PACKET=y CONFIG_UNIX=y # CONFIG_UNIX_DIAG is not set CONFIG_XFRM=y +CONFIG_XFRM_ALGO=m # CONFIG_XFRM_USER is not set # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set @@ -530,6 +544,7 @@ CONFIG_NETFILTER_XTABLES=m # Xtables targets # # CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_HMARK is not set # CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set # CONFIG_NETFILTER_XT_TARGET_LED is not set # CONFIG_NETFILTER_XT_TARGET_LOG is not set @@ -596,7 +611,6 @@ CONFIG_IP_NF_TARGET_REJECT=m # IPv6: Netfilter Configuration # # CONFIG_NF_DEFRAG_IPV6 is not set -# CONFIG_IP6_NF_QUEUE is not set CONFIG_IP6_NF_IPTABLES=m # CONFIG_IP6_NF_MATCH_AH is not set # CONFIG_IP6_NF_MATCH_EUI64 is not set @@ -626,12 +640,12 @@ CONFIG_IP6_NF_TARGET_REJECT=m # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set -# CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set # CONFIG_PHONET is not set # CONFIG_IEEE802154 is not set # CONFIG_NET_SCHED is not set # CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y # CONFIG_BATMAN_ADV is not set # CONFIG_OPENVSWITCH is not set CONFIG_RPS=y @@ -663,6 +677,7 @@ CONFIG_BT_HCIUART_H4=y CONFIG_BT_HCIUART_BCSP=y # CONFIG_BT_HCIUART_ATH3K is not set CONFIG_BT_HCIUART_LL=y +# CONFIG_BT_HCIUART_3WIRE is not set CONFIG_BT_HCIBCM203X=m CONFIG_BT_HCIBPA10X=m CONFIG_BT_HCIBFUSB=m @@ -680,10 +695,10 @@ CONFIG_CFG80211=y # CONFIG_NL80211_TESTMODE is not set # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set # CONFIG_CFG80211_REG_DEBUG is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set CONFIG_CFG80211_DEFAULT_PS=y # CONFIG_CFG80211_INTERNAL_REGDB is not set CONFIG_CFG80211_WEXT=y -CONFIG_WIRELESS_EXT_SYSFS=y CONFIG_LIB80211=y CONFIG_LIB80211_CRYPT_WEP=m CONFIG_LIB80211_CRYPT_CCMP=m @@ -698,6 +713,7 @@ CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" # CONFIG_MAC80211_MESH is not set CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_MESSAGE_TRACING is not set # CONFIG_MAC80211_DEBUG_MENU is not set # CONFIG_WIMAX is not set CONFIG_RFKILL=y @@ -826,7 +842,6 @@ CONFIG_MTD_UBI=y CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MTD_UBI_BEB_RESERVE=1 # CONFIG_MTD_UBI_GLUEBI is not set -# CONFIG_MTD_UBI_DEBUG is not set # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set @@ -860,6 +875,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # # CONFIG_SENSORS_LIS3LV02D is not set # CONFIG_AD525X_DPOT is not set +# CONFIG_ATMEL_PWM is not set # CONFIG_PHANTOM is not set # CONFIG_INTEL_MID_PTI is not set # CONFIG_SGI_IOC4 is not set @@ -876,7 +892,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_SENSORS_APDS990X is not set # CONFIG_HMC6352 is not set # CONFIG_DS1682 is not set -# CONFIG_BMP085 is not set +# CONFIG_BMP085_I2C is not set # CONFIG_PCH_PHUB is not set # CONFIG_USB_SWITCH_FSA9480 is not set # CONFIG_C2PORT is not set @@ -927,7 +943,6 @@ CONFIG_CHR_DEV_SG=y # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set # CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m # # SCSI Transports @@ -1164,6 +1179,7 @@ CONFIG_NET_VENDOR_BROADCOM=y # CONFIG_NET_VENDOR_TI is not set # CONFIG_NET_VENDOR_TOSHIBA is not set # CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_PHYLIB is not set @@ -1178,7 +1194,6 @@ CONFIG_PPP_ASYNC=m CONFIG_PPP_SYNC_TTY=m # CONFIG_SLIP is not set CONFIG_SLHC=m -# CONFIG_TR is not set # # USB Network Adapters @@ -1215,7 +1230,6 @@ CONFIG_ATH9K_BTCOEX_SUPPORT=y CONFIG_ATH9K=m # CONFIG_ATH9K_PCI is not set # CONFIG_ATH9K_AHB is not set -# CONFIG_ATH9K_DFS_CERTIFIED is not set CONFIG_ATH9K_RATE_CONTROL=y CONFIG_ATH9K_HTC=m CONFIG_CARL9170=m @@ -1239,6 +1253,7 @@ CONFIG_HOSTAP_FIRMWARE=y # CONFIG_IPW2100 is not set # CONFIG_IPW2200 is not set CONFIG_IWLWIFI=m +CONFIG_IWLDVM=m # # Debugging Options @@ -1280,12 +1295,16 @@ CONFIG_RT2X00_LIB_LEDS=y # CONFIG_RTL8192SE is not set # CONFIG_RTL8192DE is not set # CONFIG_RTL8192CU is not set +CONFIG_WL_TI=y CONFIG_WL1251=m -# CONFIG_WL12XX_MENU is not set +CONFIG_WL12XX=m +CONFIG_WL18XX=m +CONFIG_WLCORE=m CONFIG_ZD1211RW=m # CONFIG_ZD1211RW_DEBUG is not set CONFIG_MWIFIEX=y # CONFIG_MWIFIEX_PCIE is not set +CONFIG_MWIFIEX_USB=m # # Enable WiMAX (Networking options) to see the WiMAX drivers @@ -1301,6 +1320,7 @@ CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set CONFIG_INPUT_POLLDEV=m # CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set # # Userland interfaces @@ -1326,11 +1346,13 @@ CONFIG_INPUT_KEYBOARD=y # CONFIG_KEYBOARD_TCA6416 is not set # CONFIG_KEYBOARD_TCA8418 is not set # CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set # CONFIG_KEYBOARD_MAX7359 is not set # CONFIG_KEYBOARD_MCS is not set # CONFIG_KEYBOARD_MPR121 is not set # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set # CONFIG_KEYBOARD_STOWAWAY is not set # CONFIG_KEYBOARD_SUNKBD is not set # CONFIG_KEYBOARD_OMAP4 is not set @@ -1397,18 +1419,20 @@ CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y # CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_ATMEL is not set +# CONFIG_HW_RANDOM_EXYNOS is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y -# CONFIG_RAMOOPS is not set CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=y # CONFIG_I2C_MUX is not set CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=m # # I2C Hardware Bus support @@ -1435,6 +1459,7 @@ CONFIG_I2C_HELPER_AUTO=y # # I2C system bus drivers (mostly embedded / system-on-chip) # +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set # CONFIG_I2C_DESIGNWARE_PCI is not set # CONFIG_I2C_EG20T is not set # CONFIG_I2C_INTEL_MID is not set @@ -1478,8 +1503,23 @@ CONFIG_I2C_HELPER_AUTO=y # # Enable Device Drivers -> PPS to see the PTP clock options. # +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y # CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_POWER_AVS is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set # CONFIG_WATCHDOG is not set @@ -1499,10 +1539,13 @@ CONFIG_BCMA_POSSIBLE=y # # Multifunction device drivers # -# CONFIG_MFD_CORE is not set +CONFIG_MFD_CORE=m # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_LM3533 is not set # CONFIG_TPS6105X is not set # CONFIG_TPS6507X is not set # CONFIG_MFD_TPS65217 is not set @@ -1514,60 +1557,57 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_PMIC_DA903X is not set # CONFIG_MFD_DA9052_I2C is not set # CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set # CONFIG_MFD_MAX8925 is not set # CONFIG_MFD_MAX8997 is not set # CONFIG_MFD_MAX8998 is not set -# CONFIG_MFD_S5M_CORE is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_ARIZONA_I2C is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM831X_I2C is not set # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set # CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13XXX_I2C is not set # CONFIG_ABX500_CORE is not set # CONFIG_LPC_SCH is not set +# CONFIG_LPC_ICH is not set # CONFIG_MFD_RDC321X is not set # CONFIG_MFD_JANZ_CMODIO is not set # CONFIG_MFD_VX855 is not set -# CONFIG_MFD_WL1273_CORE is not set +CONFIG_MFD_WL1273_CORE=m # CONFIG_MFD_TPS65090 is not set # CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_PALMAS is not set # CONFIG_REGULATOR is not set CONFIG_MEDIA_SUPPORT=y # # Multimedia core support # +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_RC_SUPPORT=y # CONFIG_MEDIA_CONTROLLER is not set -CONFIG_VIDEO_DEV=m -CONFIG_VIDEO_V4L2_COMMON=m +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y CONFIG_DVB_CORE=y CONFIG_DVB_NET=y -CONFIG_VIDEO_MEDIA=m # -# Multimedia drivers +# Media drivers # +CONFIG_VIDEO_SAA7146=m +CONFIG_VIDEO_SAA7146_VV=m CONFIG_RC_CORE=y -CONFIG_LIRC=y CONFIG_RC_MAP=y -CONFIG_IR_NEC_DECODER=y -CONFIG_IR_RC5_DECODER=y -CONFIG_IR_RC6_DECODER=y -CONFIG_IR_JVC_DECODER=y -CONFIG_IR_SONY_DECODER=y -CONFIG_IR_RC5_SZ_DECODER=y -CONFIG_IR_SANYO_DECODER=y -CONFIG_IR_MCE_KBD_DECODER=y -CONFIG_IR_LIRC_CODEC=y -# CONFIG_RC_ATI_REMOTE is not set -# CONFIG_IR_IMON is not set -# CONFIG_IR_MCEUSB is not set -# CONFIG_IR_REDRAT3 is not set -# CONFIG_IR_STREAMZAP is not set -# CONFIG_RC_LOOPBACK is not set -# CONFIG_IR_GPIO_CIR is not set +# CONFIG_RC_DECODERS is not set +# CONFIG_RC_DEVICES is not set # CONFIG_MEDIA_ATTACH is not set -CONFIG_MEDIA_TUNER=m +CONFIG_MEDIA_TUNER=y CONFIG_MEDIA_TUNER_CUSTOMISE=y # @@ -1594,19 +1634,27 @@ CONFIG_MEDIA_TUNER_MXL5007T=m CONFIG_MEDIA_TUNER_MC44S803=m CONFIG_MEDIA_TUNER_MAX2165=m CONFIG_MEDIA_TUNER_TDA18218=m -CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_MEDIA_TUNER_FC0011=m +CONFIG_MEDIA_TUNER_FC0012=m +CONFIG_MEDIA_TUNER_FC0013=m CONFIG_MEDIA_TUNER_TDA18212=m -CONFIG_VIDEO_V4L2=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_VIDEO_V4L2=y CONFIG_VIDEOBUF_GEN=m +CONFIG_VIDEOBUF_DMA_SG=m CONFIG_VIDEOBUF_VMALLOC=m CONFIG_VIDEOBUF_DVB=m CONFIG_VIDEO_TVEEPROM=m CONFIG_VIDEO_TUNER=m +CONFIG_VIDEOBUF2_CORE=m +CONFIG_VIDEOBUF2_MEMOPS=m +CONFIG_VIDEOBUF2_DMA_CONTIG=m +CONFIG_VIDEOBUF2_VMALLOC=m CONFIG_VIDEO_CAPTURE_DRIVERS=y # CONFIG_VIDEO_ADV_DEBUG is not set # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set # CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set -CONFIG_VIDEO_IR_I2C=m +# CONFIG_VIDEO_IR_I2C is not set # # Encoders, decoders, sensors and other helper chips @@ -1620,11 +1668,11 @@ CONFIG_VIDEO_IR_I2C=m # CONFIG_VIDEO_TDA9840 is not set # CONFIG_VIDEO_TEA6415C is not set # CONFIG_VIDEO_TEA6420 is not set -# CONFIG_VIDEO_MSP3400 is not set +CONFIG_VIDEO_MSP3400=m # CONFIG_VIDEO_CS5345 is not set -# CONFIG_VIDEO_CS53L32A is not set +CONFIG_VIDEO_CS53L32A=m # CONFIG_VIDEO_TLV320AIC23B is not set -# CONFIG_VIDEO_WM8775 is not set +CONFIG_VIDEO_WM8775=m # CONFIG_VIDEO_WM8739 is not set # CONFIG_VIDEO_VP27SMPX is not set @@ -1643,7 +1691,7 @@ CONFIG_VIDEO_IR_I2C=m # CONFIG_VIDEO_BT866 is not set # CONFIG_VIDEO_KS0127 is not set # CONFIG_VIDEO_SAA7110 is not set -# CONFIG_VIDEO_SAA711X is not set +CONFIG_VIDEO_SAA711X=m # CONFIG_VIDEO_SAA7191 is not set # CONFIG_VIDEO_TVP514X is not set # CONFIG_VIDEO_TVP5150 is not set @@ -1654,12 +1702,12 @@ CONFIG_VIDEO_IR_I2C=m # Video and audio decoders # # CONFIG_VIDEO_SAA717X is not set -# CONFIG_VIDEO_CX25840 is not set +CONFIG_VIDEO_CX25840=m # # MPEG video encoders # -# CONFIG_VIDEO_CX2341X is not set +CONFIG_VIDEO_CX2341X=m # # Video encoders @@ -1669,12 +1717,13 @@ CONFIG_VIDEO_IR_I2C=m # CONFIG_VIDEO_ADV7170 is not set # CONFIG_VIDEO_ADV7175 is not set # CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set # CONFIG_VIDEO_AK881X is not set # # Camera sensor devices # -# CONFIG_VIDEO_OV7670 is not set +CONFIG_VIDEO_OV7670=m # CONFIG_VIDEO_VS6624 is not set # CONFIG_VIDEO_MT9V011 is not set # CONFIG_VIDEO_TCM825X is not set @@ -1697,87 +1746,115 @@ CONFIG_VIDEO_IR_I2C=m # CONFIG_VIDEO_M52790 is not set # CONFIG_VIDEO_VIVI is not set CONFIG_V4L_USB_DRIVERS=y -# CONFIG_USB_VIDEO_CLASS is not set + +# +# Webcam devices +# +CONFIG_USB_VIDEO_CLASS=m CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y CONFIG_USB_GSPCA=m -# CONFIG_USB_M5602 is not set -# CONFIG_USB_STV06XX is not set -# CONFIG_USB_GL860 is not set -# CONFIG_USB_GSPCA_BENQ is not set -# CONFIG_USB_GSPCA_CONEX is not set -# CONFIG_USB_GSPCA_CPIA1 is not set -# CONFIG_USB_GSPCA_ETOMS is not set -# CONFIG_USB_GSPCA_FINEPIX is not set -# CONFIG_USB_GSPCA_JEILINJ is not set -# CONFIG_USB_GSPCA_JL2005BCD is not set -# CONFIG_USB_GSPCA_KINECT is not set -# CONFIG_USB_GSPCA_KONICA is not set -# CONFIG_USB_GSPCA_MARS is not set -# CONFIG_USB_GSPCA_MR97310A is not set -# CONFIG_USB_GSPCA_NW80X is not set -# CONFIG_USB_GSPCA_OV519 is not set -# CONFIG_USB_GSPCA_OV534 is not set -# CONFIG_USB_GSPCA_OV534_9 is not set -# CONFIG_USB_GSPCA_PAC207 is not set -# CONFIG_USB_GSPCA_PAC7302 is not set -# CONFIG_USB_GSPCA_PAC7311 is not set -# CONFIG_USB_GSPCA_SE401 is not set -# CONFIG_USB_GSPCA_SN9C2028 is not set -# CONFIG_USB_GSPCA_SN9C20X is not set -# CONFIG_USB_GSPCA_SONIXB is not set -# CONFIG_USB_GSPCA_SONIXJ is not set -# CONFIG_USB_GSPCA_SPCA500 is not set -# CONFIG_USB_GSPCA_SPCA501 is not set -# CONFIG_USB_GSPCA_SPCA505 is not set -# CONFIG_USB_GSPCA_SPCA506 is not set -# CONFIG_USB_GSPCA_SPCA508 is not set -# CONFIG_USB_GSPCA_SPCA561 is not set -# CONFIG_USB_GSPCA_SPCA1528 is not set -# CONFIG_USB_GSPCA_SQ905 is not set -# CONFIG_USB_GSPCA_SQ905C is not set -# CONFIG_USB_GSPCA_SQ930X is not set -# CONFIG_USB_GSPCA_STK014 is not set -# CONFIG_USB_GSPCA_STV0680 is not set -# CONFIG_USB_GSPCA_SUNPLUS is not set -# CONFIG_USB_GSPCA_T613 is not set -# CONFIG_USB_GSPCA_TOPRO is not set -# CONFIG_USB_GSPCA_TV8532 is not set -# CONFIG_USB_GSPCA_VC032X is not set -# CONFIG_USB_GSPCA_VICAM is not set -# CONFIG_USB_GSPCA_XIRLINK_CIT is not set -# CONFIG_USB_GSPCA_ZC3XX is not set -# CONFIG_VIDEO_PVRUSB2 is not set -# CONFIG_VIDEO_HDPVR is not set +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_GL860=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_PWC=m +# CONFIG_USB_PWC_DEBUG is not set +CONFIG_USB_PWC_INPUT_EVDEV=y +CONFIG_VIDEO_CPIA2=m +CONFIG_USB_ZR364XX=m +CONFIG_USB_STKWEBCAM=m +CONFIG_USB_S2255=m +CONFIG_USB_SN9C102=m + +# +# Webcam and/or TV USB devices +# CONFIG_VIDEO_EM28XX=m CONFIG_VIDEO_EM28XX_ALSA=m CONFIG_VIDEO_EM28XX_DVB=m -CONFIG_VIDEO_EM28XX_RC=y -# CONFIG_VIDEO_TLG2300 is not set -# CONFIG_VIDEO_CX231XX is not set -# CONFIG_VIDEO_TM6000 is not set -# CONFIG_VIDEO_USBVISION is not set -# CONFIG_USB_ET61X251 is not set -# CONFIG_USB_SN9C102 is not set -# CONFIG_USB_PWC is not set -# CONFIG_VIDEO_CPIA2 is not set -# CONFIG_USB_ZR364XX is not set -# CONFIG_USB_STKWEBCAM is not set -# CONFIG_USB_S2255 is not set +CONFIG_VIDEO_EM28XX_RC=m + +# +# TV USB devices +# +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_PVRUSB2_DVB=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_TLG2300=m +CONFIG_VIDEO_CX231XX=m +# CONFIG_VIDEO_CX231XX_RC is not set +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_TM6000_DVB=m +CONFIG_VIDEO_USBVISION=m # CONFIG_V4L_PCI_DRIVERS is not set -# CONFIG_V4L_PLATFORM_DRIVERS is not set +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_CAFE_CCIC=m +# CONFIG_SOC_CAMERA is not set # CONFIG_V4L_MEM2MEM_DRIVERS is not set CONFIG_RADIO_ADAPTERS=y -# CONFIG_RADIO_SI470X is not set -# CONFIG_USB_MR800 is not set -# CONFIG_USB_DSBR is not set -# CONFIG_RADIO_MAXIRADIO is not set -# CONFIG_I2C_SI4713 is not set -# CONFIG_RADIO_SI4713 is not set -# CONFIG_USB_KEENE is not set -# CONFIG_RADIO_TEA5764 is not set -# CONFIG_RADIO_SAA7706H is not set -# CONFIG_RADIO_TEF6862 is not set -# CONFIG_RADIO_WL1273 is not set +CONFIG_RADIO_SI470X=y +CONFIG_USB_SI470X=m +CONFIG_I2C_SI470X=m +CONFIG_USB_MR800=m +CONFIG_USB_DSBR=m +CONFIG_RADIO_MAXIRADIO=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_I2C_SI4713=m +CONFIG_RADIO_SI4713=m +CONFIG_USB_KEENE=m +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_TEF6862=m +CONFIG_RADIO_WL1273=m # # Texas Instruments WL128x FM driver (ST based) @@ -1790,13 +1867,14 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # Supported SAA7146 based PCI Adapters # CONFIG_TTPCI_EEPROM=m -# CONFIG_DVB_AV7110 is not set +CONFIG_DVB_AV7110=m +# CONFIG_DVB_AV7110_OSD is not set # CONFIG_DVB_BUDGET_CORE is not set # # Supported USB Adapters # -CONFIG_DVB_USB=y +CONFIG_DVB_USB=m # CONFIG_DVB_USB_DEBUG is not set CONFIG_DVB_USB_A800=m CONFIG_DVB_USB_DIBUSB_MB=m @@ -1817,15 +1895,13 @@ CONFIG_DVB_USB_TTUSB2=m CONFIG_DVB_USB_DTT200U=m CONFIG_DVB_USB_OPERA1=m CONFIG_DVB_USB_AF9005=m -CONFIG_DVB_USB_AF9005_REMOTE=m +# CONFIG_DVB_USB_AF9005_REMOTE is not set CONFIG_DVB_USB_PCTV452E=m CONFIG_DVB_USB_DW2102=m CONFIG_DVB_USB_CINERGY_T2=m CONFIG_DVB_USB_ANYSEE=m CONFIG_DVB_USB_DTV5100=m CONFIG_DVB_USB_AF9015=m -CONFIG_DVB_USB_AF9035=m -CONFIG_DVB_USB_RTL2832=m CONFIG_DVB_USB_CE6230=m CONFIG_DVB_USB_FRIIO=m CONFIG_DVB_USB_EC168=m @@ -1836,7 +1912,7 @@ CONFIG_DVB_USB_TECHNISAT_USB2=m CONFIG_DVB_USB_IT913X=m CONFIG_DVB_USB_MXL111SF=m CONFIG_DVB_USB_RTL28XXU=m -CONFIG_DVB_USB_A867=m +CONFIG_DVB_USB_AF9035=m # CONFIG_DVB_TTUSB_BUDGET is not set # CONFIG_DVB_TTUSB_DEC is not set CONFIG_SMS_SIANO_MDTV=m @@ -1957,12 +2033,12 @@ CONFIG_DVB_DIB7000P=m CONFIG_DVB_DIB9000=m CONFIG_DVB_TDA10048=m CONFIG_DVB_AF9013=m -CONFIG_DVB_AF9033=m CONFIG_DVB_EC100=m CONFIG_DVB_HD29L2=m CONFIG_DVB_STV0367=m CONFIG_DVB_CXD2820R=m CONFIG_DVB_RTL2830=m +CONFIG_DVB_RTL2832=m # # DVB-C (cable) frontends @@ -1981,8 +2057,11 @@ CONFIG_DVB_OR51132=m CONFIG_DVB_BCM3510=m CONFIG_DVB_LGDT330X=m CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LG2160=m CONFIG_DVB_S5H1409=m CONFIG_DVB_AU8522=m +CONFIG_DVB_AU8522_DTV=m +CONFIG_DVB_AU8522_V4L=m CONFIG_DVB_S5H1411=m # @@ -2015,6 +2094,7 @@ CONFIG_DVB_TDA665x=m CONFIG_DVB_IX2505V=m CONFIG_DVB_IT913X_FE=m CONFIG_DVB_M88RS2000=m +CONFIG_DVB_AF9033=m # # Tools to develop new frontends @@ -2077,12 +2157,14 @@ CONFIG_FB=y # CONFIG_FB_ARK is not set # CONFIG_FB_PM3 is not set # CONFIG_FB_CARMINE is not set +# CONFIG_FB_TMIO is not set # CONFIG_FB_SMSCUFX is not set # CONFIG_FB_UDL is not set # CONFIG_FB_VIRTUAL is not set # CONFIG_FB_METRONOME is not set # CONFIG_FB_MB862XX is not set # CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_AUO_K190X is not set # CONFIG_EXYNOS_VIDEO is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set @@ -2134,21 +2216,21 @@ CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_SBAWE_SEQ is not set # CONFIG_SND_EMU10K1_SEQ is not set # CONFIG_SND_DRIVERS is not set +CONFIG_SND_TEA575X=m # CONFIG_SND_PCI is not set # CONFIG_SND_MIPS is not set # CONFIG_SND_USB is not set # CONFIG_SND_SOC is not set # CONFIG_SOUND_PRIME is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -CONFIG_HIDRAW=y # -# USB Input Devices +# HID support # -CONFIG_USB_HID=y -# CONFIG_HID_PID is not set -CONFIG_USB_HIDDEV=y +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +CONFIG_HIDRAW=y +# CONFIG_UHID is not set +CONFIG_HID_GENERIC=y # # Special HID drivers @@ -2156,6 +2238,7 @@ CONFIG_USB_HIDDEV=y # CONFIG_HID_A4TECH is not set # CONFIG_HID_ACRUX is not set # CONFIG_HID_APPLE is not set +# CONFIG_HID_AUREAL is not set # CONFIG_HID_BELKIN is not set # CONFIG_HID_CHERRY is not set # CONFIG_HID_CHICONY is not set @@ -2174,6 +2257,7 @@ CONFIG_USB_HIDDEV=y # CONFIG_HID_TWINHAN is not set # CONFIG_HID_KENSINGTON is not set # CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LENOVO_TPKBD is not set CONFIG_HID_LOGITECH=y CONFIG_HID_LOGITECH_DJ=y # CONFIG_LOGITECH_FF is not set @@ -2202,10 +2286,16 @@ CONFIG_HID_LOGITECH_DJ=y # CONFIG_HID_TOPSEED is not set # CONFIG_HID_THRUSTMASTER is not set CONFIG_HID_WACOM=m -# CONFIG_HID_WACOM_POWER_SUPPLY is not set # CONFIG_HID_WIIMOTE is not set # CONFIG_HID_ZEROPLUS is not set # CONFIG_HID_ZYDACRON is not set + +# +# USB HID support +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +CONFIG_USB_HIDDEV=y CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y CONFIG_USB_ARCH_HAS_XHCI=y @@ -2219,8 +2309,6 @@ CONFIG_USB=y # # Miscellaneous USB options # -CONFIG_USB_DEVICEFS=y -CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set @@ -2241,6 +2329,7 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_CHIPIDEA is not set # # USB Device Class drivers @@ -2306,7 +2395,7 @@ CONFIG_USB_SERIAL_FTDI_SIO=m CONFIG_USB_SERIAL_F81232=m # CONFIG_USB_SERIAL_GARMIN is not set # CONFIG_USB_SERIAL_IPW is not set -CONFIG_USB_SERIAL_IUU=m +# CONFIG_USB_SERIAL_IUU is not set # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set CONFIG_USB_SERIAL_KEYSPAN=m # CONFIG_USB_SERIAL_KEYSPAN_MPR is not set @@ -2349,6 +2438,7 @@ CONFIG_USB_SERIAL_OPTION=m # CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set # CONFIG_USB_SERIAL_ZIO is not set # CONFIG_USB_SERIAL_SSU100 is not set +# CONFIG_USB_SERIAL_QT2 is not set # CONFIG_USB_SERIAL_DEBUG is not set # @@ -2373,6 +2463,11 @@ CONFIG_USB_SERIAL_OPTION=m # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set # CONFIG_USB_YUREX is not set + +# +# USB Physical Layer drivers +# +# CONFIG_USB_ISP1301 is not set # CONFIG_USB_GADGET is not set # @@ -2397,13 +2492,16 @@ CONFIG_LEDS_CLASS=y # CONFIG_LEDS_PCA9633 is not set # CONFIG_LEDS_BD2802 is not set # CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_LM3556 is not set # CONFIG_LEDS_OT200 is not set +# CONFIG_LEDS_BLINKM is not set CONFIG_LEDS_TRIGGERS=y # # LED Triggers # # CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_ONESHOT is not set # CONFIG_LEDS_TRIGGER_HEARTBEAT is not set # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set @@ -2411,6 +2509,7 @@ CONFIG_LEDS_TRIGGERS=y # # iptables trigger is under Netfilter config (LED target) # +# CONFIG_LEDS_TRIGGER_TRANSIENT is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_RTC_LIB=y @@ -2450,12 +2549,10 @@ CONFIG_R8712U=m # CONFIG_IDE_PHISON is not set # CONFIG_LINE6_USB is not set # CONFIG_USB_SERIAL_QUATECH2 is not set -# CONFIG_USB_SERIAL_QUATECH_USB2 is not set # CONFIG_VT6655 is not set # CONFIG_VT6656 is not set -# CONFIG_VME_BUS is not set # CONFIG_DX_SEP is not set -# CONFIG_IIO is not set +# CONFIG_ZSMALLOC is not set # CONFIG_FB_SM7XX is not set # CONFIG_CRYSTALHD is not set # CONFIG_FB_XGI is not set @@ -2471,11 +2568,22 @@ CONFIG_R8712U=m CONFIG_STAGING_MEDIA=y CONFIG_DVB_AS102=m # CONFIG_DVB_CXD2099 is not set -# CONFIG_VIDEO_DT3155 is not set -# CONFIG_EASYCAP is not set -# CONFIG_VIDEO_GO7007 is not set -# CONFIG_SOLO6X10 is not set -# CONFIG_LIRC_STAGING is not set +CONFIG_VIDEO_DT3155=m +CONFIG_DT3155_CCIR=y +CONFIG_DT3155_STREAMING=y +CONFIG_EASYCAP=m +# CONFIG_EASYCAP_DEBUG is not set +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m +CONFIG_VIDEO_GO7007_OV7640=m +CONFIG_VIDEO_GO7007_SAA7113=m +CONFIG_VIDEO_GO7007_SAA7115=m +CONFIG_VIDEO_GO7007_TW9903=m +CONFIG_VIDEO_GO7007_UDA1342=m +CONFIG_VIDEO_GO7007_SONY_TUNER=m +CONFIG_VIDEO_GO7007_TW2804=m +CONFIG_SOLO6X10=m # # Android @@ -2483,6 +2591,12 @@ CONFIG_DVB_AS102=m # CONFIG_ANDROID is not set # CONFIG_PHONE is not set CONFIG_USB_WPAN_HCD=m +# CONFIG_IPACK_BUS is not set +CONFIG_WIMAX_GDM72XX=m +# CONFIG_WIMAX_GDM72XX_QOS is not set +# CONFIG_WIMAX_GDM72XX_K_MODE is not set +# CONFIG_WIMAX_GDM72XX_WIMAX2 is not set +CONFIG_WIMAX_GDM72XX_USB=y # # Hardware Spinlock drivers @@ -2498,6 +2612,11 @@ CONFIG_USB_WPAN_HCD=m # # CONFIG_VIRT_DRIVERS is not set # CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +# CONFIG_VME_BUS is not set +# CONFIG_PWM is not set # # File systems @@ -2578,6 +2697,7 @@ CONFIG_TMPFS=y CONFIG_MISC_FILESYSTEMS=y # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set CONFIG_HFS_FS=y CONFIG_HFSPLUS_FS=y # CONFIG_BEFS_FS is not set @@ -2599,11 +2719,9 @@ CONFIG_JFFS2_RUBIN=y # CONFIG_JFFS2_CMODE_SIZE is not set CONFIG_JFFS2_CMODE_FAVOURLZO=y CONFIG_UBIFS_FS=y -# CONFIG_UBIFS_FS_XATTR is not set # CONFIG_UBIFS_FS_ADVANCED_COMPR is not set CONFIG_UBIFS_FS_LZO=y CONFIG_UBIFS_FS_ZLIB=y -# CONFIG_UBIFS_FS_DEBUG is not set # CONFIG_LOGFS is not set # CONFIG_CRAMFS is not set CONFIG_SQUASHFS=m @@ -2627,10 +2745,17 @@ CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_UFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y +CONFIG_NFS_V2=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set -# CONFIG_NFS_V4 is not set +CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y +CONFIG_NFS_V4_1=y +CONFIG_PNFS_FILE_LAYOUT=m +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" CONFIG_ROOT_NFS=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y CONFIG_NFSD=m CONFIG_NFSD_V3=y # CONFIG_NFSD_V3_ACL is not set @@ -2639,13 +2764,18 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_SUNRPC_BACKCHANNEL=y +CONFIG_SUNRPC_SWAP=y # CONFIG_SUNRPC_DEBUG is not set # CONFIG_CEPH_FS is not set CONFIG_CIFS=y # CONFIG_CIFS_STATS is not set # CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_UPCALL is not set # CONFIG_CIFS_XATTR is not set # CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DFS_UPCALL is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set @@ -2688,6 +2818,17 @@ CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=y CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set CONFIG_NLS_UTF8=y # @@ -2701,6 +2842,7 @@ CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 CONFIG_FRAME_WARN=0 # CONFIG_MAGIC_SYSRQ is not set # CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set @@ -2709,6 +2851,8 @@ CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set # CONFIG_LOCKUP_DETECTOR is not set # CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 # CONFIG_DETECT_HUNG_TASK is not set # CONFIG_SCHED_DEBUG is not set # CONFIG_SCHEDSTATS is not set @@ -2746,6 +2890,7 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=60 # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_DEBUG_PAGEALLOC is not set CONFIG_HAVE_FUNCTION_TRACER=y @@ -2772,7 +2917,9 @@ CONFIG_CMDLINE="bmem=216M ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs conso # # Security options # -# CONFIG_KEYS is not set +CONFIG_KEYS=y +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set # CONFIG_SECURITY_DMESG_RESTRICT is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set @@ -2833,7 +2980,7 @@ CONFIG_CRYPTO_HMAC=y # # Digest # -# CONFIG_CRYPTO_CRC32C is not set +CONFIG_CRYPTO_CRC32C=y # CONFIG_CRYPTO_GHASH is not set CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y @@ -2917,5 +3064,7 @@ CONFIG_CPU_RMAP=y CONFIG_DQL=y CONFIG_NLATTR=y CONFIG_GENERIC_ATOMIC64=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y CONFIG_AVERAGE=y # CONFIG_CORDIC is not set +# CONFIG_DDR is not set diff --git a/meta-openpli/recipes-linux/linux/linux-etxx00/it913x-fix-bulk-read-write-retry-loop.patch b/meta-openpli/recipes-linux/linux/linux-etxx00/it913x-fix-bulk-read-write-retry-loop.patch deleted file mode 100644 index 88d13a9505..0000000000 --- a/meta-openpli/recipes-linux/linux/linux-etxx00/it913x-fix-bulk-read-write-retry-loop.patch +++ /dev/null @@ -1,30 +0,0 @@ -Misuses of "||". -Just check for -EBUSY && -ETIMEDOUT - -Signed-off-by: Malcolm Priestley ---- - drivers/media/dvb/dvb-usb/it913x.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/media/dvb/dvb-usb/it913x.c b/drivers/media/dvb/dvb-usb/it913x.c -index 482d249..6244fe9 100644 ---- a/drivers/media/dvb/dvb-usb/it913x.c -+++ b/drivers/media/dvb/dvb-usb/it913x.c -@@ -81,7 +81,7 @@ static int it913x_bulk_write(struct usb_device *dev, - for (i = 0; i < IT913X_RETRY; i++) { - ret = usb_bulk_msg(dev, usb_sndbulkpipe(dev, pipe), - snd, len , &actual_l, IT913X_SND_TIMEOUT); -- if (ret == 0 || ret != -EBUSY || ret != -ETIMEDOUT) -+ if (ret != -EBUSY && ret != -ETIMEDOUT) - break; - } - -@@ -99,7 +99,7 @@ static int it913x_bulk_read(struct usb_device *dev, - for (i = 0; i < IT913X_RETRY; i++) { - ret = usb_bulk_msg(dev, usb_rcvbulkpipe(dev, pipe), - rev, len , &actual_l, IT913X_RCV_TIMEOUT); -- if (ret == 0 || ret != -EBUSY || ret != -ETIMEDOUT) -+ if (ret != -EBUSY && ret != -ETIMEDOUT) - break; - } - diff --git a/meta-openpli/recipes-linux/linux/linux-etxx00_3.4.3.bb b/meta-openpli/recipes-linux/linux/linux-etxx00_3.6.0.bb similarity index 82% rename from meta-openpli/recipes-linux/linux/linux-etxx00_3.4.3.bb rename to meta-openpli/recipes-linux/linux/linux-etxx00_3.6.0.bb index e41f4bbfaf..b14aacf1de 100644 --- a/meta-openpli/recipes-linux/linux/linux-etxx00_3.4.3.bb +++ b/meta-openpli/recipes-linux/linux/linux-etxx00_3.6.0.bb @@ -2,14 +2,14 @@ DESCRIPTION = "Linux kernel for ${MACHINE}" SECTION = "kernel" LICENSE = "GPLv2" -KERNEL_RELEASE = "3.4.3" +KERNEL_RELEASE = "3.6.0" -SRC_URI[md5sum] = "57a986f69a0f0601b77710b4829e4b47" -SRC_URI[sha256sum] = "d81d051e6f702fc4bda0cb6b18db7319ed3b36401a924b682b0b0b94e0c23ad7" +SRC_URI[md5sum] = "fad4c270fe68fcc8d15258c868bc2733" +SRC_URI[sha256sum] = "df8c6071cbdd6a709aebb8a272dca60791edb379103597670609ef90e148d8bb" LIC_FILES_CHKSUM = "file://${WORKDIR}/linux-${PV}/COPYING;md5=d7810fab7487fb0aad327b76f1be7cd7" -MACHINE_KERNEL_PR_append = ".9" +MACHINE_KERNEL_PR_append = ".1" # By default, kernel.bbclass modifies package names to allow multiple kernels # to be installed in parallel. We revert this change and rprovide the versioned @@ -21,27 +21,23 @@ RPROVIDES_kernel-image = "kernel-image-${KERNEL_VERSION}" SRC_URI += "http://www.et-view.com/download/linux-${PV}.tar.gz \ file://defconfig \ - file://fix-proc-cputype.patch \ + file://0001-Revert-MIPS-mm-Add-compound-tail-page-_mapcount-when.patch \ file://0001-Revert-MIPS-Add-fast-get_user_pages.patch \ - file://iosched-slice_idle-1.patch \ file://add-dmx-source-timecode.patch \ - file://dvb-usb-af9035.patch \ - file://tda18218-7mhz-lopass.patch \ - file://dvb-usb-a867.patch \ - file://dvb-usb-rtl2832.patch \ - file://cxd2820r-enable-LNA-for-DVB-T.patch \ - file://cxd2820r-changed-condition-to-break-out-from-wait-lock-loop.patch \ - file://cxd2820r-output-full-range-SNR.patch \ - file://cinergy_s2_usb_r2.patch \ - file://as102-scale-MER-to-full-range.patch \ - file://as102-adjust-signal-strength-report.patch \ - file://em28xx-dvb-stop-URBs-when-stopping-the-streaming.patch \ file://af9015-output-full-range-SNR.patch \ - file://it913x-switch-off-PID-filter-by-default.patch \ - file://it913x-fix-bulk-read-write-retry-loop.patch \ + file://as102-adjust-signal-strength-report.patch \ + file://as102-scale-MER-to-full-range.patch \ + file://cinergy_s2_usb_r2.patch \ + file://cxd2820r-output-full-range-SNR.patch \ + file://dvb-usb-a867.patch \ file://dvb-usb-dib0700-disable-sleep.patch \ + file://dvb-usb-rtl2832.patch \ file://dvb_usb_disable_rc_polling.patch \ file://em28xx_add_terratec_h5_rev3.patch \ + file://fix-proc-cputype.patch \ + file://iosched-slice_idle-1.patch \ + file://it913x-switch-off-PID-filter-by-default.patch \ + file://tda18218-7mhz-lopass.patch \ " S = "${WORKDIR}/linux-${PV}" From 1a68bdec490a904d51fee07d4156957bb71b1092 Mon Sep 17 00:00:00 2001 From: pieterg Date: Mon, 22 Oct 2012 08:46:07 +0200 Subject: [PATCH 17/17] enigma2-plugin-picons-ziggo.casema: 20121021 update by gjstroom --- ...0904.bb => enigma2-plugin-picons-ziggo.casema_20121021.bb} | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) rename meta-openpli/recipes-openpli/enigma2-picons/{enigma2-plugin-picons-ziggo.casema_20120904.bb => enigma2-plugin-picons-ziggo.casema_20121021.bb} (53%) diff --git a/meta-openpli/recipes-openpli/enigma2-picons/enigma2-plugin-picons-ziggo.casema_20120904.bb b/meta-openpli/recipes-openpli/enigma2-picons/enigma2-plugin-picons-ziggo.casema_20121021.bb similarity index 53% rename from meta-openpli/recipes-openpli/enigma2-picons/enigma2-plugin-picons-ziggo.casema_20120904.bb rename to meta-openpli/recipes-openpli/enigma2-picons/enigma2-plugin-picons-ziggo.casema_20121021.bb index 70ad2f90bd..c2b61b7bd6 100644 --- a/meta-openpli/recipes-openpli/enigma2-picons/enigma2-plugin-picons-ziggo.casema_20120904.bb +++ b/meta-openpli/recipes-openpli/enigma2-picons/enigma2-plugin-picons-ziggo.casema_20121021.bb @@ -6,5 +6,5 @@ SRC_URI = "http://downloads.pli-images.org/picons/picons-ziggo-casema-${PV}.tar. include enigma2-plugin-picons.inc -SRC_URI[md5sum] = "994ed6acae79aae33a7beb18c7c93982" -SRC_URI[sha256sum] = "aeef3ce2c75949fe7abf7b2fc9b3f756c178d2ce78067b78176be3e82ca964f7" +SRC_URI[md5sum] = "d9511adb46393a8c582b3e576389a6d8" +SRC_URI[sha256sum] = "46cdd9634dedec2cc3546da16fc1359589f31ef78182193fa2189b5c31ac02d2"