JitcX86 stub

CMakeLists.txt

@@ -1,7 +1,19 @@
 cmake_minimum_required (VERSION 2.8.11)
 project (DolwinPlayground)
 
-set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -Wl,-Ttext-segment=400000")
+# Choose an X86/X64 build
+
+if (CMAKE_C_SIZEOF_DATA_PTR EQUAL 8)
+  set(X86 OFF)
+  set(X64 ON)
+else ()
+  set(X86 ON)
+  set(X64 OFF)
+endif ()
+
+# Previously, the HLE subsystem required a base address of 0x400000 for the VMCall instruction. VMCall is now disabled and will be redone.
+
+#set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -Wl,-Ttext-segment=400000")
 
 add_definitions (-D_LINUX)
 add_definitions (-DCMAKE_BUILD_TYPE=Debug)

SRC/GekkoCore/GekkoDefs.h

@@ -104,7 +104,7 @@ namespace Gekko
 
 namespace Gekko
 {
-	enum class SPR : int
+	enum SPR
 	{
 		XER = 1,
 		LR = 8,
@@ -159,6 +159,15 @@ namespace Gekko
 	};
 }
 
+namespace Gekko
+{
+	enum class TBR
+	{
+		TBL = 268,
+		TBU = 269,
+	};
+}
+
 // Quantization data types
 
 enum class GEKKO_QUANT_TYPE

SRC/GekkoCore/GekkoDisasm.cpp

@@ -803,8 +803,8 @@ namespace Gekko
 		switch(tbr)
 		{
 			// General architecture time-base registers.
-			case 268: return "TBL";
-			case 269: return "TBU";
+			case (int)TBR::TBL: return "TBL";
+			case (int)TBR::TBU: return "TBU";
 		}
 
 		char def[8] = { 0, };

SRC/GekkoCore/Interpreter/System.cpp

@@ -169,11 +169,11 @@ namespace Gekko
 
 		switch (spr)
 		{
-			case (int)SPR::WPAR:
+			case SPR::WPAR:
 				value = (core->regs.spr[spr] & ~0x1f) | (core->gatherBuffer->NotEmpty() ? 1 : 0);
 				break;
 
-			case (int)SPR::HID1:
+			case SPR::HID1:
 				// Gekko PLL_CFG = 0b1000
 				value = 0x8000'0000;
 				break;
@@ -192,11 +192,11 @@ namespace Gekko
 	{
 		int tbr = info.paramBits[1];
 
-		if (tbr == 268)
+		if (tbr == (int)TBR::TBL)
 		{
 			core->regs.gpr[info.paramBits[0]] = core->regs.tb.Part.l;
 		}
-		else if (tbr == 269)
+		else if (tbr == (int)TBR::TBU)
 		{
 			core->regs.gpr[info.paramBits[0]] = core->regs.tb.Part.u;
 		}
@@ -253,7 +253,9 @@ namespace Gekko
 	{
 		int spr = info.paramBits[0];
 
-		if (spr >= 528 && spr <= 543)
+		// Diagnostic output when the BAT registers are changed.
+
+		if (spr >= SPR::IBAT0U && spr <= SPR::DBAT3L)
 		{
 			static const char* bat[] = {
 				"IBAT0U", "IBAT0L", "IBAT1U", "IBAT1L",
@@ -266,17 +268,18 @@ namespace Gekko
 			bool msr_dr = (core->regs.msr & MSR_DR) ? true : false;
 
 			Report(Channel::CPU, "%s <- %08X (IR:%i DR:%i pc:%08X)\n",
-				bat[spr - 528], core->regs.gpr[info.paramBits[1]], msr_ir, msr_dr, core->regs.pc);
+				bat[spr - SPR::IBAT0U], core->regs.gpr[info.paramBits[1]], msr_ir, msr_dr, core->regs.pc);
 		}
-		else switch (spr)
+
+		switch (spr)
 		{
 			// decrementer
-			case (int)SPR::DEC:
+			case SPR::DEC:
 				//DBReport2(DbgChannel::CPU, "set decrementer (OS alarm) to %08X\n", RRS);
 				break;
 
 			// page table base
-			case (int)SPR::SDR1:
+			case SPR::SDR1:
 			{
 				bool msr_ir = (core->regs.msr & MSR_IR) ? true : false;
 				bool msr_dr = (core->regs.msr & MSR_DR) ? true : false;
@@ -289,22 +292,22 @@ namespace Gekko
 			}
 			break;
 
-			case (int)SPR::TBL:
+			case SPR::TBL:
 				core->regs.tb.Part.l = core->regs.gpr[info.paramBits[1]];
 				Report(Channel::CPU, "Set TBL: 0x%08X\n", core->regs.tb.Part.l);
 				break;
-			case (int)SPR::TBU:
+			case SPR::TBU:
 				core->regs.tb.Part.u = core->regs.gpr[info.paramBits[1]];
 				Report(Channel::CPU, "Set TBU: 0x%08X\n", core->regs.tb.Part.u);
 				break;
 
 			// write gathering buffer
-			case (int)SPR::WPAR:
+			case SPR::WPAR:
 				// A mtspr to WPAR invalidates the data.
 				core->gatherBuffer->Reset();
 				break;
 
-			case (int)SPR::HID0:
+			case SPR::HID0:
 			{
 				uint32_t bits = core->regs.gpr[info.paramBits[1]];
 				core->cache.Enable((bits & HID0_DCE) ? true : false);
@@ -332,12 +335,12 @@ namespace Gekko
 			}
 			break;
 
-			case (int)SPR::HID1:
+			case SPR::HID1:
 				// Read only
 				core->regs.pc += 4;
 				return;
 
-			case (int)SPR::HID2:
+			case SPR::HID2:
 			{
 				uint32_t bits = core->regs.gpr[info.paramBits[1]];
 				core->cache.LockedEnable((bits & HID2_LCE) ? true : false);
@@ -346,10 +349,10 @@ namespace Gekko
 
 			// Locked cache DMA
 
-			case (int)SPR::DMAU:
+			case SPR::DMAU:
 				//DBReport2(DbgChannel::CPU, "DMAU: 0x%08X\n", RRS);
 				break;
-			case (int)SPR::DMAL:
+			case SPR::DMAL:
 			{
 				core->regs.spr[spr] = core->regs.gpr[info.paramBits[1]];
 				//DBReport2(DbgChannel::CPU, "DMAL: 0x%08X\n", RRS);
@@ -378,44 +381,35 @@ namespace Gekko
 			}
 			break;
 
-			// When the GQR values change, the recompiler is invalidated.
-			// This rarely happens.
-
-			case (int)SPR::GQR0:
-			case (int)SPR::GQR1:
-			case (int)SPR::GQR2:
-			case (int)SPR::GQR3:
-			case (int)SPR::GQR4:
-			case (int)SPR::GQR5:
-			case (int)SPR::GQR6:
-			case (int)SPR::GQR7:
-			{
-				if (core->regs.spr[spr] != core->regs.gpr[info.paramBits[1]])
-				{
-					core->jitc->Reset();
-				}
-			}
-			break;
+			case SPR::GQR0:
+			case SPR::GQR1:
+			case SPR::GQR2:
+			case SPR::GQR3:
+			case SPR::GQR4:
+			case SPR::GQR5:
+			case SPR::GQR6:
+			case SPR::GQR7:
+				break;
 
-			case (int)SPR::IBAT0U:
-			case (int)SPR::IBAT0L:
-			case (int)SPR::IBAT1U:
-			case (int)SPR::IBAT1L:
-			case (int)SPR::IBAT2U:
-			case (int)SPR::IBAT2L:
-			case (int)SPR::IBAT3U:
-			case (int)SPR::IBAT3L:
+			case SPR::IBAT0U:
+			case SPR::IBAT0L:
+			case SPR::IBAT1U:
+			case SPR::IBAT1L:
+			case SPR::IBAT2U:
+			case SPR::IBAT2L:
+			case SPR::IBAT3U:
+			case SPR::IBAT3L:
 				core->itlb.InvalidateAll();
 				break;
 
-			case (int)SPR::DBAT0U:
-			case (int)SPR::DBAT0L:
-			case (int)SPR::DBAT1U:
-			case (int)SPR::DBAT1L:
-			case (int)SPR::DBAT2U:
-			case (int)SPR::DBAT2L:
-			case (int)SPR::DBAT3U:
-			case (int)SPR::DBAT3L:
+			case SPR::DBAT0U:
+			case SPR::DBAT0L:
+			case SPR::DBAT1U:
+			case SPR::DBAT1L:
+			case SPR::DBAT2U:
+			case SPR::DBAT2L:
+			case SPR::DBAT3U:
+			case SPR::DBAT3L:
 				core->dtlb.InvalidateAll();
 				break;
 		}

SRC/GekkoCore/JitcX64/JitcCompare.cpp

@@ -0,0 +1,2 @@
+// Integer Compare Instructions
+#include "../pch.h"

SRC/GekkoCore/JitcX64/JitcCondition.cpp

@@ -0,0 +1,2 @@
+// Condition Register Logical Instructions
+#include "../pch.h"

SRC/GekkoCore/JitcX64/JitcFPLoadStore.cpp

@@ -0,0 +1,2 @@
+// Floating-Point Load and Store Instructions
+#include "../pch.h"

SRC/GekkoCore/JitcX64/JitcFloatingPoint.cpp

@@ -0,0 +1,2 @@
+// Floating-Point Instructions
+#include "../pch.h"

SRC/GekkoCore/JitcX64/JitcLogical.cpp

@@ -0,0 +1,2 @@
+// Logical Instructions
+#include "../pch.h"

SRC/GekkoCore/JitcX64/JitcPSLoadStore.cpp

@@ -3,9 +3,10 @@
 
 // Under normal conditions, GQR registers are set once and for a long time (__OSPSInit, OSInitFastCast)
 // We use this fact here and do not get the Type/Scale value in runtime, but in compile time.
-
 // When the GQR values change, the recompiler is invalidated.
 
+// ERRATA: This hypothesis did not pass the test, so this code needs to be redone.
+
 namespace Gekko
 {
 	#define LD_SCALE(n) ((core->regs.spr[(int)SPR::GQRs + n] >> 24) & 0x3f)

SRC/GekkoCore/JitcX64/JitcShift.cpp

@@ -0,0 +1,2 @@
+// Integer Shift Instructions
+#include "../pch.h"

SRC/GekkoCore/JitcX64/JitcSystem.cpp

@@ -0,0 +1,2 @@
+// System Instructions
+#include "../pch.h"

SRC/GekkoCore/JitcX86/Common.cpp

@@ -0,0 +1 @@
+#include "../pch.h"

SRC/GekkoCore/JitcX86/Fallback.cpp

@@ -0,0 +1 @@
+#include "../pch.h"

SRC/GekkoCore/JitcX86/JitcBranch.cpp

@@ -0,0 +1,2 @@
+// Branch Instructions
+#include "../pch.h"

SRC/GekkoCore/JitcX86/JitcCompare.cpp

@@ -0,0 +1,2 @@
+// Integer Compare Instructions
+#include "../pch.h"

SRC/GekkoCore/JitcX86/JitcCondition.cpp

@@ -0,0 +1,2 @@
+// Condition Register Logical Instructions
+#include "../pch.h"

SRC/GekkoCore/JitcX86/JitcFPLoadStore.cpp

@@ -0,0 +1,2 @@
+// Floating-Point Load and Store Instructions
+#include "../pch.h"

SRC/GekkoCore/JitcX86/JitcFloatingPoint.cpp

@@ -0,0 +1,2 @@
+// Floating-Point Instructions
+#include "../pch.h"

SRC/GekkoCore/JitcX86/JitcInteger.cpp

@@ -0,0 +1,2 @@
+// Integer Instructions
+#include "../pch.h"

SRC/GekkoCore/JitcX86/JitcLoadStore.cpp

@@ -0,0 +1,2 @@
+// Integer Load and Store Instructions
+#include "../pch.h"

SRC/GekkoCore/JitcX86/JitcLogical.cpp

@@ -0,0 +1,2 @@
+// Logical Instructions
+#include "../pch.h"

SRC/GekkoCore/JitcX86/JitcPSLoadStore.cpp

@@ -0,0 +1,2 @@
+// Paired Single Load and Store Instructions
+#include "../pch.h"

SRC/GekkoCore/JitcX86/JitcPairedSingle.cpp

@@ -0,0 +1,2 @@
+// Paired Single Instructions
+#include "../pch.h"

SRC/GekkoCore/JitcX86/JitcRotate.cpp

@@ -0,0 +1,2 @@
+// Integer Rotate Instructions
+#include "../pch.h"

SRC/GekkoCore/JitcX86/JitcShift.cpp

@@ -0,0 +1,2 @@
+// Integer Shift Instructions
+#include "../pch.h"

SRC/GekkoCore/JitcX86/JitcSystem.cpp

@@ -0,0 +1,2 @@
+// System Instructions
+#include "../pch.h"