hardware_mister_de0-nano-soc
MiSTer add-on board for DE0-Nano-SoC FPGA dev board.
Caution: althoug the version 0.2d was tested and seems to work, consider it as BETA. That means there might be slight modifications of the design in the future. There is a bunch of cores for the board released here: app.box.com in a form of an SD card image for DE0-nano-Soc board.
What is it for: an add-on board for Terasic DE0-Nano-SOC FPGA development board which is compatible (on hardware level) with the MiSTer project. Software (cores) are only compatible on the source code level, therefore have to be recompiled for DE0-Nano-SOC.
Who is it for: for adventurous tinkerers who already have DE0-Nano-Soc or DE0-Altas-SOC dev boards. If you don't have such a dev board, then the recomendation is to use DE10-Nano board which is superior to DE0-Nano-SOC and also have official support of MiSTer cores.
What can I find here: you can find a design file for the add-on board (IO board). It can be opened and edited in free gEDA-pcb editor (http://pcb.geda-project.org/). Also the gerber files are provided - the gerber zip file can be uploaded to PCB manufacturesrs like pcbway or allpcb and possibly others. Both of the mentioned PCB manufacturers had no problem producing the boards in the past using the provided zip file. You can also export your own gerbers directly from gEDA-pcb editor, just press the 'Export' option in the File menu to do that.
Manufacturing parameters:
- Type: Single PCB
- Size: 68 x 99mm (W x H)
- Layers: 2
- Thickness of board: 1.6mm
- Min hole size: 0.4mm
- Min spacing: 6/6 mil
- Finish: any is good, HASL with lead is the cheapest
- Via process: tenting
- Finished copper (thickness): 1oz
Schematic:
The board is hardware compatible with the original MiSTer IO board for DE10-nano, therefore the schematic is almost the same (missing TOS link on DE0ns).
Links: