diff --git a/LAB2.gise b/LAB2.gise index bcab7aa..c9bc3ef 100644 --- a/LAB2.gise +++ b/LAB2.gise @@ -88,11 +88,15 @@ + + + + @@ -133,11 +137,11 @@ + + - - @@ -173,17 +177,20 @@ - + - + + + + @@ -194,6 +201,7 @@ + @@ -206,25 +214,27 @@ - + - + - + - + + + @@ -235,6 +245,7 @@ + @@ -247,22 +258,30 @@ - + + + + + - - + + - + + + + + - + diff --git a/LAB2.xise b/LAB2.xise index cb5f812..4315350 100644 --- a/LAB2.xise +++ b/LAB2.xise @@ -17,7 +17,7 @@ - + @@ -30,11 +30,11 @@ - + - + @@ -50,7 +50,7 @@ - + @@ -60,7 +60,7 @@ - + @@ -74,7 +74,7 @@ - + @@ -102,11 +102,11 @@ - + - - + + @@ -115,22 +115,22 @@ - - + + - + - + - + @@ -139,15 +139,25 @@ - - + + - + + + + + + + + + + + @@ -374,8 +384,8 @@ - - + + @@ -391,7 +401,7 @@ - + @@ -441,7 +451,7 @@ - + diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs index 6952683..b581608 100644 --- a/_xmsgs/pn_parser.xmsgs +++ b/_xmsgs/pn_parser.xmsgs @@ -8,7 +8,16 @@ -Parsing VHDL file "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/fetch.vhd" into library work +Parsing VHDL file "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/cpu.vhd" into library work + + +"C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/cpu.vhd" Line 101. Syntax error near "in". + + +"C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/cpu.vhd" Line 123. Syntax error near "ControlSignals". + + +"C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/cpu.vhd" Line 127. Syntax error near "end". diff --git a/asm/test1.asm b/asm/test1.asm index 3fd9769..97907b1 100644 --- a/asm/test1.asm +++ b/asm/test1.asm @@ -2,6 +2,8 @@ val: .word 10,7,5 .text -li $t1,10 -li $t2,15 -add $t3, $t2, $t1 \ No newline at end of file +li $t1,0x10010000 +lw $t2,1($t1) +add $t3, $t2, $t1 +sub $t3, $t2, $t1 + diff --git a/asm/test2.hex b/asm/test2.hex new file mode 100644 index 0000000..bac8ede --- /dev/null +++ b/asm/test2.hex @@ -0,0 +1,2 @@ +8d490064 +8d2b000e diff --git a/asm/zero.hex b/asm/zero.hex new file mode 100644 index 0000000..728c801 --- /dev/null +++ b/asm/zero.hex @@ -0,0 +1,2 @@ +8d480064 +8d2b000e diff --git a/cpu.vhd b/cpu.vhd new file mode 100644 index 0000000..03ef8b2 --- /dev/null +++ b/cpu.vhd @@ -0,0 +1,128 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 05:33:54 10/24/2013 +-- Design Name: +-- Module Name: cpu - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity cpu is + Port ( CLK : in STD_LOGIC; + DInstruction : out std_logic_vector(31 downto 0); + DRamWord0 : out std_logic_vector(31 downto 0); + DRamWord1 : out std_logic_vector(31 downto 0)); +end cpu; + +architecture Behavioral of cpu is + +component fetch is + Port(CLK : in std_logic; + isJump : in std_logic; + jumpAddress : in std_logic_vector(31 downto 0); + programCounter : out std_logic_vector(31 downto 0); + currentInstruction : out std_logic_vector(31 downto 0)); + +end component; + +component decode is + PORT( CLK : in std_logic; + CurrentInstruction : in std_logic_vector(31 downto 0); + WriteAddr : in std_logic_vector(4 downto 0); + WriteData : in std_logic_vector(31 downto 0); + RegWrite : in std_logic; + AluOP1 : out std_logic_vector(31 downto 0); + AluOP2 : out std_logic_vector(31 downto 0); + AluControl : out std_logic_vector(5 downto 0); + ControlSignals : out std_logic_vector(5 downto 0)); +end component; + +component alu is +Port ( Clk : in STD_LOGIC; + Control : in STD_LOGIC_VECTOR (5 downto 0); + Operand1 : in STD_LOGIC_VECTOR (31 downto 0); + Operand2 : in STD_LOGIC_VECTOR (31 downto 0); + Result1 : out STD_LOGIC_VECTOR (31 downto 0); + Result2 : out STD_LOGIC_VECTOR (31 downto 0); + Debug : out STD_LOGIC_VECTOR (31 downto 0)); +end component; + +component ram is + port (CLK : in std_logic; + WE : in std_logic; + EN : in std_logic; + ADDR : in std_logic_vector(11 downto 0); + DI : in std_logic_vector(31 downto 0); + DO : out std_logic_vector(31 downto 0)); +end component; + +signal fetch_isJump : std_logic := '0'; +signal fetch_jumpAddress : std_logic_vector(31 downto 0) := (others => '0'); +signal fetch_programCounter : std_logic_vector(31 downto 0) := (others => '0'); + +signal decode_CurrentInstruction : std_logic_vector(31 downto 0) := (others => '0'); +signal decode_WriteAddr : std_logic_vector(4 downto 0) := (others => '0'); +signal decode_WriteData : std_logic_vector(31 downto 0) := (others => '0'); +signal decode_RegWrite : std_logic := '0'; +signal decode_AluOP1 : std_logic_vector(31 downto 0) := (others => '0'); +signal decode_AluOP2 : std_logic_vector(31 downto 0) := (others => '0'); +signal decode_AluControl : std_logic_vector(5 downto 0) := (others => '0'); +signal decode_ControlSignals : std_logic_vector(5 downto 0) := (others => '0'); + +signal alu_control : std_logic_vector(5 downto 0) := (others => '0'); +signal alu_op1 : std_logic_vector(31 downto 0) := (others => '0'); +signal alu_op2 : std_logic_vector(31 downto 0) := (others => '0'); +signal alu_r1 : std_logic_vector(31 downto 0) := (others => '0'); +signal alu_r2 : std_logic_vector(31 downto 0) := (others => '0'); +signal alu_debug : std_logic_vector(31 downto 0) := (others => '0'); + +signal ram_we : in std_logic := '0'; +signal ram_en : in std_logic := '1'; +signal ram_addr : in std_logic_vector(11 downto 0) := (others => '0'); +signal ram_di : std_logic_vector(31 downto 0) := (others => '0'); +signal ram_do : std_logic_vector(31 downto 0) := (others => '0'); + +begin + +ifetch : fetch port map (CLK => CLK, + isJump => fetch_isJump, + jumpAddress => fetch_jumpAddress, + programCounter => fetch_programCounter, + currentInstruction => decode_currentInstruction); + +idecode : fetch port map (CLK => CLK, + CurrentInstruction => decode_currentInstruction, + WriteAddr => decode_WriteAddr, + WriteData => decode_WriteData, + RegWrite => decode_RegWrite, + AluOP1 => decode_AluOP1, + AluOP2 => decode_AluOP2, + AluControl => decode_AluControl + ControlSignals => decode_ControlSignals); + +ialu : alu port map + +end Behavioral; + diff --git a/decode.vhd b/decode.vhd new file mode 100644 index 0000000..616e032 --- /dev/null +++ b/decode.vhd @@ -0,0 +1,103 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 03:23:31 10/24/2013 +-- Design Name: +-- Module Name: decode - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.utils.ALL; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity decode is + PORT( CLK : in std_logic; + CurrentInstruction : in std_logic_vector(31 downto 0); + WriteAddr : in std_logic_vector(4 downto 0); + WriteData : in std_logic_vector(31 downto 0); + RegWrite : in std_logic; + AluOP1 : out std_logic_vector(31 downto 0); + AluOP2 : out std_logic_vector(31 downto 0); + AluControl : out std_logic_vector(5 downto 0); + ControlSignals : out std_logic_vector(5 downto 0)); +end decode; + +architecture Behavioral of decode is + +begin + +process(CLK) + variable registerFile : RegisterSet := (others => (others => '0')); + variable opcode : std_logic_vector(5 downto 0) := (others => '0'); +begin + if rising_edge(CLK) then + + opcode := currentInstruction(31 downto 26); + ControlSignals <= (others => '0'); + -- R type + if opcode = b"000000" then + + -- funct portion of Current Instruction + AluControl <= CurrentInstruction(5 downto 0); + + -- load operand 1 with register whose address is in rs + AluOP1 <= registerFile(to_integer(unsigned(currentInstruction(25 downto 21)))); + + + if (CurrentInstruction(5 downto 0) = b"00000" or + CurrentInstruction(5 downto 0) = b"00010" or + CurrentInstruction(5 downto 0) = b"00011") then + -- load operand 2 with shamt + AluOP2 <= x"000000" & b"000" & CurrentInstruction(10 downto 6); + else + -- load operand 2 with register whose address is in rt + AluOP2 <= registerFile(to_integer(unsigned(currentInstruction(20 downto 16)))); + end if; + -- sets register whose address is at rd to alu_result1 + --registerFile(to_integer(unsigned(currentInstruction(15 downto 11)))) := alu_result1; + + -- I types + elsif opcode = b"100011" then + -- Load Word (23) + -- sign extension to offset + AluOP2 <= x"0000" & CurrentInstruction(15 downto 0); + -- currentInstruction (25 downto 21) denotes rs, which contains base address + AluOp1 <= registerFile(to_integer(unsigned(currentInstruction(25 downto 21)))); + -- Alu Control set to Add. + AluControl <= b"100000"; + -- TODO set ControlSignals appropriately + + elsif opcode = b"101011" then + -- Store Word (2B) + AluOP2 <= x"0000" & CurrentInstruction(15 downto 0); + -- currentInstruction (25 downto 21) denotes rs, which contains base address + AluOp1 <= registerFile(to_integer(unsigned(currentInstruction(25 downto 21)))); + -- Alu Control set to Add. + AluControl <= b"100000"; + + end if; + + end if; +end process; + +end Behavioral; + diff --git a/fetch.prj b/fetch.prj new file mode 100644 index 0000000..3c1657a --- /dev/null +++ b/fetch.prj @@ -0,0 +1,3 @@ +vhdl work "utils.vhd" +vhdl work "rom.vhd" +vhdl work "fetch.vhd" diff --git a/fetch.vhd b/fetch.vhd index 349cac5..a239547 100644 --- a/fetch.vhd +++ b/fetch.vhd @@ -40,7 +40,7 @@ end fetch; architecture Behavioral of fetch is component rom is - port (CLK : in std_logic; + port ( EN : in std_logic; ADDR : in std_logic_vector(31 downto 0); DATA : out std_logic_vector(31 downto 0)); @@ -54,7 +54,7 @@ signal rom_DATA : std_logic_vector(31 downto 0); begin -hunars_rom : rom port map(CLK => CLK, +hunars_rom : rom port map( EN => rom_EN, ADDR => rom_ADDR, DATA => rom_DATA); @@ -66,19 +66,14 @@ begin if rising_edge(CLK) then ciR := rom_data; - - - + pcR := std_logic_vector(unsigned(pcR) + 4); programCounter <= pcr; currentInstruction <= ciR; if isJump = '1' then pcR := jumpAddress; - end if; + end if; - - - pcR := std_logic_vector(unsigned(pcR) + 4); rom_addr <= pcR; end if; end process; diff --git a/fetch.xst b/fetch.xst new file mode 100644 index 0000000..d853712 --- /dev/null +++ b/fetch.xst @@ -0,0 +1,5 @@ +set -tmpdir "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/xst/projnav.tmp" +set -xsthdpdir "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/xst" +elaborate +-ifn fetch.prj +-ifmt mixed diff --git a/fetch_vhdl.prj b/fetch_vhdl.prj new file mode 100644 index 0000000..0417ced --- /dev/null +++ b/fetch_vhdl.prj @@ -0,0 +1,3 @@ +vhdl work "C:\Users\Hunar Khanna\Desktop\CG3207\VHDL\lab2\cg3207-project\utils.vhd" +vhdl work "C:\Users\Hunar Khanna\Desktop\CG3207\VHDL\lab2\cg3207-project\rom.vhd" +vhdl work "C:\Users\Hunar Khanna\Desktop\CG3207\VHDL\lab2\cg3207-project\fetch.vhd" diff --git a/fuse.log b/fuse.log index bb99bc4..7107f64 100644 --- a/fuse.log +++ b/fuse.log @@ -1,12 +1,11 @@ -Running: C:\Xilinx\13.2\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/test_fetch_isim_beh.exe -prj C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/test_fetch_beh.prj work.test_fetch +Running: C:\Xilinx\13.2\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/ram_test_isim_beh.exe -prj C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/ram_test_beh.prj work.ram_test ISim O.61xd (signature 0x1cce1bb2) Number of CPUs detected in this system: 4 Turning on mult-threading, number of parallel sub-compilation jobs: 8 Determining compilation order of HDL files Parsing VHDL file "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/utils.vhd" into library work -Parsing VHDL file "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/rom.vhd" into library work -Parsing VHDL file "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/fetch.vhd" into library work -Parsing VHDL file "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/test_fetch.vhd" into library work +Parsing VHDL file "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/ram.vhd" into library work +Parsing VHDL file "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/ram_test.vhd" into library work Starting static elaboration Completed static elaboration Compiling package standard @@ -15,12 +14,13 @@ Compiling package numeric_std Compiling package textio Compiling package std_logic_textio Compiling package utils -Compiling architecture behavioral of entity rom [rom_default] -Compiling architecture behavioral of entity fetch [fetch_default] -Compiling architecture behavior of entity test_fetch +Compiling package std_logic_arith +Compiling package std_logic_unsigned +Compiling architecture behavioral of entity ram [ram_default] +Compiling architecture behavior of entity ram_test Time Resolution for simulation is 1ps. -Waiting for 2 sub-compilation(s) to finish... +Waiting for 1 sub-compilation(s) to finish... Compiled 11 VHDL Units -Built simulation executable C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/test_fetch_isim_beh.exe -Fuse Memory Usage: 24952 KB -Fuse CPU Usage: 280 ms +Built simulation executable C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/ram_test_isim_beh.exe +Fuse Memory Usage: 29232 KB +Fuse CPU Usage: 483 ms diff --git a/fuseRelaunch.cmd b/fuseRelaunch.cmd index 685bc24..70d336b 100644 --- a/fuseRelaunch.cmd +++ b/fuseRelaunch.cmd @@ -1 +1 @@ --intstyle "ise" -incremental -o "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/test_fetch_isim_beh.exe" -prj "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/test_fetch_beh.prj" "work.test_fetch" +-intstyle "ise" -incremental -o "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/ram_test_isim_beh.exe" -prj "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/ram_test_beh.prj" "work.ram_test" diff --git a/isim.log b/isim.log index e08b394..a950757 100644 --- a/isim.log +++ b/isim.log @@ -1,5 +1,5 @@ ISim log file -Running: C:\Users\Hunar Khanna\Desktop\CG3207\VHDL\lab2\cg3207-project\test_fetch_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/test_fetch_isim_beh.wdb +Running: C:\Users\Hunar Khanna\Desktop\CG3207\VHDL\lab2\cg3207-project\ram_test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/ram_test_isim_beh.wdb ISim O.61xd (signature 0x1cce1bb2) WARNING: A WEBPACK license was found. WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. diff --git a/isim/isim_usage_statistics.html b/isim/isim_usage_statistics.html index 9c18548..db1311d 100644 --- a/isim/isim_usage_statistics.html +++ b/isim/isim_usage_statistics.html @@ -2,4 +2,15 @@ ISim Statistics Xilinx HDL Libraries Used=ieee, std -Fuse Resource Usage=280 ms, 24952 KB +Fuse Resource Usage=483 ms, 29232 KB + +Total Signals=13 +Total Nets=32855 +Total Blocks=9 +Total Processes=3 +Total Simulation Time=400 ns +Simulation Resource Usage=0.0936 sec, 496300 KB +Simulation Mode=gui +Hardware CoSim=0 + + diff --git a/isim/precompiled.exe.sim/ieee/p_1242562249.didat b/isim/precompiled.exe.sim/ieee/p_1242562249.didat index ad8365b..4442062 100644 Binary files a/isim/precompiled.exe.sim/ieee/p_1242562249.didat and b/isim/precompiled.exe.sim/ieee/p_1242562249.didat differ diff --git a/isim/precompiled.exe.sim/ieee/p_2592010699.didat b/isim/precompiled.exe.sim/ieee/p_2592010699.didat index 1ae506d..dee5f1b 100644 Binary files a/isim/precompiled.exe.sim/ieee/p_2592010699.didat and b/isim/precompiled.exe.sim/ieee/p_2592010699.didat differ diff --git a/pepExtractor.prj b/pepExtractor.prj index f20c600..9ad6916 100644 --- a/pepExtractor.prj +++ b/pepExtractor.prj @@ -1,3 +1,2 @@ -work "fetch.vhd" -work "rom.vhd" +work "decode.vhd" work "utils.vhd" diff --git a/rom.vhd b/rom.vhd index 1b1c602..9edb79f 100644 --- a/rom.vhd +++ b/rom.vhd @@ -46,7 +46,6 @@ use work.utils.ALL; entity rom is port (EN : in std_logic; - CLK: in std_logic; ADDR : in std_logic_vector(31 downto 0); DATA : out std_logic_vector(31 downto 0)); end rom; @@ -56,19 +55,11 @@ architecture Behavioral of rom is signal rom_data : RomData := read_rom_from_file("asm\test1.hex"); begin -process(CLK) -begin - if rising_edge(CLK) then - if EN = '1' then - data <= (rom_data(to_integer(unsigned(addr) + 3))) & - (rom_data(to_integer(unsigned(addr) + 2))) & - (rom_data(to_integer(unsigned(addr) + 1))) & - (rom_data(to_integer(unsigned(addr)))); - else - data <= (others => '0'); - end if; - end if; - -end process; + data <= (rom_data(to_integer(unsigned(addr) + 3))) & + (rom_data(to_integer(unsigned(addr) + 2))) & + (rom_data(to_integer(unsigned(addr) + 1))) & + (rom_data(to_integer(unsigned(addr)))) when en ='1' else + (others => '0'); + end Behavioral; diff --git a/rom_test.vhd b/rom_test.vhd index 515b2f2..248c941 100644 --- a/rom_test.vhd +++ b/rom_test.vhd @@ -41,7 +41,7 @@ ARCHITECTURE behavior OF rom_test IS COMPONENT rom PORT( - CLK : IN std_logic; + -- CLK : IN std_logic; EN : IN std_logic; ADDR : IN std_logic_vector(31 downto 0); DATA : OUT std_logic_vector(31 downto 0) @@ -50,7 +50,7 @@ ARCHITECTURE behavior OF rom_test IS --Inputs - signal CLK : std_logic := '0'; + --signal CLK : std_logic := '0'; signal EN : std_logic := '1'; signal ADDR : std_logic_vector(31 downto 0) := (others => '0'); @@ -64,20 +64,20 @@ BEGIN -- Instantiate the Unit Under Test (UUT) uut: rom PORT MAP ( - CLK => CLK, + -- CLK => CLK, EN => EN, ADDR => ADDR, DATA => DATA ); -- Clock process definitions - CLK_process :process - begin - CLK <= '0'; - wait for CLK_period/2; - CLK <= '1'; - wait for CLK_period/2; - end process; + -- CLK_process :process +-- begin +-- --CLK <= '0'; +-- wait for CLK_period/2; +-- --CLK <= '1'; +-- wait for CLK_period/2; +-- end process; -- Stimulus process @@ -87,20 +87,20 @@ BEGIN wait for 100 ns; addr <= ( others => '0'); - wait for CLK_period*2; + --wait for CLK_period*2; addr <= (2=> '1' , others => '0'); - wait for CLK_period*2; + -- wait for CLK_period*2; addr <= (3=> '1' , others => '0'); - wait for CLK_period*2; + -- wait for CLK_period*2; addr <= std_logic_vector(unsigned(addr) + 4); - wait for CLK_period*2; + -- wait for CLK_period*2; addr <= std_logic_vector(unsigned(addr) + 4); - wait for CLK_period*2; + -- wait for CLK_period*2; addr <= std_logic_vector(unsigned(addr) + 4); diff --git a/test_decode.vhd b/test_decode.vhd new file mode 100644 index 0000000..7339566 --- /dev/null +++ b/test_decode.vhd @@ -0,0 +1,116 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 03:57:07 10/24/2013 +-- Design Name: +-- Module Name: C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/test_decode.vhd +-- Project Name: LAB2 +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: decode +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY test_decode IS +END test_decode; + +ARCHITECTURE behavior OF test_decode IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT decode + PORT( + CLK : IN std_logic; + CurrentInstruction : IN std_logic_vector(31 downto 0); + WriteAddr : IN std_logic_vector(4 downto 0); + WriteData : IN std_logic_vector(31 downto 0); + RegWrite : IN std_logic; + AluOP1 : OUT std_logic_vector(31 downto 0); + AluOP2 : OUT std_logic_vector(31 downto 0); + AluControl : OUT std_logic_vector(5 downto 0); + ControlSignals : OUT std_logic_vector(5 downto 0) + ); + END COMPONENT; + + + --Inputs + signal CLK : std_logic := '0'; + signal CurrentInstruction : std_logic_vector(31 downto 0) := (others => '0'); + signal WriteAddr : std_logic_vector(4 downto 0) := (others => '0'); + signal WriteData : std_logic_vector(31 downto 0) := (others => '0'); + signal RegWrite : std_logic := '0'; + + --Outputs + signal AluOP1 : std_logic_vector(31 downto 0); + signal AluOP2 : std_logic_vector(31 downto 0); + signal AluControl : std_logic_vector(5 downto 0); + signal ControlSignals : std_logic_vector(5 downto 0); + + -- Clock period definitions + constant CLK_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: decode PORT MAP ( + CLK => CLK, + CurrentInstruction => CurrentInstruction, + WriteAddr => WriteAddr, + WriteData => WriteData, + RegWrite => RegWrite, + AluOP1 => AluOP1, + AluOP2 => AluOP2, + AluControl => AluControl, + ControlSignals => ControlSignals + ); + + -- Clock process definitions + CLK_process :process + begin + CLK <= '0'; + wait for CLK_period/2; + CLK <= '1'; + wait for CLK_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ns. + wait for 100 ns; + CurrentInstruction <= x"01495820"; + + wait for CLK_period; + CurrentInstruction <= x"8d490064"; + + wait for CLK_period; + CurrentInstruction <= x"8d2b000e"; + + -- insert stimulus here + + wait; + end process; + +END; diff --git a/xst/work/hdllib.ref b/xst/work/hdllib.ref index 7869750..4a665ff 100644 --- a/xst/work/hdllib.ref +++ b/xst/work/hdllib.ref @@ -1,16 +1,17 @@ -PH utils NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/utils.vhd" sub00/vhpl22 1382092833 +PH utils NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/utils.vhd" sub00/vhpl22 1382555193 AR addsub32 behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/addsub32.vhd" sub00/vhpl06 1382092836 EN udiv32 NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/udiv32.vhd" sub00/vhpl18 1381434600 EN uaddsub32 NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/uaddsub32.vhd" sub00/vhpl07 1382092837 AR uaddsub32 behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/uaddsub32.vhd" sub00/vhpl08 1382092838 AR control_unit behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/control_unit.vhd" sub00/vhpl27 1382092850 -EN rom NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/rom.vhd" sub00/vhpl20 1382092847 -AR rom behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/rom.vhd" sub00/vhpl21 1382092848 +EN rom NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/rom.vhd" sub00/vhpl20 1382555195 +AR rom behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/rom.vhd" sub00/vhpl21 1382555196 EN lab2 NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/LAB2.vhd" sub00/vhpl13 1381437351 EN mul32 NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/mul32.vhd" sub00/vhpl10 1382092839 AR uadder32 behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/uadder32.vhd" sub00/vhpl02 1382092830 EN addsub32 NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/addsub32.vhd" sub00/vhpl05 1382092835 EN uadder32 NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/uadder32.vhd" sub00/vhpl01 1382092829 +AR fetch behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/fetch.vhd" sub00/vhpl29 1382555198 AR ram behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/ram.vhd" sub00/vhpl25 1382092846 AR umul32 behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/umul32.vhd" sub00/vhpl16 1381425090 AR udiv32 behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/udiv32.vhd" sub00/vhpl19 1381434601 @@ -19,9 +20,10 @@ AR adder32 behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-pro EN adder32 NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/adder32.vhd" sub00/vhpl03 1382092831 EN umul32 NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/umul32.vhd" sub00/vhpl15 1381425089 AR alu behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/alu.vhd" sub00/vhpl09 1382092844 -PB utils utils "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/utils.vhd" sub00/vhpl23 1382092834 +PB utils utils "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/utils.vhd" sub00/vhpl23 1382555194 EN control_unit NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/control_unit.vhd" sub00/vhpl26 1382092849 EN ram NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/ram.vhd" sub00/vhpl24 1382092845 +EN fetch NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/fetch.vhd" sub00/vhpl28 1382555197 AR lab2 structural "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/LAB2.vhd" sub00/vhpl14 1381437352 AR mul32 behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/mul32.vhd" sub00/vhpl17 1382092840 EN alu NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/alu.vhd" sub00/vhpl00 1382092843 diff --git a/xst/work/hdpdeps.ref b/xst/work/hdpdeps.ref index 8adcf6e..bb8d920 100644 --- a/xst/work/hdpdeps.ref +++ b/xst/work/hdpdeps.ref @@ -1,4 +1,4 @@ -V3 60 +V3 63 FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/adder32.vhd" 2013/10/09.09:07:55 O.61xd EN work/adder32 1382092831 \ FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/adder32.vhd" \ @@ -23,7 +23,7 @@ AR work/alu/Behavioral 1382092844 \ FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/control_unit.vhd" 2013/10/18.18:40:27 O.61xd EN work/control_unit 1382092849 \ FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/control_unit.vhd" \ - PB ieee/std_logic_1164 1308643377 PB work/utils 1382092834 \ + PB ieee/std_logic_1164 1308643377 PB work/utils 1382555194 \ PB ieee/NUMERIC_STD 1308643378 AR work/control_unit/Behavioral 1382092850 \ FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/control_unit.vhd" \ @@ -35,6 +35,13 @@ EN work/div32 1382092841 \ AR work/div32/Behavioral 1382092842 \ FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/div32.vhd" \ EN work/div32 1382092841 +FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/fetch.vhd" 2013/10/24.03:06:14 O.61xd +EN work/fetch 1382555197 \ + FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/fetch.vhd" \ + PB ieee/std_logic_1164 1308643377 PB ieee/NUMERIC_STD 1308643378 +AR work/fetch/Behavioral 1382555198 \ + FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/fetch.vhd" \ + EN work/fetch 1382555197 CP rom FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/LAB2.vhd" 2013/10/09.09:07:55 O.61xd EN work/LAB2 1381437351 \ FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/LAB2.vhd" \ @@ -54,19 +61,19 @@ FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/ram.vhd" 2013/ EN work/ram 1382092845 \ FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/ram.vhd" \ PB ieee/std_logic_1164 1308643377 PB ieee/NUMERIC_STD 1308643378 \ - PB work/utils 1382092834 PB ieee/STD_LOGIC_UNSIGNED 1308643379 + PB work/utils 1382555194 PB ieee/STD_LOGIC_UNSIGNED 1308643379 AR work/ram/Behavioral 1382092846 \ FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/ram.vhd" \ EN work/ram 1382092845 -FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/rom.vhd" 2013/10/18.16:52:21 O.61xd -EN work/rom 1382092847 \ +FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/rom.vhd" 2013/10/24.03:02:45 O.61xd +EN work/rom 1382555195 \ FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/rom.vhd" \ PB std/TEXTIO 1308643377 PB ieee/std_logic_1164 1308643377 \ PB ieee/STD_LOGIC_TEXTIO 1308643378 PB ieee/NUMERIC_STD 1308643378 \ - PB work/utils 1382092834 -AR work/rom/Behavioral 1382092848 \ + PB work/utils 1382555194 +AR work/rom/Behavioral 1382555196 \ FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/rom.vhd" \ - EN work/rom 1382092847 + EN work/rom 1382555195 FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/uadder32.vhd" 2013/10/09.09:07:55 O.61xd EN work/uadder32 1382092829 \ FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/uadder32.vhd" \ @@ -96,13 +103,13 @@ AR work/umul32/Behavioral 1381425090 \ FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/umul32.vhd" \ EN work/umul32 1381425089 FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/utils.vhd" 2013/10/18.18:25:06 O.61xd -PH work/utils 1382092833 \ +PH work/utils 1382555193 \ FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/utils.vhd" \ PB std/TEXTIO 1308643377 PB ieee/std_logic_1164 1308643377 \ PB ieee/STD_LOGIC_TEXTIO 1308643378 PB ieee/NUMERIC_STD 1308643378 -PB work/utils 1382092834 \ +PB work/utils 1382555194 \ FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/utils.vhd" \ - PH work/utils 1382092833 + PH work/utils 1382555193 FL "C:/Users/pc richard/Documents/CG3207/cg3207-project/adder32.vhd" 2013/10/05.22:29:37 O.61xd FL "C:/Users/pc richard/Documents/CG3207/cg3207-project/addsub32.vhd" 2013/10/05.22:47:14 O.61xd FL "C:/Users/pc richard/Documents/CG3207/cg3207-project/alu.vhd" 2013/10/09.11:38:42 O.61xd