ISim Statistics |
Xilinx HDL Libraries Used=ieee, std |
-Fuse Resource Usage=280 ms, 24952 KB |
+Fuse Resource Usage=483 ms, 29232 KB |
+
+Total Signals=13 |
+Total Nets=32855 |
+Total Blocks=9 |
+Total Processes=3 |
+Total Simulation Time=400 ns |
+Simulation Resource Usage=0.0936 sec, 496300 KB |
+Simulation Mode=gui |
+Hardware CoSim=0 |
+
+
diff --git a/isim/precompiled.exe.sim/ieee/p_1242562249.didat b/isim/precompiled.exe.sim/ieee/p_1242562249.didat
index ad8365b..4442062 100644
Binary files a/isim/precompiled.exe.sim/ieee/p_1242562249.didat and b/isim/precompiled.exe.sim/ieee/p_1242562249.didat differ
diff --git a/isim/precompiled.exe.sim/ieee/p_2592010699.didat b/isim/precompiled.exe.sim/ieee/p_2592010699.didat
index 1ae506d..dee5f1b 100644
Binary files a/isim/precompiled.exe.sim/ieee/p_2592010699.didat and b/isim/precompiled.exe.sim/ieee/p_2592010699.didat differ
diff --git a/pepExtractor.prj b/pepExtractor.prj
index f20c600..9ad6916 100644
--- a/pepExtractor.prj
+++ b/pepExtractor.prj
@@ -1,3 +1,2 @@
-work "fetch.vhd"
-work "rom.vhd"
+work "decode.vhd"
work "utils.vhd"
diff --git a/rom.vhd b/rom.vhd
index 1b1c602..9edb79f 100644
--- a/rom.vhd
+++ b/rom.vhd
@@ -46,7 +46,6 @@ use work.utils.ALL;
entity rom is
port (EN : in std_logic;
- CLK: in std_logic;
ADDR : in std_logic_vector(31 downto 0);
DATA : out std_logic_vector(31 downto 0));
end rom;
@@ -56,19 +55,11 @@ architecture Behavioral of rom is
signal rom_data : RomData := read_rom_from_file("asm\test1.hex");
begin
-process(CLK)
-begin
- if rising_edge(CLK) then
- if EN = '1' then
- data <= (rom_data(to_integer(unsigned(addr) + 3))) &
- (rom_data(to_integer(unsigned(addr) + 2))) &
- (rom_data(to_integer(unsigned(addr) + 1))) &
- (rom_data(to_integer(unsigned(addr))));
- else
- data <= (others => '0');
- end if;
- end if;
-
-end process;
+ data <= (rom_data(to_integer(unsigned(addr) + 3))) &
+ (rom_data(to_integer(unsigned(addr) + 2))) &
+ (rom_data(to_integer(unsigned(addr) + 1))) &
+ (rom_data(to_integer(unsigned(addr)))) when en ='1' else
+ (others => '0');
+
end Behavioral;
diff --git a/rom_test.vhd b/rom_test.vhd
index 515b2f2..248c941 100644
--- a/rom_test.vhd
+++ b/rom_test.vhd
@@ -41,7 +41,7 @@ ARCHITECTURE behavior OF rom_test IS
COMPONENT rom
PORT(
- CLK : IN std_logic;
+ -- CLK : IN std_logic;
EN : IN std_logic;
ADDR : IN std_logic_vector(31 downto 0);
DATA : OUT std_logic_vector(31 downto 0)
@@ -50,7 +50,7 @@ ARCHITECTURE behavior OF rom_test IS
--Inputs
- signal CLK : std_logic := '0';
+ --signal CLK : std_logic := '0';
signal EN : std_logic := '1';
signal ADDR : std_logic_vector(31 downto 0) := (others => '0');
@@ -64,20 +64,20 @@ BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: rom PORT MAP (
- CLK => CLK,
+ -- CLK => CLK,
EN => EN,
ADDR => ADDR,
DATA => DATA
);
-- Clock process definitions
- CLK_process :process
- begin
- CLK <= '0';
- wait for CLK_period/2;
- CLK <= '1';
- wait for CLK_period/2;
- end process;
+ -- CLK_process :process
+-- begin
+-- --CLK <= '0';
+-- wait for CLK_period/2;
+-- --CLK <= '1';
+-- wait for CLK_period/2;
+-- end process;
-- Stimulus process
@@ -87,20 +87,20 @@ BEGIN
wait for 100 ns;
addr <= ( others => '0');
- wait for CLK_period*2;
+ --wait for CLK_period*2;
addr <= (2=> '1' , others => '0');
- wait for CLK_period*2;
+ -- wait for CLK_period*2;
addr <= (3=> '1' , others => '0');
- wait for CLK_period*2;
+ -- wait for CLK_period*2;
addr <= std_logic_vector(unsigned(addr) + 4);
- wait for CLK_period*2;
+ -- wait for CLK_period*2;
addr <= std_logic_vector(unsigned(addr) + 4);
- wait for CLK_period*2;
+ -- wait for CLK_period*2;
addr <= std_logic_vector(unsigned(addr) + 4);
diff --git a/test_decode.vhd b/test_decode.vhd
new file mode 100644
index 0000000..7339566
--- /dev/null
+++ b/test_decode.vhd
@@ -0,0 +1,116 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 03:57:07 10/24/2013
+-- Design Name:
+-- Module Name: C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/test_decode.vhd
+-- Project Name: LAB2
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: decode
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY test_decode IS
+END test_decode;
+
+ARCHITECTURE behavior OF test_decode IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT decode
+ PORT(
+ CLK : IN std_logic;
+ CurrentInstruction : IN std_logic_vector(31 downto 0);
+ WriteAddr : IN std_logic_vector(4 downto 0);
+ WriteData : IN std_logic_vector(31 downto 0);
+ RegWrite : IN std_logic;
+ AluOP1 : OUT std_logic_vector(31 downto 0);
+ AluOP2 : OUT std_logic_vector(31 downto 0);
+ AluControl : OUT std_logic_vector(5 downto 0);
+ ControlSignals : OUT std_logic_vector(5 downto 0)
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal CLK : std_logic := '0';
+ signal CurrentInstruction : std_logic_vector(31 downto 0) := (others => '0');
+ signal WriteAddr : std_logic_vector(4 downto 0) := (others => '0');
+ signal WriteData : std_logic_vector(31 downto 0) := (others => '0');
+ signal RegWrite : std_logic := '0';
+
+ --Outputs
+ signal AluOP1 : std_logic_vector(31 downto 0);
+ signal AluOP2 : std_logic_vector(31 downto 0);
+ signal AluControl : std_logic_vector(5 downto 0);
+ signal ControlSignals : std_logic_vector(5 downto 0);
+
+ -- Clock period definitions
+ constant CLK_period : time := 10 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: decode PORT MAP (
+ CLK => CLK,
+ CurrentInstruction => CurrentInstruction,
+ WriteAddr => WriteAddr,
+ WriteData => WriteData,
+ RegWrite => RegWrite,
+ AluOP1 => AluOP1,
+ AluOP2 => AluOP2,
+ AluControl => AluControl,
+ ControlSignals => ControlSignals
+ );
+
+ -- Clock process definitions
+ CLK_process :process
+ begin
+ CLK <= '0';
+ wait for CLK_period/2;
+ CLK <= '1';
+ wait for CLK_period/2;
+ end process;
+
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ wait for 100 ns;
+ CurrentInstruction <= x"01495820";
+
+ wait for CLK_period;
+ CurrentInstruction <= x"8d490064";
+
+ wait for CLK_period;
+ CurrentInstruction <= x"8d2b000e";
+
+ -- insert stimulus here
+
+ wait;
+ end process;
+
+END;
diff --git a/xst/work/hdllib.ref b/xst/work/hdllib.ref
index 7869750..4a665ff 100644
--- a/xst/work/hdllib.ref
+++ b/xst/work/hdllib.ref
@@ -1,16 +1,17 @@
-PH utils NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/utils.vhd" sub00/vhpl22 1382092833
+PH utils NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/utils.vhd" sub00/vhpl22 1382555193
AR addsub32 behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/addsub32.vhd" sub00/vhpl06 1382092836
EN udiv32 NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/udiv32.vhd" sub00/vhpl18 1381434600
EN uaddsub32 NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/uaddsub32.vhd" sub00/vhpl07 1382092837
AR uaddsub32 behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/uaddsub32.vhd" sub00/vhpl08 1382092838
AR control_unit behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/control_unit.vhd" sub00/vhpl27 1382092850
-EN rom NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/rom.vhd" sub00/vhpl20 1382092847
-AR rom behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/rom.vhd" sub00/vhpl21 1382092848
+EN rom NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/rom.vhd" sub00/vhpl20 1382555195
+AR rom behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/rom.vhd" sub00/vhpl21 1382555196
EN lab2 NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/LAB2.vhd" sub00/vhpl13 1381437351
EN mul32 NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/mul32.vhd" sub00/vhpl10 1382092839
AR uadder32 behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/uadder32.vhd" sub00/vhpl02 1382092830
EN addsub32 NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/addsub32.vhd" sub00/vhpl05 1382092835
EN uadder32 NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/uadder32.vhd" sub00/vhpl01 1382092829
+AR fetch behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/fetch.vhd" sub00/vhpl29 1382555198
AR ram behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/ram.vhd" sub00/vhpl25 1382092846
AR umul32 behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/umul32.vhd" sub00/vhpl16 1381425090
AR udiv32 behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/udiv32.vhd" sub00/vhpl19 1381434601
@@ -19,9 +20,10 @@ AR adder32 behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-pro
EN adder32 NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/adder32.vhd" sub00/vhpl03 1382092831
EN umul32 NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/umul32.vhd" sub00/vhpl15 1381425089
AR alu behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/alu.vhd" sub00/vhpl09 1382092844
-PB utils utils "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/utils.vhd" sub00/vhpl23 1382092834
+PB utils utils "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/utils.vhd" sub00/vhpl23 1382555194
EN control_unit NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/control_unit.vhd" sub00/vhpl26 1382092849
EN ram NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/ram.vhd" sub00/vhpl24 1382092845
+EN fetch NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/fetch.vhd" sub00/vhpl28 1382555197
AR lab2 structural "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/LAB2.vhd" sub00/vhpl14 1381437352
AR mul32 behavioral "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/mul32.vhd" sub00/vhpl17 1382092840
EN alu NULL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/alu.vhd" sub00/vhpl00 1382092843
diff --git a/xst/work/hdpdeps.ref b/xst/work/hdpdeps.ref
index 8adcf6e..bb8d920 100644
--- a/xst/work/hdpdeps.ref
+++ b/xst/work/hdpdeps.ref
@@ -1,4 +1,4 @@
-V3 60
+V3 63
FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/adder32.vhd" 2013/10/09.09:07:55 O.61xd
EN work/adder32 1382092831 \
FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/adder32.vhd" \
@@ -23,7 +23,7 @@ AR work/alu/Behavioral 1382092844 \
FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/control_unit.vhd" 2013/10/18.18:40:27 O.61xd
EN work/control_unit 1382092849 \
FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/control_unit.vhd" \
- PB ieee/std_logic_1164 1308643377 PB work/utils 1382092834 \
+ PB ieee/std_logic_1164 1308643377 PB work/utils 1382555194 \
PB ieee/NUMERIC_STD 1308643378
AR work/control_unit/Behavioral 1382092850 \
FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/control_unit.vhd" \
@@ -35,6 +35,13 @@ EN work/div32 1382092841 \
AR work/div32/Behavioral 1382092842 \
FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/div32.vhd" \
EN work/div32 1382092841
+FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/fetch.vhd" 2013/10/24.03:06:14 O.61xd
+EN work/fetch 1382555197 \
+ FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/fetch.vhd" \
+ PB ieee/std_logic_1164 1308643377 PB ieee/NUMERIC_STD 1308643378
+AR work/fetch/Behavioral 1382555198 \
+ FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/fetch.vhd" \
+ EN work/fetch 1382555197 CP rom
FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/LAB2.vhd" 2013/10/09.09:07:55 O.61xd
EN work/LAB2 1381437351 \
FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/LAB2.vhd" \
@@ -54,19 +61,19 @@ FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/ram.vhd" 2013/
EN work/ram 1382092845 \
FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/ram.vhd" \
PB ieee/std_logic_1164 1308643377 PB ieee/NUMERIC_STD 1308643378 \
- PB work/utils 1382092834 PB ieee/STD_LOGIC_UNSIGNED 1308643379
+ PB work/utils 1382555194 PB ieee/STD_LOGIC_UNSIGNED 1308643379
AR work/ram/Behavioral 1382092846 \
FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/ram.vhd" \
EN work/ram 1382092845
-FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/rom.vhd" 2013/10/18.16:52:21 O.61xd
-EN work/rom 1382092847 \
+FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/rom.vhd" 2013/10/24.03:02:45 O.61xd
+EN work/rom 1382555195 \
FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/rom.vhd" \
PB std/TEXTIO 1308643377 PB ieee/std_logic_1164 1308643377 \
PB ieee/STD_LOGIC_TEXTIO 1308643378 PB ieee/NUMERIC_STD 1308643378 \
- PB work/utils 1382092834
-AR work/rom/Behavioral 1382092848 \
+ PB work/utils 1382555194
+AR work/rom/Behavioral 1382555196 \
FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/rom.vhd" \
- EN work/rom 1382092847
+ EN work/rom 1382555195
FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/uadder32.vhd" 2013/10/09.09:07:55 O.61xd
EN work/uadder32 1382092829 \
FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/uadder32.vhd" \
@@ -96,13 +103,13 @@ AR work/umul32/Behavioral 1381425090 \
FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/umul32.vhd" \
EN work/umul32 1381425089
FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/utils.vhd" 2013/10/18.18:25:06 O.61xd
-PH work/utils 1382092833 \
+PH work/utils 1382555193 \
FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/utils.vhd" \
PB std/TEXTIO 1308643377 PB ieee/std_logic_1164 1308643377 \
PB ieee/STD_LOGIC_TEXTIO 1308643378 PB ieee/NUMERIC_STD 1308643378
-PB work/utils 1382092834 \
+PB work/utils 1382555194 \
FL "C:/Users/Hunar Khanna/Desktop/CG3207/VHDL/lab2/cg3207-project/utils.vhd" \
- PH work/utils 1382092833
+ PH work/utils 1382555193
FL "C:/Users/pc richard/Documents/CG3207/cg3207-project/adder32.vhd" 2013/10/05.22:29:37 O.61xd
FL "C:/Users/pc richard/Documents/CG3207/cg3207-project/addsub32.vhd" 2013/10/05.22:47:14 O.61xd
FL "C:/Users/pc richard/Documents/CG3207/cg3207-project/alu.vhd" 2013/10/09.11:38:42 O.61xd