CAPI=2:
# TOP block core file example
name: "X:Y:top_block:1.0.0"
description: Top block example
filesets:
  files_rtl:
    depend:
      - X:Y:Z1:1.0.0
      - X:Y:Z2:1.0.0
      - X:Y:analog_block:1.0.0
    files:
      - src/top1.v
      - src/top2.v
      - src/top3.v
    file_type: verilogSource

#
targets:
  default: &default_target
    filesets:
      - files_rtl
    toplevel: top_block

  sim:
    <<: *default_target
    default_tool: vcs
#