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4bc042b initial public release v1.50
Patrick Titiano authored
1 /*
2 *
3 * @Component OMAPCONF
4 * @Filename vc.c
5 * @Description VOLTAGE CONTROLLER (VC) Common Definitions &
6 * Functions
7 * @Author Patrick Titiano (p-titiano@ti.com)
8 * @Date 2006
9 * @Copyright Texas Instruments Incorporated
10 *
11 *
12 * Copyright (C) 2006 Texas Instruments Incorporated - http://www.ti.com/
13 *
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 *
19 * Redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer.
21 *
22 * Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the
25 * distribution.
26 *
27 * Neither the name of Texas Instruments Incorporated nor the names of
28 * its contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 */
44
45
46 #include <vc.h>
47 #include <lib.h>
48 #include <cpuinfo.h>
49 #include <clock44xx.h>
50 #include <clock54xx.h>
51 #include <autoadjust_table.h>
52
53
54 #define VC_ON_POS 24
55 #define VC_ON_LEN 8
56 #define VC_ONLP_POS 16
57 #define VC_ONLP_LEN 8
58 #define VC_RET_POS 8
59 #define VC_RET_LEN 8
60 #define VC_OFF_POS 0
61 #define VC_OFF_LEN 8
62
63 #define VC_DFILTEREN_POS 6
64 #define VC_SRMODEEN_POS 4
65 #define VC_HSMODEEN_POS 3
66 #define VC_HSMCODE_POS 0
67 #define VC_HSMCODE_LEN 3
68
69 #define VC_HSSCLL_POS 24
70 #define VC_HSSCLL_LEN 8
71 #define VC_HSSCLH_POS 16
72 #define VC_HSSCLH_LEN 8
73 #define VC_SCLL_POS 8
74 #define VC_SCLL_LEN 8
75 #define VC_SCLH_POS 0
76 #define VC_SCLH_LEN 8
77
78
79 /* ------------------------------------------------------------------------*//**
80 * @FUNCTION vc_cmd_values_get
81 * @BRIEF return ON/ONLP/RET/OFF command values
82 * @RETURNS 0 in case of success
83 * OMAPCONF_ERR_ARG
84 * @param[in] prm_vc_val_cmd: PRM_VC_VAL_CMD register content
85 * @param[in,out] cmd_on: ON command value (RETURNED)
86 * @param[in,out] cmd_onlp: ONLP command value (RETURNED)
87 * @param[in,out] cmd_ret: RET command value (RETURNED)
88 * @param[in,out] cmd_off: OFF command value (RETURNED)
89 * @DESCRIPTION return ON/ONLP/RET/OFF command values
90 *//*------------------------------------------------------------------------ */
91 short int vc_cmd_values_get(unsigned int prm_vc_val_cmd,
92 unsigned char *cmd_on, unsigned char *cmd_onlp,
93 unsigned char *cmd_ret, unsigned char *cmd_off)
94 {
95 CHECK_NULL_ARG(cmd_on, OMAPCONF_ERR_ARG);
96 CHECK_NULL_ARG(cmd_onlp, OMAPCONF_ERR_ARG);
97 CHECK_NULL_ARG(cmd_ret, OMAPCONF_ERR_ARG);
98 CHECK_NULL_ARG(cmd_off, OMAPCONF_ERR_ARG);
99
100 *cmd_on = extract_bitfield(prm_vc_val_cmd, VC_ON_POS, VC_ON_LEN);
101 *cmd_onlp = extract_bitfield(prm_vc_val_cmd, VC_ONLP_POS, VC_ONLP_LEN);
102 *cmd_ret = extract_bitfield(prm_vc_val_cmd, VC_RET_POS, VC_RET_LEN);
103 *cmd_off = extract_bitfield(prm_vc_val_cmd, VC_OFF_POS, VC_OFF_LEN);
104
105 return 0;
106 }
107
108
109 /* ------------------------------------------------------------------------*//**
110 * @FUNCTION sri2c_is_double_filtering_enabled
111 * @BRIEF check if double filtering is enabled
112 * @RETURNS 1 if double filtering is enabled
113 * 0 if double filtering is disabled
114 * @param[in] prm_vc_cfg_i2c_mode: PRM_VC_CFG_I2C_MODE register
115 * content
116 * @DESCRIPTION check if double filtering is enabled
117 *//*------------------------------------------------------------------------ */
118 unsigned char sri2c_is_double_filtering_enabled(
119 unsigned int prm_vc_cfg_i2c_mode)
120 {
121 return extract_bit(prm_vc_cfg_i2c_mode, VC_DFILTEREN_POS);
122 }
123
124
125 /* ------------------------------------------------------------------------*//**
126 * @FUNCTION sri2c_is_sr_mode_enabled
127 * @BRIEF check if I2C repeated start operation mode is enabled
128 * @RETURNS 1 if I2C repeated start operation mode is enabled
129 * 0 if I2C repeated start operation mode is disabled
130 * @param[in] prm_vc_cfg_i2c_mode: PRM_VC_CFG_I2C_MODE register
131 * content
132 * @DESCRIPTION check if I2C repeated start operation mode is enabled
133 *//*------------------------------------------------------------------------ */
134 unsigned char sri2c_is_sr_mode_enabled(unsigned int prm_vc_cfg_i2c_mode)
135 {
136 return extract_bit(prm_vc_cfg_i2c_mode, VC_SRMODEEN_POS);
137 }
138
139
140 /* ------------------------------------------------------------------------*//**
141 * @FUNCTION sri2c_is_hs_mode_enabled
142 * @BRIEF check if I2C high speed mode is enabled
143 * @RETURNS 1 if I2C high speed mode is enabled
144 * 0 if I2C high speed mode is disabled
145 * @param[in] prm_vc_cfg_i2c_mode: PRM_VC_CFG_I2C_MODE register
146 * content
147 * @DESCRIPTION check if I2C high speed mode is enabled
148 *//*------------------------------------------------------------------------ */
149 unsigned char sri2c_is_hs_mode_enabled(unsigned int prm_vc_cfg_i2c_mode)
150 {
151 return extract_bit(prm_vc_cfg_i2c_mode, VC_HSMODEEN_POS);
152 }
153
154
155 /* ------------------------------------------------------------------------*//**
156 * @FUNCTION sri2c_master_code_get
157 * @BRIEF return the master code value for I2C High Speed preamble
158 * transmission
159 * @RETURNS master code value for I2C High Speed preamble
160 * transmission
161 * @param[in] prm_vc_cfg_i2c_mode: PRM_VC_CFG_I2C_MODE register
162 * content
163 * @DESCRIPTION return the master code value for I2C High Speed preamble
164 * transmission
165 *//*------------------------------------------------------------------------ */
166 unsigned char sri2c_master_code_get(unsigned int prm_vc_cfg_i2c_mode)
167 {
168 return extract_bitfield(prm_vc_cfg_i2c_mode,
169 VC_HSMCODE_POS, VC_HSMCODE_LEN);
170 }
171
172
173
174 /* ------------------------------------------------------------------------*//**
175 * @FUNCTION sri2c_low_clock_cycles_count_get
176 * @BRIEF return the system clock cycles, necessary to count
177 * the low period of the I2C clock signal
178 * @RETURNS 0 in case of success
179 * OMAPCONF_ERR_ARG
180 * OMAPCONF_ERR_CPU
181 * @param[in] prm_vc_cfg_i2c_mode: PRM_VC_CFG_I2C_MODE register
182 * content
183 * @param[in] prm_vc_cfg_i2c_clk: PRM_VC_CFG_I2C_CLK register content
184 * @param[in,out] cycles: I2C clock signal low period (in SYSCLK cycles)
185 * (RETURNED)
186 * @param[in,out] us: I2C clock signal low period (in micro-second)
187 * (RETURNED)
188 * @DESCRIPTION return the system clock cycles, necessary to count
189 * the low period of the I2C clock signal
190 *//*------------------------------------------------------------------------ */
191 int sri2c_low_clock_cycles_count_get(unsigned int prm_vc_cfg_i2c_mode,
192 unsigned int prm_vc_cfg_i2c_clk,
193 unsigned char *cycles, double *us)
194 {
195 double sysclk;
196
197 CHECK_NULL_ARG(cycles, OMAPCONF_ERR_ARG);
198 CHECK_NULL_ARG(us, OMAPCONF_ERR_ARG);
199
200 if (cpu_is_omap44xx()) {
201 sysclk = clk44xx_get_system_clock_speed();
202 } else if (cpu_is_omap54xx()) {
203 sysclk = clk54xx_sysclk_rate_get();
204 } else {
205 fprintf(stderr, "%s(): cpu not supported!!!\n", __func__);
206 return OMAPCONF_ERR_CPU;
207 }
208
209 if (sri2c_is_hs_mode_enabled(prm_vc_cfg_i2c_mode))
210 *cycles = extract_bitfield(prm_vc_cfg_i2c_clk,
211 VC_HSSCLL_POS, VC_HSSCLL_LEN);
212 else
213 *cycles = extract_bitfield(prm_vc_cfg_i2c_clk,
214 VC_SCLL_POS, VC_SCLL_LEN);
215 *us = ((double) *cycles) / sysclk;
216
217 return 0;
218 }
219
220
221 /* ------------------------------------------------------------------------*//**
222 * @FUNCTION sri2c_high_clock_cycles_count_get
223 * @BRIEF return the system clock cycles, necessary to count
224 * the high period of the I2C clock signal
225 * @RETURNS 0 in case of success
226 * OMAPCONF_ERR_ARG
227 * OMAPCONF_ERR_CPU
228 * @param[in] prm_vc_cfg_i2c_mode: PRM_VC_CFG_I2C_MODE register
229 * content
230 * @param[in] prm_vc_cfg_i2c_clk: PRM_VC_CFG_I2C_CLK register content
231 * @param[in,out] cycles: I2C clock signal high period (in SYSCLK cycles)
232 * (RETURNED)
233 * @param[in,out] us: I2C clock signal low period (in micro-second)
234 * (RETURNED)
235 * @DESCRIPTION return the system clock cycles, necessary to count
236 * the high period of the I2C clock signal
237 *//*------------------------------------------------------------------------ */
238 int sri2c_high_clock_cycles_count_get(unsigned int prm_vc_cfg_i2c_mode,
239 unsigned int prm_vc_cfg_i2c_clk,
240 unsigned char *cycles, double *us)
241 {
242 double sysclk;
243
244 CHECK_NULL_ARG(cycles, OMAPCONF_ERR_ARG);
245 CHECK_NULL_ARG(us, OMAPCONF_ERR_ARG);
246
247 if (cpu_is_omap44xx()) {
248 sysclk = clk44xx_get_system_clock_speed();
249 } else if (cpu_is_omap54xx()) {
250 sysclk = clk54xx_sysclk_rate_get();
251 } else {
252 fprintf(stderr, "%s(): cpu not supported!!!\n", __func__);
253 return OMAPCONF_ERR_CPU;
254 }
255
256 if (sri2c_is_hs_mode_enabled(prm_vc_cfg_i2c_mode))
257 *cycles = extract_bitfield(prm_vc_cfg_i2c_clk,
258 VC_HSSCLH_POS, VC_HSSCLH_LEN);
259 else
260 *cycles = extract_bitfield(prm_vc_cfg_i2c_clk,
261 VC_SCLH_POS, VC_SCLH_LEN);
262 *us = ((double) *cycles) / sysclk;
263
264 return 0;
265 }
266
267
268 /* ------------------------------------------------------------------------*//**
269 * @FUNCTION sri2c_config_show
270 * @BRIEF decode and show VC SR I2C current configuration
271 * @RETURNS 0 in case of success
272 * OMAPCONF_ERR_CPU
273 * OMAPCONF_ERR_REG_ACCESS
274 * @param[in,out] stream: output file (NULL: no output (silent))
275 * @param[in] prm_vc_cfg_i2c_mode: PRM_VC_CFG_I2C_MODE register
276 * content
277 * @param[in] prm_vc_cfg_i2c_clk: PRM_VC_CFG_I2C_CLK register content
278 * @DESCRIPTION decode and show VC SR I2C current configuration
279 *//*------------------------------------------------------------------------ */
280 int sri2c_config_show(FILE *stream, unsigned int prm_vc_cfg_i2c_mode,
281 unsigned int prm_vc_cfg_i2c_clk)
282 {
283 unsigned char low_cycles, high_cycles;
284 double low_us, high_us;
285 char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN];
286 unsigned int row = 0;
287
288 if (!cpu_is_omap44xx() && !cpu_is_omap54xx()) {
289 fprintf(stderr, "%s(): cpu not supported!!!\n", __func__);
290 return OMAPCONF_ERR_CPU;
291 }
292
293 row = 0;
294 autoadjust_table_init(table);
295 autoadjust_table_strncpy(table, row++, 0, "SR HS-I2C Configuration");
296
297
298 autoadjust_table_strncpy(table, row, 0, "Double Filtering");
299 if (sri2c_is_double_filtering_enabled(prm_vc_cfg_i2c_mode))
300 autoadjust_table_strncpy(table, row, 1,
301 "Enabled (rejects glitches < 2 SYSCLK cycle)");
302 else
303 autoadjust_table_strncpy(table, row, 1,
304 "Disabled (rejects glitches < 1 SYSCLK cycle)");
305 row++;
306
307 autoadjust_table_strncpy(table, row, 0,
308 "Repeated Start Mode (SRMODEEN)");
309 if (sri2c_is_sr_mode_enabled(prm_vc_cfg_i2c_mode))
310 autoadjust_table_strncpy(table, row, 1, "Enabled");
311 else
312 autoadjust_table_strncpy(table, row, 1, "Disabled");
313 row++;
314
315 autoadjust_table_strncpy(table, row, 0, "High-Speed Mode (HSMODEEN)");
316 if (sri2c_is_hs_mode_enabled(prm_vc_cfg_i2c_mode)) {
317 autoadjust_table_strncpy(table, row, 1, "Enabled");
318 row++;
319 autoadjust_table_strncpy(table, row, 0,
320 " HS Master Code (HSMCODE)");
321 snprintf(table[row][1], TABLE_MAX_ELT_LEN,
322 "0x%02X", sri2c_master_code_get(prm_vc_cfg_i2c_mode));
323 } else {
324 autoadjust_table_strncpy(table, row, 1, "Disabled");
325 }
326 row++;
327
328 autoadjust_table_strncpy(table, row++, 0, "I2C Clock Configuration:");
329 sri2c_low_clock_cycles_count_get(
330 prm_vc_cfg_i2c_mode, prm_vc_cfg_i2c_clk, &low_cycles, &low_us);
331 sri2c_high_clock_cycles_count_get(
332 prm_vc_cfg_i2c_mode, prm_vc_cfg_i2c_clk,
333 &high_cycles, &high_us);
334 if (sri2c_is_hs_mode_enabled(prm_vc_cfg_i2c_mode)) {
335 autoadjust_table_strncpy(table, row, 0,
336 " Low Period (HSSCLL)");
337 snprintf(table[row++][1], TABLE_MAX_ELT_LEN, "0x%02X (%.3lfus)",
338 low_cycles, low_us);
339 autoadjust_table_strncpy(table, row, 0,
340 " High Period (HSSCLH)");
341 snprintf(table[row][1], TABLE_MAX_ELT_LEN, "0x%02X (%.3lfus)",
342 high_cycles, high_us);
343 } else {
344 autoadjust_table_strncpy(table, row, 0, " Low Period (SCLL)");
345 snprintf(table[row++][1], TABLE_MAX_ELT_LEN, "0x%02X (%.3lfus)",
346 low_cycles, low_us);
347 autoadjust_table_strncpy(table, row, 0, " High Period (SCLH)");
348 snprintf(table[row][1], TABLE_MAX_ELT_LEN, "0x%02X (%.3lfus)",
349 high_cycles, high_us);
350 }
351 row++;
352
353 if (stream != NULL)
354 autoadjust_table_fprint(stream, table, row, 2);
355
356 return 0;
357 }
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