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4bc042b initial public release v1.50
Patrick Titiano authored Sep 21, 2012
1 /* ======================================================================= *//**
2 * @Component OMAPCONF
3 * @Filename camera-regbits-44xx.h
4 * @Description OMAP4 Camera Configuration
5 * @Author Edward Lee (edward.lee@ti.com)
6 * @Date 2012
7 * @Copyright TEXAS INSTRUMENTS Incorporated
8 *//*======================================================================== */
9 /*
10 * camera-regbits-44xx.h
11 *
12 * OMAP Power Configuration Tool ("omapconf")
13 * OMAP4 Camera Configuration
14 *
15 * Copyright (C) 2012 Texas Instruments, Inc.
16 *
17 * Written by Edward Lee (edward.lee@ti.com)
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
31 * MA 02110-1301 USA.
32 */
33
34
35 #ifndef __CAMERA_REGBITS_44XX_H__
36 #define __CAMERA_REGBITS_44XX_H__
37
38 typedef unsigned int _Uint32t;
39
40 /* Aparently these are somewhat generic accross ISS sub-blocks */
41 struct iss_csi2_sysconfig_bits {
42 _Uint32t auto_idle:1;
43 _Uint32t soft_reset:1;
44 _Uint32t __reserved1:10;
45 _Uint32t mstandby_mode:2;
46 _Uint32t __reserved2:18;
47 };
48
49 /* CAREFUL: Bits under TI Maximum restrictions! */
50 struct iss_revision_bits {
51 _Uint32t y_minor:6;
52 _Uint32t custom:2;
53 _Uint32t x_major:3;
54 _Uint32t r_rtl:5;
55 _Uint32t func:12;
56 _Uint32t __reserved1:2;
57 _Uint32t scheme:2;
58 };
59
60 /* ISS HL */
61 struct iss_hl_sysconfig_bits {
62 _Uint32t softreset:1;
63 _Uint32t __reserved1:1;
64 _Uint32t idlemode:2;
65 _Uint32t standbymode:2;
66 _Uint32t __reserved2:26;
67 };
68
69 enum iss_ctrl_input_sel {
70 ISS_CTRL_INPUT_SEL_CSI2A,
71 ISS_CTRL_INPUT_SEL_CSI2B,
72 ISS_CTRL_INPUT_SEL_CCP2,
73 ISS_CTRL_INPUT_SEL_CPI,
74 };
75
76 enum iss_ctrl_input_sel2 {
77 ISS_CTRL_INPUT_SEL_1,
78 ISS_CTRL_INPUT_SEL_CSI2C,
79 ISS_CTRL_INPUT_SEL_CSI3,
80 RESERVED,
81 };
82
83 struct iss_ctrl_bits {
84 _Uint32t sync_detect:2;
85 _Uint32t input_sel:2;
86 _Uint32t iss_clk_div:2;
87 _Uint32t __reserved1:10;
88 _Uint32t ccp2r_tag_cnt:4;
89 _Uint32t ccp2w_tag_cnt:4;
90 _Uint32t csi2_a_tag_cnt:4;
91 _Uint32t csi2_b_tag_cnt:4;
92 };
93
94 struct iss_clk_bits {
95 _Uint32t simcop:1;
96 _Uint32t isp:1;
97 _Uint32t csi2_a:1;
98 _Uint32t csi2_b:1;
99 _Uint32t ccp2:1;
100 _Uint32t __reserved1:23;
101 _Uint32t vport0_clk:1;
102 _Uint32t vport1_clk:1;
103 _Uint32t vport2_clk:1;
104 _Uint32t vport3_clk:1;/* OMAP4460 and OMAP4470 only */
105 };
106
107 struct iss_pm_status_bits {
108 _Uint32t csi2_a_pm:2;
109 _Uint32t csi2_b_pm:2;
110 _Uint32t ccp2_pm:2;
111 _Uint32t isp_pm:2;
112 _Uint32t simcop_pm:2;
113 _Uint32t bte_pm:2;
114 _Uint32t cbuff_pm:2;
115 _Uint32t __reserved1:18;
116 };
117
118 struct iss_top_irq_regs {
119 _Uint32t status_raw;
120 _Uint32t status;
121 _Uint32t enable_set;
122 _Uint32t enable_clr;
123 };
124
125 struct iss_top_regs {
126 struct iss_revision_bits hl_revision;
127 _Uint32t __reserved1[3];
128 struct iss_hl_sysconfig_bits hl_sysconfig;
129 _Uint32t __reserved2[3];
130 struct iss_top_irq_regs irq[6];
131 struct iss_ctrl_bits ctrl;
132 struct iss_clk_bits clkctrl;
133 struct iss_clk_bits clkstat;
134 struct iss_pm_status_bits pm_status;
135 };
136
137 /* CAREFUL: Bits under TI Maximum restrictions! */
138 struct iss_csi2_revision_bits {
139 _Uint32t minor:4;
140 _Uint32t major:4;
141 _Uint32t __reserved1:24;
142 };
143
144 struct iss_csi2_sysstatus_bits {
145 _Uint32t reset_done:1;
146 _Uint32t __reserved1:31;
147 };
148
149 enum iss_csi2_ctrl_vp_out_ctrl {
150 CSI2_CTRL_VP_OUT_CTRL_DIV1,
151 CSI2_CTRL_VP_OUT_CTRL_DIV2,
152 CSI2_CTRL_VP_OUT_CTRL_DIV3,
153 CSI2_CTRL_VP_OUT_CTRL_DIV4,
154 };
155
156 struct iss_csi2_ctrl_bits {
157 _Uint32t if_en:1;
158 _Uint32t __reserved1:1;
159 _Uint32t ecc_en:1;
160 _Uint32t frame:1;
161 _Uint32t endianness:1;
162 _Uint32t burst_size:2;
163 _Uint32t dbg_en:1;
164 _Uint32t vp_out_ctrl:2;
165 _Uint32t streaming_32_bit:1;
166 _Uint32t vp_only_en:1;
167 _Uint32t __reserved2:1;
168 _Uint32t non_posted_write:1;
169 _Uint32t __reserved3:1;
170 _Uint32t vp_clk_en:1;
171 _Uint32t burst_size_expand:1;
172 _Uint32t mflag_levl:1;
173 _Uint32t mflag_levh:1;
174 _Uint32t __reserved4:7;
175 };
176
177 struct iss_csi2_complexio_cfg_bits {
178 _Uint32t clock_position:3;
179 _Uint32t clock_pol:1;
180 _Uint32t data1_position:3;
181 _Uint32t data1_pol:1;
182 _Uint32t data2_position:3;
183 _Uint32t data2_pol:1;
184 _Uint32t data3_position:3;
185 _Uint32t data3_pol:1;
186 _Uint32t data4_position:3;
187 _Uint32t data4_pol:1;
188 _Uint32t __reserved1:4;
189 _Uint32t pwr_auto:1;
190 _Uint32t pwr_status:2;
191 _Uint32t pwr_cmd:2;
192 _Uint32t reset_done:1;
193 _Uint32t reset_ctrl:1;
194 _Uint32t __reserved2:1;
195 };
196
197 struct iss_csi2_timing_bits {
198 _Uint32t stop_state_counter_io1:13;
199 _Uint32t stop_state_x4_io1:1;
200 _Uint32t stop_state_x16_io1:1;
201 _Uint32t force_rx_mode_io1:1;
202 _Uint32t __reserved1:16;
203 };
204
205 struct iss_csi2_ctx_ctrl1_bits {
206 _Uint32t ctx_en:1;
207 _Uint32t line_modulo:1;
208 _Uint32t vp_force:1;
209 _Uint32t ping_pong:1;
210 _Uint32t count_unlock:1;
211 _Uint32t cs_en:1;
212 _Uint32t eol_en:1;
213 _Uint32t eof_en:1;
214 _Uint32t count:8;
215 _Uint32t fec_number:8;
216 _Uint32t transcode:4;
217 _Uint32t hscale:1;
218 _Uint32t __reserved1:1;
219 _Uint32t generic:1;
220 _Uint32t byteswap:1;
221 };
222
223 struct iss_csi2_ctx_ctrl2_bits {
224 _Uint32t format:10;
225 _Uint32t dpcm_pred:1;
226 _Uint32t virtual_id:2;
227 _Uint32t user_def_mapping:2;
228 _Uint32t __reserved1:1;
229 _Uint32t frame:16;
230 };
231
232 struct iss_csi2_ctx_ctrl3_bits {
233 _Uint32t line_number:16;
234 _Uint32t alpha:14;
235 _Uint32t __reserved1:2;
236 };
237
238 struct iss_csi2_ctx_regs {
239 struct iss_csi2_ctx_ctrl1_bits ctrl1;
240 struct iss_csi2_ctx_ctrl2_bits ctrl2;
241 _Uint32t dat_ofst;
242 _Uint32t dat_ping_addr;
243 _Uint32t dat_pong_addr;
244 _Uint32t irq_enable;
245 _Uint32t irq_status;
246 struct iss_csi2_ctx_ctrl3_bits ctrl3;
247 };
248
249 struct iss_csi2_regs {
250 struct iss_csi2_revision_bits revision;
251 _Uint32t __reserved1[3];
252 struct iss_csi2_sysconfig_bits sysconfig;
253 struct iss_csi2_sysstatus_bits sysstatus;
254 _Uint32t irqenable;
255 _Uint32t irqstatus;
256 _Uint32t __reserved2[8];
257 struct iss_csi2_ctrl_bits ctrl;
258 _Uint32t dbg_h;
259 _Uint32t __reserved3[2];
260 struct iss_csi2_complexio_cfg_bits complexio_cfg;
261 _Uint32t complexio_irqstatus;
262 _Uint32t __reserved4;
263 _Uint32t short_packet;
264 _Uint32t complexio_irqenable;
265 _Uint32t __reserved5;
266 _Uint32t dbg_p;
267 struct iss_csi2_timing_bits timing;
268 struct iss_csi2_ctx_regs ctx[8];
269 };
270
271 struct iss_ccp2_regs {
272 _Uint32t revision;
273 _Uint32t sysconfig;
274 _Uint32t sysstatus;
275 _Uint32t lc01_irqenable;
276 _Uint32t lc01_irqstatus;
277 _Uint32t lc23_irqenable;
278 _Uint32t lc23_irqstatus;
279 _Uint32t __reserved1[4];
280 _Uint32t lcm_irqenable;
281 _Uint32t lcm_irqstatus;
282 _Uint32t __reserved2[3];
283 _Uint32t ctrl;
284 _Uint32t dbg;
285 _Uint32t gnq;
286 _Uint32t ctrl1;
287 _Uint32t __reserve4[96];
288 _Uint32t lcm_ctrl;
289 _Uint32t lcm_vsize;
290 _Uint32t lcm_hsize;
291 _Uint32t lcm_prefetch;
292 _Uint32t lcm_src_addr;
293 _Uint32t lcm_src_ofst;
294 _Uint32t lcm_dst_addr;
295 _Uint32t lcm_dst_ofst;
296 _Uint32t lcm_history;
297
298
299 };
300
301 /* ISP5_SYS1 */
302 struct iss_isp5_sysconfig_bits {
303 _Uint32t auto_idle:1;
304 _Uint32t softreset:1;
305 _Uint32t __reserved1:2;
306 _Uint32t standbymode:2;
307 _Uint32t __reserved2:26;
308 };
309
310 struct iss_isp5_ctrl_bits {
311 _Uint32t ocp_wrnp:1;
312 _Uint32t vbusm_cpriority:3;
313 _Uint32t vbusm_cids:4;
314 _Uint32t psync_clk_sel:1;
315 _Uint32t sync_enable:1;
316 _Uint32t ipipeif_clk_enable:1;
317 _Uint32t ipipe_clk_enable:1;
318 _Uint32t rsz_clk_enable:1;
319 _Uint32t h3a_clk_enable:1;
320 _Uint32t isif_clk_enable:1;
321 _Uint32t bl_clk_enable:1;
322 _Uint32t __reserved1:4;
323 _Uint32t mstandby_wait:1;
324 _Uint32t mflag:1;
325 _Uint32t pclk_inv:1;
326 _Uint32t vd_pulse_ext:1;
327 _Uint32t mstandby:1;
328 _Uint32t dpc_evt_ini:1;
329 _Uint32t hst_rd_chk:1;
330 _Uint32t bsc_rd_chk:1;
331 _Uint32t __reserved2:2;
332 _Uint32t dma3_cfg:2;
333 };
334
335 struct iss_isp5_sys1_regs {
336 struct iss_revision_bits revision;
337 _Uint32t hwinfo1;
338 _Uint32t hwinfo2;
339 _Uint32t __reserved1;
340 struct iss_isp5_sysconfig_bits sysconfig;
341 _Uint32t __reserved2[4];
342 struct iss_top_irq_regs irq[4];
343 _Uint32t dmaenable_set;
344 _Uint32t dmaenable_clr;
345 struct iss_isp5_ctrl_bits ctrl;
346 _Uint32t pg;
347 _Uint32t pg_pulse_ctrl;
348 _Uint32t pg_frame_size;
349 _Uint32t mpsr;
350 _Uint32t bl_mtc1;
351 _Uint32t bl_mtc2;
352 _Uint32t bl_vbusm;
353 };
354
355 /* ISS_RESIZER */
356 struct iss_resizer_revision_bits {
357 _Uint32t minor:4;
358 _Uint32t major:4;
359 _Uint32t __reserved1:24;
360 };
361
362 struct iss_resizer_sysconfig_bits {
363 _Uint32t autogating:1;
364 _Uint32t __reserved1:7;
365 _Uint32t rsza_clk_en:1;
366 _Uint32t rszb_clk_en:1;
367 _Uint32t __reserved2:22;
368 };
369
370 struct iss_resizer_ab_regs {
371 _Uint32t en;
372 _Uint32t mode;
373 _Uint32t n420;
374 _Uint32t i_vps;
375 _Uint32t i_hps;
376 _Uint32t o_vsz;
377 _Uint32t o_hsz;
378 _Uint32t v_phs_y;
379 _Uint32t v_phs_c;
380 _Uint32t v_dif;
381 _Uint32t v_typ;
382 _Uint32t v_lpf;
383 _Uint32t h_phs;
384 _Uint32t h_phs_adj;
385 _Uint32t h_dif;
386 _Uint32t h_typ;
387 _Uint32t h_lpf;
388 _Uint32t dwn_en;
389 _Uint32t dwn_av;
390 _Uint32t rgb_en;
391 _Uint32t rgb_typ;
392 _Uint32t rgb_bld;
393 _Uint32t sdr_y_bad_h;
394 _Uint32t sdr_y_bad_l;
395 _Uint32t sdr_y_sad_h;
396 _Uint32t sdr_y_sad_l;
397 _Uint32t sdr_y_oft;
398 _Uint32t sdr_y_ptr_s;
399 _Uint32t sdr_y_ptr_e;
400 _Uint32t sdr_c_bad_h;
401 _Uint32t sdr_c_bad_l;
402 _Uint32t sdr_c_sad_h;
403 _Uint32t sdr_c_sad_l;
404 _Uint32t sdr_c_oft;
405 _Uint32t sdr_c_ptr_s;
406 _Uint32t sdr_c_ptr_e;
407 };
408
409 struct iss_resizer_src_en_bits {
410 _Uint32t en:1;
411 _Uint32t __reserved:31;
412 };
413
414 struct iss_resizer_src_mode_bits {
415 _Uint32t ost:1;
416 _Uint32t wrt:1;
417 _Uint32t __reserved:30;
418 };
419
420 struct iss_resizer_src_fmt0_bits {
421 _Uint32t sel:1;
422 _Uint32t bypass:1;
423 _Uint32t __reserved:30;
424 };
425
426 struct iss_resizer_src_fmt1_bits {
427 _Uint32t raw:1;
428 _Uint32t in420:1;
429 _Uint32t col:1;
430 _Uint32t chr:1;
431 _Uint32t __reserved:28;
432 };
433
434 struct iss_resizer_regs {
435 struct iss_resizer_revision_bits revision;
436 struct iss_resizer_sysconfig_bits sysconfig;
437 _Uint32t __reserved1;
438 _Uint32t in_fifo_ctrl;
439 _Uint32t gnc;
440 _Uint32t fracdiv;
441 _Uint32t __reserved2[2];
442 struct iss_resizer_src_en_bits src_en;
443 struct iss_resizer_src_mode_bits src_mode;
444 struct iss_resizer_src_fmt0_bits src_fmt0;
445 struct iss_resizer_src_fmt1_bits src_fmt1;
446 _Uint32t src_vps;
447 _Uint32t src_vsz;
448 _Uint32t src_hps;
449 _Uint32t src_hsz;
450 _Uint32t dma_rza;
451 _Uint32t dma_rzb;
452 _Uint32t dma_sta;
453 _Uint32t gck_mmr;
454 _Uint32t __reserved3;
455 _Uint32t gck_sdr;
456 _Uint32t irq_rza;
457 _Uint32t irq_rzb;
458 _Uint32t yuv_y_min;
459 _Uint32t yuv_y_max;
460 _Uint32t yuv_c_min;
461 _Uint32t yuv_c_max;
462 _Uint32t yuv_phs;
463 _Uint32t seq;
464 struct iss_resizer_ab_regs rza;
465 struct iss_resizer_ab_regs rzb;
466 };
467
468 /* ISS_IPIPE */
469 struct iss_ipipe_src_en_bits {
470 _Uint32t en:1;
471 _Uint32t __reserved:31;
472 };
473
474 struct iss_ipipe_src_mode_bits {
475 _Uint32t ost:1;
476 _Uint32t wrt:1;
477 _Uint32t __reserved:30;
478 };
479
480 struct iss_ipipe_src_fmt_bits {
481 _Uint32t fmt:2;
482 _Uint32t __reserved:30;
483 };
484
485 struct iss_ipipe_regs {
486 struct iss_ipipe_src_en_bits src_en;
487 struct iss_ipipe_src_mode_bits src_mode;
488 struct iss_ipipe_src_fmt_bits src_fmt;
489 _Uint32t src_col;
490 _Uint32t src_vps;
491 _Uint32t src_vsz;
492 _Uint32t src_hps;
493 _Uint32t src_hsz;
494 _Uint32t sel_sbu;
495 _Uint32t src_sta;
496 _Uint32t gck_mmr;
497 _Uint32t gck_pix;
498 _Uint32t __reserved1;
499 /* TODO: Add the rest! */
500 };
501
502 /* ISS_ISIF */
503 struct iss_isif_syncen_bits {
504 _Uint32t syen:1;
505 _Uint32t dwen:1;
506 _Uint32t __reserved:30;
507 };
508
509 struct iss_isif_modeset_bits {
510 _Uint32t hdvdd:1;
511 _Uint32t fidd:1;
512 _Uint32t vdpol:1;
513 _Uint32t hdpol:1;
514 _Uint32t fdpol:1;/* OMAP4460 and OMAP4470 only */
515 _Uint32t swen:1;
516 _Uint32t dpol:1;
517 _Uint32t ccdmd:1;
518 _Uint32t ccdw:3;
519 _Uint32t ovf:1;
520 _Uint32t inpmod:2;
521 _Uint32t hlpf:1;/* OMAP4460 and OMAP4470 only */
522 _Uint32t __reserved3:17;
523 };
524
525 struct iss_isif_ccdcfg_bits {
526 _Uint32t sdrpack:2;
527 _Uint32t __reserved1:2;
528 _Uint32t ycinswp:1;
529 _Uint32t bt656:1;
530 _Uint32t fidmd:2;
531 _Uint32t wenlog:1;
532 _Uint32t trgsel:1;
533 _Uint32t extrg:1;
534 _Uint32t y8pos:1;
535 _Uint32t bswd:1;
536 _Uint32t msbinvi:1;
537 _Uint32t __reserved2:1;
538 _Uint32t vldc:1;
539 _Uint32t __reserved3:16;
540 };
541
542 struct iss_isif_regs {
543 struct iss_isif_syncen_bits syncen;
544 struct iss_isif_modeset_bits modeset;
545 _Uint32t hdw;
546 _Uint32t vdw;
547 _Uint32t ppln;
548 _Uint32t lpfr;
549 _Uint32t sph;
550 _Uint32t lnh;
551 _Uint32t __reserved1[2];
552 _Uint32t lnv;
553 _Uint32t culh;
554 _Uint32t culv;
555 _Uint32t hsize;
556 _Uint32t __reserved2;
557 _Uint32t cadu;
558 _Uint32t cadl;
559 _Uint32t lincfg0;
560 _Uint32t lincfg1;
561 _Uint32t ccolp;
562 _Uint32t crgain;
563 _Uint32t cgrgain;
564 _Uint32t cgbgain;
565 _Uint32t cbgain;
566 _Uint32t cofsta;
567 _Uint32t vdint[3];
568 _Uint32t misc;
569 _Uint32t cgammawd;
570 _Uint32t rec656if;
571 struct iss_isif_ccdcfg_bits ccdcfg;
572 _Uint32t dfcctl;
573 _Uint32t vdfsatlv;
574 _Uint32t dfcmemctl;
575 _Uint32t dfcmem[5];
576 _Uint32t clampcfg;
577 /* TODO: Add the rest! */
578 };
579
580 /* ISS_IPIPEIF */
581 struct iss_ipipeif_enable_bits {
582 _Uint32t enable:1;
583 _Uint32t syncoff:1;
584 _Uint32t __reserved:30;
585 };
586
587 struct iss_ipipeif_cfg1_bits {
588 _Uint32t oneshot:1;
589 _Uint32t decim:1;
590 _Uint32t inpsrc2:2;
591 _Uint32t __reserved1:3;
592 _Uint32t avgfilt:1;
593 _Uint32t unpack:2;
594 _Uint32t clksel:1;
595 _Uint32t datasft:3;
596 _Uint32t inpsrc1:2;
597 _Uint32t __reserved2:16;
598 };
599
600 struct iss_ipipeif_cfg2_bits {
601 _Uint32t intsw:1;
602 _Uint32t hdpol:1;
603 _Uint32t vdpol:1;
604 _Uint32t yuv16:1;
605 _Uint32t __reserved1:1;
606 _Uint32t dfsdir:1;
607 _Uint32t yuv8:1;
608 _Uint32t yuv8p:1;
609 _Uint32t __reserved2:24;
610 };
611
612 struct iss_ipipeif_regs {
613 struct iss_ipipeif_enable_bits enable;
614 struct iss_ipipeif_cfg1_bits cfg1;
615 _Uint32t ppln;
616 _Uint32t lpfr;
617 _Uint32t hnum;
618 _Uint32t vnum;
619 _Uint32t addru;
620 _Uint32t addrl;
621 _Uint32t adofs;
622 _Uint32t rsz;
623 _Uint32t gain;
624 _Uint32t dpcm;
625 struct iss_ipipeif_cfg2_bits cfg2;
626 _Uint32t inirsz;
627 _Uint32t oclip;
628 _Uint32t dtudf;
629 _Uint32t clkdiv;
630 _Uint32t dpc1;
631 _Uint32t dpc2;
632 _Uint32t rsz3a;
633 _Uint32t inirsz3a;
634 };
635
636 /* ISS_H3A */
637 struct iss_h3a_regs {
638 struct iss_revision_bits pid;
639 };
640
641 #endif
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