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4bc042b initial public release v1.50
Patrick Titiano authored Sep 21, 2012
1 /*
2 *
3 * @Component OMAPCONF
4 * @Filename clkdm54xx.c
5 * @Description OMAP5 Clock Domain Definitions & APIs
6 * @Author Patrick Titiano (p-titiano@ti.com)
7 * @Date 2011
8 * @Copyright Texas Instruments Incorporated
9 *
10 *
11 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
12 *
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 *
18 * Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 *
21 * Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the
24 * distribution.
25 *
26 * Neither the name of Texas Instruments Incorporated nor the names of
27 * its contributors may be used to endorse or promote products derived
28 * from this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 */
43
44
45 #include <lib.h>
46 #include <clkdm54xx.h>
47 #include <cm54xx.h>
48 #include <prm54xx.h>
49 #include <string.h>
50 #include <stdio.h>
51 #include <cpuinfo.h>
52
53
54 /* #define CLKDM54XX_DEBUG */
55 #ifdef CLKDM54XX_DEBUG
56 #define dprintf(format, ...) printf(format, ## __VA_ARGS__)
57 #else
58 #define dprintf(format, ...)
59 #endif
60
61
62 static const char
63 clkdm54xx_names_table[CLKDM54XX_ID_MAX][CLKDM54XX_MAX_NAME_LENGTH] = {
64 "EMU",
65 "WKUPAON",
66 "COREAON",
67 "CAM",
68 "L4_CFG",
69 "EMIF",
70 "IPU",
71 "L3_MAIN2",
72 "L3_INSTR",
73 "L3_MAIN1",
74 "C2C",
75 "DMA",
76 "MIPIEXT",
77 "DSS",
78 "CUST_EFUSE",
79 "L3INIT",
80 "L4PER",
81 "L4SEC",
82 "ABE",
83 "DSP",
84 "GPU",
85 "IVA",
86 "MPU",
87 "NONE (PRCM)"};
88
89
90 static reg *clkdm54xx_cm_clkstctrl_table[CLKDM54XX_ID_MAX] = {
91 &omap5430_cm_emu_clkstctrl, /* CLKDM54XX_EMU */
92 &omap5430_cm_wkupaon_clkstctrl, /* CLKDM54XX_WKUPAON */
93 &omap5430_cm_coreaon_clkstctrl, /* CLKDM54XX_COREAON */
94 &omap5430_cm_cam_clkstctrl, /* CLKDM54XX_CAM */
95 &omap5430_cm_l4cfg_clkstctrl, /* CLKDM54XX_L4_CFG */
96 &omap5430_cm_emif_clkstctrl, /* EMIF */
97 &omap5430_cm_ipu_clkstctrl, /* IPU */
98 &omap5430_cm_l3main2_clkstctrl, /* L3_MAIN2 */
99 &omap5430_cm_l3instr_clkstctrl, /* L3_INSTR */
100 &omap5430_cm_l3main1_clkstctrl, /* L3_MAIN1 */
101 &omap5430_cm_c2c_clkstctrl, /* C2C */
102 &omap5430_cm_dma_clkstctrl, /* DMA */
103 &omap5430_cm_mipiext_clkstctrl, /* MIPIEXT */
104 &omap5430_cm_dss_clkstctrl, /* DSS */
105 &omap5430_cm_custefuse_clkstctrl, /* CUST_EFUSE */
106 &omap5430_cm_l3init_clkstctrl, /* L3_INIT */
107 &omap5430_cm_l4per_clkstctrl, /* L4_PER */
108 NULL /* FIXME &OMAP5430_CM_L4SEC_CLKSTCTRL*/, /* L4_SEC */
109 &omap5430_cm_abe_clkstctrl, /* ABE */
110 &omap5430_cm_dsp_clkstctrl, /* DSP */
111 &omap5430_cm_gpu_clkstctrl, /* GPU */
112 &omap5430_cm_iva_clkstctrl, /* IVA */
113 &omap5430_cm_mpu_clkstctrl, /* MPU */
114 NULL}; /* CLKDM54XX_NONE */
115
116
117 static const pwrdm54xx_id clkdm54xx_partition_table[CLKDM54XX_ID_MAX] = {
118 PWRDM54XX_EMU, /* CLKDM54XX_EMU */
119 PWRDM54XX_WKUPAON, /* CLKDM54XX_WKUPAON */
120 PWRDM54XX_COREAON, /* CLKDM54XX_COREAON */
121 PWRDM54XX_CAM, /* CLKDM54XX_CAM */
122 PWRDM54XX_CORE, /* CLKDM54XX_L4_CFG */
123 PWRDM54XX_CORE, /* CLKDM54XX_EMIF */
124 PWRDM54XX_CORE, /* CLKDM54XX_IPU */
125 PWRDM54XX_CORE, /* CLKDM54XX_L3_MAIN2 */
126 PWRDM54XX_CORE, /* CLKDM54XX_L3_INSTR */
127 PWRDM54XX_CORE, /* CLKDM54XX_L3_MAIN1 */
128 PWRDM54XX_CORE, /* CLKDM54XX_C2C */
129 PWRDM54XX_CORE, /* CLKDM54XX_DMA */
130 PWRDM54XX_CORE, /* CLKDM54XX_MIPIEXT */
131 PWRDM54XX_DSS, /* CLKDM54XX_DSS */
132 PWRDM54XX_CUST_EFUSE, /* CLKDM54XX_CUST_EFUSE */
133 PWRDM54XX_L3_INIT, /* CLKDM54XX_L3_INIT */
134 PWRDM54XX_L4_PER, /* CLKDM54XX_L4_PER */
135 PWRDM54XX_L4_PER, /* CLKDM54XX_L4_SEC */
136 PWRDM54XX_ABE, /* CLKDM54XX_ABE */
137 PWRDM54XX_DSP, /* CLKDM54XX_DSP */
138 PWRDM54XX_GPU, /* CLKDM54XX_GPU */
139 PWRDM54XX_IVA, /* CLKDM54XX_IVA */
140 PWRDM54XX_MPU, /* CLKDM54XX_MPU */
141 PWRDM54XX_ID_MAX}; /* CLKDM54XX_NONE */
142
143
144 /* ------------------------------------------------------------------------*//**
145 * @FUNCTION clkdm54xx_name_get
146 * @BRIEF return clock domain name
147 * @RETURNS clock domain name on success
148 * NULL in case of error
149 * @param[in] id: clock domain ID
150 * @DESCRIPTION return clock domain name
151 *//*------------------------------------------------------------------------ */
152 const char *clkdm54xx_name_get(clkdm54xx_id id)
153 {
154 CHECK_ARG_LESS_THAN(id, CLKDM54XX_ID_MAX, NULL);
155
156 return clkdm54xx_names_table[id];
157 }
158
159
160 /* ------------------------------------------------------------------------*//**
161 * @FUNCTION clkdm54xx_pwrdm_get
162 * @BRIEF return the ID of the power domain a given clock domain
163 * is part of.
164 * @RETURNS power domain ID a given clock domain is part of
165 * (< PWRDM54XX_ID_MAX)
166 * PWRDM54XX_ID_MAX in case of error
167 * @param[in] id: valid clock domain ID
168 * @DESCRIPTION return the ID of the power domain a given clock domain
169 * is part of.
170 *//*------------------------------------------------------------------------ */
171 pwrdm54xx_id clkdm54xx_pwrdm_get(clkdm54xx_id id)
172 {
173 CHECK_ARG_LESS_THAN(id, CLKDM54XX_ID_MAX, PWRDM54XX_ID_MAX);
174
175 return clkdm54xx_partition_table[id];
176 }
177
178
179 /* ------------------------------------------------------------------------*//**
180 * @FUNCTION clkdm54xx_voltdm_get
181 * @BRIEF return the ID of the voltage domain a given clock domain
182 * is part of.
183 * @RETURNS voltage domain ID a given clock domain is part of
184 * (< VDD54XX_ID_MAX)
185 * VDD54XX_ID_MAX in case of error
186 * @param[in] id: valid clock domain ID
187 * @DESCRIPTION return the ID of the voltage domain a given clock domain
188 * is part of.
189 *//*------------------------------------------------------------------------ */
190 voltdm54xx_id clkdm54xx_voltdm_get(clkdm54xx_id id)
191 {
192 CHECK_ARG_LESS_THAN(id, CLKDM54XX_ID_MAX, VDD54XX_ID_MAX);
193
194 return pwrdm54xx_voltdm_get(clkdm54xx_pwrdm_get(id));
195 }
196
197
198 /* ------------------------------------------------------------------------*//**
199 * @FUNCTION clkdm54xx_clkstctrl_reg_get
200 * @BRIEF return CM_XYZ_CLKSTCTRL register of a given clock domain
201 * @RETURNS CM_XYZ_CLKSTCTRL register on success
202 * NULL in case of error
203 * @param[in] id: valid clock domain ID
204 * @DESCRIPTION return CM_XYZ_CLKSTCTRL register of a given clock domain
205 *//*------------------------------------------------------------------------ */
206 reg *clkdm54xx_clkstctrl_reg_get(clkdm54xx_id id)
207 {
208 CHECK_ARG_LESS_THAN(id, CLKDM54XX_ID_MAX, NULL);
209
210 return clkdm54xx_cm_clkstctrl_table[id];
211 }
212
213
214 /* ------------------------------------------------------------------------*//**
215 * @FUNCTION clkdm54xx_ctrl_mode_get
216 * @BRIEF return clock domain transition control mode
217 * @RETURNS clock domain transition control mode on success
218 * CLKM_CTRL_MODE_MAX in case of error
219 * @param[in] id: valid clock domain ID
220 * @DESCRIPTION return clock domain transition control mode
221 *//*------------------------------------------------------------------------ */
222 clkdm_ctrl_mode clkdm54xx_ctrl_mode_get(clkdm54xx_id id)
223 {
224 CHECK_CPU(54xx, CLKM_CTRL_MODE_MAX);
225 CHECK_ARG_LESS_THAN(id, CLKDM54XX_ID_MAX, CLKM_CTRL_MODE_MAX);
226
227 return clkdm_ctrl_mode_get(
228 clkdm54xx_cm_clkstctrl_table[id]);
229 }
230
231
232 /* ------------------------------------------------------------------------*//**
233 * @FUNCTION clkdm54xx_status_get
234 * @BRIEF return clock domain status from register
235 * @RETURNS clock domain status on success
236 * CLKDM_STATUS_MAX in case of error
237 * @param[in] id: valid clock domain ID
238 * @DESCRIPTION return clock domain status from register
239 *//*------------------------------------------------------------------------ */
240 clkdm_status clkdm54xx_status_get(clkdm54xx_id id)
241 {
242 reg *clkstctrl_reg;
243 clkdm_status st;
244
245 CHECK_CPU(54xx, CLKDM_STATUS_MAX);
246 CHECK_ARG_LESS_THAN(id, CLKDM54XX_ID_MAX, CLKDM_STATUS_MAX);
247
248 clkstctrl_reg = clkdm54xx_clkstctrl_reg_get(id);
249 if (clkstctrl_reg != NULL) {
250 st = clkdm_status_get(clkstctrl_reg);
251 dprintf("%s(%u (%s)): CM_CLKSTCTRL=%s status=%s\n", __func__,
252 id, clkdm54xx_name_get(id), reg_name_get(clkstctrl_reg),
253 clkdm_status_name_get(st));
254 return st;
255 } else {
256 dprintf("%s(%u (%s)): CM_CLKSTCTRL==NULL\n", __func__, id,
257 clkdm54xx_name_get(id));
258 return CLKDM_STATUS_MAX;
259 }
260 }
261
262
263 /* ------------------------------------------------------------------------*//**
264 * @FUNCTION clkdm54xx_s2id
265 * @BRIEF retrieve clock domain ID matching string s
266 * @RETURNS valid clock domain ID
267 * CLKDM54XX_ID_MAX if no match found
268 * @param[in] s: string
269 * List of recognized strings: "emu", "wkupaon", "coreaon",
270 * "cam", "l4cfg", "emif", "ipu", "l3main2", "l3instr",
271 * "l3main1", "c2c", "dma", "mipiext", "dss", "custefuse",
272 * "l3init", "l4per", "l4sec", "abe", "dsp", "gpu, "iva",
273 * "mpu"
274 * @DESCRIPTION retrieve clock domain ID matching string s
275 *//*------------------------------------------------------------------------ */
276 clkdm54xx_id clkdm54xx_s2id(char *s)
277 {
278 clkdm54xx_id id;
279
280 if (s == NULL)
281 id = CLKDM54XX_ID_MAX;
282 else if (strcmp(lowercase(s), "emu") == 0)
283 id = CLKDM54XX_EMU;
284 else if (strcmp(lowercase(s), "wkupaon") == 0)
285 id = CLKDM54XX_WKUPAON;
286 else if (strcmp(lowercase(s), "coreaon") == 0)
287 id = CLKDM54XX_COREAON;
288 else if (strcmp(lowercase(s), "cam") == 0)
289 id = CLKDM54XX_CAM;
290 else if (strcmp(lowercase(s), "l4cfg") == 0)
291 id = CLKDM54XX_L4_CFG;
292 else if (strcmp(lowercase(s), "emif") == 0)
293 id = CLKDM54XX_EMIF;
294 else if (strcmp(lowercase(s), "ipu") == 0)
295 id = CLKDM54XX_IPU;
296 else if (strcmp(lowercase(s), "l3main2") == 0)
297 id = CLKDM54XX_L3_MAIN2;
298 else if (strcmp(lowercase(s), "l3instr") == 0)
299 id = CLKDM54XX_L3_INSTR;
300 else if (strcmp(lowercase(s), "l3main1") == 0)
301 id = CLKDM54XX_L3_MAIN1;
302 else if (strcmp(lowercase(s), "c2c") == 0)
303 id = CLKDM54XX_C2C ;
304 else if (strcmp(lowercase(s), "dma") == 0)
305 id = CLKDM54XX_DMA ;
306 else if (strcmp(lowercase(s), "mipiext") == 0)
307 id = CLKDM54XX_MIPIEXT ;
308 else if (strcmp(lowercase(s), "dss") == 0)
309 id = CLKDM54XX_DSS ;
310 else if (strcmp(lowercase(s), "custefuse") == 0)
311 id = CLKDM54XX_CUST_EFUSE ;
312 else if (strcmp(lowercase(s), "l3init") == 0)
313 id = CLKDM54XX_L3_INIT ;
314 else if (strcmp(lowercase(s), "l4per") == 0)
315 id = CLKDM54XX_L4_PER ;
316 else if (strcmp(lowercase(s), "l4sec") == 0)
317 id = CLKDM54XX_L4_SEC ;
318 else if (strcmp(lowercase(s), "abe") == 0)
319 id = CLKDM54XX_ABE ;
320 else if (strcmp(lowercase(s), "dsp") == 0)
321 id = CLKDM54XX_DSP ;
322 else if (strcmp(lowercase(s), "gpu") == 0)
323 id = CLKDM54XX_GPU ;
324 else if (strcmp(lowercase(s), "iva") == 0)
325 id = CLKDM54XX_IVA ;
326 else if (strcmp(lowercase(s), "mpu") == 0)
327 id = CLKDM54XX_MPU ;
328 else
329 id = CLKDM54XX_ID_MAX;
330
331 dprintf("%s(%s) = %s\n", __func__, s, clkdm54xx_name_get(id));
332 return id;
333 }
334
335
336 /* ------------------------------------------------------------------------*//**
337 * @FUNCTION clkdm54xx_config_show
338 * @BRIEF display clock domain configuration
339 * @RETURNS 0 in case of success
340 * OMAPCONF_ERR_CPU
341 * OMAPCONF_ERR_ARG
342 * @param[in,out] stream: output file
343 * @param[in] id: valid clock domain ID
344 * @DESCRIPTION display clock domain configuration
345 *//*------------------------------------------------------------------------ */
346 int clkdm54xx_config_show(FILE *stream, clkdm54xx_id id)
347 {
348 unsigned int cm_clkstctrl;
349 reg *cm_clkstctrl_reg;
350 char s[64];
351
352 CHECK_CPU(54xx, OMAPCONF_ERR_CPU);
353 CHECK_ARG_LESS_THAN(id, CLKDM54XX_ID_MAX, OMAPCONF_ERR_ARG);
354
355 /* Get clock domain's CLKSTCTRL register pointer */
356 cm_clkstctrl_reg = clkdm54xx_clkstctrl_reg_get(id);
357 if (cm_clkstctrl_reg == NULL)
358 /* Nothing to show */
359 return 0;
360 /* Read register */
361 cm_clkstctrl = reg_read(cm_clkstctrl_reg);
362
363 /* Decode and display clock domain's configuration */
364 fprintf(stream, "|---------------------------------------------------"
365 "-------------|\n");
366 strcpy(s, clkdm54xx_name_get(id));
367 strcat(s, " Clock Domain Configuration");
368 fprintf(stream, "| %-62s |\n", s);
369 fprintf(stream, "|--------------------------------------|------------"
370 "-------------|\n");
371 fprintf(stream, "| %-36s | %-23s |\n", "Clock State Transition control",
372 clkdm_ctrl_mode_name_get(clkdm54xx_ctrl_mode_get(id)));
373
374 switch (id) {
375 case CLKDM54XX_EMU:
376 fprintf(stream, "| %-36s | %-23s |\n", " EMU_SYS_CLK",
377 clkdm_status_name_get(
378 (clkdm_status) extract_bit(cm_clkstctrl, 8)));
379 break;
380
381 case CLKDM54XX_WKUPAON:
382 fprintf(stream, "| %-36s | %-23s |\n",
383 " WKUPAON_IO_SRCOMP_GFCLK",
384 clkdm_status_name_get(
385 (clkdm_status) extract_bit(cm_clkstctrl, 13)));
386 fprintf(stream, "| %-36s | %-23s |\n", " L4_WKUPAON_GICLK",
387 clkdm_status_name_get(
388 (clkdm_status) extract_bit(cm_clkstctrl, 12)));
389 fprintf(stream, "| %-36s | %-23s |\n", " WKUPAON_32K_GFCLK",
390 clkdm_status_name_get(
391 (clkdm_status) extract_bit(cm_clkstctrl, 11)));
392 fprintf(stream, "| %-36s | %-23s |\n", " ABE_LP_CLK",
393 clkdm_status_name_get(
394 (clkdm_status) extract_bit(cm_clkstctrl, 9)));
395 fprintf(stream, "| %-36s | %-23s |\n", " SYS_CLK",
396 clkdm_status_name_get(
397 (clkdm_status) extract_bit(cm_clkstctrl, 8)));
398 break;
399
400 case CLKDM54XX_COREAON:
401 fprintf(stream, "| %-36s | %-23s |\n",
402 " COREAON_IO_SRCOMP_GFCLK",
403 clkdm_status_name_get(
404 (clkdm_status) extract_bit(cm_clkstctrl, 14)));
405 fprintf(stream, "| %-36s | %-23s |\n", " COREAON_TS_GFCLK",
406 clkdm_status_name_get(
407 (clkdm_status) extract_bit(cm_clkstctrl, 13)));
408 fprintf(stream, "| %-36s | %-23s |\n", " COREAON_32K_GFCLK",
409 clkdm_status_name_get(
410 (clkdm_status) extract_bit(cm_clkstctrl, 12)));
411 fprintf(stream, "| %-36s | %-23s |\n", " SR_CORE_SYS_GFCLK",
412 clkdm_status_name_get(
413 (clkdm_status) extract_bit(cm_clkstctrl, 11)));
414 fprintf(stream, "| %-36s | %-23s |\n", " SR_MM_SYS_GFCLK",
415 clkdm_status_name_get(
416 (clkdm_status) extract_bit(cm_clkstctrl, 10)));
417 fprintf(stream, "| %-36s | %-23s |\n", " SR_MPU_SYS_GFCLK",
418 clkdm_status_name_get(
419 (clkdm_status) extract_bit(cm_clkstctrl, 9)));
420 fprintf(stream, "| %-36s | %-23s |\n", " COREAON_L4_GICLK",
421 clkdm_status_name_get(
422 (clkdm_status) extract_bit(cm_clkstctrl, 8)));
423 break;
424
425 case CLKDM54XX_CAM:
426 fprintf(stream, "| %-36s | %-23s |\n", " CAM_L3_GIFCLK",
427 clkdm_status_name_get(
428 (clkdm_status) extract_bit(cm_clkstctrl, 12)));
429 fprintf(stream, "| %-36s | %-23s |\n", " CAM_BOOST_GCLK",
430 clkdm_status_name_get(
431 (clkdm_status) extract_bit(cm_clkstctrl, 11)));
432 fprintf(stream, "| %-36s | %-23s |\n", " FDIF_GCLK",
433 clkdm_status_name_get(
434 (clkdm_status) extract_bit(cm_clkstctrl, 10)));
435 fprintf(stream, "| %-36s | %-23s |\n", " CSI_PHY_GFCLK",
436 clkdm_status_name_get(
437 (clkdm_status) extract_bit(cm_clkstctrl, 9)));
438 fprintf(stream, "| %-36s | %-23s |\n", " CAM_GCLK",
439 clkdm_status_name_get(
440 (clkdm_status) extract_bit(cm_clkstctrl, 8)));
441 break;
442
443 case CLKDM54XX_L4_CFG:
444 fprintf(stream, "| %-36s | %-23s |\n", " CORE_TS_GFCLK",
445 clkdm_status_name_get(
446 (clkdm_status) extract_bit(cm_clkstctrl, 9)));
447 fprintf(stream, "| %-36s | %-23s |\n", " L4CFG_L4_GICLK",
448 clkdm_status_name_get(
449 (clkdm_status) extract_bit(cm_clkstctrl, 8)));
450 break;
451
452 case CLKDM54XX_EMIF:
453 fprintf(stream, "| %-36s | %-23s |\n", " EMIF_PHY_GCLK",
454 clkdm_status_name_get(
455 (clkdm_status) extract_bit(cm_clkstctrl, 10)));
456 fprintf(stream, "| %-36s | %-23s |\n", " DLL_GCLK",
457 clkdm_status_name_get(
458 (clkdm_status) extract_bit(cm_clkstctrl, 9)));
459 fprintf(stream, "| %-36s | %-23s |\n", " EMIF_L3_GICLK",
460 clkdm_status_name_get(
461 (clkdm_status) extract_bit(cm_clkstctrl, 8)));
462 break;
463
464 case CLKDM54XX_IPU:
465 fprintf(stream, "| %-36s | %-23s |\n", " IPU_CLK",
466 clkdm_status_name_get(
467 (clkdm_status) extract_bit(cm_clkstctrl, 8)));
468 break;
469
470 case CLKDM54XX_L3_MAIN2:
471 fprintf(stream, "| %-36s | %-23s |\n", " L3MAIN2_L3_GICLK",
472 clkdm_status_name_get(
473 (clkdm_status) extract_bit(cm_clkstctrl, 8)));
474 break;
475
476 case CLKDM54XX_L3_INSTR:
477 fprintf(stream, "| %-36s | %-23s |\n",
478 " L3INSTR_DLL_AGING_GCLK",
479 clkdm_status_name_get(
480 (clkdm_status) extract_bit(cm_clkstctrl, 9)));
481 fprintf(stream, "| %-36s | %-23s |\n", " L3INSTR_L3_GICLK",
482 clkdm_status_name_get(
483 (clkdm_status) extract_bit(cm_clkstctrl, 8)));
484 break;
485
486 case CLKDM54XX_L3_MAIN1:
487 fprintf(stream, "| %-36s | %-23s |\n", " L3MAIN1_L3_GICLK",
488 clkdm_status_name_get(
489 (clkdm_status) extract_bit(cm_clkstctrl, 8)));
490 break;
491
492 case CLKDM54XX_C2C:
493 fprintf(stream, "| %-36s | %-23s |\n", " C2C_L4_GICLK",
494 clkdm_status_name_get(
495 (clkdm_status) extract_bit(cm_clkstctrl, 9)));
496 fprintf(stream, "| %-36s | %-23s |\n", " C2C_L3_GICLK",
497 clkdm_status_name_get(
498 (clkdm_status) extract_bit(cm_clkstctrl, 8)));
499 break;
500
501 case CLKDM54XX_DMA:
502 fprintf(stream, "| %-36s | %-23s |\n", " DMA_L3_GICLK",
503 clkdm_status_name_get(
504 (clkdm_status) extract_bit(cm_clkstctrl, 8)));
505 break;
506
507 case CLKDM54XX_MIPIEXT:
508 fprintf(stream, "| %-36s | %-23s |\n", " UNIPRO1_PHY_GFCLK",
509 clkdm_status_name_get(
510 (clkdm_status) extract_bit(cm_clkstctrl, 13)));
511 fprintf(stream, "| %-36s | %-23s |\n",
512 " UNIPRO1_TXPHY_LS_GFCLK",
513 clkdm_status_name_get(
514 (clkdm_status) extract_bit(cm_clkstctrl, 12)));
515 fprintf(stream, "| %-36s | %-23s |\n",
516 " MIPIEXT_PHY_REF_GFCLK",
517 clkdm_status_name_get(
518 (clkdm_status) extract_bit(cm_clkstctrl, 11)));
519 fprintf(stream, "| %-36s | %-23s |\n", " UNIPRO1_DPLL_CLK",
520 clkdm_status_name_get(
521 (clkdm_status) extract_bit(cm_clkstctrl, 10)));
522 fprintf(stream, "| %-36s | %-23s |\n", " MIPIEXT_L3_GICLK",
523 clkdm_status_name_get(
524 (clkdm_status) extract_bit(cm_clkstctrl, 8)));
525 break;
526
527 case CLKDM54XX_DSS:
528 fprintf(stream, "| %-36s | %-23s |\n", " HDMI_CEC_GFCLK",
529 clkdm_status_name_get(
530 (clkdm_status) extract_bit(cm_clkstctrl, 12)));
531 fprintf(stream, "| %-36s | %-23s |\n", " HDMI_PHY_GFCLK",
532 clkdm_status_name_get(
533 (clkdm_status) extract_bit(cm_clkstctrl, 11)));
534 fprintf(stream, "| %-36s | %-23s |\n", " DSS_SYS_GFCLK",
535 clkdm_status_name_get(
536 (clkdm_status) extract_bit(cm_clkstctrl, 10)));
537 fprintf(stream, "| %-36s | %-23s |\n", " DSS_GFCLK",
538 clkdm_status_name_get(
539 (clkdm_status) extract_bit(cm_clkstctrl, 9)));
540 fprintf(stream, "| %-36s | %-23s |\n", " DSS_L[3-4]_GICLK",
541 clkdm_status_name_get(
542 (clkdm_status) extract_bit(cm_clkstctrl, 8)));
543 break;
544
545 case CLKDM54XX_CUST_EFUSE:
546 fprintf(stream, "| %-36s | %-23s |\n", " CUSTEFUSE_SYS_GFCLK",
547 clkdm_status_name_get(
548 (clkdm_status) extract_bit(cm_clkstctrl, 9)));
549 fprintf(stream, "| %-36s | %-23s |\n", " CUSTEFUSE_L4_GICLK",
550 clkdm_status_name_get(
551 (clkdm_status) extract_bit(cm_clkstctrl, 8)));
552 break;
553
554 case CLKDM54XX_L3_INIT:
555 fprintf(stream, "| %-36s | %-23s |\n", " USB_OTG_SS_REF_CLK",
556 clkdm_status_name_get(
557 (clkdm_status) extract_bit(cm_clkstctrl, 31)));
558 fprintf(stream, "| %-36s | %-23s |\n", " UTMI_P3_GFCLK",
559 clkdm_status_name_get(
560 (clkdm_status) extract_bit(cm_clkstctrl, 30)));
561 fprintf(stream, "| %-36s | %-23s |\n", " L3INIT_60M_P2_GFCLK",
562 clkdm_status_name_get(
563 (clkdm_status) extract_bit(cm_clkstctrl, 29)));
564 fprintf(stream, "| %-36s | %-23s |\n", " L3INIT_60M_P1_GFCLK",
565 clkdm_status_name_get(
566 (clkdm_status) extract_bit(cm_clkstctrl, 28)));
567 fprintf(stream, "| %-36s | %-23s |\n", " HSIC_P2_GFCLK",
568 clkdm_status_name_get(
569 (clkdm_status) extract_bit(cm_clkstctrl, 27)));
570 fprintf(stream, "| %-36s | %-23s |\n", " HSIC_P1_GFCLK",
571 clkdm_status_name_get(
572 (clkdm_status) extract_bit(cm_clkstctrl, 26)));
573 fprintf(stream, "| %-36s | %-23s |\n", " UTMI_ROOT_GFCLK",
574 clkdm_status_name_get(
575 (clkdm_status) extract_bit(cm_clkstctrl, 25)));
576 fprintf(stream, "| %-36s | %-23s |\n", " TLL_CH2_GFCLK",
577 clkdm_status_name_get(
578 (clkdm_status) extract_bit(cm_clkstctrl, 24)));
579 fprintf(stream, "| %-36s | %-23s |\n", " TLL_CH1_GFCLK",
580 clkdm_status_name_get(
581 (clkdm_status) extract_bit(cm_clkstctrl, 23)));
582 fprintf(stream, "| %-36s | %-23s |\n", " TLL_CH0_GFCLK",
583 clkdm_status_name_get(
584 (clkdm_status) extract_bit(cm_clkstctrl, 22)));
585 fprintf(stream, "| %-36s | %-23s |\n", " L3INIT_P2_480M_GFCLK",
586 clkdm_status_name_get(
587 (clkdm_status) extract_bit(cm_clkstctrl, 21)));
588 fprintf(stream, "| %-36s | %-23s |\n", " L3INIT_P1_480M_GFCLK",
589 clkdm_status_name_get(
590 (clkdm_status) extract_bit(cm_clkstctrl, 20)));
591 fprintf(stream, "| %-36s | %-23s |\n", " SATA_REF_GFCLK",
592 clkdm_status_name_get(
593 (clkdm_status) extract_bit(cm_clkstctrl, 19)));
594 fprintf(stream, "| %-36s | %-23s |\n", " MMC2_GFCLK",
595 clkdm_status_name_get(
596 (clkdm_status) extract_bit(cm_clkstctrl, 18)));
597 fprintf(stream, "| %-36s | %-23s |\n", " MMC1_GFCLK",
598 clkdm_status_name_get(
599 (clkdm_status) extract_bit(cm_clkstctrl, 17)));
600 fprintf(stream, "| %-36s | %-23s |\n", " HSI_GFCLK",
601 clkdm_status_name_get(
602 (clkdm_status) extract_bit(cm_clkstctrl, 16)));
603 fprintf(stream, "| %-36s | %-23s |\n", " USB_DPLL_HS_CLK",
604 clkdm_status_name_get(
605 (clkdm_status) extract_bit(cm_clkstctrl, 15)));
606 fprintf(stream, "| %-36s | %-23s |\n", " USB_DPLL_CLK",
607 clkdm_status_name_get(
608 (clkdm_status) extract_bit(cm_clkstctrl, 14)));
609 fprintf(stream, "| %-36s | %-23s |\n", " UNIPRO2_PHY_GFCLK",
610 clkdm_status_name_get(
611 (clkdm_status) extract_bit(cm_clkstctrl, 13)));
612 fprintf(stream, "| %-36s | %-23s |\n", " L3INIT_48M_GFCLK",
613 clkdm_status_name_get(
614 (clkdm_status) extract_bit(cm_clkstctrl, 12)));
615 fprintf(stream, "| %-36s | %-23s |\n",
616 " L3INIT_USB_OTG_SS_LFPS_TX_GFCLK",
617 clkdm_status_name_get(
618 (clkdm_status) extract_bit(cm_clkstctrl, 11)));
619 fprintf(stream, "| %-36s | %-23s |\n", " UNIPRO2_DPLL_CLK",
620 clkdm_status_name_get(
621 (clkdm_status) extract_bit(cm_clkstctrl, 10)));
622 fprintf(stream, "| %-36s | %-23s |\n", " L3INIT_L4_GICLK",
623 clkdm_status_name_get(
624 (clkdm_status) extract_bit(cm_clkstctrl, 9)));
625 fprintf(stream, "| %-36s | %-23s |\n", " L3INIT_L3_GICLK",
626 clkdm_status_name_get(
627 (clkdm_status) extract_bit(cm_clkstctrl, 8)));
628 fprintf(stream, "| %-36s | %-23s |\n", " HSIC_P3_GFCLK",
629 clkdm_status_name_get(
630 (clkdm_status) extract_bit(cm_clkstctrl, 7)));
631 fprintf(stream, "| %-36s | %-23s |\n", " HSIC_P3_480M_GFCLK",
632 clkdm_status_name_get(
633 (clkdm_status) extract_bit(cm_clkstctrl, 6)));
634 fprintf(stream, "| %-36s | %-23s |\n",
635 " UNIPRO2_PHY_REF_GFCLK",
636 clkdm_status_name_get(
637 (clkdm_status) extract_bit(cm_clkstctrl, 5)));
638 fprintf(stream, "| %-36s | %-23s |\n", " PAD_XCLK60MHSP2",
639 clkdm_status_name_get(
640 (clkdm_status) extract_bit(cm_clkstctrl, 4)));
641 fprintf(stream, "| %-36s | %-23s |\n", " PAD_XCLK60MHSP1",
642 clkdm_status_name_get(
643 (clkdm_status) extract_bit(cm_clkstctrl, 3)));
644 break;
645
646 case CLKDM54XX_L4_PER:
647 fprintf(stream, "| %-36s | %-23s |\n", " PAD_SLIMBUS2_CLK",
648 clkdm_status_name_get(
649 (clkdm_status) extract_bit(cm_clkstctrl, 26)));
650 fprintf(stream, "| %-36s | %-23s |\n", " PER_ABE_24M_GFCLK",
651 clkdm_status_name_get(
652 (clkdm_status) extract_bit(cm_clkstctrl, 25)));
653 fprintf(stream, "| %-36s | %-23s |\n", " PER_96M_GFCLK",
654 clkdm_status_name_get(
655 (clkdm_status) extract_bit(cm_clkstctrl, 19)));
656 fprintf(stream, "| %-36s | %-23s |\n", " PER_48M_GFCLK",
657 clkdm_status_name_get(
658 (clkdm_status) extract_bit(cm_clkstctrl, 18)));
659 fprintf(stream, "| %-36s | %-23s |\n", " PER_32K_GFCLK",
660 clkdm_status_name_get(
661 (clkdm_status) extract_bit(cm_clkstctrl, 17)));
662 fprintf(stream, "| %-36s | %-23s |\n", " PER_24M_GFCLK",
663 clkdm_status_name_get(
664 (clkdm_status) extract_bit(cm_clkstctrl, 16)));
665 fprintf(stream, "| %-36s | %-23s |\n", " PER_12M_GFCLK",
666 clkdm_status_name_get(
667 (clkdm_status) extract_bit(cm_clkstctrl, 15)));
668 fprintf(stream, "| %-36s | %-23s |\n", " TIMER9_GFCLK",
669 clkdm_status_name_get(
670 (clkdm_status) extract_bit(cm_clkstctrl, 14)));
671 fprintf(stream, "| %-36s | %-23s |\n", " TIMER4_GFCLK",
672 clkdm_status_name_get(
673 (clkdm_status) extract_bit(cm_clkstctrl, 13)));
674 fprintf(stream, "| %-36s | %-23s |\n", " TIMER3_GFCLK",
675 clkdm_status_name_get(
676 (clkdm_status) extract_bit(cm_clkstctrl, 12)));
677 fprintf(stream, "| %-36s | %-23s |\n", " TIMER2_GFCLK",
678 clkdm_status_name_get(
679 (clkdm_status) extract_bit(cm_clkstctrl, 11)));
680 fprintf(stream, "| %-36s | %-23s |\n", " TIMER11_GFCLK",
681 clkdm_status_name_get(
682 (clkdm_status) extract_bit(cm_clkstctrl, 10)));
683 fprintf(stream, "| %-36s | %-23s |\n", " TIMER10_GFCLK",
684 clkdm_status_name_get(
685 (clkdm_status) extract_bit(cm_clkstctrl, 9)));
686 fprintf(stream, "| %-36s | %-23s |\n", " L4PER_L4_GICLK",
687 clkdm_status_name_get(
688 (clkdm_status) extract_bit(cm_clkstctrl, 8)));
689 break;
690
691 case CLKDM54XX_L4_SEC:
692 fprintf(stream, "| %-36s | %-23s |\n", " L4SEC_L4_GICLK",
693 clkdm_status_name_get(
694 (clkdm_status) extract_bit(cm_clkstctrl, 9)));
695 fprintf(stream, "| %-36s | %-23s |\n", " L4SEC_L3_GICLK",
696 clkdm_status_name_get(
697 (clkdm_status) extract_bit(cm_clkstctrl, 8)));
698 break;
699
700 case CLKDM54XX_ABE:
701 fprintf(stream, "| %-36s | %-23s |\n", " PAD_SLIMBUS1_CLK",
702 clkdm_status_name_get(
703 (clkdm_status) extract_bit(cm_clkstctrl, 15)));
704 fprintf(stream, "| %-36s | %-23s |\n", " PAD_CLKS",
705 clkdm_status_name_get(
706 (clkdm_status) extract_bit(cm_clkstctrl, 14)));
707 fprintf(stream, "| %-36s | %-23s |\n", " ABE_24M_GFCLK",
708 clkdm_status_name_get(
709 (clkdm_status) extract_bit(cm_clkstctrl, 13)));
710 fprintf(stream, "| %-36s | %-23s |\n", " ABE_32K_CLK",
711 clkdm_status_name_get(
712 (clkdm_status) extract_bit(cm_clkstctrl, 12)));
713 fprintf(stream, "| %-36s | %-23s |\n", " ABE_SYS_CLK",
714 clkdm_status_name_get(
715 (clkdm_status) extract_bit(cm_clkstctrl, 11)));
716 fprintf(stream, "| %-36s | %-23s |\n", " FUNC_24M_GFCLK",
717 clkdm_status_name_get(
718 (clkdm_status) extract_bit(cm_clkstctrl, 10)));
719 fprintf(stream, "| %-36s | %-23s |\n", " ABE_GICLK",
720 clkdm_status_name_get(
721 (clkdm_status) extract_bit(cm_clkstctrl, 9)));
722 fprintf(stream, "| %-36s | %-23s |\n", " DPLL_ABE_X2_CLK",
723 clkdm_status_name_get(
724 (clkdm_status) extract_bit(cm_clkstctrl, 8)));
725 break;
726
727 case CLKDM54XX_DSP:
728 fprintf(stream, "| %-36s | %-23s |\n", " DSP_GCLK",
729 clkdm_status_name_get(
730 (clkdm_status) extract_bit(cm_clkstctrl, 8)));
731 break;
732
733 case CLKDM54XX_GPU:
734 fprintf(stream, "| %-36s | %-23s |\n", " GPU_HYD_GCLK",
735 clkdm_status_name_get(
736 (clkdm_status) extract_bit(cm_clkstctrl, 10)));
737 fprintf(stream, "| %-36s | %-23s |\n", " GPU_CORE_GCLK",
738 clkdm_status_name_get(
739 (clkdm_status) extract_bit(cm_clkstctrl, 9)));
740 fprintf(stream, "| %-36s | %-23s |\n", " GPU_L3_GICLK",
741 clkdm_status_name_get(
742 (clkdm_status) extract_bit(cm_clkstctrl, 8)));
743 break;
744
745 case CLKDM54XX_IVA:
746 fprintf(stream, "| %-36s | %-23s |\n", " IVA_GCLK",
747 clkdm_status_name_get(
748 (clkdm_status) extract_bit(cm_clkstctrl, 8)));
749 break;
750
751 case CLKDM54XX_MPU:
752 fprintf(stream, "| %-36s | %-23s |\n", " MPU_GCLK",
753 clkdm_status_name_get(
754 (clkdm_status) extract_bit(cm_clkstctrl, 8)));
755 break;
756
757 default:
758 break;
759 }
760
761 fprintf(stream, "|---------------------------------------------------"
762 "-------------|\n\n");
763
764 return 0;
765 }
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