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4bc042b initial public release v1.50
Patrick Titiano authored
1 /*
2 *
3 * @Component OMAPCONF
4 * @Filename clock54xx.h
5 * @Description OMAP5 Clocks Definitions & Functions
6 * @Author Patrick Titiano (p-titiano@ti.com)
7 * @Date 2011
8 * @Copyright Texas Instruments Incorporated
9 *
10 *
11 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
12 *
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 *
18 * Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 *
21 * Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the
24 * distribution.
25 *
26 * Neither the name of Texas Instruments Incorporated nor the names of
27 * its contributors may be used to endorse or promote products derived
28 * from this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 */
43
44
45 #ifndef __CLOCK54XX_H__
46 #define __CLOCK54XX_H__
47
48 #define CLK54XX_MAX_NAME_LENGTH 32
49
50 typedef enum {
51 /* 32K CLKS */
52 CLK54XX_SYS_32K,
53 CLK54XX_FUNC_32K_CLK,
54 CLK54XX_SECURE_32K_CLK,
55 CLK54XX_HDMI_CEC_GFCLK,
56 CLK54XX_WKUPAON_32K_GFCLK,
57 CLK54XX_COREAON_32K_GFCLK,
58 CLK54XX_PER_32K_GFCLK,
59 CLK54XX_ABE_32K_CLK,
60 /* SYS CLKS */
61 CLK54XX_SYS_CLKIN,
62 CLK54XX_SYS_CLK,
63 CLK54XX_CUSTEFUSE_SYS_GFCLK,
64 CLK54XX_EMU_SYS_CLK,
65 CLK54XX_CORE_DPLL_CLK,
66 CLK54XX_PER_DPLL_CLK,
67 CLK54XX_IVA_DPLL_CLK,
68 CLK54XX_MPU_DPLL_CLK,
69 CLK54XX_UNIPRO2_DPLL_CLK,
70 CLK54XX_USB_DPLL_CLK,
71 CLK54XX_USB_OTG_SS_REF_CLK,
72 CLK54XX_UNIPRO1_DPLL_CLK,
73 CLK54XX_WKUPAON_IO_SRCOMP_GFCLK,
74 CLK54XX_COREAON_IO_SRCOMP_GFCLK,
75 CLK54XX_UNIPRO2_PHY_REF_GFCLK,
76 CLK54XX_MIPIEXT_PHY_REF_GFCLK,
77 CLK54XX_SATA_REF_GFCLK,
78 CLK54XX_DSS_SYS_CLK,
79 CLK54XX_ABE_SYS_CLK,
80 /* DPLL BYPASS INPUT CLKS */
81 CLK54XX_ABE_DPLL_CLK,
82 CLK54XX_ABE_DPLL_BYPASS_CLK,
83 CLK54XX_MPU_DPLL_HS_CLK,
84 CLK54XX_IVA_DPLL_HS_CLK,
85 CLK54XX_PER_DPLL_HS_CLK,
86 CLK54XX_USB_DPLL_HS_CLK,
87 /* DPLL ABE OUTPUT CLKS */
88 CLK54XX_PER_ABE_X1_GFCLK,
89 CLK54XX_DPLL_ABE_X2_FCLK,
90 CLK54XX_CORE_DPLL_HS_CLK,
91 /* DPLL CORE OUTPUTS */
92 CLK54XX_EMIF_PHY_GCLK,
93 CLK54XX_CORE_DPLL_SCRM_CLK,
94 CLK54XX_CORE_DLL_GCLK,
95 CLK54XX_CORE_X2_CLK,
96 CLK54XX_CORE_USB_OTG_SS_LFPS_TX_CLK,
97 CLK54XX_CORE_GPU_CLK,
98 CLK54XX_CORE_IPU_ISS_BOOST_CLK,
99 CLK54XX_CORE_ISS_MAIN_CLK,
100 /* DPLL PER OUTPUTS */
101 CLK54XX_FUNC_96M_AON_CLK,
102 CLK54XX_FUNC_192M_FCLK,
103 CLK54XX_PER_DPLL_SCRM_CLK,
104 CLK54XX_FUNC_128M_CLK,
105 CLK54XX_DSS_GFCLK,
106 CLK54XX_PER_GPU_CLK,
107 /* DPLL MPU OUTPUTS */
108 CLK54XX_MPU_GCLK,
109 /* DPLL IVA OUTPUTS */
110 CLK54XX_DSP_GCLK,
111 CLK54XX_IVA_GCLK,
112 /* DPLL USB OUTPUTS */
113 CLK54XX_L3INIT_480M_GFCLK,
114 CLK54XX_L3INIT_960M_FCLK,
115 /* DPLL UNIPRO1 OUTPUTS */
116 CLK54XX_UNIPRO1_TXPHY_LS_GFCLK,
117 CLK54XX_UNIPRO1_PHY_GFCLK,
118 /* DPLL UNIPRO2 OUTPUTS */
119 CLK54XX_UNIPRO2_TXPHY_LS_GFCLK,
120 CLK54XX_UNIPRO2_PHY_GFCLK,
121 /* COREAON CLKDM Clocks */
122 CLK54XX_FUNC_24M_CLK,
123 CLK54XX_FUNC_24M_GFCLK,
124 CLK54XX_CORE_CLK,
125 CLK54XX_L3_ICLK,
126 CLK54XX_EMIF_L3_GICLK,
127 CLK54XX_L4SEC_L3_GICLK,
128 CLK54XX_CAM_L3_GICLK,
129 CLK54XX_C2C_L3_GICLK,
130 CLK54XX_DMA_L3_GICLK,
131 CLK54XX_L3INSTR_L3_GICLK,
132 CLK54XX_L3MAIN1_L3_GICLK,
133 CLK54XX_L3MAIN2_L3_GICLK,
134 CLK54XX_MIPIEXT_L3_GICLK,
135 CLK54XX_DSS_L3_GICLK,
136 CLK54XX_L3INIT_L3_GICLK,
137 CLK54XX_CM_CORE_AON_PROFILING_L3_GICLK,
138 CLK54XX_L4_ROOT_CLK,
139 CLK54XX_L4_ICLK,
140 CLK54XX_L4PER_L4_GICLK,
141 CLK54XX_L4SEC_L4_GICLK,
142 CLK54XX_C2C_L4_GICLK,
143 CLK54XX_L4CFG_L4_GICLK,
144 CLK54XX_MIPIEXT_L4_GICLK,
145 CLK54XX_L3INIT_L4_GICLK,
146 CLK54XX_CM_CORE_AON_PROFILING_L4_GICLK,
147 /* PRM CLKDM Clocks */
148 CLK54XX_ABE_LP_CLK,
149 CLK54XX_WKUPAON_ICLK,
150 CLK54XX_SR_MM_SYS_GFCLK,
151 CLK54XX_SR_MPU_SYS_GFCLK,
152 CLK54XX_SR_CORE_SYS_GFCLK,
153 CLK54XX_WKUPAON_GCLK,
154 CLK54XX_WKUPAON_GICLK,
155 CLK54XX_CM_CORE_AON_SYS_CLK,
156 CLK54XX_WKUPAON_PROFILING_GCLK,
157 CLK54XX_CORE_TS_GFCLK,
158 CLK54XX_COREAON_TS_GFCLK,
159 CLK54XX_L3INSTR_DLL_AGING_GCLK,
160 /* PRM TIMER Clocks */
161 CLK54XX_TIMER1_GFCLK,
162 CLK54XX_TIMER2_GFCLK,
163 CLK54XX_TIMER3_GFCLK,
164 CLK54XX_TIMER4_GFCLK,
165 CLK54XX_TIMER9_GFCLK,
166 CLK54XX_TIMER10_GFCLK,
167 CLK54XX_TIMER11_GFCLK,
168 /* CKGEN_USB Clocks */
169 CLK54XX_UTMI_P3_GFCLK,
170 CLK54XX_HSIC_P3_GFCLK,
171 CLK54XX_HSIC_P2_GFCLK,
172 CLK54XX_HSIC_P1_GFCLK,
173 CLK54XX_L3INIT_60M_P1_GFCLK,
174 CLK54XX_L3INIT_60M_P2_GFCLK,
175 CLK54XX_UTMI_ROOT_GFCLK,
176 CLK54XX_TLL_CH0_GFCLK,
177 CLK54XX_TLL_CH1_GFCLK,
178 CLK54XX_TLL_CH2_GFCLK,
179 CLK54XX_L3INIT_60M_FCLK,
180 CLK54XX_HSIC_P1_480M_GFCLK,
181 CLK54XX_HSIC_P2_480M_GFCLK,
182 CLK54XX_HSIC_P3_480M_GFCLK,
183 CLK54XX_XCLK_60M_HSP2,
184 CLK54XX_XCLK_60M_HSP1,
185 CLK54XX_UTMI_P1_GFCLK,
186 CLK54XX_UTMI_P2_GFCLK,
187 /* CKGEN_ABE Clocks */
188 CLK54XX_PAD_UCLKS,
189 CLK54XX_SLIMBUS_UCLKS,
190 CLK54XX_ABE_CLK,
191 CLK54XX_AESS_FCLK,
192 CLK54XX_ABE_GICLK,
193 CLK54XX_ABE_24M_FCLK,
194 CLK54XX_PAD_GCLKS,
195 CLK54XX_SLIMBUS_CLK,
196 CLK54XX_MCBSP1_INT_GFCLK,
197 CLK54XX_MCBSP2_INT_GFCLK,
198 CLK54XX_MCBSP3_INT_GFCLK,
199 CLK54XX_MCASP1_INT_GFCLK,
200 CLK54XX_DMIC_INT_GFCLK,
201 CLK54XX_MCBSP1_GFCLK,
202 CLK54XX_MCBSP2_GFCLK,
203 CLK54XX_MCBSP3_GFCLK,
204 CLK54XX_MCASP1_GFCLK,
205 CLK54XX_DMIC_GFCLK,
206 CLK54XX_TIMER5_GFCLK,
207 CLK54XX_TIMER6_GFCLK,
208 CLK54XX_TIMER7_GFCLK,
209 CLK54XX_TIMER8_GFCLK,
210 /* CM_CORE Clocks */
211 CLK54XX_GPU_HYD_GCLK,
212 CLK54XX_GPU_CORE_GCLK,
213 CLK54XX_FDIF_GFCLK,
214 CLK54XX_PER_ABE_24M_FCLK,
215 CLK54XX_FUNC_96M_FCLK,
216 CLK54XX_FUNC_48M_FCLK,
217 CLK54XX_FUNC_24M_FCLK,
218 CLK54XX_HSI_FCLK,
219 CLK54XX_FUNC_12M_FCLK,
220 CLK54XX_MMC1_GFCLK,
221 CLK54XX_MMC2_GFCLK,
222 CLK54XX_PER_ABE_24M_GFCLK,
223 CLK54XX_PER_96M_GFCLK,
224 CLK54XX_PER_48M_GFCLK,
225 CLK54XX_PER_24M_GFCLK,
226 CLK54XX_HSI_GFCLK,
227 CLK54XX_PER_12M_GFCLK,
228 CLK54XX_ID_MAX
229 } clk54xx_id;
230
231
232 double clk54xx_sysclk_rate_get(void);
233 const char *clk54xx_name_get(clk54xx_id id);
234 double clk54xx_rate_get(clk54xx_id clk, unsigned short ignore);
235 double clk54xx_rate_get_fw(clk54xx_id clk);
236 const char *clk54xx_name_get_fw(clk54xx_id id);
237
238
239 #endif
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