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4bc042b initial public release v1.50
Patrick Titiano authored Sep 21, 2012
1 /*
2 *
3 * @Component OMAPCONF
4 * @Filename ctrlmod_core54xx-defs.h
5 * @Description OMAP5 CONTROL MODULE Registers Definitions
6 * @Author Patrick Titiano (p-titiano@ti.com)
7 * @Date 2011
8 * @Copyright Texas Instruments Incorporated
9 *
10 *
11 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
12 *
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 *
18 * Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 *
21 * Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the
24 * distribution.
25 *
26 * Neither the name of Texas Instruments Incorporated nor the names of
27 * its contributors may be used to endorse or promote products derived
28 * from this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 */
43
44
45 #ifndef __CTRLMOD_CORE54XX_DEFS_H__
46 #define __CTRLMOD_CORE54XX_DEFS_H__
47
48 #include <reg.h>
49 #include <stdio.h>
50
51 #define OMAP5430_CONTROL_CORE_REVISION 0x4a002000
52 extern reg omap5430_control_core_revision;
53 #define OMAP5430_CONTROL_CORE_HWINFO 0x4a002004
54 extern reg omap5430_control_core_hwinfo;
55 #define OMAP5430_CONTROL_CORE_SYSCONFIG 0x4a002010
56 extern reg omap5430_control_core_sysconfig;
57 #define OMAP5430_CONTROL_L3_HW_FW_EXPORTED_VALUES_CONF_DBG 0x4a002114
58 extern reg omap5430_control_l3_hw_fw_exported_values_conf_dbg;
59 #define OMAP5430_CONTROL_L3_HW_FW_EXPORTED_VALUES_CONF_FUNC 0x4a002118
60 extern reg omap5430_control_l3_hw_fw_exported_values_conf_func;
61 #define OMAP5430_CONTROL_STATUS 0x4a002134
62 extern reg omap5430_control_status;
63 #define OMAP5430_CONTROL_FORCEWRNP 0x4a00215c
64 extern reg omap5430_control_forcewrnp;
65 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MM_0 0x4a002194
66 extern reg omap5430_control_std_fuse_opp_vdd_mm_0;
67 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MM_1 0x4a002198
68 extern reg omap5430_control_std_fuse_opp_vdd_mm_1;
69 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MM_2 0x4a00219c
70 extern reg omap5430_control_std_fuse_opp_vdd_mm_2;
71 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MM_3 0x4a0021a0
72 extern reg omap5430_control_std_fuse_opp_vdd_mm_3;
73 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MM_4 0x4a0021a4
74 extern reg omap5430_control_std_fuse_opp_vdd_mm_4;
75 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MM_5 0x4a0021a8
76 extern reg omap5430_control_std_fuse_opp_vdd_mm_5;
77 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MPU_0 0x4a0021ac
78 extern reg omap5430_control_std_fuse_opp_vdd_mpu_0;
79 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MPU_1 0x4a0021b0
80 extern reg omap5430_control_std_fuse_opp_vdd_mpu_1;
81 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MPU_2 0x4a0021b4
82 extern reg omap5430_control_std_fuse_opp_vdd_mpu_2;
83 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MPU_3 0x4a0021b8
84 extern reg omap5430_control_std_fuse_opp_vdd_mpu_3;
85 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MPU_4 0x4a0021bc
86 extern reg omap5430_control_std_fuse_opp_vdd_mpu_4;
87 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MPU_5 0x4a0021c0
88 extern reg omap5430_control_std_fuse_opp_vdd_mpu_5;
89 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MPU_6 0x4a0021c4
90 extern reg omap5430_control_std_fuse_opp_vdd_mpu_6;
91 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MPU_7 0x4a0021c8
92 extern reg omap5430_control_std_fuse_opp_vdd_mpu_7;
93 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_CORE_0 0x4a0021cc
94 extern reg omap5430_control_std_fuse_opp_vdd_core_0;
95 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_CORE_1 0x4a0021d0
96 extern reg omap5430_control_std_fuse_opp_vdd_core_1;
97 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_CORE_2 0x4a0021d4
98 extern reg omap5430_control_std_fuse_opp_vdd_core_2;
99 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_CORE_3 0x4a0021d8
100 extern reg omap5430_control_std_fuse_opp_vdd_core_3;
101 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_CORE_4 0x4a0021dc
102 extern reg omap5430_control_std_fuse_opp_vdd_core_4;
103 #define OMAP5430_CONTROL_STD_FUSE_OPP_BGAP_MM 0x4a0021e0
104 extern reg omap5430_control_std_fuse_opp_bgap_mm;
105 #define OMAP5430_CONTROL_STD_FUSE_OPP_BGAP_MPU 0x4a0021e4
106 extern reg omap5430_control_std_fuse_opp_bgap_mpu;
107 #define OMAP5430_CONTROL_STD_FUSE_OPP_BGAP_CORE 0x4a0021e8
108 extern reg omap5430_control_std_fuse_opp_bgap_core;
109 #define OMAP5430_CONTROL_STD_FUSE_DIE_ID_0 0x4a002200
110 extern reg omap5430_control_std_fuse_die_id_0;
111 #define OMAP5430_CONTROL_STD_FUSE_DIE_ID_1 0x4a002208
112 extern reg omap5430_control_std_fuse_die_id_1;
113 #define OMAP5430_CONTROL_STD_FUSE_DIE_ID_2 0x4a00220c
114 extern reg omap5430_control_std_fuse_die_id_2;
115 #define OMAP5430_CONTROL_STD_FUSE_DIE_ID_3 0x4a002210
116 extern reg omap5430_control_std_fuse_die_id_3;
117 #define OMAP5430_CONTROL_STD_FUSE_PROD_ID 0x4a002214
118 extern reg omap5430_control_std_fuse_prod_id;
119 #define OMAP5430_CONTROL_STD_FUSE_CONF_ID_0 0x4a002218
120 extern reg omap5430_control_std_fuse_conf_id_0;
121 #define OMAP5430_CONTROL_STD_FUSE_CONF_ID_1 0x4a00221c
122 extern reg omap5430_control_std_fuse_conf_id_1;
123 #define OMAP5430_CONTROL_STD_FUSE_MPK_0 0x4a002220
124 extern reg omap5430_control_std_fuse_mpk_0;
125 #define OMAP5430_CONTROL_STD_FUSE_MPK_1 0x4a002224
126 extern reg omap5430_control_std_fuse_mpk_1;
127 #define OMAP5430_CONTROL_STD_FUSE_MPK_2 0x4a002228
128 extern reg omap5430_control_std_fuse_mpk_2;
129 #define OMAP5430_CONTROL_STD_FUSE_MPK_3 0x4a00222c
130 extern reg omap5430_control_std_fuse_mpk_3;
131 #define OMAP5430_CONTROL_STD_FUSE_MPK_4 0x4a002230
132 extern reg omap5430_control_std_fuse_mpk_4;
133 #define OMAP5430_CONTROL_STD_FUSE_MPK_5 0x4a002234
134 extern reg omap5430_control_std_fuse_mpk_5;
135 #define OMAP5430_CONTROL_STD_FUSE_MPK_6 0x4a002238
136 extern reg omap5430_control_std_fuse_mpk_6;
137 #define OMAP5430_CONTROL_STD_FUSE_MPK_7 0x4a00223c
138 extern reg omap5430_control_std_fuse_mpk_7;
139 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MM_LVT_0 0x4a002240
140 extern reg omap5430_control_std_fuse_opp_vdd_mm_lvt_0;
141 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MM_LVT_1 0x4a002244
142 extern reg omap5430_control_std_fuse_opp_vdd_mm_lvt_1;
143 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MM_LVT_2 0x4a002248
144 extern reg omap5430_control_std_fuse_opp_vdd_mm_lvt_2;
145 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MM_LVT_3 0x4a00224c
146 extern reg omap5430_control_std_fuse_opp_vdd_mm_lvt_3;
147 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MM_LVT_4 0x4a002250
148 extern reg omap5430_control_std_fuse_opp_vdd_mm_lvt_4;
149 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MM_LVT_5 0x4a002254
150 extern reg omap5430_control_std_fuse_opp_vdd_mm_lvt_5;
151 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MPU_LVT_0 0x4a002258
152 extern reg omap5430_control_std_fuse_opp_vdd_mpu_lvt_0;
153 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MPU_LVT_1 0x4a00225c
154 extern reg omap5430_control_std_fuse_opp_vdd_mpu_lvt_1;
155 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MPU_LVT_2 0x4a002260
156 extern reg omap5430_control_std_fuse_opp_vdd_mpu_lvt_2;
157 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MPU_LVT_3 0x4a002264
158 extern reg omap5430_control_std_fuse_opp_vdd_mpu_lvt_3;
159 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MPU_LVT_4 0x4a002268
160 extern reg omap5430_control_std_fuse_opp_vdd_mpu_lvt_4;
161 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MPU_LVT_5 0x4a00226c
162 extern reg omap5430_control_std_fuse_opp_vdd_mpu_lvt_5;
163 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MPU_LVT_6 0x4a002270
164 extern reg omap5430_control_std_fuse_opp_vdd_mpu_lvt_6;
165 #define OMAP5430_CONTROL_STD_FUSE_OPP_VDD_MPU_LVT_7 0x4a002274
166 extern reg omap5430_control_std_fuse_opp_vdd_mpu_lvt_7;
167 #define OMAP5430_CONTROL_CUST_FUSE_SWRV_0 0x4a0022bc
168 extern reg omap5430_control_cust_fuse_swrv_0;
169 #define OMAP5430_CONTROL_CUST_FUSE_SWRV_1 0x4a0022c0
170 extern reg omap5430_control_cust_fuse_swrv_1;
171 #define OMAP5430_CONTROL_CUST_FUSE_SWRV_2 0x4a0022c4
172 extern reg omap5430_control_cust_fuse_swrv_2;
173 #define OMAP5430_CONTROL_CUST_FUSE_SWRV_3 0x4a0022c8
174 extern reg omap5430_control_cust_fuse_swrv_3;
175 #define OMAP5430_CONTROL_CUST_FUSE_SWRV_4 0x4a0022cc
176 extern reg omap5430_control_cust_fuse_swrv_4;
177 #define OMAP5430_CONTROL_CUST_FUSE_SWRV_5 0x4a0022d0
178 extern reg omap5430_control_cust_fuse_swrv_5;
179 #define OMAP5430_CONTROL_CUST_FUSE_SWRV_6 0x4a0022d4
180 extern reg omap5430_control_cust_fuse_swrv_6;
181 #define OMAP5430_CONTROL_DEV_CONF 0x4a002300
182 extern reg omap5430_control_dev_conf;
183 #define OMAP5430_CONTROL_DSP_BOOTADDR 0x4a002304
184 extern reg omap5430_control_dsp_bootaddr;
185 #define OMAP5430_CONTROL_TEMP_SENSOR_MPU 0x4a00232c
186 extern reg omap5430_control_temp_sensor_mpu;
187 #define OMAP5430_CONTROL_TEMP_SENSOR_MM 0x4a002330
188 extern reg omap5430_control_temp_sensor_mm;
189 #define OMAP5430_CONTROL_TEMP_SENSOR_CORE 0x4a002334
190 extern reg omap5430_control_temp_sensor_core;
191 #define OMAP5430_CONTROL_LDOSRAM_MPU_LVT_VOLTAGE_CTRL 0x4a002338
192 extern reg omap5430_control_ldosram_mpu_lvt_voltage_ctrl;
193 #define OMAP5430_CONTROL_CORTEX_M4_MMUADDRTRANSLTR 0x4a002358
194 extern reg omap5430_control_cortex_m4_mmuaddrtransltr;
195 #define OMAP5430_CONTROL_CORTEX_M4_MMUADDRLOGICTR 0x4a00235c
196 extern reg omap5430_control_cortex_m4_mmuaddrlogictr;
197 #define OMAP5430_CONTROL_HWOBS_CONTROL 0x4a002360
198 extern reg omap5430_control_hwobs_control;
199 #define OMAP5430_CONTROL_PCS1 0x4a002364
200 extern reg omap5430_control_pcs1;
201 #define OMAP5430_CONTROL_PCS2 0x4a002368
202 extern reg omap5430_control_pcs2;
203 #define OMAP5430_CONTROL_PCS_REVISION 0x4a00236c
204 extern reg omap5430_control_pcs_revision;
205 #define OMAP5430_CONTROL_PHY_POWER_USB 0x4a002370
206 extern reg omap5430_control_phy_power_usb;
207 #define OMAP5430_CONTROL_PHY_POWER_SATA 0x4a002374
208 extern reg omap5430_control_phy_power_sata;
209 #define OMAP5430_CONTROL_SLIMBUS_KEEPER 0x4a002378
210 extern reg omap5430_control_slimbus_keeper;
211 #define OMAP5430_CONTROL_PHY_SEL 0x4a00237c
212 extern reg omap5430_control_phy_sel;
213 #define OMAP5430_CONTROL_BANDGAP_MASK 0x4a002380
214 extern reg omap5430_control_bandgap_mask;
215 #define OMAP5430_CONTROL_BANDGAP_THRESHOLD_MPU 0x4a002384
216 extern reg omap5430_control_bandgap_threshold_mpu;
217 #define OMAP5430_CONTROL_BANDGAP_THRESHOLD_MM 0x4a002388
218 extern reg omap5430_control_bandgap_threshold_mm;
219 #define OMAP5430_CONTROL_BANDGAP_THRESHOLD_CORE 0x4a00238c
220 extern reg omap5430_control_bandgap_threshold_core;
221 #define OMAP5430_CONTROL_BANDGAP_TSHUT_MPU 0x4a002390
222 extern reg omap5430_control_bandgap_tshut_mpu;
223 #define OMAP5430_CONTROL_BANDGAP_TSHUT_MM 0x4a002394
224 extern reg omap5430_control_bandgap_tshut_mm;
225 #define OMAP5430_CONTROL_BANDGAP_TSHUT_CORE 0x4a002398
226 extern reg omap5430_control_bandgap_tshut_core;
227 #define OMAP5430_CONTROL_BANDGAP_COUNTER_MPU 0x4a00239c
228 extern reg omap5430_control_bandgap_counter_mpu;
229 #define OMAP5430_CONTROL_BANDGAP_COUNTER_MM 0x4a0023a0
230 extern reg omap5430_control_bandgap_counter_mm;
231 #define OMAP5430_CONTROL_BANDGAP_COUNTER_CORE 0x4a0023a4
232 extern reg omap5430_control_bandgap_counter_core;
233 #define OMAP5430_CONTROL_BANDGAP_STATUS 0x4a0023a8
234 extern reg omap5430_control_bandgap_status;
235 #define OMAP5430_CONTROL_SATA_EXT_MODE 0x4a0023ac
236 extern reg omap5430_control_sata_ext_mode;
237 #define OMAP5430_CONTROL_OCPREG_SPARE 0x4a0023fc
238 extern reg omap5430_control_ocpreg_spare;
239 #define OMAP5430_CONTROL_DEBOBS_FINAL_MUX_SEL 0x4a002400
240 extern reg omap5430_control_debobs_final_mux_sel;
241 #define OMAP5430_CONTROL_DEBOBS_OCPWP_SYS_EVENT_SEL 0x4a002404
242 extern reg omap5430_control_debobs_ocpwp_sys_event_sel;
243 #define OMAP5430_CONTROL_DEBOBS_MMR_MPU 0x4a002408
244 extern reg omap5430_control_debobs_mmr_mpu;
245 #define OMAP5430_CONTROL_CONF_MDMA_REQ_SEL0 0x4a002410
246 extern reg omap5430_control_conf_mdma_req_sel0;
247 #define OMAP5430_CONTROL_CONF_MDMA_REQ_SEL1 0x4a002414
248 extern reg omap5430_control_conf_mdma_req_sel1;
249 #define OMAP5430_CONTROL_CONF_MDMA_REQ_SEL2 0x4a002418
250 extern reg omap5430_control_conf_mdma_req_sel2;
251 #define OMAP5430_CONTROL_CONF_MDMA_REQ_SEL3 0x4a00241c
252 extern reg omap5430_control_conf_mdma_req_sel3;
253 #define OMAP5430_CONTROL_CONF_MDMA_REQ_SEL4 0x4a002420
254 extern reg omap5430_control_conf_mdma_req_sel4;
255 #define OMAP5430_CONTROL_CONF_MDMA_REQ_SEL5 0x4a002424
256 extern reg omap5430_control_conf_mdma_req_sel5;
257 #define OMAP5430_CONTROL_CONF_SDMA_REQ_SEL0 0x4a00242c
258 extern reg omap5430_control_conf_sdma_req_sel0;
259 #define OMAP5430_CONTROL_CONF_SDMA_REQ_SEL1 0x4a002430
260 extern reg omap5430_control_conf_sdma_req_sel1;
261 #define OMAP5430_CONTROL_CONF_SDMA_REQ_SEL2 0x4a002434
262 extern reg omap5430_control_conf_sdma_req_sel2;
263 #define OMAP5430_CONTROL_CONF_SDMA_REQ_SEL3 0x4a002438
264 extern reg omap5430_control_conf_sdma_req_sel3;
265 #define OMAP5430_CONTROL_CONF_CLK_SEL0 0x4a002440
266 extern reg omap5430_control_conf_clk_sel0;
267 #define OMAP5430_CONTROL_CONF_CLK_SEL1 0x4a002444
268 extern reg omap5430_control_conf_clk_sel1;
269 #define OMAP5430_CONTROL_CONF_CLK_SEL2 0x4a002448
270 extern reg omap5430_control_conf_clk_sel2;
271 #define OMAP5430_CONTROL_CONF_DPLL_FREQLOCK_SEL 0x4a00244c
272 extern reg omap5430_control_conf_dpll_freqlock_sel;
273 #define OMAP5430_CONTROL_CONF_DPLL_TINITZ_SEL 0x4a002450
274 extern reg omap5430_control_conf_dpll_tinitz_sel;
275 #define OMAP5430_CONTROL_CONF_DPLL_PHASELOCK_SEL 0x4a002454
276 extern reg omap5430_control_conf_dpll_phaselock_sel;
277 #define OMAP5430_CONTROL_CONF_DPLL_TENABLE_SEL 0x4a002458
278 extern reg omap5430_control_conf_dpll_tenable_sel;
279 #define OMAP5430_CONTROL_CONF_DPLL_TENABLEDIV_SEL 0x4a00245c
280 extern reg omap5430_control_conf_dpll_tenablediv_sel;
281 #define OMAP5430_CONTROL_CONF_DPLL_BYPASSACK_SEL 0x4a002460
282 extern reg omap5430_control_conf_dpll_bypassack_sel;
283 #define OMAP5430_CONTROL_CONF_DPLL_IDLE_SEL 0x4a002464
284 extern reg omap5430_control_conf_dpll_idle_sel;
285 #define OMAP5430_CONTROL_CONF_DPLLCTRL_PLLLOCK_SEL 0x4a002468
286 extern reg omap5430_control_conf_dpllctrl_plllock_sel;
287 #define OMAP5430_CONTROL_CONF_DPLLCTRL_PLLRECAL_SEL 0x4a00246c
288 extern reg omap5430_control_conf_dpllctrl_pllrecal_sel;
289 #define OMAP5430_CONTROL_CONF_DPLLCTRL_STOPCLOCK_SEL 0x4a002470
290 extern reg omap5430_control_conf_dpllctrl_stopclock_sel;
291 #define OMAP5430_CONTROL_CONF_DPLLCTRL_STOPCLOCKACKZ_SEL 0x4a002474
292 extern reg omap5430_control_conf_dpllctrl_stopclockackz_sel;
293 #define OMAP5430_CONTROL_CONF_DPLLCTRL_DISPCUPDATESYNC_SEL 0x4a002478
294 extern reg omap5430_control_conf_dpllctrl_dispcupdatesync_sel;
295 #define OMAP5430_CONTROL_CONF_DPLLCTRL_SCPENPLLCTRL_SEL 0x4a00247c
296 extern reg omap5430_control_conf_dpllctrl_scpenpllctrl_sel;
297 #define OMAP5430_CONTROL_CONF_DPLLCTRL_SCPCMD1_SEL 0x4a002480
298 extern reg omap5430_control_conf_dpllctrl_scpcmd1_sel;
299 #define OMAP5430_CONTROL_CONF_DPLLCTRL_SCPCMD0_SEL 0x4a002484
300 extern reg omap5430_control_conf_dpllctrl_scpcmd0_sel;
301 #define OMAP5430_CONTROL_CONF_DPLLCTRL_SCPADDR3_SEL 0x4a002488
302 extern reg omap5430_control_conf_dpllctrl_scpaddr3_sel;
303 #define OMAP5430_CONTROL_CONF_DPLLCTRL_SCPADDR2_SEL 0x4a00248c
304 extern reg omap5430_control_conf_dpllctrl_scpaddr2_sel;
305 #define OMAP5430_CONTROL_CONF_DPLLCTRL_SCPADDR1_SEL 0x4a002490
306 extern reg omap5430_control_conf_dpllctrl_scpaddr1_sel;
307 #define OMAP5430_CONTROL_CONF_DPLLCTRL_SCPADDR0_SEL 0x4a002494
308 extern reg omap5430_control_conf_dpllctrl_scpaddr0_sel;
309 #define OMAP5430_CONTROL_CONF_DPLLCTRL_SCPOUT_SEL 0x4a002498
310 extern reg omap5430_control_conf_dpllctrl_scpout_sel;
311 #define OMAP5430_CONTROL_CONF_DPLLCTRL_SCPINPLLCTRL_SEL 0x4a00249c
312 extern reg omap5430_control_conf_dpllctrl_scpinpllctrl_sel;
313 #define OMAP5430_CONTROL_CONF_DPLLCTRL_SCPBUSY_SEL 0x4a0024a0
314 extern reg omap5430_control_conf_dpllctrl_scpbusy_sel;
315 #define OMAP5430_CONTROL_CONF_MMCX_ADPIDLE_SEL 0x4a0024ac
316 extern reg omap5430_control_conf_mmcx_adpidle_sel;
317 #define OMAP5430_CONTROL_CONF_MMCX_ADPDAT1PADEN_SEL 0x4a0024b0
318 extern reg omap5430_control_conf_mmcx_adpdat1paden_sel;
319 #define OMAP5430_CONTROL_CONF_MMCX_OCPL4IDLEREQ_SEL 0x4a0024b4
320 extern reg omap5430_control_conf_mmcx_ocpl4idlereq_sel;
321 #define OMAP5430_CONTROL_CONF_MMCX_OCPL3MWAIT_SEL 0x4a0024b8
322 extern reg omap5430_control_conf_mmcx_ocpl3mwait_sel;
323 #define OMAP5430_CONTROL_CONF_MMCX_PIRFFRET_SEL 0x4a0024bc
324 extern reg omap5430_control_conf_mmcx_pirffret_sel;
325 #define OMAP5430_CONTROL_CONF_MMCX_OCPL4SIDLEACKO1_SEL 0x4a0024c0
326 extern reg omap5430_control_conf_mmcx_ocpl4sidleacko1_sel;
327 #define OMAP5430_CONTROL_CONF_MMCX_OCPL4SIDLEACKO0_SEL 0x4a0024c4
328 extern reg omap5430_control_conf_mmcx_ocpl4sidleacko0_sel;
329 #define OMAP5430_CONTROL_CONF_MMCX_OCPL3MSTANDBYO_SEL 0x4a0024c8
330 extern reg omap5430_control_conf_mmcx_ocpl3mstandbyo_sel;
331 #define OMAP5430_CONTROL_CONF_MMCX_SWAKEUP_SEL 0x4a0024cc
332 extern reg omap5430_control_conf_mmcx_swakeup_sel;
333 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_0 0x4a0024d0
334 extern reg omap5430_control_core_conf_debug_sel_tst_0;
335 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_1 0x4a0024d4
336 extern reg omap5430_control_core_conf_debug_sel_tst_1;
337 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_2 0x4a0024d8
338 extern reg omap5430_control_core_conf_debug_sel_tst_2;
339 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_3 0x4a0024dc
340 extern reg omap5430_control_core_conf_debug_sel_tst_3;
341 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_4 0x4a0024e0
342 extern reg omap5430_control_core_conf_debug_sel_tst_4;
343 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_5 0x4a0024e4
344 extern reg omap5430_control_core_conf_debug_sel_tst_5;
345 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_6 0x4a0024e8
346 extern reg omap5430_control_core_conf_debug_sel_tst_6;
347 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_7 0x4a0024ec
348 extern reg omap5430_control_core_conf_debug_sel_tst_7;
349 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_8 0x4a0024f0
350 extern reg omap5430_control_core_conf_debug_sel_tst_8;
351 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_9 0x4a0024f4
352 extern reg omap5430_control_core_conf_debug_sel_tst_9;
353 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_10 0x4a0024f8
354 extern reg omap5430_control_core_conf_debug_sel_tst_10;
355 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_11 0x4a0024fc
356 extern reg omap5430_control_core_conf_debug_sel_tst_11;
357 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_12 0x4a002500
358 extern reg omap5430_control_core_conf_debug_sel_tst_12;
359 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_13 0x4a002504
360 extern reg omap5430_control_core_conf_debug_sel_tst_13;
361 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_14 0x4a002508
362 extern reg omap5430_control_core_conf_debug_sel_tst_14;
363 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_15 0x4a00250c
364 extern reg omap5430_control_core_conf_debug_sel_tst_15;
365 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_16 0x4a002510
366 extern reg omap5430_control_core_conf_debug_sel_tst_16;
367 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_17 0x4a002514
368 extern reg omap5430_control_core_conf_debug_sel_tst_17;
369 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_18 0x4a002518
370 extern reg omap5430_control_core_conf_debug_sel_tst_18;
371 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_19 0x4a00251c
372 extern reg omap5430_control_core_conf_debug_sel_tst_19;
373 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_20 0x4a002520
374 extern reg omap5430_control_core_conf_debug_sel_tst_20;
375 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_21 0x4a002524
376 extern reg omap5430_control_core_conf_debug_sel_tst_21;
377 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_22 0x4a002528
378 extern reg omap5430_control_core_conf_debug_sel_tst_22;
379 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_23 0x4a00252c
380 extern reg omap5430_control_core_conf_debug_sel_tst_23;
381 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_24 0x4a002530
382 extern reg omap5430_control_core_conf_debug_sel_tst_24;
383 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_25 0x4a002534
384 extern reg omap5430_control_core_conf_debug_sel_tst_25;
385 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_26 0x4a002538
386 extern reg omap5430_control_core_conf_debug_sel_tst_26;
387 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_27 0x4a00253c
388 extern reg omap5430_control_core_conf_debug_sel_tst_27;
389 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_28 0x4a002540
390 extern reg omap5430_control_core_conf_debug_sel_tst_28;
391 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_29 0x4a002544
392 extern reg omap5430_control_core_conf_debug_sel_tst_29;
393 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_30 0x4a002548
394 extern reg omap5430_control_core_conf_debug_sel_tst_30;
395 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_31 0x4a00254c
396 extern reg omap5430_control_core_conf_debug_sel_tst_31;
397 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_32 0x4a002550
398 extern reg omap5430_control_core_conf_debug_sel_tst_32;
399 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_33 0x4a002554
400 extern reg omap5430_control_core_conf_debug_sel_tst_33;
401 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_34 0x4a002558
402 extern reg omap5430_control_core_conf_debug_sel_tst_34;
403 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_35 0x4a00255c
404 extern reg omap5430_control_core_conf_debug_sel_tst_35;
405 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_36 0x4a002560
406 extern reg omap5430_control_core_conf_debug_sel_tst_36;
407 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_37 0x4a002564
408 extern reg omap5430_control_core_conf_debug_sel_tst_37;
409 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_38 0x4a002568
410 extern reg omap5430_control_core_conf_debug_sel_tst_38;
411 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_39 0x4a00256c
412 extern reg omap5430_control_core_conf_debug_sel_tst_39;
413 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_40 0x4a002570
414 extern reg omap5430_control_core_conf_debug_sel_tst_40;
415 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_41 0x4a002574
416 extern reg omap5430_control_core_conf_debug_sel_tst_41;
417 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_42 0x4a002578
418 extern reg omap5430_control_core_conf_debug_sel_tst_42;
419 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_43 0x4a00257c
420 extern reg omap5430_control_core_conf_debug_sel_tst_43;
421 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_44 0x4a002580
422 extern reg omap5430_control_core_conf_debug_sel_tst_44;
423 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_45 0x4a002584
424 extern reg omap5430_control_core_conf_debug_sel_tst_45;
425 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_46 0x4a002588
426 extern reg omap5430_control_core_conf_debug_sel_tst_46;
427 #define OMAP5430_CONTROL_CORE_CONF_DEBUG_SEL_TST_47 0x4a00258c
428 extern reg omap5430_control_core_conf_debug_sel_tst_47;
429 #define OMAP5430_CTRL_MODULE_CORE_MOD_REGCOUNT 189
430 extern reg *omap5430_ctrl_module_core_mod[OMAP5430_CTRL_MODULE_CORE_MOD_REGCOUNT + 1];
431
432
433 #endif
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