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/*
*
* @Component OMAPCONF
* @Filename mpuss44xx.h
* @Description OMAP4 MPU Subsystem Definitions & Functions
* @Author Patrick Titiano (p-titiano@ti.com)
* @Date 2010
* @Copyright Texas Instruments Incorporated
*
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/


#ifndef __MPUSS44XX_H__
#define __MPUSS44XX_H__

#include <lib.h>

#define OMAP44XX_SCU_BASE 0x48240000

#define OMAP4430_SCU_CONTROL_REGISTER (OMAP44XX_SCU_BASE + 0x0)
#define OMAP4430_SCU_CONFIGURATION_REGISTER (OMAP44XX_SCU_BASE + 0x4)
#define OMAP4430_SCU_CPU_POWER_STATUS (OMAP44XX_SCU_BASE + 0x8)
#define OMAP4430_SCU_INVALIDATE_ALL_REGISTER (OMAP44XX_SCU_BASE + 0xC)
#define OMAP4430_FILTERING_START_ADDRESS_REGISTER (OMAP44XX_SCU_BASE + 0x40)
#define OMAP4430_FILTERING_END_ADDRESS_REGISTER (OMAP44XX_SCU_BASE + 0x44)
#define OMAP4430_SCU_ACCESS_CONTROL_REGISTER (OMAP44XX_SCU_BASE + 0x50)
#define OMAP4430_SCU_SECURE_ACCESS_CONTROL_REGISTER (OMAP44XX_SCU_BASE + 0x54)


#define OMAP44XX_PL310_BASE 0x48242000

#define OMAP44XX_GIC_CPU_BASE 0x48240100

#define OMAP4430_ICPICR (OMAP44XX_GIC_CPU_BASE + 0x0)
#define OMAP4430_ICCIPMR (OMAP44XX_GIC_CPU_BASE + 0x4)
#define OMAP4430_ICCBPR (OMAP44XX_GIC_CPU_BASE + 0x8)
#define OMAP4430_ICCIAR (OMAP44XX_GIC_CPU_BASE + 0xC)
#define OMAP4430_ICCEOIR (OMAP44XX_GIC_CPU_BASE + 0x10)
#define OMAP4430_ICCRPR (OMAP44XX_GIC_CPU_BASE + 0x14)
#define OMAP4430_ICCHPIR (OMAP44XX_GIC_CPU_BASE + 0x18)
#define OMAP4430_ICCABPR (OMAP44XX_GIC_CPU_BASE + 0x1C)
#define OMAP4430_ICCPIIIR (OMAP44XX_GIC_CPU_BASE + 0xFC)


#define OMAP44XX_GIC_DIST_BASE 0x48241000

#define OMAP4430_ENABLE_S (OMAP44XX_GIC_DIST_BASE + 0x0)
#define OMAP4430_IC_TYPE_REG (OMAP44XX_GIC_DIST_BASE + 0x4)
#define OMAP4430_DIST_IDENT_REG (OMAP44XX_GIC_DIST_BASE + 0x8)
#define OMAP4430_INT_SECURITY_31_0 (OMAP44XX_GIC_DIST_BASE + 0x80)
#define OMAP4430_INT_SECURITY_63_32 (OMAP44XX_GIC_DIST_BASE + 0x84)
#define OMAP4430_INT_SECURITY_95_64 (OMAP44XX_GIC_DIST_BASE + 0x88)
#define OMAP4430_INT_SECURITY_127_96 (OMAP44XX_GIC_DIST_BASE + 0x8C)
#define OMAP4430_INT_SECURITY_159_128 (OMAP44XX_GIC_DIST_BASE + 0x90)
#define OMAP4430_ENABLE_SET_31_0 (OMAP44XX_GIC_DIST_BASE + 0x100)
#define OMAP4430_ENABLE_SET_63_32 (OMAP44XX_GIC_DIST_BASE + 0x104)
#define OMAP4430_ENABLE_SET_95_64 (OMAP44XX_GIC_DIST_BASE + 0x108)
#define OMAP4430_ENABLE_SET_127_96 (OMAP44XX_GIC_DIST_BASE + 0x10C)
#define OMAP4430_ENABLE_SET_159_128 (OMAP44XX_GIC_DIST_BASE + 0x110)
#define OMAP4430_ENABLE_CLR_31_0 (OMAP44XX_GIC_DIST_BASE + 0x180)
#define OMAP4430_ENABLE_CLR_63_32 (OMAP44XX_GIC_DIST_BASE + 0x184)
#define OMAP4430_ENABLE_CLR_95_64 (OMAP44XX_GIC_DIST_BASE + 0x188)
#define OMAP4430_ENABLE_CLR_127_96 (OMAP44XX_GIC_DIST_BASE + 0x18C)
#define OMAP4430_ENABLE_CLR_159_128 (OMAP44XX_GIC_DIST_BASE + 0x190)
#define OMAP4430_PENDING_SET_31_0 (OMAP44XX_GIC_DIST_BASE + 0x200)
#define OMAP4430_PENDING_SET_63_32 (OMAP44XX_GIC_DIST_BASE + 0x204)
#define OMAP4430_PENDING_SET_95_64 (OMAP44XX_GIC_DIST_BASE + 0x208)
#define OMAP4430_PENDING_SET_127_96 (OMAP44XX_GIC_DIST_BASE + 0x20C)
#define OMAP4430_PENDING_SET_159_128 (OMAP44XX_GIC_DIST_BASE + 0x210)
#define OMAP4430_PENDING_CLR_31_0 (OMAP44XX_GIC_DIST_BASE + 0x280)
#define OMAP4430_PENDING_CLR_63_32 (OMAP44XX_GIC_DIST_BASE + 0x284)
#define OMAP4430_PENDING_CLR_95_64 (OMAP44XX_GIC_DIST_BASE + 0x288)
#define OMAP4430_PENDING_CLR_127_96 (OMAP44XX_GIC_DIST_BASE + 0x28C)
#define OMAP4430_PENDING_CLR_159_128 (OMAP44XX_GIC_DIST_BASE + 0x290)
#define OMAP4430_ACTIVE_STATUS_31_0 (OMAP44XX_GIC_DIST_BASE + 0x300)
#define OMAP4430_ACTIVE_STATUS_63_32 (OMAP44XX_GIC_DIST_BASE + 0x304)
#define OMAP4430_ACTIVE_STATUS_95_64 (OMAP44XX_GIC_DIST_BASE + 0x308)
#define OMAP4430_ACTIVE_STATUS_127_96 (OMAP44XX_GIC_DIST_BASE + 0x30C)
#define OMAP4430_ACTIVE_STATUS_159_128 (OMAP44XX_GIC_DIST_BASE + 0x310)
#define OMAP4430_PRIORITY_LEVEL_3_0 (OMAP44XX_GIC_DIST_BASE + 0x400)
#define OMAP4430_PRIORITY_LEVEL_7_4 (OMAP44XX_GIC_DIST_BASE + 0x404)
#define OMAP4430_PRIORITY_LEVEL_11_8 (OMAP44XX_GIC_DIST_BASE + 0x408)
#define OMAP4430_PRIORITY_LEVEL_15_12 (OMAP44XX_GIC_DIST_BASE + 0x40C)
#define OMAP4430_PRIORITY_LEVEL_31_28 (OMAP44XX_GIC_DIST_BASE + 0x41C)
#define OMAP4430_PRIORITY_LEVEL_35_32 (OMAP44XX_GIC_DIST_BASE + 0x420)
#define OMAP4430_PRIORITY_LEVEL_39_36 (OMAP44XX_GIC_DIST_BASE + 0x424)
#define OMAP4430_PRIORITY_LEVEL_43_40 (OMAP44XX_GIC_DIST_BASE + 0x428)
#define OMAP4430_PRIORITY_LEVEL_47_44 (OMAP44XX_GIC_DIST_BASE + 0x42C)
#define OMAP4430_PRIORITY_LEVEL_51_48 (OMAP44XX_GIC_DIST_BASE + 0x430)
#define OMAP4430_PRIORITY_LEVEL_55_52 (OMAP44XX_GIC_DIST_BASE + 0x434)
#define OMAP4430_PRIORITY_LEVEL_59_56 (OMAP44XX_GIC_DIST_BASE + 0x438)
#define OMAP4430_PRIORITY_LEVEL_63_60 (OMAP44XX_GIC_DIST_BASE + 0x43C)
#define OMAP4430_PRIORITY_LEVEL_67_64 (OMAP44XX_GIC_DIST_BASE + 0x440)
#define OMAP4430_PRIORITY_LEVEL_71_68 (OMAP44XX_GIC_DIST_BASE + 0x444)
#define OMAP4430_PRIORITY_LEVEL_75_72 (OMAP44XX_GIC_DIST_BASE + 0x448)
#define OMAP4430_PRIORITY_LEVEL_79_76 (OMAP44XX_GIC_DIST_BASE + 0x44C)
#define OMAP4430_PRIORITY_LEVEL_83_80 (OMAP44XX_GIC_DIST_BASE + 0x450)
#define OMAP4430_PRIORITY_LEVEL_87_84 (OMAP44XX_GIC_DIST_BASE + 0x454)
#define OMAP4430_PRIORITY_LEVEL_91_88 (OMAP44XX_GIC_DIST_BASE + 0x458)
#define OMAP4430_PRIORITY_LEVEL_95_92 (OMAP44XX_GIC_DIST_BASE + 0x45C)
#define OMAP4430_PRIORITY_LEVEL_99_96 (OMAP44XX_GIC_DIST_BASE + 0x460)
#define OMAP4430_PRIORITY_LEVEL_103_100 (OMAP44XX_GIC_DIST_BASE + 0x464)
#define OMAP4430_PRIORITY_LEVEL_107_104 (OMAP44XX_GIC_DIST_BASE + 0x468)
#define OMAP4430_PRIORITY_LEVEL_111_108 (OMAP44XX_GIC_DIST_BASE + 0x46C)
#define OMAP4430_PRIORITY_LEVEL_115_112 (OMAP44XX_GIC_DIST_BASE + 0x470)
#define OMAP4430_PRIORITY_LEVEL_119_116 (OMAP44XX_GIC_DIST_BASE + 0x474)
#define OMAP4430_PRIORITY_LEVEL_123_120 (OMAP44XX_GIC_DIST_BASE + 0x478)
#define OMAP4430_PRIORITY_LEVEL_127_124 (OMAP44XX_GIC_DIST_BASE + 0x47C)
#define OMAP4430_PRIORITY_LEVEL_131_128 (OMAP44XX_GIC_DIST_BASE + 0x480)
#define OMAP4430_PRIORITY_LEVEL_135_132 (OMAP44XX_GIC_DIST_BASE + 0x484)
#define OMAP4430_PRIORITY_LEVEL_139_136 (OMAP44XX_GIC_DIST_BASE + 0x488)
#define OMAP4430_PRIORITY_LEVEL_143_140 (OMAP44XX_GIC_DIST_BASE + 0x48C)
#define OMAP4430_PRIORITY_LEVEL_147_144 (OMAP44XX_GIC_DIST_BASE + 0x490)
#define OMAP4430_PRIORITY_LEVEL_151_148 (OMAP44XX_GIC_DIST_BASE + 0x494)
#define OMAP4430_PRIORITY_LEVEL_155_152 (OMAP44XX_GIC_DIST_BASE + 0x498)
#define OMAP4430_PRIORITY_LEVEL_159_156 (OMAP44XX_GIC_DIST_BASE + 0x49C)
#define OMAP4430_SPI_TARGET_3_0 (OMAP44XX_GIC_DIST_BASE + 0x800)
#define OMAP4430_SPI_TARGET_7_4 (OMAP44XX_GIC_DIST_BASE + 0x804)
#define OMAP4430_SPI_TARGET_11_8 (OMAP44XX_GIC_DIST_BASE + 0x808)
#define OMAP4430_SPI_TARGET_15_12 (OMAP44XX_GIC_DIST_BASE + 0x80C)
#define OMAP4430_SPI_TARGET_31_28 (OMAP44XX_GIC_DIST_BASE + 0x81C)
#define OMAP4430_SPI_TARGET_35_32 (OMAP44XX_GIC_DIST_BASE + 0x820)
#define OMAP4430_SPI_TARGET_39_36 (OMAP44XX_GIC_DIST_BASE + 0x824)
#define OMAP4430_SPI_TARGET_43_40 (OMAP44XX_GIC_DIST_BASE + 0x828)
#define OMAP4430_SPI_TARGET_47_44 (OMAP44XX_GIC_DIST_BASE + 0x82C)
#define OMAP4430_SPI_TARGET_51_48 (OMAP44XX_GIC_DIST_BASE + 0x830)
#define OMAP4430_SPI_TARGET_55_52 (OMAP44XX_GIC_DIST_BASE + 0x834)
#define OMAP4430_SPI_TARGET_59_56 (OMAP44XX_GIC_DIST_BASE + 0x838)
#define OMAP4430_SPI_TARGET_63_60 (OMAP44XX_GIC_DIST_BASE + 0x83C)
#define OMAP4430_SPI_TARGET_67_64 (OMAP44XX_GIC_DIST_BASE + 0x840)
#define OMAP4430_SPI_TARGET_71_68 (OMAP44XX_GIC_DIST_BASE + 0x844)
#define OMAP4430_SPI_TARGET_75_72 (OMAP44XX_GIC_DIST_BASE + 0x848)
#define OMAP4430_SPI_TARGET_79_76 (OMAP44XX_GIC_DIST_BASE + 0x84C)
#define OMAP4430_SPI_TARGET_83_80 (OMAP44XX_GIC_DIST_BASE + 0x850)
#define OMAP4430_SPI_TARGET_87_84 (OMAP44XX_GIC_DIST_BASE + 0x854)
#define OMAP4430_SPI_TARGET_91_88 (OMAP44XX_GIC_DIST_BASE + 0x858)
#define OMAP4430_SPI_TARGET_95_92 (OMAP44XX_GIC_DIST_BASE + 0x85C)
#define OMAP4430_SPI_TARGET_99_96 (OMAP44XX_GIC_DIST_BASE + 0x860)
#define OMAP4430_SPI_TARGET_103_100 (OMAP44XX_GIC_DIST_BASE + 0x864)
#define OMAP4430_SPI_TARGET_107_104 (OMAP44XX_GIC_DIST_BASE + 0x868)
#define OMAP4430_SPI_TARGET_111_108 (OMAP44XX_GIC_DIST_BASE + 0x86C)
#define OMAP4430_SPI_TARGET_115_112 (OMAP44XX_GIC_DIST_BASE + 0x870)
#define OMAP4430_SPI_TARGET_119_116 (OMAP44XX_GIC_DIST_BASE + 0x874)
#define OMAP4430_SPI_TARGET_123_120 (OMAP44XX_GIC_DIST_BASE + 0x878)
#define OMAP4430_SPI_TARGET_127_124 (OMAP44XX_GIC_DIST_BASE + 0x87C)
#define OMAP4430_SPI_TARGET_131_128 (OMAP44XX_GIC_DIST_BASE + 0x880)
#define OMAP4430_SPI_TARGET_135_132 (OMAP44XX_GIC_DIST_BASE + 0x884)
#define OMAP4430_SPI_TARGET_139_136 (OMAP44XX_GIC_DIST_BASE + 0x888)
#define OMAP4430_SPI_TARGET_143_140 (OMAP44XX_GIC_DIST_BASE + 0x88C)
#define OMAP4430_SPI_TARGET_147_144 (OMAP44XX_GIC_DIST_BASE + 0x890)
#define OMAP4430_SPI_TARGET_151_148 (OMAP44XX_GIC_DIST_BASE + 0x894)
#define OMAP4430_SPI_TARGET_155_152 (OMAP44XX_GIC_DIST_BASE + 0x898)
#define OMAP4430_SPI_TARGET_159_156 (OMAP44XX_GIC_DIST_BASE + 0x89C)
#define OMAP4430_INT_CONFIG_15_0 (OMAP44XX_GIC_DIST_BASE + 0xC00)
#define OMAP4430_INT_CONFIG_31_16 (OMAP44XX_GIC_DIST_BASE + 0xC04)
#define OMAP4430_INT_CONFIG_47_32 (OMAP44XX_GIC_DIST_BASE + 0xC08)
#define OMAP4430_INT_CONFIG_63_48 (OMAP44XX_GIC_DIST_BASE + 0xC0C)
#define OMAP4430_INT_CONFIG_79_64 (OMAP44XX_GIC_DIST_BASE + 0xC10)
#define OMAP4430_INT_CONFIG_95_80 (OMAP44XX_GIC_DIST_BASE + 0xC14)
#define OMAP4430_INT_CONFIG_111_96 (OMAP44XX_GIC_DIST_BASE + 0xC18)
#define OMAP4430_INT_CONFIG_127_112 (OMAP44XX_GIC_DIST_BASE + 0xC1C)
#define OMAP4430_INT_CONFIG_143_128 (OMAP44XX_GIC_DIST_BASE + 0xC20)
#define OMAP4430_INT_CONFIG_159_144 (OMAP44XX_GIC_DIST_BASE + 0xC24)
#define OMAP4430_PPI_STATUS (OMAP44XX_GIC_DIST_BASE + 0xD00)
#define OMAP4430_SPI_STATUS_31_0 (OMAP44XX_GIC_DIST_BASE + 0xD04)
#define OMAP4430_SPI_STATUS_63_32 (OMAP44XX_GIC_DIST_BASE + 0xD08)
#define OMAP4430_SPI_STATUS_95_64 (OMAP44XX_GIC_DIST_BASE + 0xD0C)
#define OMAP4430_SPI_STATUS_127_96 (OMAP44XX_GIC_DIST_BASE + 0xD10)
#define OMAP4430_SGI_TRIGGER (OMAP44XX_GIC_DIST_BASE + 0xF00)
#define OMAP4430_PERIPH_ID_4 (OMAP44XX_GIC_DIST_BASE + 0xFD0)
#define OMAP4430_PERIPH_ID_0 (OMAP44XX_GIC_DIST_BASE + 0xFE0)
#define OMAP4430_PERIPH_ID_1 (OMAP44XX_GIC_DIST_BASE + 0xFE4)
#define OMAP4430_PERIPH_ID_2 (OMAP44XX_GIC_DIST_BASE + 0xFE8)
#define OMAP4430_PERIPH_ID_3 (OMAP44XX_GIC_DIST_BASE + 0xFEC)
#define OMAP4430_COMPONENT_ID_0 (OMAP44XX_GIC_DIST_BASE + 0xFF0)
#define OMAP4430_COMPONENT_ID_1 (OMAP44XX_GIC_DIST_BASE + 0xFF4)
#define OMAP4430_COMPONENT_ID_2 (OMAP44XX_GIC_DIST_BASE + 0xFF8)
#define OMAP4430_COMPONENT_ID_3 (OMAP44XX_GIC_DIST_BASE + 0xFFC)


#define OMAP44XX_WKG_BASE 0x48281000

#define OMAP4430_WKG_CONTROL_0 (OMAP44XX_WKG_BASE + 0x0)
#define OMAP4430_WKG_ENB_A_0 (OMAP44XX_WKG_BASE + 0x10)
#define OMAP4430_WKG_ENB_B_0 (OMAP44XX_WKG_BASE + 0x14)
#define OMAP4430_WKG_ENB_C_0 (OMAP44XX_WKG_BASE + 0x18)
#define OMAP4430_WKG_ENB_D_0 (OMAP44XX_WKG_BASE + 0x1C)
#define OMAP4430_WKG_ENB_E_0 (OMAP44XX_WKG_BASE + 0x20)
#define OMAP4430_WKG_CONTROL_1 (OMAP44XX_WKG_BASE + 0x400)
#define OMAP4430_WKG_ENB_A_1 (OMAP44XX_WKG_BASE + 0x410)
#define OMAP4430_WKG_ENB_B_1 (OMAP44XX_WKG_BASE + 0x414)
#define OMAP4430_WKG_ENB_C_1 (OMAP44XX_WKG_BASE + 0x418)
#define OMAP4430_WKG_ENB_D_1 (OMAP44XX_WKG_BASE + 0x41C)
#define OMAP4430_WKG_ENB_E_1 (OMAP44XX_WKG_BASE + 0x420)
#define OMAP4430_AUX_CORE_BOOT_0 (OMAP44XX_WKG_BASE + 0x800)
#define OMAP4430_AUX_CORE_BOOT_1 (OMAP44XX_WKG_BASE + 0x804)


#define OMAP44XX_SCM_BASE 0x48280000

#define OMAP4430_TZ_LOCKING (OMAP44XX_SCM_BASE + 0x4)
#define OMAP4430_SSM_SECMEM_STATUS (OMAP44XX_SCM_BASE + 0x8)
#define OMAP4430_PLATFORM_STATUS (OMAP44XX_SCM_BASE + 0x10)
#define OMAP4430_SDP_PAGE_ACT (OMAP44XX_SCM_BASE + 0x14)
#define OMAP4430_SDP_PAGE_RD (OMAP44XX_SCM_BASE + 0x18)
#define OMAP4430_SDP_PAGE_WR (OMAP44XX_SCM_BASE + 0x1C)
#define OMAP4430_SDP_LRU_LIST_HIGH (OMAP44XX_SCM_BASE + 0x20)
#define OMAP4430_SDP_LRU_LIST_LOW (OMAP44XX_SCM_BASE + 0x24)


typedef enum {
L2CC44XX_EVT_CNT_DISABLED = 0x0,
L2CC44XX_EVT_CNT_CO = 0x1,
L2CC44XX_EVT_CNT_DRHIT = 0x2,
L2CC44XX_EVT_CNT_DRREQ = 0x3,
L2CC44XX_EVT_CNT_DWHIT = 0x4,
L2CC44XX_EVT_CNT_DWREQ = 0x5,
L2CC44XX_EVT_CNT_DWTREQ = 0x6,
L2CC44XX_EVT_CNT_IRHIT = 0x7,
L2CC44XX_EVT_CNT_IRREQ = 0x8,
L2CC44XX_EVT_CNT_WA = 0x9,
L2CC44XX_EVT_CNT_IPFALLOC = 0xA,
L2CC44XX_EVT_CNT_EPFHIT = 0xB,
L2CC44XX_EVT_CNT_EPFALLOC = 0xC,
L2CC44XX_EVT_CNT_SRRCVD = 0xD,
L2CC44XX_EVT_CNT_SRCONF = 0xE,
L2CC44XX_EVT_CNT_EPFRCVD = 0xF,
L2CC44XX_EVT_CNT_MAX = 0x11
} l2cc44xx_event_cnt_ids;


static const reg_table omap4_mpuss_pl310_reg_table[] = {
/* Init MPUSS PL310 registers table */
{"CACHEID", OMAP44XX_PL310_BASE + 0x0},
{"CACHETYPE", OMAP44XX_PL310_BASE + 0x4},
{"CONTROL", OMAP44XX_PL310_BASE + 0x100},
{"AUXILLARY_CONTROL", OMAP44XX_PL310_BASE + 0x104},
{"TAG_RAM_LATENCY_CONTROL_REGISTER", OMAP44XX_PL310_BASE + 0x108},
{"DATA_RAM_LATENCY_CONTROL_REGISTER", OMAP44XX_PL310_BASE + 0x10C},
{"EVENT_COUNTER_CONTROL", OMAP44XX_PL310_BASE + 0x200},
{"EVENT_COUNTER1_CONFIGURATION", OMAP44XX_PL310_BASE + 0x204},
{"EVENT_COUNTER0_CONFIGURATION", OMAP44XX_PL310_BASE + 0x208},
{"EVENT_COUNTER1_VALUE", OMAP44XX_PL310_BASE + 0x20C},
{"EVENT_COUNTER0_VALUE", OMAP44XX_PL310_BASE + 0x210},
{"INTERRUPT_MASK", OMAP44XX_PL310_BASE + 0x214},
{"MASKED_INTERRUPT_STATUS", OMAP44XX_PL310_BASE + 0x218},
{"RAW_INTERRUPT_STATUS", OMAP44XX_PL310_BASE + 0x21C},
{"INTERRUPT_CLEAR", OMAP44XX_PL310_BASE + 0x220},
{"CACHE_SYNC", OMAP44XX_PL310_BASE + 0x730},
{"INVALIDATE_LINE_BY_PA", OMAP44XX_PL310_BASE + 0x770},
{"INVALIDATE_BY_WAY", OMAP44XX_PL310_BASE + 0x77C},
{"CLEAN_LINE_BY_PA", OMAP44XX_PL310_BASE + 0x7B0},
{"CLEAN_LINE_BY_INDEX", OMAP44XX_PL310_BASE + 0x7B8},
{"CLEAN_BY_WAY", OMAP44XX_PL310_BASE + 0x7BC},
{"CLEAN_AND_INVALIDATE_LINE_BY_PA", OMAP44XX_PL310_BASE + 0x7F0},
{"CLEAN_AND_INVALIDATE_LINE_BY_INDEX", OMAP44XX_PL310_BASE + 0x7F8},
{"CLEAN_AND_INVALIDATE_BY_WAY", OMAP44XX_PL310_BASE + 0x7FC},
{"DATA_LOCKDOWN_0_BY_WAY", OMAP44XX_PL310_BASE + 0x900},
{"INSTRUCTION_LOCKDOWN_0_BY_WAY", OMAP44XX_PL310_BASE + 0x904},
{"DATA_LOCKDOWN_1_BY_WAY", OMAP44XX_PL310_BASE + 0x908},
{"INSTRUCTION_LOCKDOWN_1_BY_WAY", OMAP44XX_PL310_BASE + 0x90C},
{"DATA_LOCKDOWN_2_BY_WAY", OMAP44XX_PL310_BASE + 0x910},
{"INSTRUCTION_LOCKDOWN_2_BY_WAY", OMAP44XX_PL310_BASE + 0x914},
{"DATA_LOCKDOWN_3_BY_WAY", OMAP44XX_PL310_BASE + 0x918},
{"INSTRUCTION_LOCKDOWN_3_BY_WAY", OMAP44XX_PL310_BASE + 0x91C},
{"DATA_LOCKDOWN_4_BY_WAY", OMAP44XX_PL310_BASE + 0x920},
{"INSTRUCTION_LOCKDOWN_4_BY_WAY", OMAP44XX_PL310_BASE + 0x924},
{"DATA_LOCKDOWN_5_BY_WAY", OMAP44XX_PL310_BASE + 0x928},
{"INSTRUCTION_LOCKDOWN_5_BY_WAY", OMAP44XX_PL310_BASE + 0x92C},
{"DATA_LOCKDOWN_6_BY_WAY", OMAP44XX_PL310_BASE + 0x930},
{"INSTRUCTION_LOCKDOWN_6_BY_WAY", OMAP44XX_PL310_BASE + 0x934},
{"DATA_LOCKDOWN_7_BY_WAY", OMAP44XX_PL310_BASE + 0x938},
{"INSTRUCTION_LOCKDOWN_7_BY_WAY", OMAP44XX_PL310_BASE + 0x93C},
{"LOCKDOWN_BY_LINE_ENABLE", OMAP44XX_PL310_BASE + 0x950},
{"UNLOCK_ALL_LINES_BY_WAY", OMAP44XX_PL310_BASE + 0x954},
{"ADDRESS_FILTERING_START", OMAP44XX_PL310_BASE + 0xC00},
{"ADDRESS_FILTERING_END", OMAP44XX_PL310_BASE + 0xC04},
{"DEBUG_CONTROL_REGISTER", OMAP44XX_PL310_BASE + 0xF40},
{"END", 0} };


static const char omap44xx_mpu_irq_names[160][25] = {
"SGI_0",
"SGI_1",
"SGI_2",
"SGI_3",
"SGI_4",
"SGI_5",
"SGI_6",
"SGI_7",
"SGI_8",
"SGI_9",
"SGI_10",
"SGI_11",
"SGI_12",
"SGI_13",
"SGI_14",
"SGI_15",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Legacy FIQ",
"Private Timer",
"Private Watchdog",
"Legacy IRQ",
"PL310_IRQ",
"CTIIRQ[0]",
"CTIIRQ[1]",
"Reserved",
"ELM_IRQ",
"Reserved",
"Reserved",
"SYS.IRQ1n",
"SECURITY_EVENTS_IRQ",
"L3_DBG_IRQ",
"L3_APP_IRQ",
"PRCM_MPU_IRQ",
"SDMA_IRQ0",
"SDMA_IRQ1",
"SDMA_IRQ2",
"SDMA_IRQ3",
"MCBSP4_IRQ",
"MCBSP1_IRQ",
"SR_MCU_IRQ",
"SR_CORE_IRQ",
"GPMC_IRQ",
"vGFX_IRQ",
"MCBSP2_IRQ",
"MCBSP3_IRQ",
"ISS_IRQ[5]",
"DSS_DISPC_IRQ",
"MAIL_U0_MPU_IRQ",
"C2C_SSCM_IRQ0",
"DSP_MMU_IRQ",
"GPIO1_MPU_IRQ",
"GPIO2_MPU_IRQ",
"GPIO3_MPU_IRQ",
"GPIO4_MPU_IRQ",
"GPIO5_MPU_IRQ",
"GPIO6_MPU_IRQ",
"Reserved",
"WDT3_IRQ",
"GPT1_IRQ",
"GPT2_IRQ",
"GPT3_IRQ",
"GPT4_IRQ",
"GPT5_IRQ",
"GPT6_IRQ",
"GPT7_IRQ",
"GPT8_IRQ",
"GPT9_IRQ",
"GPT10_IRQ",
"GPT11_IRQ",
"SPI4_IRQ",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"DSS_DSI1_IRQ",
"Reserved",
"Reserved",
"I2C1_IRQ",
"I2C2_IRQ",
"HDQ_IRQ",
"MMC5_IRQ",
"Reserved",
"I2C3_IRQ",
"I2C4_IRQ",
"Reserved",
"Reserved",
"SPI1_IRQ",
"SPI2_IRQ",
"HSI_P1_MPU_IRQ",
"HSI_P2_MPU_IRQ",
"FDIF_IRQ3",
"UART4_IRQ",
"HSI_DMA_MPU_IRQ",
"UART1_IRQ",
"UART2_IRQ",
"UART3_IRQ",
"PBIAS_IRQ",
"OHCI_IRQ",
"EHCI_IRQ",
"TLL_IRQ",
"Reserved",
"WDT2_IRQ",
"DES_IRQ_S",
"DES_IRQ_P",
"MMC1_IRQ",
"DSS_DSI2_IRQ",
"Reserved",
"MMC2_IRQ",
"MPU_ICR_IRQ",
"C2C_SSCM_IRQ1",
"FSUSB_IRQ",
"FSUSB_SMI_IRQ",
"SPI3_IRQ",
"HS_USB_MC_NINT",
"HS_USB_DMA_NINT",
"MMC3_IRQ",
"Reserved",
"MMC4_IRQ",
"SLIMBUS1_IRQ",
"SLIMBUS2_IRQ",
"ABE_MPU_IRQ",
"MPU_M3_MMU_IRQ",
"DSS_HDMI_IRQ",
"SR_IVA_IRQ",
"IVA-HD_POSYNCITRPEND[1]",
"IVA-HD_POSYNCITRPEND[0]",
"Reserved",
"Reserved",
"IVA-HD_POMBINTRPEND[0]",
"McASP1_ARINT",
"McASP1_AXINT",
"EMIF4_1_IRQ",
"EMIF4_2_IRQ",
"McPDM_IRQ",
"DMM_IRQ",
"DMIC_IRQ",
"CDMA_IRQ0",
"CDMA_IRQ1",
"CDMA_IRQ2",
"CDMA_IRQ3",
"SYS.IRQ2n",
"KBD_CTL_IRQ",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved"
};


static const name_desc_val_table l2cc_event_counters_table[] = {
/* Name (<= 50chars), Description (<= 128 chars.), Value */
{"DISABLED", "Counters disabled.", L2CC44XX_EVT_CNT_DISABLED},
{"CO", "Count Eviction (CastOUT) of a line from the L2 cache.", L2CC44XX_EVT_CNT_CO},
{"DRHIT", "Count Data read hit.", L2CC44XX_EVT_CNT_DRHIT},
{"DRREQ", "Count Data read lookup to the L2 cache.", L2CC44XX_EVT_CNT_DRREQ},
{"DWHIT", "Count Data write hit.", L2CC44XX_EVT_CNT_DWHIT},
{"DWREQ", "Count Data write lookup to the L2 cache.", L2CC44XX_EVT_CNT_DWREQ},
{"DWTREQ", "Count Data write lookup with Write-Through attribute.", L2CC44XX_EVT_CNT_DWTREQ},
{"IRHIT", "Count Instruction read hit in the L2 cache.", L2CC44XX_EVT_CNT_IRHIT},
{"IRREQ", "Count Instruction read lookup.", L2CC44XX_EVT_CNT_IRREQ},
{"WA", "Count Allocation caused by write (w/ write-allocate) miss.", L2CC44XX_EVT_CNT_WA},
{"IPFALLOC", "Count Allocation of a prefetch to the L2 cache.", L2CC44XX_EVT_CNT_IPFALLOC},
{"EPFHIT", "Count Prefetch hint hits in the L2 cache.", L2CC44XX_EVT_CNT_EPFHIT},
{"EPFALLOC", "Count Prefetch hint allocated into the L2 cache.", L2CC44XX_EVT_CNT_EPFALLOC},
{"SRRCVD", "Count Speculative read received.", L2CC44XX_EVT_CNT_SRRCVD},
{"SRCONF", "Count Speculative read confirmed.", L2CC44XX_EVT_CNT_SRCONF},
{"EPFRCVD", "Count Prefetch hint received.", L2CC44XX_EVT_CNT_EPFRCVD},
{"END", "END of Table.", 0} };


int mpuss44xx_scu_dump(void);
int mpuss44xx_scu_config_show(void);
int mpuss44xx_gic_dump(void);
int mpuss44xx_gic_config_show(void);
int mpuss44xx_pl310_dump(void);
int mpuss44xx_wkg_dump(void);
int mpuss44xx_scm_dump(void);
int mpuss44xx_name2addr(char *name, unsigned int *addr);


/* DEPRECATED, DO NOT USE ANYMORE */
int mpuss44xx_main(int argc, char *argv[]);


#endif
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