A 32-bit RISC-V processor for mriscv project
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ALU
DECO_INSTR
FSM
IRQ
MEMORY_INTERFACE
MULT
REG_FILE
UTILITIES
firmware
tests
.gitignore
LICENSE
Makefile
README.md
mriscvcore.v
mriscvcore_tb.v
riscv_core.png
seecode.sh

README.md

mriscvcore

./riscv_core.png