From 935ba831ed35e237654d9f3fb2a5454f776ef0db Mon Sep 17 00:00:00 2001 From: "White, Paul" Date: Wed, 7 Dec 2022 01:44:19 -0800 Subject: [PATCH 01/22] add fpga_template source code from add-empty-design branch --- DirectProgramming/DPC++FPGA/README.md | 3 +- .../experimental/fpga_template/CMakeLists.txt | 20 ++ .../experimental/fpga_template/README.md | 214 ++++++++++++++++++ .../experimental/fpga_template/sample.json | 94 ++++++++ .../fpga_template/src/CMakeLists.txt | 134 +++++++++++ .../fpga_template/src/fpga_template.cpp | 94 ++++++++ 6 files changed, 558 insertions(+), 1 deletion(-) create mode 100644 DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/CMakeLists.txt create mode 100644 DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md create mode 100644 DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/sample.json create mode 100644 DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt create mode 100644 DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/fpga_template.cpp diff --git a/DirectProgramming/DPC++FPGA/README.md b/DirectProgramming/DPC++FPGA/README.md index 49b221e71f..6664fcddd7 100644 --- a/DirectProgramming/DPC++FPGA/README.md +++ b/DirectProgramming/DPC++FPGA/README.md @@ -56,6 +56,7 @@ flowchart LR |:--- |:--- |:--- | [fpga_compile](Tutorials/GettingStarted/fpga_compile) | [Tutorials/GettingStarted](Tutorials/GettingStarted) | How and why compiling SYCL* code for FPGA differs from CPU or GPU
FPGA device image types and when to use them.
The compile options used to target FPGA | [fast_recompile](Tutorials/GettingStarted/fast_recompile) | [Tutorials/GettingStarted](Tutorials/GettingStarted) | Why to separate host and device code compilation in your FPGA project
How to use the `-reuse-exe` and device link.
Which method to choose for your project +| [fpga_template](Tutorials/GettingStarted/fpga_template) | [Tutorials/GettingStarted](Tutorials/GettingStarted) | Showcases the CMake build system that is used in other code samples, and serves as a template that you can re-use in your own designs. #### Tier 2: Explore the Fundamentals @@ -92,7 +93,7 @@ flowchart LR | [pipes](Tutorials/Features/pipes) | [Tutorials/Features](Tutorials/Features) | The basics of using SYCL*-compliant pipes extension for FPGA
How to declare and use pipes | [printf](Tutorials/Features/printf) | [Tutorials/DesignPatterns](Tutorials/DesignPatterns) | How to declare and use `printf` in program -#### Tier 3: Explore the Advances Techniques +#### Tier 3: Explore the Advanced Techniques ```mermaid flowchart LR diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/CMakeLists.txt new file mode 100644 index 0000000000..831a75579a --- /dev/null +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/CMakeLists.txt @@ -0,0 +1,20 @@ +if(UNIX) + # Direct CMake to use icpx rather than the default C++ compiler/linker + set(CMAKE_CXX_COMPILER icpx) +else() # Windows + # Force CMake to use icpx rather than the default C++ compiler/linker + # (needed on Windows only) + include (CMakeForceCompiler) + CMAKE_FORCE_CXX_COMPILER (icx-cl IntelDPCPP) + include (Platform/Windows-Clang) +endif() + +cmake_minimum_required (VERSION 3.4) + +project(FPGATemplate CXX) + +set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) +set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) +set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) + +add_subdirectory (src) \ No newline at end of file diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md new file mode 100644 index 0000000000..cb6ee37eaf --- /dev/null +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md @@ -0,0 +1,214 @@ +# FPGA Template + +This project serves as a template for Intel® oneAPI FPGA designs. + +| Optimized for | Description +|:--- |:--- +| OS | Linux* Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 +| Hardware | Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX)
Intel® FPGA 3rd party / custom platforms with oneAPI support (and SYCL USM support) Note: Intel® FPGA PAC hardware is only compatible with Ubuntu 18.04* +| Software | Intel® oneAPI DPC++ Compiler
Intel® Quartus Prime Pro Edition +| What you will learn | Best practices for creating and managing a oneAPI FPGA project +| Time to complete | 10 minutes + +***Notice**: SYCL Unified Shared Memory (USM) host allocations (and therefore the code in this tutorial) are only supported by Board Support Packages (BSPs) with USM support (e.g. the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) `intel_s10sx_pac:pac_s10_usm`)* + +## Purpose + +Use this project as a starting point when you build designs for the Intel® oneAPI FPGA compiler. It includes a CMake build system to automate selecting the various command-line flags for the oneAPI FPGA compiler, and a simple single-source design to serve as an example. You can customize the build flags by modifying the top part of `src/CMakeLists.txt`: if you want to pass additional flags to the Intel® oneAPI FPGA compiler, you can change the `USER_FLAGS` and `USER_HARDWARE_FLAGS` variables defined in `src/CMakeLists.txt`. + +> **Note**: The code sample in this design only uses USM for improved code simplicity as compared with buffers/accessors. The included CMake build system can also be used for designs that do not use USM. + +| Variable | Description | +|:--- |:--- +| `USER_HARDWARE_FLAGS` | These flags apply only to flows that generate FPGA hardware (i.e. report, simulation, hardware). You can specify flags such as `-Xsclock` or `-Xshyper-optimized-handshaking=off` | +| `USER_FLAGS` | These flags apply to all flows, including emulation. You can specify flags such as `-v` or define macros such as `-DYOUR_OWN_MACRO=3` | + +```bash +############################################################################### +### Customize these build variables +############################################################################### +set(SOURCE_FILE fpga_template.cpp) +set(TARGET_NAME fpga_template) + +# Use cmake -DFPGA_DEVICE=: to choose a +# different device. Here are a few device examples (this list is not +# exhaustive): +# intel_s10sx_pac:pac_s10 +# intel_s10sx_pac:pac_s10_usm +# intel_a10gx_pac:pac_a10 +# Note that depending on your installation, you may need to specify the full +# path to the board support package (BSP), this usually is in your install +# folder. +# +# You can also specify a device family (E.g. "Arria10" or "Stratix10") or a +# specific part number (E.g. "10AS066N3F40E2SG") to generate a standalone IP. +if(NOT DEFINED FPGA_DEVICE) + set(FPGA_DEVICE "intel_s10sx_pac:pac_s10_usm") +endif() + +# Use cmake -DUSER_HARDWARE_FLAGS= to set extra flags for FPGA backend +# compilation. +set(USER_HARDWARE_FLAGS "${USER_HARDWARE_FLAGS}") + +# Use cmake -DUSER_FLAGS= to set extra flags for general compilation. +set(USER_FLAGS "${USER_FLAGS}") +``` + +Everything below this in the `src/CMakeLists.txt` is necessary for selecting the compiler flags that are necessary to support the build targets specified below, and should not need to be modified. + +## Building the `fpga_template` Tutorial + +> **Note**: If you have not already done so, set up your CLI +> environment by sourcing the `setvars` script located in +> the root of your oneAPI installation. +> +> Linux*: +> - For system wide installations: `/opt/intel/oneapi/setvars.sh` +> - For private installations: `~/intel/oneapi/setvars.sh` +> +> Windows*: +> - `C:\Program Files(x86)\Intel\oneAPI\setvars.bat` +> - For PowerShell*, use the following command: `cmd.exe "/K" '"C:\Program Files (x86)\Intel\oneAPI\setvars.bat" && powershell'` +> +>For more information on environment variables, see **Use the setvars Script** for [Linux or macOS](https://www.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/oneapi-development-environment-setup/use-the-setvars-script-with-linux-or-macos.html), or [Windows](https://www.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/oneapi-development-environment-setup/use-the-setvars-script-with-windows.html). + +### Running Samples in Intel® DevCloud +If running a sample in the Intel® DevCloud, remember that you must specify the type of compute node and whether to run in batch or interactive mode. Compiles to FPGA are only supported on fpga_compile nodes. Executing programs on FPGA hardware is only supported on fpga_runtime nodes of the appropriate type, such as fpga_runtime:arria10 or fpga_runtime:stratix10. Neither compiling nor executing programs on FPGA hardware are supported on the login nodes. For more information, see the Intel® oneAPI Base Toolkit Get Started Guide ([https://devcloud.intel.com/oneapi/documentation/base-toolkit/](https://devcloud.intel.com/oneapi/documentation/base-toolkit/)). +When compiling for FPGA hardware, it is recommended to increase the job timeout to 12h. +### Using Visual Studio Code* (Optional) +You can use Visual Studio Code (VS Code) extensions to set your environment, create launch configurations, +and browse and download samples. +The basic steps to build and run a sample using VS Code include: + - Download a sample using the extension **Code Sample Browser for Intel® oneAPI Toolkits**. + - Configure the oneAPI environment with the extension **Environment Configurator for Intel® oneAPI Toolkits**. + - Open a Terminal in VS Code (**Terminal>New Terminal**). + - Run the sample in the VS Code terminal using the instructions below. + - (Linux only) Debug your GPU application with GDB for Intel® oneAPI toolkits using the **Generate Launch Configurations** extension. +To learn more about the extensions, see the +[Using Visual Studio Code with Intel® oneAPI Toolkits User Guide](https://www.intel.com/content/www/us/en/develop/documentation/using-vs-code-with-intel-oneapi/top.html). + +Use these commands to run the design, depending on your OS. + +### On a Linux* System +This design uses CMake to generate a build script for GNU/make. + +1. Generate the `Makefile` by running `cmake`. + + ```bash + mkdir build + cd build + ``` + + To compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: + + ```bash + cmake .. + ``` + + You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: + + ``` + cmake .. -DFPGA_DEVICE=: + ``` + + > **NOTE**: This design will **not** work on the Intel® PAC with Intel Arria® 10 GX FPGA, because the design depends on USM. + +2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: + + | Target | Expected Time | Output | Description + |:--- |:--- |:--- |:--- + | `make fpga_emu` | Seconds | x86-64 binary | Compiles the FPGA device code to the CPU. Use the Intel® FPGA Emulation Platform for OpenCL™ software to verify your SYCL code’s functional correctness. + | `make report` | Minutes | RTL + FPGA reports | Compiles the FPGA device code to RTL and generates an optimization report that describes the structures generated on the FPGA, identifies performance bottlenecks, and estimates resource utilization. This report will include the interfaces defined in your selected Board Support Package. + | `make fpga_sim` | Minutes | RTL + FPGA reports + x86-64 binary | Compiles the FPGA device code to RTL and generates a simulation testbench. Use the Questa*-Intel® FPGA Edition simulator to verify your design. + | `make fpga` | Multiple Hours | Quartus Place & Route (Full accelerator) + FPGA reports + x86-64 host binary | Compiles the FPGA device code to RTL and generate an FPGA image that you can run on a supported accelerator board. + + The `fpga_emu`, `fpga_sim` and `fpga` targets produce binaries that you can run. The executables will be called `TARGET_NAME.fpga_emu`, `TARGET_NAME.fpga_sim`, and `TARGET_NAME.fpga`, where `TARGET_NAME` is the value you specify in `src/CMakeLists.txt`. + +### On a Windows* System +This design uses CMake to generate a build script for `nmake`. + +1. Generate the `Makefile` by running `cmake`. + + ```bash + mkdir build + cd build + ``` + + To compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: + + ```bash + cmake -G "NMake Makefiles" .. + ``` + + You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: + + ``` + cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + ``` + + > **NOTE**: This design will **not** work on the Intel® PAC with Intel Arria® 10 GX FPGA, because the design depends on USM. + + +2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: + + | Target | Expected Time | Output | Description + |:--- |:--- |:--- |:--- + | `nmake fpga_emu` | Seconds | x86-64 binary | Compiles the FPGA device code to the CPU. Use the Intel® FPGA Emulation Platform for OpenCL™ software to verify your SYCL code’s functional correctness. + | `nmake report` | Minutes | RTL + FPGA reports | Compiles the FPGA device code to RTL and generates an optimization report that describes the structures generated on the FPGA, identifies performance bottlenecks, and estimates resource utilization. This report will include the interfaces defined in your selected Board Support Package. + | `nmake fpga_sim` | Minutes | RTL + FPGA reports + x86-64 binary | Compiles the FPGA device code to RTL and generates a simulation testbench. Use the Questa*-Intel® FPGA Edition simulator to verify your design. + | `nmake fpga` | Multiple Hours | Quartus Place & Route (Full accelerator) + FPGA reports + x86-64 host binary | Compiles the FPGA device code to RTL and generate an FPGA image that you can run on a supported accelerator board. + + The `fpga_emu`, `fpga_sim`, and `fpga` targets also produce binaries that you can run. The executables will be called `TARGET_NAME.fpga_emu.exe`, `TARGET_NAME.fpga_sim.exe`, and `TARGET_NAME.fpga.exe`, where `TARGET_NAME` is the value you specify in `src/CMakeLists.txt`. + + > **Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. + + > **Note**: If you encounter any issues with long paths when compiling under Windows*, you may have to create your ‘build’ directory in a shorter path, for example c:\samples\build. You can then run cmake from that directory, and provide cmake with the full path to your sample directory. + +### Additional Documentation +- [Explore SYCL* Through Intel® FPGA Code Samples](https://software.intel.com/content/www/us/en/develop/articles/explore-dpcpp-through-intel-fpga-code-samples.html) helps you to navigate the samples and build your knowledge of FPGAs and SYCL. +- [FPGA Optimization Guide for Intel® oneAPI Toolkits](https://software.intel.com/content/www/us/en/develop/documentation/oneapi-fpga-optimization-guide) helps you understand how to target FPGAs using SYCL and Intel® oneAPI Toolkits. +- [Intel® oneAPI Programming Guide](https://software.intel.com/en-us/oneapi-programming-guide) helps you understand target-independent, SYCL-compliant programming using Intel® oneAPI Toolkits. + +### Troubleshooting +If an error occurs, you can get more details by running `make` with the `VERBOSE=1` argument (on Windows use `nmake` instead): + +``` +make VERBOSE=1 +``` + +``` +nmake VERBOSE=1 +``` + +For more comprehensive troubleshooting, use the Diagnostics Utility for Intel® oneAPI Toolkits, which provides system checks to find missing dependencies and permissions errors. [Learn more](https://www.intel.com/content/www/us/en/develop/documentation/diagnostic-utility-user-guide/top.html). + +### In Third-Party Integrated Development Environments (IDEs) + +You can compile and run this tutorial in the Eclipse* IDE (in Linux*) and the Visual Studio* IDE (in Windows*). For instructions, refer to the following link: [FPGA Workflows on Third-Party IDEs for Intel® oneAPI Toolkits](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-oneapi-dpcpp-fpga-workflow-on-ide.html). + +## Running the Sample + +1. Run the sample on the FPGA emulator (the kernel executes on the CPU): + + ``` + ./fpga_template.fpga_emu (Linux) + fpga_template.fpga_emu.exe (Windows) + ``` + +2. Run the sample on the FPGA simulator device: + ``` + ./fpga_template.fpga_sim (Linux) + fpga_template.fpga_sim.exe (Windows) + ``` + +3. Run the sample on the FPGA device: + ``` + ./fpga_template.fpga (Linux) + fpga_template.fpga.exe (Windows) + ``` + +## License +Code samples are licensed under the MIT license. See +[License.txt](https://github.com/oneapi-src/oneAPI-samples/blob/master/License.txt) for details. + +Third party program Licenses can be found here: [third-party-programs.txt](https://github.com/oneapi-src/oneAPI-samples/blob/master/third-party-programs.txt). \ No newline at end of file diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/sample.json b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/sample.json new file mode 100644 index 0000000000..748e9e594a --- /dev/null +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/sample.json @@ -0,0 +1,94 @@ +{ + "guid": "418AA4D8-0A61-4FDB-845A-CDA4DA0655E7", + "name": "FPGA Template", + "categories": ["Toolkit/oneAPI Direct Programming/DPC++ FPGA/Getting Started Tutorials"], + "description": "This project serves as a template for Intel® oneAPI FPGA designs. ", + "toolchain": ["dpcpp"], + "os": ["linux", "windows"], + "targetDevice": ["FPGA"], + "builder": ["cmake"], + "languages": [{"cpp":{}}], + "commonFolder": { + "base": "../../..", + "include": [ + "README.md", + "Tutorials/GettingStarted/experimental/fpga_template", + "include" + ], + "exclude": [] + }, + "ciTests": { + "linux": [ + { + "id": "fpga_emu", + "steps": [ + "dpcpp --version", + "mkdir build", + "cd build", + "cmake ..", + "make fpga_emu", + "./fpga_template.fpga_emu" + ] + }, + { + "id": "report", + "steps": [ + "dpcpp --version", + "mkdir build", + "cd build", + "cmake ..", + "make report" + ] + }, + { + "id": "fpga_sim", + "steps": [ + "dpcpp --version", + "mkdir build", + "cd build", + "cmake ..", + "make fpga_sim", + "./fpga_template.fpga_sim" + ] + } + ], + "windows": [ + { + "id": "fpga_emu", + "steps": [ + "dpcpp --version", + "cd ../../../..", + "mkdir build", + "cd build", + "cmake -G \"NMake Makefiles\" ../Tutorials/GettingStarted/experimental/fpga_template", + "nmake fpga_emu", + "fpga_template.fpga_emu.exe" + ] + }, + { + "id": "report", + "steps": [ + "dpcpp --version", + "cd ../../../..", + "mkdir build", + "cd build", + "cmake -G \"NMake Makefiles\" ../Tutorials/GettingStarted/experimental/fpga_template", + "nmake report" + ] + }, + { + "id": "fpga_sim", + "steps": [ + "dpcpp --version", + "cd ../../../..", + "mkdir build", + "cd build", + "cmake -G \"NMake Makefiles\" ../Tutorials/GettingStarted/experimental/fpga_template", + "nmake fpga_sim", + "fpga_template.fpga_sim.exe" + ] + } + ] + }, + "expertise": "Getting Started" +} diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt new file mode 100644 index 0000000000..ca033e7a7d --- /dev/null +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt @@ -0,0 +1,134 @@ +############################################################################### +### Customize these build variables +############################################################################### +set(SOURCE_FILE fpga_template.cpp) +set(TARGET_NAME fpga_template) + +# Use cmake -DFPGA_DEVICE=: to choose a +# different device. Here are a few device examples (this list is not +# exhaustive): +# intel_s10sx_pac:pac_s10 +# intel_s10sx_pac:pac_s10_usm +# intel_a10gx_pac:pac_a10 +# Note that depending on your installation, you may need to specify the full +# path to the board support package (BSP), this usually is in your install +# folder. +# +# You can also specify a device family (E.g. "Arria10" or "Stratix10") or a +# specific part number (E.g. "10AS066N3F40E2SG") to generate a standalone IP. +if(NOT DEFINED FPGA_DEVICE) + set(FPGA_DEVICE "intel_s10sx_pac:pac_s10_usm") +endif() + +# Use cmake -DUSER_HARDWARE_FLAGS= to set extra flags for FPGA backend +# compilation. +set(USER_HARDWARE_FLAGS "${USER_HARDWARE_FLAGS}") + +# Use cmake -DUSER_FLAGS= to set extra flags for general compilation. +set(USER_FLAGS "${USER_FLAGS}") +############################################################################### +### no changes after here +############################################################################### + +# define the different build targets the generated build script will support. +set(EMULATOR_TARGET ${TARGET_NAME}.fpga_emu) +# set(REPORT_TARGET ${TARGET_NAME}.report) +set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) +set(FPGA_TARGET ${TARGET_NAME}.fpga) +# set(IP_EXPORT_TARGET ${TARGET_NAME}.fpga_ip_export) + +# FPGA device selection +if(DEFINED FPGA_DEVICE) + message(STATUS "Configuring the design to run on ${FPGA_DEVICE}") +endif() + +# This is a Windows-specific flag that enables exception handling in host code +if(WIN32) + # add qactypes to link command on Windows only + set(QACTYPES_COMPILE "/Qactypes") + set(QACTYPES_LINK "/Qactypes") + set(WIN_FLAG "/EHsc") +else() + # add qactypes for Linux + set(QACTYPES_COMPILE "-qactypes") + set(QACTYPES_LINK "-qactypes") +endif() + +# A DPC++ ahead-of-time (AoT) compile processes the device code in two stages. +# 1. The "compile" stage compiles the device code to an intermediate +# representation (SPIR-V). +# 2. The "link" stage invokes the compiler's FPGA backend before linking. For +# this reason, FPGA backend flags must be passed as link flags in CMake. + +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${QACTYPES_COMPILE} ${EXPERIMENTAL_INCLUDE}") +set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${QACTYPES_LINK}") +set(FPGA_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${QACTYPES_COMPILE} ${EXPERIMENTAL_INCLUDE}") +set(FPGA_REPORT_FLAGS "-fsycl -fintelfpga -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") +set(FPGA_LINK_FLAGS "${FPGA_REPORT_FLAGS} ${QACTYPES_LINK}") + +############################################################################### +### FPGA Emulator +############################################################################### +# To compile in a single command: +# icpx -fsycl -fintelfpga -DFPGA_EMULATOR fpga_compile.cpp -o fpga_compile.fpga_emu +# CMake executes: +# [compile] icpx -fsycl -fintelfpga -DFPGA_EMULATOR -o fpga_compile.cpp.o -c fpga_compile.cpp +# [link] icpx -fsycl -fintelfpga fpga_compile.cpp.o -o fpga_compile.fpga_emu +add_executable(${EMULATOR_TARGET} ${SOURCE_FILE}) +add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET}) +set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_COMPILE_FLAGS} -DFPGA_EMULATOR ${USER_FLAGS}") +set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS} -DFPGA_EMULATOR ${USER_FLAGS}") + +############################################################################### +### Report +############################################################################### +# To compile manually: +# icpx -fsycl -fintelfpga -Xshardware -Xstarget= -fsycl-link=early fpga_compile.cpp -o fpga_compile.report.a +set(REPORT_TARGET ${TARGET_NAME}.report.a) +# The compile output is not an executable, but an intermediate compilation result unique to DPC++. +add_executable(${REPORT_TARGET} ${SOURCE_FILE}) +add_custom_target(report DEPENDS ${REPORT_TARGET}) +set_target_properties(${REPORT_TARGET} PROPERTIES COMPILE_FLAGS "${FPGA_COMPILE_FLAGS} -DFPGA_HARDWARE ${USER_FLAGS}") +set_target_properties(${REPORT_TARGET} PROPERTIES LINK_FLAGS "${FPGA_REPORT_FLAGS} ${USER_FLAGS} -Xshardware -fsycl-link=early") +# fsycl-link=early stops the compiler after RTL generation, before invoking Quartus® + +############################################################################### +### FPGA Simulation +############################################################################### +# To compile in a single command: +# icpx -fsycl -fintelfpga -Xstarget= -Xssimulation -Xsghdl=1 fpga_compile.cpp -o fpga_compile.fpga_sim +# CMake executes: +# [compile] icpx -fsycl -fintelfpga -o fpga_compile.cpp.o -c fpga_compile.cpp +# [link] icpx -fsycl -fintelfpga -Xstarget= -Xssimulation -Xsghdl=1 fpga_compile.cpp.o -o fpga_compile.fpga_sim +add_executable(${SIMULATOR_TARGET} EXCLUDE_FROM_ALL ${SOURCE_FILE}) +add_custom_target(fpga_sim DEPENDS ${SIMULATOR_TARGET}) +set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${FPGA_COMPILE_FLAGS} -DFPGA_SIMULATOR ${USER_FLAGS}") +set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${FPGA_LINK_FLAGS} -Xssimulation -Xsghdl=1 ${USER_FLAGS}") + +############################################################################### +### FPGA Board +############################################################################### +# To compile in a single command: +# icpx -fsycl -fintelfpga -Xshardware -Xstarget= fpga_compile.cpp -o fpga_compile.fpga +# CMake executes: +# [compile] icpx -fsycl -fintelfpga -o fpga_compile.cpp.o -c fpga_compile.cpp +# [link] icpx -fsycl -fintelfpga -Xshardware -Xstarget= fpga_compile.cpp.o -o fpga_compile.fpga +add_executable(${FPGA_TARGET} EXCLUDE_FROM_ALL ${SOURCE_FILE}) +add_custom_target(fpga DEPENDS ${FPGA_TARGET}) +set_target_properties(${FPGA_TARGET} PROPERTIES COMPILE_FLAGS "${FPGA_COMPILE_FLAGS} -DFPGA_HARDWARE ${USER_FLAGS}") +set_target_properties(${FPGA_TARGET} PROPERTIES LINK_FLAGS "${FPGA_LINK_FLAGS} -Xshardware ${USER_FLAGS}") + +############################################################################### +### FPGA IP Export (apparently only necessary until 'correct' implementation of host pipes) +############################################################################### +# To compile in a single command: +# icpx -fsycl -fintelfpga -Xshardware -Xstarget= -fsycl-link=early -fsycl-device-code-split=per_kernel fpga_compile.cpp -o fpga_compile.fpga_ip_export +# CMake executes: +# [compile] icpx -fsycl -fintelfpga -o fpga_compile.cpp.o -c fpga_compile.cpp +# [link] icpx -fsycl -fintelfpga -Xshardware -Xstarget= fpga_compile.cpp.o -o fpga_compile.fpga_ip_export +set(IP_EXPORT_TARGET ${TARGET_NAME}.fpga_ip_export.a) +# The compile output is not an executable, but an intermediate compilation result unique to DPC++. +add_executable(${IP_EXPORT_TARGET} ${SOURCE_FILE}) +add_custom_target(fpga_ip_export DEPENDS ${IP_EXPORT_TARGET}) +set_target_properties(${IP_EXPORT_TARGET} PROPERTIES COMPILE_FLAGS "${FPGA_COMPILE_FLAGS} -DFPGA_HARDWARE ${USER_FLAGS}") +set_target_properties(${IP_EXPORT_TARGET} PROPERTIES LINK_FLAGS "${FPGA_REPORT_FLAGS} -Xshardware -fsycl-link=early -fsycl-device-code-split=per_kernel ${USER_FLAGS}") diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/fpga_template.cpp b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/fpga_template.cpp new file mode 100644 index 0000000000..1c3b7658c5 --- /dev/null +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/fpga_template.cpp @@ -0,0 +1,94 @@ +#include + +// oneAPI headers +#include +#include + +// Forward declare the kernel name in the global scope. This is an FPGA best +// practice that reduces name mangling in the optimization reports. +class vector_add_ID; + +class vector_add { + public: + int *A_in; + int *B_in; + int *C_out; + int len; + + void operator()() const { + for (int idx = 0; idx < len; idx++) { + int a_val = A_in[idx]; + int b_val = B_in[idx]; + int sum = a_val + b_val; + C_out[idx] = sum; + } + } +}; + +#define VECT_SIZE 256 + +int main() { + bool passed = false; + + try { +#if FPGA_SIMULATOR + std::cout << "using FPGA Simulator." << std::endl; + sycl::queue q(sycl::ext::intel::fpga_simulator_selector{}); +#elif FPGA_HARDWARE + std::cout << "using FPGA Hardware." << std::endl; + sycl::queue q(sycl::ext::intel::fpga_selector{}); +#else // #if FPGA_EMULATOR + std::cout << "using FPGA Emulator." << std::endl; + sycl::queue q(sycl::ext::intel::fpga_emulator_selector{}); +#endif + + int count = VECT_SIZE; // pass array size by value + + // declare arrays and fill them + // allocate in shared memory so the kernel can see them + int *A = sycl::malloc_shared(count, q); + int *B = sycl::malloc_shared(count, q); + int *C = sycl::malloc_shared(count, q); + for (int i = 0; i < count; i++) { + A[i] = i; + B[i] = (count - i); + } + + std::cout << "add two vectors of size " << count << std::endl; + + q.single_task(vector_add{A, B, C, count}).wait(); + + // verify that VC is correct + passed = true; + for (int i = 0; i < count; i++) { + int expected = A[i] + B[i]; + if (C[i] != expected) { + std::cout << "idx=" << i << ": result " << C[i] << ", expected (" + << expected << ") A=" << A[i] << " + B=" << B[i] << std::endl; + passed = false; + } + } + + std::cout << (passed ? "PASSED" : "FAILED") << std::endl; + + sycl::free(A, q); + sycl::free(B, q); + sycl::free(C, q); + + } catch (sycl::exception const &e) { + // Catches exceptions in the host code. + std::cerr << "Caught a SYCL host exception:\n" << e.what() << "\n"; + + // Most likely the runtime couldn't find FPGA hardware! + if (e.code().value() == CL_DEVICE_NOT_FOUND) { + std::cerr << "If you are targeting an FPGA, please ensure that your " + "system has a correctly configured FPGA board.\n"; + std::cerr << "Run sys_check in the oneAPI root directory to verify.\n"; + std::cerr << "If you are targeting the FPGA emulator, compile with " + "-DFPGA_EMULATOR.\n"; + } + std::terminate(); + } + + return passed ? EXIT_SUCCESS : EXIT_FAILURE; +} \ No newline at end of file From 6167e7bc0174d514f267fd9b2401a902e289ee82 Mon Sep 17 00:00:00 2001 From: "White, Paul" Date: Wed, 7 Dec 2022 08:13:03 -0800 Subject: [PATCH 02/22] add support for 2023.1 and 2023.0 --- .../fpga_template/src/fpga_template.cpp | 21 +++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/fpga_template.cpp b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/fpga_template.cpp index 1c3b7658c5..49c78214fe 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/fpga_template.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/fpga_template.cpp @@ -31,6 +31,20 @@ int main() { bool passed = false; try { +// This design is tested with 2023.0, but also accounts for a syntax change in +// 2023.1 +#if __INTEL_CLANG_COMPILER >= 20230100 +#if FPGA_SIMULATOR + std::cout << "using FPGA Simulator." << std::endl; + sycl::queue q(sycl::ext::intel::fpga_simulator_selector_v); +#elif FPGA_HARDWARE + std::cout << "using FPGA Hardware." << std::endl; + sycl::queue q(sycl::ext::intel::fpga_selector_v); +#else // #if FPGA_EMULATOR + std::cout << "using FPGA Emulator." << std::endl; + sycl::queue q(sycl::ext::intel::fpga_emulator_selector_v); +#endif +#elif __INTEL_CLANG_COMPILER >= 20230000 #if FPGA_SIMULATOR std::cout << "using FPGA Simulator." << std::endl; sycl::queue q(sycl::ext::intel::fpga_simulator_selector{}); @@ -41,8 +55,11 @@ int main() { std::cout << "using FPGA Emulator." << std::endl; sycl::queue q(sycl::ext::intel::fpga_emulator_selector{}); #endif - - int count = VECT_SIZE; // pass array size by value +#else + assert(false) && "this design requires oneAPI 2023.0 or 2023.1!" +#else + assert(false) && "this design requires oneAPI 2023.0 or 2023.1!" std::cout + << "using FPGA Emulator." << std::endl; // declare arrays and fill them // allocate in shared memory so the kernel can see them From 9fa05347eb76a28274a468b52aefd96ddab6f96b Mon Sep 17 00:00:00 2001 From: "White, Paul" Date: Wed, 7 Dec 2022 08:38:32 -0800 Subject: [PATCH 03/22] fix for errant clang-format --- .../experimental/fpga_template/src/fpga_template.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/fpga_template.cpp b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/fpga_template.cpp index 49c78214fe..e3fb32ee32 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/fpga_template.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/fpga_template.cpp @@ -57,9 +57,9 @@ int main() { #endif #else assert(false) && "this design requires oneAPI 2023.0 or 2023.1!" -#else - assert(false) && "this design requires oneAPI 2023.0 or 2023.1!" std::cout - << "using FPGA Emulator." << std::endl; +#endif + + int count = VECT_SIZE; // pass array size by value // declare arrays and fill them // allocate in shared memory so the kernel can see them From 4736d41deed75d697cb096d208d6f609d2f46687 Mon Sep 17 00:00:00 2001 From: "White, Paul" Date: Thu, 8 Dec 2022 04:23:24 -0800 Subject: [PATCH 04/22] add note about CL... environment variable --- .../GettingStarted/experimental/fpga_template/README.md | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md index cb6ee37eaf..99c9b3be30 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md @@ -196,9 +196,12 @@ You can compile and run this tutorial in the Eclipse* IDE (in Linux*) and the Vi ``` 2. Run the sample on the FPGA simulator device: + + > **NOTE**: you need to define the `CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 environment variable in oneAPI 2023.1 + ``` - ./fpga_template.fpga_sim (Linux) - fpga_template.fpga_sim.exe (Windows) + CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./fpga_template.fpga_sim (Linux) + cmd /V /C "set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1&& fpga_template.fpga_sim.exe" (Windows) ``` 3. Run the sample on the FPGA device: From 98a0dfc8e81aab55aa08e0cfff93c3bf023a4098 Mon Sep 17 00:00:00 2001 From: "White, Paul" Date: Fri, 9 Dec 2022 06:03:59 -0800 Subject: [PATCH 05/22] improve verbosity of CMake file. open issue: doesn't print object file --- .../fpga_template/src/CMakeLists.txt | 154 +++++++++++------- 1 file changed, 96 insertions(+), 58 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt index ca033e7a7d..43b9b53428 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt @@ -20,9 +20,9 @@ if(NOT DEFINED FPGA_DEVICE) set(FPGA_DEVICE "intel_s10sx_pac:pac_s10_usm") endif() -# Use cmake -DUSER_HARDWARE_FLAGS= to set extra flags for FPGA backend +# Use cmake -DUSER_FPGA_FLAGS= to set extra flags for FPGA backend # compilation. -set(USER_HARDWARE_FLAGS "${USER_HARDWARE_FLAGS}") +set(USER_FPGA_FLAGS "${USER_FPGA_FLAGS}") # Use cmake -DUSER_FLAGS= to set extra flags for general compilation. set(USER_FLAGS "${USER_FLAGS}") @@ -30,12 +30,18 @@ set(USER_FLAGS "${USER_FLAGS}") ### no changes after here ############################################################################### +set(EMULATOR_EXTENSION fpga_emu) +set(REPORT_EXTENSION report) +set(SIMULATOR_EXTENSION fpga_sim) +set(FPGA_EXTENSION fpga) +set(IP_EXPORT_EXTENSION fpga_ip_export) + # define the different build targets the generated build script will support. -set(EMULATOR_TARGET ${TARGET_NAME}.fpga_emu) -# set(REPORT_TARGET ${TARGET_NAME}.report) -set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) -set(FPGA_TARGET ${TARGET_NAME}.fpga) -# set(IP_EXPORT_TARGET ${TARGET_NAME}.fpga_ip_export) +set(EMULATOR_TARGET ${TARGET_NAME}.${EMULATOR_EXTENSION}) +set(REPORT_TARGET ${TARGET_NAME}.${REPORT_EXTENSION}) +set(SIMULATOR_TARGET ${TARGET_NAME}.${SIMULATOR_EXTENSION}) +set(FPGA_TARGET ${TARGET_NAME}.${FPGA_EXTENSION}) +set(IP_EXPORT_TARGET ${TARGET_NAME}.${IP_EXPORT_EXTENSION}) # FPGA device selection if(DEFINED FPGA_DEVICE) @@ -51,7 +57,7 @@ if(WIN32) else() # add qactypes for Linux set(QACTYPES_COMPILE "-qactypes") - set(QACTYPES_LINK "-qactypes") + set(QACTYPES_LINK "") endif() # A DPC++ ahead-of-time (AoT) compile processes the device code in two stages. @@ -60,75 +66,107 @@ endif() # 2. The "link" stage invokes the compiler's FPGA backend before linking. For # this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${QACTYPES_COMPILE} ${EXPERIMENTAL_INCLUDE}") -set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${QACTYPES_LINK}") -set(FPGA_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${QACTYPES_COMPILE} ${EXPERIMENTAL_INCLUDE}") -set(FPGA_REPORT_FLAGS "-fsycl -fintelfpga -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(FPGA_LINK_FLAGS "${FPGA_REPORT_FLAGS} ${QACTYPES_LINK}") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_EMULATOR ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") +set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_EMULATOR ${QACTYPES_LINK} ${USER_FLAGS} ") +set(REPORT_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") +set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_LINK} ${USER_FLAGS} ${USER_FPGA_FLAGS} -Xshardware -fsycl-link=early") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_SIMULATOR ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_SIMULATOR ${QACTYPES_LINK} ${USER_FLAGS} ${USER_FPGA_FLAGS} -Xssimulation -Xsghdl=1") +set(FULL_SYSTEM_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") +set(FULL_SYSTEM_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_LINK} ${USER_FLAGS} ${USER_FPGA_FLAGS} -Xshardware") + +# get rid of this once host pipes work properly +set(IP_EXPORT_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") +set(IP_EXPORT_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_LINK} ${USER_FLAGS} ${USER_FPGA_FLAGS} -Xshardware -fsycl-link=early -fsycl-device-code-split=per_kernel") + +# remove extra spaces +string(REGEX REPLACE "( +)" " " EMULATOR_COMPILE_FLAGS ${EMULATOR_COMPILE_FLAGS}) +string(REGEX REPLACE "( +)" " " EMULATOR_LINK_FLAGS ${EMULATOR_LINK_FLAGS}) +string(REGEX REPLACE "( +)" " " REPORT_COMPILE_FLAGS ${REPORT_COMPILE_FLAGS}) +string(REGEX REPLACE "( +)" " " REPORT_LINK_FLAGS ${REPORT_LINK_FLAGS}) +string(REGEX REPLACE "( +)" " " SIMULATOR_COMPILE_FLAGS ${SIMULATOR_COMPILE_FLAGS}) +string(REGEX REPLACE "( +)" " " SIMULATOR_LINK_FLAGS ${SIMULATOR_LINK_FLAGS}) +string(REGEX REPLACE "( +)" " " FULL_SYSTEM_COMPILE_FLAGS ${FULL_SYSTEM_COMPILE_FLAGS}) +string(REGEX REPLACE "( +)" " " FULL_SYSTEM_COMPILE_FLAGS ${FULL_SYSTEM_COMPILE_FLAGS}) +string(REGEX REPLACE "( +)" " " IP_EXPORT_COMPILE_FLAGS ${IP_EXPORT_COMPILE_FLAGS}) +string(REGEX REPLACE "( +)" " " IP_EXPORT_LINK_FLAGS ${IP_EXPORT_LINK_FLAGS}) ############################################################################### ### FPGA Emulator ############################################################################### -# To compile in a single command: -# icpx -fsycl -fintelfpga -DFPGA_EMULATOR fpga_compile.cpp -o fpga_compile.fpga_emu -# CMake executes: -# [compile] icpx -fsycl -fintelfpga -DFPGA_EMULATOR -o fpga_compile.cpp.o -c fpga_compile.cpp -# [link] icpx -fsycl -fintelfpga fpga_compile.cpp.o -o fpga_compile.fpga_emu add_executable(${EMULATOR_TARGET} ${SOURCE_FILE}) -add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET}) -set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_COMPILE_FLAGS} -DFPGA_EMULATOR ${USER_FLAGS}") -set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS} -DFPGA_EMULATOR ${USER_FLAGS}") + +add_custom_target( displayEmulationCompileCommand ALL + ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" + COMMENT "${CMAKE_CXX_COMPILER} ${EMULATOR_COMPILE_FLAGS} -o ${OBJ_FILE} -c ${SOURCE_FILE}") + +add_dependencies(${EMULATOR_TARGET} displayEmulationCompileCommand) +set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_COMPILE_FLAGS}") +add_custom_command(TARGET ${EMULATOR_TARGET} POST_BUILD COMMENT "${CMAKE_CXX_COMPILER} ${EMULATOR_LINK_FLAGS} ${OBJ_FILE} -o ${EMULATOR_TARGET}") + +set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS}") +add_custom_target(${EMULATOR_EXTENSION} DEPENDS ${EMULATOR_TARGET}) ############################################################################### ### Report ############################################################################### -# To compile manually: -# icpx -fsycl -fintelfpga -Xshardware -Xstarget= -fsycl-link=early fpga_compile.cpp -o fpga_compile.report.a -set(REPORT_TARGET ${TARGET_NAME}.report.a) -# The compile output is not an executable, but an intermediate compilation result unique to DPC++. add_executable(${REPORT_TARGET} ${SOURCE_FILE}) -add_custom_target(report DEPENDS ${REPORT_TARGET}) -set_target_properties(${REPORT_TARGET} PROPERTIES COMPILE_FLAGS "${FPGA_COMPILE_FLAGS} -DFPGA_HARDWARE ${USER_FLAGS}") -set_target_properties(${REPORT_TARGET} PROPERTIES LINK_FLAGS "${FPGA_REPORT_FLAGS} ${USER_FLAGS} -Xshardware -fsycl-link=early") -# fsycl-link=early stops the compiler after RTL generation, before invoking Quartus® + +add_custom_target( displayReportCompileCommand ALL + ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" + COMMENT "${CMAKE_CXX_COMPILER} ${REPORT_COMPILE_FLAGS} -o ${OBJ_FILE} -c ${SOURCE_FILE}") + +add_dependencies(${REPORT_TARGET} displayReportCompileCommand) +set_target_properties(${REPORT_TARGET} PROPERTIES COMPILE_FLAGS "${REPORT_COMPILE_FLAGS}") +add_custom_command(TARGET ${REPORT_TARGET} POST_BUILD COMMENT "${CMAKE_CXX_COMPILER} ${REPORT_LINK_FLAGS} ${OBJ_FILE} -o ${REPORT_TARGET}") + +set_target_properties(${REPORT_TARGET} PROPERTIES LINK_FLAGS "${REPORT_LINK_FLAGS}") +add_custom_target(${REPORT_EXTENSION} DEPENDS ${REPORT_TARGET}) ############################################################################### ### FPGA Simulation ############################################################################### -# To compile in a single command: -# icpx -fsycl -fintelfpga -Xstarget= -Xssimulation -Xsghdl=1 fpga_compile.cpp -o fpga_compile.fpga_sim -# CMake executes: -# [compile] icpx -fsycl -fintelfpga -o fpga_compile.cpp.o -c fpga_compile.cpp -# [link] icpx -fsycl -fintelfpga -Xstarget= -Xssimulation -Xsghdl=1 fpga_compile.cpp.o -o fpga_compile.fpga_sim -add_executable(${SIMULATOR_TARGET} EXCLUDE_FROM_ALL ${SOURCE_FILE}) -add_custom_target(fpga_sim DEPENDS ${SIMULATOR_TARGET}) -set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${FPGA_COMPILE_FLAGS} -DFPGA_SIMULATOR ${USER_FLAGS}") -set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${FPGA_LINK_FLAGS} -Xssimulation -Xsghdl=1 ${USER_FLAGS}") +add_executable(${SIMULATOR_TARGET} ${SOURCE_FILE}) + +add_custom_target( displaySimulatorCompileCommand ALL + ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" + COMMENT "${CMAKE_CXX_COMPILER} ${SIMULATOR_COMPILE_FLAGS} -o ${OBJ_FILE} -c ${SOURCE_FILE}") + +add_dependencies(${SIMULATOR_TARGET} displaySimulatorCompileCommand) +set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${SIMULATOR_COMPILE_FLAGS}") +add_custom_command(TARGET ${SIMULATOR_TARGET} POST_BUILD COMMENT "${CMAKE_CXX_COMPILER} ${SIMULATOR_LINK_FLAGS} ${OBJ_FILE} -o ${SIMULATOR_TARGET}") + +set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${SIMULATOR_LINK_FLAGS}") +add_custom_target(${SIMULATOR_EXTENSION} DEPENDS ${SIMULATOR_TARGET}) ############################################################################### ### FPGA Board ############################################################################### -# To compile in a single command: -# icpx -fsycl -fintelfpga -Xshardware -Xstarget= fpga_compile.cpp -o fpga_compile.fpga -# CMake executes: -# [compile] icpx -fsycl -fintelfpga -o fpga_compile.cpp.o -c fpga_compile.cpp -# [link] icpx -fsycl -fintelfpga -Xshardware -Xstarget= fpga_compile.cpp.o -o fpga_compile.fpga -add_executable(${FPGA_TARGET} EXCLUDE_FROM_ALL ${SOURCE_FILE}) -add_custom_target(fpga DEPENDS ${FPGA_TARGET}) -set_target_properties(${FPGA_TARGET} PROPERTIES COMPILE_FLAGS "${FPGA_COMPILE_FLAGS} -DFPGA_HARDWARE ${USER_FLAGS}") -set_target_properties(${FPGA_TARGET} PROPERTIES LINK_FLAGS "${FPGA_LINK_FLAGS} -Xshardware ${USER_FLAGS}") +add_executable(${FPGA_TARGET} ${SOURCE_FILE}) + +add_custom_target( displayFpgaCompileCommand ALL + ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" + COMMENT "${CMAKE_CXX_COMPILER} ${FULL_SYSTEM_COMPILE_FLAGS} -o ${OBJ_FILE} -c ${SOURCE_FILE}") + +add_dependencies(${FPGA_TARGET} displayFpgaCompileCommand) +set_target_properties(${FPGA_TARGET} PROPERTIES COMPILE_FLAGS "${FULL_SYSTEM_COMPILE_FLAGS}") +add_custom_command(TARGET ${FPGA_TARGET} POST_BUILD COMMENT "${CMAKE_CXX_COMPILER} ${FULL_SYSTEM_LINK_FLAGS} ${OBJ_FILE} -o ${FPGA_TARGET}") + +set_target_properties(${FPGA_TARGET} PROPERTIES LINK_FLAGS "${FULL_SYSTEM_LINK_FLAGS}") +add_custom_target(${FPGA_EXTENSION} DEPENDS ${FPGA_TARGET}) ############################################################################### -### FPGA IP Export (apparently only necessary until 'correct' implementation of host pipes) +### FPGA IP Export (only necessary until native host pipes) ############################################################################### -# To compile in a single command: -# icpx -fsycl -fintelfpga -Xshardware -Xstarget= -fsycl-link=early -fsycl-device-code-split=per_kernel fpga_compile.cpp -o fpga_compile.fpga_ip_export -# CMake executes: -# [compile] icpx -fsycl -fintelfpga -o fpga_compile.cpp.o -c fpga_compile.cpp -# [link] icpx -fsycl -fintelfpga -Xshardware -Xstarget= fpga_compile.cpp.o -o fpga_compile.fpga_ip_export -set(IP_EXPORT_TARGET ${TARGET_NAME}.fpga_ip_export.a) -# The compile output is not an executable, but an intermediate compilation result unique to DPC++. add_executable(${IP_EXPORT_TARGET} ${SOURCE_FILE}) -add_custom_target(fpga_ip_export DEPENDS ${IP_EXPORT_TARGET}) -set_target_properties(${IP_EXPORT_TARGET} PROPERTIES COMPILE_FLAGS "${FPGA_COMPILE_FLAGS} -DFPGA_HARDWARE ${USER_FLAGS}") -set_target_properties(${IP_EXPORT_TARGET} PROPERTIES LINK_FLAGS "${FPGA_REPORT_FLAGS} -Xshardware -fsycl-link=early -fsycl-device-code-split=per_kernel ${USER_FLAGS}") + +add_custom_target( displayExportCompileCommand ALL + ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" + COMMENT "${CMAKE_CXX_COMPILER} ${IP_EXPORT_COMPILE_FLAGS} -o ${OBJ_FILE} -c ${SOURCE_FILE}") + +add_dependencies(${IP_EXPORT_TARGET} displayExportCompileCommand) +set_target_properties(${IP_EXPORT_TARGET} PROPERTIES COMPILE_FLAGS "${IP_EXPORT_COMPILE_FLAGS}") +add_custom_command(TARGET ${IP_EXPORT_TARGET} POST_BUILD COMMENT "${CMAKE_CXX_COMPILER} ${IP_EXPORT_LINK_FLAGS} ${OBJ_FILE} -o ${IP_EXPORT_TARGET}") + +set_target_properties(${IP_EXPORT_TARGET} PROPERTIES LINK_FLAGS "${IP_EXPORT_LINK_FLAGS}") +add_custom_target(${IP_EXPORT_EXTENSION} DEPENDS ${IP_EXPORT_TARGET}) \ No newline at end of file From 259be827caa80609ff69bac1e66efd70452edb05 Mon Sep 17 00:00:00 2001 From: "White, Paul" Date: Fri, 9 Dec 2022 06:48:24 -0800 Subject: [PATCH 06/22] Revert "improve verbosity of CMake file. open issue: doesn't print object file" This reverts commit 98a0dfc8e81aab55aa08e0cfff93c3bf023a4098. --- .../fpga_template/src/CMakeLists.txt | 154 +++++++----------- 1 file changed, 58 insertions(+), 96 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt index 43b9b53428..ca033e7a7d 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt @@ -20,9 +20,9 @@ if(NOT DEFINED FPGA_DEVICE) set(FPGA_DEVICE "intel_s10sx_pac:pac_s10_usm") endif() -# Use cmake -DUSER_FPGA_FLAGS= to set extra flags for FPGA backend +# Use cmake -DUSER_HARDWARE_FLAGS= to set extra flags for FPGA backend # compilation. -set(USER_FPGA_FLAGS "${USER_FPGA_FLAGS}") +set(USER_HARDWARE_FLAGS "${USER_HARDWARE_FLAGS}") # Use cmake -DUSER_FLAGS= to set extra flags for general compilation. set(USER_FLAGS "${USER_FLAGS}") @@ -30,18 +30,12 @@ set(USER_FLAGS "${USER_FLAGS}") ### no changes after here ############################################################################### -set(EMULATOR_EXTENSION fpga_emu) -set(REPORT_EXTENSION report) -set(SIMULATOR_EXTENSION fpga_sim) -set(FPGA_EXTENSION fpga) -set(IP_EXPORT_EXTENSION fpga_ip_export) - # define the different build targets the generated build script will support. -set(EMULATOR_TARGET ${TARGET_NAME}.${EMULATOR_EXTENSION}) -set(REPORT_TARGET ${TARGET_NAME}.${REPORT_EXTENSION}) -set(SIMULATOR_TARGET ${TARGET_NAME}.${SIMULATOR_EXTENSION}) -set(FPGA_TARGET ${TARGET_NAME}.${FPGA_EXTENSION}) -set(IP_EXPORT_TARGET ${TARGET_NAME}.${IP_EXPORT_EXTENSION}) +set(EMULATOR_TARGET ${TARGET_NAME}.fpga_emu) +# set(REPORT_TARGET ${TARGET_NAME}.report) +set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) +set(FPGA_TARGET ${TARGET_NAME}.fpga) +# set(IP_EXPORT_TARGET ${TARGET_NAME}.fpga_ip_export) # FPGA device selection if(DEFINED FPGA_DEVICE) @@ -57,7 +51,7 @@ if(WIN32) else() # add qactypes for Linux set(QACTYPES_COMPILE "-qactypes") - set(QACTYPES_LINK "") + set(QACTYPES_LINK "-qactypes") endif() # A DPC++ ahead-of-time (AoT) compile processes the device code in two stages. @@ -66,107 +60,75 @@ endif() # 2. The "link" stage invokes the compiler's FPGA backend before linking. For # this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_EMULATOR ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") -set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_EMULATOR ${QACTYPES_LINK} ${USER_FLAGS} ") -set(REPORT_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") -set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_LINK} ${USER_FLAGS} ${USER_FPGA_FLAGS} -Xshardware -fsycl-link=early") -set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_SIMULATOR ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") -set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_SIMULATOR ${QACTYPES_LINK} ${USER_FLAGS} ${USER_FPGA_FLAGS} -Xssimulation -Xsghdl=1") -set(FULL_SYSTEM_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") -set(FULL_SYSTEM_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_LINK} ${USER_FLAGS} ${USER_FPGA_FLAGS} -Xshardware") - -# get rid of this once host pipes work properly -set(IP_EXPORT_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") -set(IP_EXPORT_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_LINK} ${USER_FLAGS} ${USER_FPGA_FLAGS} -Xshardware -fsycl-link=early -fsycl-device-code-split=per_kernel") - -# remove extra spaces -string(REGEX REPLACE "( +)" " " EMULATOR_COMPILE_FLAGS ${EMULATOR_COMPILE_FLAGS}) -string(REGEX REPLACE "( +)" " " EMULATOR_LINK_FLAGS ${EMULATOR_LINK_FLAGS}) -string(REGEX REPLACE "( +)" " " REPORT_COMPILE_FLAGS ${REPORT_COMPILE_FLAGS}) -string(REGEX REPLACE "( +)" " " REPORT_LINK_FLAGS ${REPORT_LINK_FLAGS}) -string(REGEX REPLACE "( +)" " " SIMULATOR_COMPILE_FLAGS ${SIMULATOR_COMPILE_FLAGS}) -string(REGEX REPLACE "( +)" " " SIMULATOR_LINK_FLAGS ${SIMULATOR_LINK_FLAGS}) -string(REGEX REPLACE "( +)" " " FULL_SYSTEM_COMPILE_FLAGS ${FULL_SYSTEM_COMPILE_FLAGS}) -string(REGEX REPLACE "( +)" " " FULL_SYSTEM_COMPILE_FLAGS ${FULL_SYSTEM_COMPILE_FLAGS}) -string(REGEX REPLACE "( +)" " " IP_EXPORT_COMPILE_FLAGS ${IP_EXPORT_COMPILE_FLAGS}) -string(REGEX REPLACE "( +)" " " IP_EXPORT_LINK_FLAGS ${IP_EXPORT_LINK_FLAGS}) +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${QACTYPES_COMPILE} ${EXPERIMENTAL_INCLUDE}") +set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${QACTYPES_LINK}") +set(FPGA_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${QACTYPES_COMPILE} ${EXPERIMENTAL_INCLUDE}") +set(FPGA_REPORT_FLAGS "-fsycl -fintelfpga -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") +set(FPGA_LINK_FLAGS "${FPGA_REPORT_FLAGS} ${QACTYPES_LINK}") ############################################################################### ### FPGA Emulator ############################################################################### +# To compile in a single command: +# icpx -fsycl -fintelfpga -DFPGA_EMULATOR fpga_compile.cpp -o fpga_compile.fpga_emu +# CMake executes: +# [compile] icpx -fsycl -fintelfpga -DFPGA_EMULATOR -o fpga_compile.cpp.o -c fpga_compile.cpp +# [link] icpx -fsycl -fintelfpga fpga_compile.cpp.o -o fpga_compile.fpga_emu add_executable(${EMULATOR_TARGET} ${SOURCE_FILE}) - -add_custom_target( displayEmulationCompileCommand ALL - ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" - COMMENT "${CMAKE_CXX_COMPILER} ${EMULATOR_COMPILE_FLAGS} -o ${OBJ_FILE} -c ${SOURCE_FILE}") - -add_dependencies(${EMULATOR_TARGET} displayEmulationCompileCommand) -set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_COMPILE_FLAGS}") -add_custom_command(TARGET ${EMULATOR_TARGET} POST_BUILD COMMENT "${CMAKE_CXX_COMPILER} ${EMULATOR_LINK_FLAGS} ${OBJ_FILE} -o ${EMULATOR_TARGET}") - -set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS}") -add_custom_target(${EMULATOR_EXTENSION} DEPENDS ${EMULATOR_TARGET}) +add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET}) +set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_COMPILE_FLAGS} -DFPGA_EMULATOR ${USER_FLAGS}") +set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS} -DFPGA_EMULATOR ${USER_FLAGS}") ############################################################################### ### Report ############################################################################### +# To compile manually: +# icpx -fsycl -fintelfpga -Xshardware -Xstarget= -fsycl-link=early fpga_compile.cpp -o fpga_compile.report.a +set(REPORT_TARGET ${TARGET_NAME}.report.a) +# The compile output is not an executable, but an intermediate compilation result unique to DPC++. add_executable(${REPORT_TARGET} ${SOURCE_FILE}) - -add_custom_target( displayReportCompileCommand ALL - ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" - COMMENT "${CMAKE_CXX_COMPILER} ${REPORT_COMPILE_FLAGS} -o ${OBJ_FILE} -c ${SOURCE_FILE}") - -add_dependencies(${REPORT_TARGET} displayReportCompileCommand) -set_target_properties(${REPORT_TARGET} PROPERTIES COMPILE_FLAGS "${REPORT_COMPILE_FLAGS}") -add_custom_command(TARGET ${REPORT_TARGET} POST_BUILD COMMENT "${CMAKE_CXX_COMPILER} ${REPORT_LINK_FLAGS} ${OBJ_FILE} -o ${REPORT_TARGET}") - -set_target_properties(${REPORT_TARGET} PROPERTIES LINK_FLAGS "${REPORT_LINK_FLAGS}") -add_custom_target(${REPORT_EXTENSION} DEPENDS ${REPORT_TARGET}) +add_custom_target(report DEPENDS ${REPORT_TARGET}) +set_target_properties(${REPORT_TARGET} PROPERTIES COMPILE_FLAGS "${FPGA_COMPILE_FLAGS} -DFPGA_HARDWARE ${USER_FLAGS}") +set_target_properties(${REPORT_TARGET} PROPERTIES LINK_FLAGS "${FPGA_REPORT_FLAGS} ${USER_FLAGS} -Xshardware -fsycl-link=early") +# fsycl-link=early stops the compiler after RTL generation, before invoking Quartus® ############################################################################### ### FPGA Simulation ############################################################################### -add_executable(${SIMULATOR_TARGET} ${SOURCE_FILE}) - -add_custom_target( displaySimulatorCompileCommand ALL - ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" - COMMENT "${CMAKE_CXX_COMPILER} ${SIMULATOR_COMPILE_FLAGS} -o ${OBJ_FILE} -c ${SOURCE_FILE}") - -add_dependencies(${SIMULATOR_TARGET} displaySimulatorCompileCommand) -set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${SIMULATOR_COMPILE_FLAGS}") -add_custom_command(TARGET ${SIMULATOR_TARGET} POST_BUILD COMMENT "${CMAKE_CXX_COMPILER} ${SIMULATOR_LINK_FLAGS} ${OBJ_FILE} -o ${SIMULATOR_TARGET}") - -set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${SIMULATOR_LINK_FLAGS}") -add_custom_target(${SIMULATOR_EXTENSION} DEPENDS ${SIMULATOR_TARGET}) +# To compile in a single command: +# icpx -fsycl -fintelfpga -Xstarget= -Xssimulation -Xsghdl=1 fpga_compile.cpp -o fpga_compile.fpga_sim +# CMake executes: +# [compile] icpx -fsycl -fintelfpga -o fpga_compile.cpp.o -c fpga_compile.cpp +# [link] icpx -fsycl -fintelfpga -Xstarget= -Xssimulation -Xsghdl=1 fpga_compile.cpp.o -o fpga_compile.fpga_sim +add_executable(${SIMULATOR_TARGET} EXCLUDE_FROM_ALL ${SOURCE_FILE}) +add_custom_target(fpga_sim DEPENDS ${SIMULATOR_TARGET}) +set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${FPGA_COMPILE_FLAGS} -DFPGA_SIMULATOR ${USER_FLAGS}") +set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${FPGA_LINK_FLAGS} -Xssimulation -Xsghdl=1 ${USER_FLAGS}") ############################################################################### ### FPGA Board ############################################################################### -add_executable(${FPGA_TARGET} ${SOURCE_FILE}) - -add_custom_target( displayFpgaCompileCommand ALL - ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" - COMMENT "${CMAKE_CXX_COMPILER} ${FULL_SYSTEM_COMPILE_FLAGS} -o ${OBJ_FILE} -c ${SOURCE_FILE}") - -add_dependencies(${FPGA_TARGET} displayFpgaCompileCommand) -set_target_properties(${FPGA_TARGET} PROPERTIES COMPILE_FLAGS "${FULL_SYSTEM_COMPILE_FLAGS}") -add_custom_command(TARGET ${FPGA_TARGET} POST_BUILD COMMENT "${CMAKE_CXX_COMPILER} ${FULL_SYSTEM_LINK_FLAGS} ${OBJ_FILE} -o ${FPGA_TARGET}") - -set_target_properties(${FPGA_TARGET} PROPERTIES LINK_FLAGS "${FULL_SYSTEM_LINK_FLAGS}") -add_custom_target(${FPGA_EXTENSION} DEPENDS ${FPGA_TARGET}) +# To compile in a single command: +# icpx -fsycl -fintelfpga -Xshardware -Xstarget= fpga_compile.cpp -o fpga_compile.fpga +# CMake executes: +# [compile] icpx -fsycl -fintelfpga -o fpga_compile.cpp.o -c fpga_compile.cpp +# [link] icpx -fsycl -fintelfpga -Xshardware -Xstarget= fpga_compile.cpp.o -o fpga_compile.fpga +add_executable(${FPGA_TARGET} EXCLUDE_FROM_ALL ${SOURCE_FILE}) +add_custom_target(fpga DEPENDS ${FPGA_TARGET}) +set_target_properties(${FPGA_TARGET} PROPERTIES COMPILE_FLAGS "${FPGA_COMPILE_FLAGS} -DFPGA_HARDWARE ${USER_FLAGS}") +set_target_properties(${FPGA_TARGET} PROPERTIES LINK_FLAGS "${FPGA_LINK_FLAGS} -Xshardware ${USER_FLAGS}") ############################################################################### -### FPGA IP Export (only necessary until native host pipes) +### FPGA IP Export (apparently only necessary until 'correct' implementation of host pipes) ############################################################################### +# To compile in a single command: +# icpx -fsycl -fintelfpga -Xshardware -Xstarget= -fsycl-link=early -fsycl-device-code-split=per_kernel fpga_compile.cpp -o fpga_compile.fpga_ip_export +# CMake executes: +# [compile] icpx -fsycl -fintelfpga -o fpga_compile.cpp.o -c fpga_compile.cpp +# [link] icpx -fsycl -fintelfpga -Xshardware -Xstarget= fpga_compile.cpp.o -o fpga_compile.fpga_ip_export +set(IP_EXPORT_TARGET ${TARGET_NAME}.fpga_ip_export.a) +# The compile output is not an executable, but an intermediate compilation result unique to DPC++. add_executable(${IP_EXPORT_TARGET} ${SOURCE_FILE}) - -add_custom_target( displayExportCompileCommand ALL - ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" - COMMENT "${CMAKE_CXX_COMPILER} ${IP_EXPORT_COMPILE_FLAGS} -o ${OBJ_FILE} -c ${SOURCE_FILE}") - -add_dependencies(${IP_EXPORT_TARGET} displayExportCompileCommand) -set_target_properties(${IP_EXPORT_TARGET} PROPERTIES COMPILE_FLAGS "${IP_EXPORT_COMPILE_FLAGS}") -add_custom_command(TARGET ${IP_EXPORT_TARGET} POST_BUILD COMMENT "${CMAKE_CXX_COMPILER} ${IP_EXPORT_LINK_FLAGS} ${OBJ_FILE} -o ${IP_EXPORT_TARGET}") - -set_target_properties(${IP_EXPORT_TARGET} PROPERTIES LINK_FLAGS "${IP_EXPORT_LINK_FLAGS}") -add_custom_target(${IP_EXPORT_EXTENSION} DEPENDS ${IP_EXPORT_TARGET}) \ No newline at end of file +add_custom_target(fpga_ip_export DEPENDS ${IP_EXPORT_TARGET}) +set_target_properties(${IP_EXPORT_TARGET} PROPERTIES COMPILE_FLAGS "${FPGA_COMPILE_FLAGS} -DFPGA_HARDWARE ${USER_FLAGS}") +set_target_properties(${IP_EXPORT_TARGET} PROPERTIES LINK_FLAGS "${FPGA_REPORT_FLAGS} -Xshardware -fsycl-link=early -fsycl-device-code-split=per_kernel ${USER_FLAGS}") From 539bba70988b222976f89eee79f202209aad24f0 Mon Sep 17 00:00:00 2001 From: "White, Paul" Date: Fri, 9 Dec 2022 08:39:17 -0800 Subject: [PATCH 07/22] clean up CMakeLists environment variables --- .../experimental/fpga_template/README.md | 4 +- .../fpga_template/src/CMakeLists.txt | 81 ++++++++++++------- 2 files changed, 54 insertions(+), 31 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md index 99c9b3be30..2f20f820c2 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md @@ -46,9 +46,9 @@ if(NOT DEFINED FPGA_DEVICE) set(FPGA_DEVICE "intel_s10sx_pac:pac_s10_usm") endif() -# Use cmake -DUSER_HARDWARE_FLAGS= to set extra flags for FPGA backend +# Use cmake -DUSER_FPGA_FLAGS= to set extra flags for FPGA backend # compilation. -set(USER_HARDWARE_FLAGS "${USER_HARDWARE_FLAGS}") +set(USER_FPGA_FLAGS "${USER_FPGA_FLAGS}") # Use cmake -DUSER_FLAGS= to set extra flags for general compilation. set(USER_FLAGS "${USER_FLAGS}") diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt index ca033e7a7d..a484a375c8 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt @@ -20,9 +20,9 @@ if(NOT DEFINED FPGA_DEVICE) set(FPGA_DEVICE "intel_s10sx_pac:pac_s10_usm") endif() -# Use cmake -DUSER_HARDWARE_FLAGS= to set extra flags for FPGA backend +# Use cmake -DUSER_FPGA_FLAGS= to set extra flags for FPGA backend # compilation. -set(USER_HARDWARE_FLAGS "${USER_HARDWARE_FLAGS}") +set(USER_FPGA_FLAGS "${USER_FPGA_FLAGS}") # Use cmake -DUSER_FLAGS= to set extra flags for general compilation. set(USER_FLAGS "${USER_FLAGS}") @@ -30,12 +30,18 @@ set(USER_FLAGS "${USER_FLAGS}") ### no changes after here ############################################################################### +set(EMULATOR_EXTENSION fpga_emu) +set(REPORT_EXTENSION report) +set(SIMULATOR_EXTENSION fpga_sim) +set(FPGA_EXTENSION fpga) +set(IP_EXPORT_EXTENSION fpga_ip_export) + # define the different build targets the generated build script will support. -set(EMULATOR_TARGET ${TARGET_NAME}.fpga_emu) -# set(REPORT_TARGET ${TARGET_NAME}.report) -set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) -set(FPGA_TARGET ${TARGET_NAME}.fpga) -# set(IP_EXPORT_TARGET ${TARGET_NAME}.fpga_ip_export) +set(EMULATOR_TARGET ${TARGET_NAME}.${EMULATOR_EXTENSION}) +set(REPORT_TARGET ${TARGET_NAME}.${REPORT_EXTENSION}) +set(SIMULATOR_TARGET ${TARGET_NAME}.${SIMULATOR_EXTENSION}) +set(FPGA_TARGET ${TARGET_NAME}.${FPGA_EXTENSION}) +set(IP_EXPORT_TARGET ${TARGET_NAME}.${IP_EXPORT_EXTENSION}) # FPGA device selection if(DEFINED FPGA_DEVICE) @@ -60,12 +66,30 @@ endif() # 2. The "link" stage invokes the compiler's FPGA backend before linking. For # this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${QACTYPES_COMPILE} ${EXPERIMENTAL_INCLUDE}") -set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${QACTYPES_LINK}") -set(FPGA_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${QACTYPES_COMPILE} ${EXPERIMENTAL_INCLUDE}") -set(FPGA_REPORT_FLAGS "-fsycl -fintelfpga -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(FPGA_LINK_FLAGS "${FPGA_REPORT_FLAGS} ${QACTYPES_LINK}") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_EMULATOR ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") +set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_EMULATOR ${QACTYPES_LINK} ${USER_FLAGS} ") +set(REPORT_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") +set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${USER_FLAGS} ${USER_FPGA_FLAGS} -Xshardware -fsycl-link=early") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_SIMULATOR ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_SIMULATOR ${QACTYPES_LINK} ${USER_FLAGS} ${USER_FPGA_FLAGS} -Xssimulation -Xsghdl=1") +set(FULL_SYSTEM_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") +set(FULL_SYSTEM_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_LINK} ${USER_FLAGS} ${USER_FPGA_FLAGS} -Xshardware") + +# get rid of this once host pipes work properly +set(IP_EXPORT_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") +set(IP_EXPORT_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${USER_FLAGS} ${USER_FPGA_FLAGS} -Xshardware -fsycl-link=early -fsycl-device-code-split=per_kernel") +# remove extra spaces +string(REGEX REPLACE "( +)" " " EMULATOR_COMPILE_FLAGS ${EMULATOR_COMPILE_FLAGS}) +string(REGEX REPLACE "( +)" " " EMULATOR_LINK_FLAGS ${EMULATOR_LINK_FLAGS}) +string(REGEX REPLACE "( +)" " " REPORT_COMPILE_FLAGS ${REPORT_COMPILE_FLAGS}) +string(REGEX REPLACE "( +)" " " REPORT_LINK_FLAGS ${REPORT_LINK_FLAGS}) +string(REGEX REPLACE "( +)" " " SIMULATOR_COMPILE_FLAGS ${SIMULATOR_COMPILE_FLAGS}) +string(REGEX REPLACE "( +)" " " SIMULATOR_LINK_FLAGS ${SIMULATOR_LINK_FLAGS}) +string(REGEX REPLACE "( +)" " " FULL_SYSTEM_COMPILE_FLAGS ${FULL_SYSTEM_COMPILE_FLAGS}) +string(REGEX REPLACE "( +)" " " FULL_SYSTEM_COMPILE_FLAGS ${FULL_SYSTEM_COMPILE_FLAGS}) +string(REGEX REPLACE "( +)" " " IP_EXPORT_COMPILE_FLAGS ${IP_EXPORT_COMPILE_FLAGS}) +string(REGEX REPLACE "( +)" " " IP_EXPORT_LINK_FLAGS ${IP_EXPORT_LINK_FLAGS}) ############################################################################### ### FPGA Emulator ############################################################################### @@ -75,9 +99,9 @@ set(FPGA_LINK_FLAGS "${FPGA_REPORT_FLAGS} ${QACTYPES_LINK}") # [compile] icpx -fsycl -fintelfpga -DFPGA_EMULATOR -o fpga_compile.cpp.o -c fpga_compile.cpp # [link] icpx -fsycl -fintelfpga fpga_compile.cpp.o -o fpga_compile.fpga_emu add_executable(${EMULATOR_TARGET} ${SOURCE_FILE}) -add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET}) -set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_COMPILE_FLAGS} -DFPGA_EMULATOR ${USER_FLAGS}") -set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS} -DFPGA_EMULATOR ${USER_FLAGS}") +add_custom_target(${EMULATOR_EXTENSION} DEPENDS ${EMULATOR_TARGET}) +set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_COMPILE_FLAGS}") +set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS}") ############################################################################### ### Report @@ -87,10 +111,9 @@ set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_ set(REPORT_TARGET ${TARGET_NAME}.report.a) # The compile output is not an executable, but an intermediate compilation result unique to DPC++. add_executable(${REPORT_TARGET} ${SOURCE_FILE}) -add_custom_target(report DEPENDS ${REPORT_TARGET}) -set_target_properties(${REPORT_TARGET} PROPERTIES COMPILE_FLAGS "${FPGA_COMPILE_FLAGS} -DFPGA_HARDWARE ${USER_FLAGS}") -set_target_properties(${REPORT_TARGET} PROPERTIES LINK_FLAGS "${FPGA_REPORT_FLAGS} ${USER_FLAGS} -Xshardware -fsycl-link=early") -# fsycl-link=early stops the compiler after RTL generation, before invoking Quartus® +add_custom_target(${REPORT_EXTENSION} DEPENDS ${REPORT_TARGET}) +set_target_properties(${REPORT_TARGET} PROPERTIES COMPILE_FLAGS "${REPORT_COMPILE_FLAGS}") +set_target_properties(${REPORT_TARGET} PROPERTIES LINK_FLAGS "${REPORT_LINK_FLAGS}") ############################################################################### ### FPGA Simulation @@ -101,9 +124,9 @@ set_target_properties(${REPORT_TARGET} PROPERTIES LINK_FLAGS "${FPGA_REPORT_FLAG # [compile] icpx -fsycl -fintelfpga -o fpga_compile.cpp.o -c fpga_compile.cpp # [link] icpx -fsycl -fintelfpga -Xstarget= -Xssimulation -Xsghdl=1 fpga_compile.cpp.o -o fpga_compile.fpga_sim add_executable(${SIMULATOR_TARGET} EXCLUDE_FROM_ALL ${SOURCE_FILE}) -add_custom_target(fpga_sim DEPENDS ${SIMULATOR_TARGET}) -set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${FPGA_COMPILE_FLAGS} -DFPGA_SIMULATOR ${USER_FLAGS}") -set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${FPGA_LINK_FLAGS} -Xssimulation -Xsghdl=1 ${USER_FLAGS}") +add_custom_target(${SIMULATOR_EXTENSION} DEPENDS ${SIMULATOR_TARGET}) +set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${SIMULATOR_COMPILE_FLAGS}") +set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${SIMULATOR_LINK_FLAGS}") ############################################################################### ### FPGA Board @@ -114,12 +137,12 @@ set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${FPGA_LINK_FLA # [compile] icpx -fsycl -fintelfpga -o fpga_compile.cpp.o -c fpga_compile.cpp # [link] icpx -fsycl -fintelfpga -Xshardware -Xstarget= fpga_compile.cpp.o -o fpga_compile.fpga add_executable(${FPGA_TARGET} EXCLUDE_FROM_ALL ${SOURCE_FILE}) -add_custom_target(fpga DEPENDS ${FPGA_TARGET}) -set_target_properties(${FPGA_TARGET} PROPERTIES COMPILE_FLAGS "${FPGA_COMPILE_FLAGS} -DFPGA_HARDWARE ${USER_FLAGS}") -set_target_properties(${FPGA_TARGET} PROPERTIES LINK_FLAGS "${FPGA_LINK_FLAGS} -Xshardware ${USER_FLAGS}") +add_custom_target(${FPGA_EXTENSION} DEPENDS ${FPGA_TARGET}) +set_target_properties(${FPGA_TARGET} PROPERTIES COMPILE_FLAGS "${FULL_SYSTEM_COMPILE_FLAGS}") +set_target_properties(${FPGA_TARGET} PROPERTIES LINK_FLAGS "${FULL_SYSTEM_LINK_FLAGS}") ############################################################################### -### FPGA IP Export (apparently only necessary until 'correct' implementation of host pipes) +### FPGA IP Export (only necessary until native host pipes) ############################################################################### # To compile in a single command: # icpx -fsycl -fintelfpga -Xshardware -Xstarget= -fsycl-link=early -fsycl-device-code-split=per_kernel fpga_compile.cpp -o fpga_compile.fpga_ip_export @@ -129,6 +152,6 @@ set_target_properties(${FPGA_TARGET} PROPERTIES LINK_FLAGS "${FPGA_LINK_FLAGS} - set(IP_EXPORT_TARGET ${TARGET_NAME}.fpga_ip_export.a) # The compile output is not an executable, but an intermediate compilation result unique to DPC++. add_executable(${IP_EXPORT_TARGET} ${SOURCE_FILE}) -add_custom_target(fpga_ip_export DEPENDS ${IP_EXPORT_TARGET}) -set_target_properties(${IP_EXPORT_TARGET} PROPERTIES COMPILE_FLAGS "${FPGA_COMPILE_FLAGS} -DFPGA_HARDWARE ${USER_FLAGS}") -set_target_properties(${IP_EXPORT_TARGET} PROPERTIES LINK_FLAGS "${FPGA_REPORT_FLAGS} -Xshardware -fsycl-link=early -fsycl-device-code-split=per_kernel ${USER_FLAGS}") +add_custom_target(${IP_EXPORT_EXTENSION} DEPENDS ${IP_EXPORT_TARGET}) +set_target_properties(${IP_EXPORT_TARGET} PROPERTIES COMPILE_FLAGS "${IP_EXPORT_COMPILE_FLAGS}") +set_target_properties(${IP_EXPORT_TARGET} PROPERTIES LINK_FLAGS "${IP_EXPORT_LINK_FLAGS}") From 9e7858469fc9ec9948518e79679a0408a5f579c2 Mon Sep 17 00:00:00 2001 From: "White, Paul" Date: Fri, 9 Dec 2022 15:00:55 -0800 Subject: [PATCH 08/22] fix bug in CMakeLists (missing Xstarget) --- .../experimental/fpga_template/src/CMakeLists.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt index a484a375c8..9ac4cdecb5 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt @@ -69,15 +69,15 @@ endif() set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_EMULATOR ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_EMULATOR ${QACTYPES_LINK} ${USER_FLAGS} ") set(REPORT_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") -set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${USER_FLAGS} ${USER_FPGA_FLAGS} -Xshardware -fsycl-link=early") +set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${USER_FLAGS} ${USER_FPGA_FLAGS} -Xstarget=${FPGA_DEVICE} -Xshardware -fsycl-link=early") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_SIMULATOR ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") -set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_SIMULATOR ${QACTYPES_LINK} ${USER_FLAGS} ${USER_FPGA_FLAGS} -Xssimulation -Xsghdl=1") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_SIMULATOR ${QACTYPES_LINK} ${USER_FLAGS} ${USER_FPGA_FLAGS} -Xstarget=${FPGA_DEVICE} -Xssimulation -Xsghdl=1") set(FULL_SYSTEM_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") -set(FULL_SYSTEM_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_LINK} ${USER_FLAGS} ${USER_FPGA_FLAGS} -Xshardware") +set(FULL_SYSTEM_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_LINK} ${USER_FLAGS} ${USER_FPGA_FLAGS} -Xstarget=${FPGA_DEVICE} -Xshardware") # get rid of this once host pipes work properly set(IP_EXPORT_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") -set(IP_EXPORT_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${USER_FLAGS} ${USER_FPGA_FLAGS} -Xshardware -fsycl-link=early -fsycl-device-code-split=per_kernel") +set(IP_EXPORT_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${USER_FLAGS} ${USER_FPGA_FLAGS} -Xstarget=${FPGA_DEVICE} -Xshardware -fsycl-link=early -fsycl-device-code-split=per_kernel") # remove extra spaces string(REGEX REPLACE "( +)" " " EMULATOR_COMPILE_FLAGS ${EMULATOR_COMPILE_FLAGS}) From fabe2eec6e873a882f91ee486b34e4596fac2428 Mon Sep 17 00:00:00 2001 From: "White, Paul" Date: Thu, 15 Dec 2022 08:38:06 -0800 Subject: [PATCH 09/22] update readme per Yohann's requests --- .../experimental/fpga_template/README.md | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md index 2f20f820c2..4f5df6d9ba 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md @@ -6,11 +6,20 @@ This project serves as a template for Intel® oneAPI FPGA designs. |:--- |:--- | OS | Linux* Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 | Hardware | Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX)
Intel® FPGA 3rd party / custom platforms with oneAPI support (and SYCL USM support) Note: Intel® FPGA PAC hardware is only compatible with Ubuntu 18.04* -| Software | Intel® oneAPI DPC++ Compiler
Intel® Quartus Prime Pro Edition +| Software | Intel® oneAPI DPC++/C++ Compiler | What you will learn | Best practices for creating and managing a oneAPI FPGA project | Time to complete | 10 minutes -***Notice**: SYCL Unified Shared Memory (USM) host allocations (and therefore the code in this tutorial) are only supported by Board Support Packages (BSPs) with USM support (e.g. the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) `intel_s10sx_pac:pac_s10_usm`)* +> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. +> +> To use the simulator flow, Intel® Quartus® Prime Pro Edition and one of the following simulators must be installed and accessible through your PATH: +> - Questa*-Intel® FPGA Edition +> - Questa*-Intel® FPGA Starter Edition +> - ModelSim® SE +> +> To use the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. + +> **Note**: In oneAPI full systems, kernels that use SYCL Unified Shared Memory (USM) host allocations or USM shared allocations (and therefore the code in this tutorial) are only supported by Board Support Packages (BSPs) with USM support (e.g. the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) `intel_s10sx_pac:pac_s10_usm`). Kernels that use these types of allocations can always be used to generate standalone IPs. ## Purpose From 19b52dd0248fecb3de9ddaf906f3c3e63ec39850 Mon Sep 17 00:00:00 2001 From: "White, Paul" Date: Fri, 16 Dec 2022 07:51:46 -0800 Subject: [PATCH 10/22] add support for additional include paths --- .../experimental/fpga_template/README.md | 13 +++++++++---- .../experimental/fpga_template/src/CMakeLists.txt | 8 ++++++++ 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md index 4f5df6d9ba..19d668a268 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md @@ -23,14 +23,15 @@ This project serves as a template for Intel® oneAPI FPGA designs. ## Purpose -Use this project as a starting point when you build designs for the Intel® oneAPI FPGA compiler. It includes a CMake build system to automate selecting the various command-line flags for the oneAPI FPGA compiler, and a simple single-source design to serve as an example. You can customize the build flags by modifying the top part of `src/CMakeLists.txt`: if you want to pass additional flags to the Intel® oneAPI FPGA compiler, you can change the `USER_FLAGS` and `USER_HARDWARE_FLAGS` variables defined in `src/CMakeLists.txt`. +Use this project as a starting point when you build designs for the Intel® oneAPI FPGA compiler. It includes a CMake build system to automate selecting the various command-line flags for the oneAPI FPGA compiler, and a simple single-source design to serve as an example. You can customize the build flags by modifying the top part of `src/CMakeLists.txt`: if you want to pass additional flags to the Intel® oneAPI FPGA compiler, you can change the `USER_FLAGS` and `USER_HARDWARE_FLAGS` variables defined in `src/CMakeLists.txt`. Similarly, you can add additional include paths to the `USER_INCLUDE_PATHS` variable. You can also explictly define these variables at the command-line if you don't want to make change to the CMake build system. > **Note**: The code sample in this design only uses USM for improved code simplicity as compared with buffers/accessors. The included CMake build system can also be used for designs that do not use USM. -| Variable | Description | +| Variable | Description |:--- |:--- -| `USER_HARDWARE_FLAGS` | These flags apply only to flows that generate FPGA hardware (i.e. report, simulation, hardware). You can specify flags such as `-Xsclock` or `-Xshyper-optimized-handshaking=off` | -| `USER_FLAGS` | These flags apply to all flows, including emulation. You can specify flags such as `-v` or define macros such as `-DYOUR_OWN_MACRO=3` | +| `USER_HARDWARE_FLAGS` | This space-separated list of flags applies only to flows that generate FPGA hardware (i.e. report, simulation, hardware). You can specify flags such as `-Xsclock` or `-Xshyper-optimized-handshaking=off` +| `USER_FLAGS` | This space-separated list of flags applies to all flows, including emulation. You can specify flags such as `-v` or define macros such as `-DYOUR_OWN_MACRO=3` +| `USER_INCLUDE_PATHS` | This space-separated list of include paths applies to all flows, including emulation. Specify include paths relative to the `src/CMakeLists.txt` file, or using absolute paths in the filesystem. ```bash ############################################################################### @@ -61,6 +62,10 @@ set(USER_FPGA_FLAGS "${USER_FPGA_FLAGS}") # Use cmake -DUSER_FLAGS= to set extra flags for general compilation. set(USER_FLAGS "${USER_FLAGS}") + +# Use cmake -DUSER_INCLUDE_PATHS= to set extra paths for general +# compilation. +set(USER_INCLUDE_PATHS "${USER_INCLUDE_PATHS}") ``` Everything below this in the `src/CMakeLists.txt` is necessary for selecting the compiler flags that are necessary to support the build targets specified below, and should not need to be modified. diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt index 9ac4cdecb5..350f137840 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt @@ -26,10 +26,18 @@ set(USER_FPGA_FLAGS "${USER_FPGA_FLAGS}") # Use cmake -DUSER_FLAGS= to set extra flags for general compilation. set(USER_FLAGS "${USER_FLAGS}") + +# Use cmake -DUSER_INCLUDE_PATHS= to set extra paths for general +# compilation. +set(USER_INCLUDE_PATHS "${USER_INCLUDE_PATHS}") ############################################################################### ### no changes after here ############################################################################### +set(INCLUDEPATHS_LIST ${USER_INCLUDE_PATHS}) +separate_arguments(INCLUDEPATHS_LIST) +include_directories(${INCLUDEPATHS_LIST}) + set(EMULATOR_EXTENSION fpga_emu) set(REPORT_EXTENSION report) set(SIMULATOR_EXTENSION fpga_sim) From 3497ef403ea2667c00fc9cd0ac2cd4101488e9ba Mon Sep 17 00:00:00 2001 From: "White, Paul" Date: Mon, 16 Jan 2023 07:53:10 -0800 Subject: [PATCH 11/22] use One True CMake file --- .../experimental/fpga_template/CMakeLists.txt | 319 +++++++++++++++++- .../fpga_template/src/CMakeLists.txt | 165 --------- 2 files changed, 313 insertions(+), 171 deletions(-) delete mode 100644 DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/CMakeLists.txt index 831a75579a..6ac9ba50d1 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/CMakeLists.txt @@ -1,20 +1,327 @@ +# Direct CMake to use icpx rather than the default C++ compiler/linker on Linux +# and icx-cl on Windows if(UNIX) - # Direct CMake to use icpx rather than the default C++ compiler/linker set(CMAKE_CXX_COMPILER icpx) else() # Windows - # Force CMake to use icpx rather than the default C++ compiler/linker - # (needed on Windows only) include (CMakeForceCompiler) CMAKE_FORCE_CXX_COMPILER (icx-cl IntelDPCPP) include (Platform/Windows-Clang) endif() -cmake_minimum_required (VERSION 3.4) +cmake_minimum_required (VERSION 3.7.2) -project(FPGATemplate CXX) +project(fpga_template CXX) set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) -add_subdirectory (src) \ No newline at end of file +############################################################################### +### Customize these build variables +############################################################################### +set(SOURCE_FILES src/fpga_template.cpp) +set(TARGET_NAME fpga_template) + +# Use cmake -DFPGA_DEVICE=: to choose a +# different device. Here are a few device examples (this list is not +# exhaustive): +# intel_s10sx_pac:pac_s10 +# intel_s10sx_pac:pac_s10_usm +# intel_a10gx_pac:pac_a10 +# Note that depending on your installation, you may need to specify the full +# path to the board support package (BSP), this usually is in your install +# folder. +# +# You can also specify a device family (E.g. "Arria10" or "Stratix10") or a +# specific part number (E.g. "10AS066N3F40E2SG") to generate a standalone IP. +if(NOT DEFINED FPGA_DEVICE) + set(FPGA_DEVICE "intel_s10sx_pac:pac_s10_usm") +endif() + +# Use cmake -DUSER_FPGA_FLAGS= to set extra flags for FPGA backend +# compilation. +set(USER_FPGA_FLAGS ${USER_FPGA_FLAGS}) + +# Use cmake -DUSER_FLAGS= to set extra flags for general compilation. +set(USER_FLAGS ${USER_FLAGS}) + +# Use cmake -DUSER_INCLUDE_PATHS= to set extra paths for general +# compilation. +set(USER_INCLUDE_PATHS ${USER_INCLUDE_PATHS} ../../../../include/) + +# Use cmake -DUSER_LIB_PATHS= to set extra paths to target_link_libraries +set(USER_LIB_PATHS ${USER_LIB_PATHS}) + +# Use cmake -DUSER_LIBS= to add extra static libraries +set(USER_LIBS ${USER_LIBS}) + +############################################################################### +### no changes after here +############################################################################### + +# Print the device being used for the compiles +message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + +# Set the names of the makefile targets to be generated by cmake +set(EMULATOR_TARGET fpga_emu) +set(SIMULATOR_TARGET fpga_sim) +set(REPORT_TARGET report) +set(FPGA_TARGET fpga) +set(IP_EXPORT_TARGET fpga_ip_export) + +# Set the names of the generated files per makefile target +set(EMULATOR_OUTPUT_NAME ${TARGET_NAME}.${EMULATOR_TARGET}) +set(SIMULATOR_OUTPUT_NAME ${TARGET_NAME}.${SIMULATOR_TARGET}) +set(REPORT_OUTPUT_NAME ${TARGET_NAME}.${REPORT_TARGET}) +set(FPGA_OUTPUT_NAME ${TARGET_NAME}.${FPGA_TARGET}) +set(IP_EXPORT_OUTPUT_NAME ${TARGET_NAME}.${IP_EXPORT_TARGET}) + +message(STATUS "Additional USER_FPGA_FLAGS=${USER_FPGA_FLAGS}") +message(STATUS "Additional USER_FLAGS=${USER_FLAGS}") + +include_directories(${USER_INCLUDE_PATHS}) +message(STATUS "Additional USER_INCLUDE_PATHS=${USER_INCLUDE_PATHS}") + +link_directories(${USER_LIB_PATHS}) +message(STATUS "Additional USER_LIB_PATHS=${USER_LIB_PATHS}") + +link_libraries(${USER_LIBS}) +message(STATUS "Additional USER_LIBS=${USER_LIBS}") + +# This is a Windows-specific flag that enables exception handling in host code +if(WIN32) + # add qactypes to link command on Windows only + set(QACTYPES "-Qactypes") + set(WIN_FLAG "/EHsc") +else() + # add qactypes for Linux + set(QACTYPES "-qactypes") +endif() + +set(COMMON_COMPILE_FLAGS -fsycl -fintelfpga -Wall ${WIN_FLAG} ${QACTYPES} ${USER_FLAGS}) +set(COMMON_LINK_FLAGS -fsycl -fintelfpga ${QACTYPES} ${USER_FLAGS}) + +# A SYCL ahead-of-time (AoT) compile processes the device code in two stages. +# 1. The "compile" stage compiles the device code to an intermediate +# representation (SPIR-V). +# 2. The "link" stage invokes the compiler's FPGA backend before linking. For +# this reason, FPGA backend flags must be passed as link flags in CMake. +set(EMULATOR_COMPILE_FLAGS -DFPGA_EMULATOR) +set(EMULATOR_LINK_FLAGS ) +set(REPORT_COMPILE_FLAGS -DFPGA_HARDWARE) +set(REPORT_LINK_FLAGS -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_FPGA_FLAGS} -fsycl-link=early) +set(SIMULATOR_COMPILE_FLAGS -Xssimulation -DFPGA_SIMULATOR) +set(SIMULATOR_LINK_FLAGS -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_FPGA_FLAGS} -reuse-exe=${CMAKE_BINARY_DIR}/${SIMULATOR_OUTPUT_NAME}) +set(HARDWARE_COMPILE_FLAGS -DFPGA_HARDWARE) +set(HARDWARE_LINK_FLAGS -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_FPGA_FLAGS} -reuse-exe=${CMAKE_BINARY_DIR}/${FPGA_OUTPUT_NAME}) +# get rid of this once host pipes work properly +set(IP_EXPORT_COMPILE_FLAGS -DFPGA_HARDWARE) +set(IP_EXPORT_LINK_FLAGS -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_FPGA_FLAGS} -fsycl-link=early -fsycl-device-code-split=per_kernel) + +############################################################################### +### FPGA Emulator +############################################################################### +add_executable(${EMULATOR_TARGET} ${SOURCE_FILES}) +target_compile_options(${EMULATOR_TARGET} PRIVATE ${COMMON_COMPILE_FLAGS}) +target_compile_options(${EMULATOR_TARGET} PRIVATE ${EMULATOR_COMPILE_FLAGS}) +target_link_libraries(${EMULATOR_TARGET} ${COMMON_LINK_FLAGS}) +target_link_libraries(${EMULATOR_TARGET} ${EMULATOR_LINK_FLAGS}) +set_target_properties(${EMULATOR_TARGET} PROPERTIES OUTPUT_NAME ${EMULATOR_OUTPUT_NAME}) + +############################################################################### +### FPGA Simulator +############################################################################### +add_executable(${SIMULATOR_TARGET} ${SOURCE_FILES}) +target_compile_options(${SIMULATOR_TARGET} PRIVATE ${COMMON_COMPILE_FLAGS}) +target_compile_options(${SIMULATOR_TARGET} PRIVATE ${SIMULATOR_COMPILE_FLAGS}) +target_link_libraries(${SIMULATOR_TARGET} ${COMMON_LINK_FLAGS}) +target_link_libraries(${SIMULATOR_TARGET} ${SIMULATOR_LINK_FLAGS}) +set_target_properties(${SIMULATOR_TARGET} PROPERTIES OUTPUT_NAME ${SIMULATOR_OUTPUT_NAME}) + +############################################################################### +### Generate Report +############################################################################### +add_executable(${REPORT_TARGET} ${SOURCE_FILES}) +target_compile_options(${REPORT_TARGET} PRIVATE ${COMMON_COMPILE_FLAGS}) +target_compile_options(${REPORT_TARGET} PRIVATE ${REPORT_COMPILE_FLAGS}) + +# The report target does not need the QACTYPES flag at link stage +set(MODIFIED_COMMON_LINK_FLAGS_REPORT ${COMMON_LINK_FLAGS}) +list(REMOVE_ITEM MODIFIED_COMMON_LINK_FLAGS_REPORT ${QACTYPES}) + +target_link_libraries(${REPORT_TARGET} ${MODIFIED_COMMON_LINK_FLAGS_REPORT}) +target_link_libraries(${REPORT_TARGET} ${REPORT_LINK_FLAGS}) +set_target_properties(${REPORT_TARGET} PROPERTIES OUTPUT_NAME ${REPORT_OUTPUT_NAME}) + +############################################################################### +### FPGA Hardware +############################################################################### +add_executable(${FPGA_TARGET} EXCLUDE_FROM_ALL ${SOURCE_FILES}) +target_compile_options(${FPGA_TARGET} PRIVATE ${COMMON_COMPILE_FLAGS}) +target_compile_options(${FPGA_TARGET} PRIVATE ${HARDWARE_COMPILE_FLAGS}) +target_link_libraries(${FPGA_TARGET} ${COMMON_LINK_FLAGS}) +target_link_libraries(${FPGA_TARGET} ${HARDWARE_LINK_FLAGS}) +set_target_properties(${FPGA_TARGET} PROPERTIES OUTPUT_NAME ${FPGA_OUTPUT_NAME}) + +############################################################################### +### FPGA IP Export (only necessary until native host pipes) +############################################################################### +add_executable(${IP_EXPORT_TARGET} ${SOURCE_FILES}) +target_compile_options(${IP_EXPORT_TARGET} PRIVATE ${COMMON_COMPILE_FLAGS}) +target_compile_options(${IP_EXPORT_TARGET} PRIVATE ${IP_EXPORT_COMPILE_FLAGS}) + +# The ip export target does not need the QACTYPES flag at link stage +set(MODIFIED_COMMON_LINK_FLAGS_EXPORT ${COMMON_LINK_FLAGS}) +list(REMOVE_ITEM MODIFIED_COMMON_LINK_FLAGS_EXPORT ${QACTYPES}) + +target_link_libraries(${IP_EXPORT_TARGET} ${MODIFIED_COMMON_LINK_FLAGS_EXPORT}) +target_link_libraries(${IP_EXPORT_TARGET} ${IP_EXPORT_LINK_FLAGS}) +set_target_properties(${IP_EXPORT_TARGET} PROPERTIES OUTPUT_NAME ${IP_EXPORT_OUTPUT_NAME}) + + +############################################################################### +### This part only manipulates cmake variables to print the commands to the user +############################################################################### + +# set the correct object file extension depending on the target platform +if(WIN32) + set(OBJ_EXTENSION "obj") +else() + set(OBJ_EXTENSION "o") +endif() + +# Set the source file names in a string +set(SOURCE_FILE_NAME "${SOURCE_FILES}") + +function(getCompileCommands common_compile_flags special_compile_flags common_link_flags special_link_flags target output_name) + + set(file_names ${SOURCE_FILE_NAME}) + set(COMPILE_COMMAND ) + set(LINK_COMMAND ) + + foreach(source ${file_names}) + # Get the relative path to the source and object files + file(RELATIVE_PATH CURRENT_SOURCE_FILE ${CMAKE_CURRENT_BINARY_DIR} ${CMAKE_CURRENT_LIST_DIR}/${source}) + file(RELATIVE_PATH OBJ_FILE ${CMAKE_CURRENT_BINARY_DIR} ${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/${target}.dir/${source}.${OBJ_EXTENSION}) + + # Creating a string that contains the compile command + # Start by the compiler invocation + set(COMPILE_COMMAND "${COMPILE_COMMAND}${CMAKE_CXX_COMPILER}") + + # Add all the potential includes + foreach(INCLUDE ${USER_INCLUDE_PATHS}) + if(NOT IS_ABSOLUTE ${INCLUDE}) + file(RELATIVE_PATH INCLUDE ${CMAKE_CURRENT_BINARY_DIR} ${CMAKE_CURRENT_LIST_DIR}/${INCLUDE}) + endif() + set(COMPILE_COMMAND "${COMPILE_COMMAND} -I${INCLUDE}") + endforeach() + + # Add all the common compile flags + foreach(FLAG ${common_compile_flags}) + set(COMPILE_COMMAND "${COMPILE_COMMAND} ${FLAG}") + endforeach() + + # Add all the specific compile flags + foreach(FLAG ${special_compile_flags}) + set(COMPILE_COMMAND "${COMPILE_COMMAND} ${FLAG}") + endforeach() + + # Get the location of the object file + file(RELATIVE_PATH OBJ_FILE ${CMAKE_CURRENT_BINARY_DIR} ${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/${target}.dir/${source}.${OBJ_EXTENSION}) + + # Add the source file and the output file + set(COMPILE_COMMAND "${COMPILE_COMMAND} -c ${CURRENT_SOURCE_FILE} -o ${OBJ_FILE}\n") + endforeach() + + set(COMPILE_COMMAND "${COMPILE_COMMAND}" PARENT_SCOPE) + + # Creating a string that contains the link command + # Start by the compiler invocation + set(LINK_COMMAND "${LINK_COMMAND}${CMAKE_CXX_COMPILER}") + + # Add all the common link flags + foreach(FLAG ${common_link_flags}) + set(LINK_COMMAND "${LINK_COMMAND} ${FLAG}") + endforeach() + + # Add all the specific link flags + foreach(FLAG ${special_link_flags}) + set(LINK_COMMAND "${LINK_COMMAND} ${FLAG}") + endforeach() + + # Add the output file + set(LINK_COMMAND "${LINK_COMMAND} -o ${output_name}") + + foreach(source ${file_names}) + # Get the relative path to the source and object files + file(RELATIVE_PATH OBJ_FILE ${CMAKE_CURRENT_BINARY_DIR} ${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/${target}.dir/${source}.${OBJ_EXTENSION}) + + # Add the source file and the output file + set(LINK_COMMAND "${LINK_COMMAND} ${OBJ_FILE}") + endforeach() + + # Add all the potential library paths + foreach(LIB_PATH ${USER_LIB_PATHS}) + if(NOT IS_ABSOLUTE ${LIB_PATH}) + file(RELATIVE_PATH LIB_PATH ${CMAKE_CURRENT_BINARY_DIR} ${CMAKE_CURRENT_LIST_DIR}/${LIB_PATH}) + endif() + if(NOT WIN32) + set(LINK_COMMAND "${LINK_COMMAND} -L${LIB_PATH}") + else() + set(LINK_COMMAND "${LINK_COMMAND} -L${LIB_PATH} -Wl,-rpath,${LIB_PATH}") + endif() + endforeach() + + # Add all the potential includes + foreach(LIB ${USER_LIBS}) + set(LINK_COMMAND "${LINK_COMMAND} -l${LIB}") + endforeach() + + set(LINK_COMMAND "${LINK_COMMAND}" PARENT_SCOPE) + +endfunction() + +# Windows executable is going to have the .exe extension +if(WIN32) + set(EXECUTABLE_EXTENSION ".exe") +endif() + +# Display the compile instructions in the emulation flow +getCompileCommands("${COMMON_COMPILE_FLAGS}" "${EMULATOR_COMPILE_FLAGS}" "${COMMON_LINK_FLAGS}" "${EMULATOR_LINK_FLAGS}" "${EMULATOR_TARGET}" "${EMULATOR_OUTPUT_NAME}${EXECUTABLE_EXTENSION}") + +add_custom_target( displayEmulationCompileCommands ALL + ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" + COMMENT "To compile manually:\n${COMPILE_COMMAND}\nTo link manually:\n${LINK_COMMAND}") +add_dependencies(${EMULATOR_TARGET} displayEmulationCompileCommands) + +# Display the compile instructions in the simulation flow +getCompileCommands("${COMMON_COMPILE_FLAGS}" "${SIMULATOR_COMPILE_FLAGS}" "${COMMON_LINK_FLAGS}" "${SIMULATOR_LINK_FLAGS}" "${SIMULATOR_TARGET}" "${SIMULATOR_OUTPUT_NAME}${EXECUTABLE_EXTENSION}") + +add_custom_target( displaySimulationCompileCommands ALL + ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" + COMMENT "To compile manually:\n${COMPILE_COMMAND}\nTo link manually:\n${LINK_COMMAND}") +add_dependencies(${SIMULATOR_TARGET} displaySimulationCompileCommands) + +# Display the compile instructions in the report flow +getCompileCommands("${COMMON_COMPILE_FLAGS}" "${REPORT_COMPILE_FLAGS}" "${MODIFIED_COMMON_LINK_FLAGS_REPORT}" "${REPORT_LINK_FLAGS}" "${REPORT_TARGET}" "${REPORT_OUTPUT_NAME}${EXECUTABLE_EXTENSION}") + +add_custom_target( displayReportCompileCommands ALL + ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" + COMMENT "To compile manually:\n${COMPILE_COMMAND}\nTo link manually:\n${LINK_COMMAND}") +add_dependencies(${REPORT_TARGET} displayReportCompileCommands) + +# Display the compile instructions in the IP export flow (Remove after native host pipes work properly) +getCompileCommands("${COMMON_COMPILE_FLAGS}" "${IP_EXPORT_COMPILE_FLAGS}" "${MODIFIED_COMMON_LINK_FLAGS_EXPORT}" "${IP_EXPORT_LINK_FLAGS}" "${IP_EXPORT_TARGET}" "${IP_EXPORT_OUTPUT_NAME}${EXECUTABLE_EXTENSION}") + +add_custom_target( displayExportCompileCommands ALL + ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" + COMMENT "To compile manually:\n${COMPILE_COMMAND}\nTo link manually:\n${LINK_COMMAND}") +add_dependencies(${IP_EXPORT_TARGET} displayExportCompileCommands) + +# Display the compile instructions in the fpga flow +getCompileCommands("${COMMON_COMPILE_FLAGS}" "${FPGA_COMPILE_FLAGS}" "${COMMON_LINK_FLAGS}" "${FPGA_LINK_FLAGS}" "${FPGA_TARGET}" "${FPGA_OUTPUT_NAME}${EXECUTABLE_EXTENSION}") + +add_custom_target( displayFPGACompileCommands ALL + ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" + COMMENT "To compile manually:\n${COMPILE_COMMAND}\nTo link manually:\n${LINK_COMMAND}") +add_dependencies(${FPGA_TARGET} displayFPGACompileCommands) \ No newline at end of file diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt deleted file mode 100644 index 350f137840..0000000000 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/CMakeLists.txt +++ /dev/null @@ -1,165 +0,0 @@ -############################################################################### -### Customize these build variables -############################################################################### -set(SOURCE_FILE fpga_template.cpp) -set(TARGET_NAME fpga_template) - -# Use cmake -DFPGA_DEVICE=: to choose a -# different device. Here are a few device examples (this list is not -# exhaustive): -# intel_s10sx_pac:pac_s10 -# intel_s10sx_pac:pac_s10_usm -# intel_a10gx_pac:pac_a10 -# Note that depending on your installation, you may need to specify the full -# path to the board support package (BSP), this usually is in your install -# folder. -# -# You can also specify a device family (E.g. "Arria10" or "Stratix10") or a -# specific part number (E.g. "10AS066N3F40E2SG") to generate a standalone IP. -if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_s10sx_pac:pac_s10_usm") -endif() - -# Use cmake -DUSER_FPGA_FLAGS= to set extra flags for FPGA backend -# compilation. -set(USER_FPGA_FLAGS "${USER_FPGA_FLAGS}") - -# Use cmake -DUSER_FLAGS= to set extra flags for general compilation. -set(USER_FLAGS "${USER_FLAGS}") - -# Use cmake -DUSER_INCLUDE_PATHS= to set extra paths for general -# compilation. -set(USER_INCLUDE_PATHS "${USER_INCLUDE_PATHS}") -############################################################################### -### no changes after here -############################################################################### - -set(INCLUDEPATHS_LIST ${USER_INCLUDE_PATHS}) -separate_arguments(INCLUDEPATHS_LIST) -include_directories(${INCLUDEPATHS_LIST}) - -set(EMULATOR_EXTENSION fpga_emu) -set(REPORT_EXTENSION report) -set(SIMULATOR_EXTENSION fpga_sim) -set(FPGA_EXTENSION fpga) -set(IP_EXPORT_EXTENSION fpga_ip_export) - -# define the different build targets the generated build script will support. -set(EMULATOR_TARGET ${TARGET_NAME}.${EMULATOR_EXTENSION}) -set(REPORT_TARGET ${TARGET_NAME}.${REPORT_EXTENSION}) -set(SIMULATOR_TARGET ${TARGET_NAME}.${SIMULATOR_EXTENSION}) -set(FPGA_TARGET ${TARGET_NAME}.${FPGA_EXTENSION}) -set(IP_EXPORT_TARGET ${TARGET_NAME}.${IP_EXPORT_EXTENSION}) - -# FPGA device selection -if(DEFINED FPGA_DEVICE) - message(STATUS "Configuring the design to run on ${FPGA_DEVICE}") -endif() - -# This is a Windows-specific flag that enables exception handling in host code -if(WIN32) - # add qactypes to link command on Windows only - set(QACTYPES_COMPILE "/Qactypes") - set(QACTYPES_LINK "/Qactypes") - set(WIN_FLAG "/EHsc") -else() - # add qactypes for Linux - set(QACTYPES_COMPILE "-qactypes") - set(QACTYPES_LINK "-qactypes") -endif() - -# A DPC++ ahead-of-time (AoT) compile processes the device code in two stages. -# 1. The "compile" stage compiles the device code to an intermediate -# representation (SPIR-V). -# 2. The "link" stage invokes the compiler's FPGA backend before linking. For -# this reason, FPGA backend flags must be passed as link flags in CMake. - -set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_EMULATOR ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") -set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_EMULATOR ${QACTYPES_LINK} ${USER_FLAGS} ") -set(REPORT_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") -set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${USER_FLAGS} ${USER_FPGA_FLAGS} -Xstarget=${FPGA_DEVICE} -Xshardware -fsycl-link=early") -set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_SIMULATOR ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") -set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_SIMULATOR ${QACTYPES_LINK} ${USER_FLAGS} ${USER_FPGA_FLAGS} -Xstarget=${FPGA_DEVICE} -Xssimulation -Xsghdl=1") -set(FULL_SYSTEM_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") -set(FULL_SYSTEM_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_LINK} ${USER_FLAGS} ${USER_FPGA_FLAGS} -Xstarget=${FPGA_DEVICE} -Xshardware") - -# get rid of this once host pipes work properly -set(IP_EXPORT_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${QACTYPES_COMPILE} ${USER_FLAGS} ${EXPERIMENTAL_INCLUDE} ${WIN_FLAG}") -set(IP_EXPORT_LINK_FLAGS "-fsycl -fintelfpga -DFPGA_HARDWARE ${USER_FLAGS} ${USER_FPGA_FLAGS} -Xstarget=${FPGA_DEVICE} -Xshardware -fsycl-link=early -fsycl-device-code-split=per_kernel") - -# remove extra spaces -string(REGEX REPLACE "( +)" " " EMULATOR_COMPILE_FLAGS ${EMULATOR_COMPILE_FLAGS}) -string(REGEX REPLACE "( +)" " " EMULATOR_LINK_FLAGS ${EMULATOR_LINK_FLAGS}) -string(REGEX REPLACE "( +)" " " REPORT_COMPILE_FLAGS ${REPORT_COMPILE_FLAGS}) -string(REGEX REPLACE "( +)" " " REPORT_LINK_FLAGS ${REPORT_LINK_FLAGS}) -string(REGEX REPLACE "( +)" " " SIMULATOR_COMPILE_FLAGS ${SIMULATOR_COMPILE_FLAGS}) -string(REGEX REPLACE "( +)" " " SIMULATOR_LINK_FLAGS ${SIMULATOR_LINK_FLAGS}) -string(REGEX REPLACE "( +)" " " FULL_SYSTEM_COMPILE_FLAGS ${FULL_SYSTEM_COMPILE_FLAGS}) -string(REGEX REPLACE "( +)" " " FULL_SYSTEM_COMPILE_FLAGS ${FULL_SYSTEM_COMPILE_FLAGS}) -string(REGEX REPLACE "( +)" " " IP_EXPORT_COMPILE_FLAGS ${IP_EXPORT_COMPILE_FLAGS}) -string(REGEX REPLACE "( +)" " " IP_EXPORT_LINK_FLAGS ${IP_EXPORT_LINK_FLAGS}) -############################################################################### -### FPGA Emulator -############################################################################### -# To compile in a single command: -# icpx -fsycl -fintelfpga -DFPGA_EMULATOR fpga_compile.cpp -o fpga_compile.fpga_emu -# CMake executes: -# [compile] icpx -fsycl -fintelfpga -DFPGA_EMULATOR -o fpga_compile.cpp.o -c fpga_compile.cpp -# [link] icpx -fsycl -fintelfpga fpga_compile.cpp.o -o fpga_compile.fpga_emu -add_executable(${EMULATOR_TARGET} ${SOURCE_FILE}) -add_custom_target(${EMULATOR_EXTENSION} DEPENDS ${EMULATOR_TARGET}) -set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_COMPILE_FLAGS}") -set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS}") - -############################################################################### -### Report -############################################################################### -# To compile manually: -# icpx -fsycl -fintelfpga -Xshardware -Xstarget= -fsycl-link=early fpga_compile.cpp -o fpga_compile.report.a -set(REPORT_TARGET ${TARGET_NAME}.report.a) -# The compile output is not an executable, but an intermediate compilation result unique to DPC++. -add_executable(${REPORT_TARGET} ${SOURCE_FILE}) -add_custom_target(${REPORT_EXTENSION} DEPENDS ${REPORT_TARGET}) -set_target_properties(${REPORT_TARGET} PROPERTIES COMPILE_FLAGS "${REPORT_COMPILE_FLAGS}") -set_target_properties(${REPORT_TARGET} PROPERTIES LINK_FLAGS "${REPORT_LINK_FLAGS}") - -############################################################################### -### FPGA Simulation -############################################################################### -# To compile in a single command: -# icpx -fsycl -fintelfpga -Xstarget= -Xssimulation -Xsghdl=1 fpga_compile.cpp -o fpga_compile.fpga_sim -# CMake executes: -# [compile] icpx -fsycl -fintelfpga -o fpga_compile.cpp.o -c fpga_compile.cpp -# [link] icpx -fsycl -fintelfpga -Xstarget= -Xssimulation -Xsghdl=1 fpga_compile.cpp.o -o fpga_compile.fpga_sim -add_executable(${SIMULATOR_TARGET} EXCLUDE_FROM_ALL ${SOURCE_FILE}) -add_custom_target(${SIMULATOR_EXTENSION} DEPENDS ${SIMULATOR_TARGET}) -set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${SIMULATOR_COMPILE_FLAGS}") -set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${SIMULATOR_LINK_FLAGS}") - -############################################################################### -### FPGA Board -############################################################################### -# To compile in a single command: -# icpx -fsycl -fintelfpga -Xshardware -Xstarget= fpga_compile.cpp -o fpga_compile.fpga -# CMake executes: -# [compile] icpx -fsycl -fintelfpga -o fpga_compile.cpp.o -c fpga_compile.cpp -# [link] icpx -fsycl -fintelfpga -Xshardware -Xstarget= fpga_compile.cpp.o -o fpga_compile.fpga -add_executable(${FPGA_TARGET} EXCLUDE_FROM_ALL ${SOURCE_FILE}) -add_custom_target(${FPGA_EXTENSION} DEPENDS ${FPGA_TARGET}) -set_target_properties(${FPGA_TARGET} PROPERTIES COMPILE_FLAGS "${FULL_SYSTEM_COMPILE_FLAGS}") -set_target_properties(${FPGA_TARGET} PROPERTIES LINK_FLAGS "${FULL_SYSTEM_LINK_FLAGS}") - -############################################################################### -### FPGA IP Export (only necessary until native host pipes) -############################################################################### -# To compile in a single command: -# icpx -fsycl -fintelfpga -Xshardware -Xstarget= -fsycl-link=early -fsycl-device-code-split=per_kernel fpga_compile.cpp -o fpga_compile.fpga_ip_export -# CMake executes: -# [compile] icpx -fsycl -fintelfpga -o fpga_compile.cpp.o -c fpga_compile.cpp -# [link] icpx -fsycl -fintelfpga -Xshardware -Xstarget= fpga_compile.cpp.o -o fpga_compile.fpga_ip_export -set(IP_EXPORT_TARGET ${TARGET_NAME}.fpga_ip_export.a) -# The compile output is not an executable, but an intermediate compilation result unique to DPC++. -add_executable(${IP_EXPORT_TARGET} ${SOURCE_FILE}) -add_custom_target(${IP_EXPORT_EXTENSION} DEPENDS ${IP_EXPORT_TARGET}) -set_target_properties(${IP_EXPORT_TARGET} PROPERTIES COMPILE_FLAGS "${IP_EXPORT_COMPILE_FLAGS}") -set_target_properties(${IP_EXPORT_TARGET} PROPERTIES LINK_FLAGS "${IP_EXPORT_LINK_FLAGS}") From 96ea1825acd0bd95476fd5747bbe59d03a7c05ca Mon Sep 17 00:00:00 2001 From: "White, Paul" Date: Tue, 17 Jan 2023 11:20:42 -0800 Subject: [PATCH 12/22] remove lib paths and lib because it doesn't work on windows --- .../experimental/fpga_template/CMakeLists.txt | 8 +- .../experimental/fpga_template/README.md | 8 +- .../fpga_template/src/fpga_template.cpp | 158 +++++++++--------- 3 files changed, 86 insertions(+), 88 deletions(-) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/CMakeLists.txt index 6ac9ba50d1..f0f11a6356 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/CMakeLists.txt @@ -47,13 +47,7 @@ set(USER_FLAGS ${USER_FLAGS}) # Use cmake -DUSER_INCLUDE_PATHS= to set extra paths for general # compilation. -set(USER_INCLUDE_PATHS ${USER_INCLUDE_PATHS} ../../../../include/) - -# Use cmake -DUSER_LIB_PATHS= to set extra paths to target_link_libraries -set(USER_LIB_PATHS ${USER_LIB_PATHS}) - -# Use cmake -DUSER_LIBS= to add extra static libraries -set(USER_LIBS ${USER_LIBS}) +set(USER_INCLUDE_PATHS ../../../../include;${USER_INCLUDE_PATHS}) ############################################################################### ### no changes after here diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md index 19d668a268..6767895347 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md @@ -37,7 +37,7 @@ Use this project as a starting point when you build designs for the Intel® oneA ############################################################################### ### Customize these build variables ############################################################################### -set(SOURCE_FILE fpga_template.cpp) +set(SOURCE_FILES src/fpga_template.cpp) set(TARGET_NAME fpga_template) # Use cmake -DFPGA_DEVICE=: to choose a @@ -58,14 +58,14 @@ endif() # Use cmake -DUSER_FPGA_FLAGS= to set extra flags for FPGA backend # compilation. -set(USER_FPGA_FLAGS "${USER_FPGA_FLAGS}") +set(USER_FPGA_FLAGS ${USER_FPGA_FLAGS}) # Use cmake -DUSER_FLAGS= to set extra flags for general compilation. -set(USER_FLAGS "${USER_FLAGS}") +set(USER_FLAGS ${USER_FLAGS}) # Use cmake -DUSER_INCLUDE_PATHS= to set extra paths for general # compilation. -set(USER_INCLUDE_PATHS "${USER_INCLUDE_PATHS}") +set(USER_INCLUDE_PATHS ../../../../include;${USER_INCLUDE_PATHS}) ``` Everything below this in the `src/CMakeLists.txt` is necessary for selecting the compiler flags that are necessary to support the build targets specified below, and should not need to be modified. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/fpga_template.cpp b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/fpga_template.cpp index e3fb32ee32..7057d8dab9 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/fpga_template.cpp +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/fpga_template.cpp @@ -1,6 +1,7 @@ #include // oneAPI headers +#include "exception_handler.hpp" #include #include @@ -9,103 +10,106 @@ class vector_add_ID; class vector_add { - public: - int *A_in; - int *B_in; - int *C_out; - int len; - - void operator()() const { - for (int idx = 0; idx < len; idx++) { - int a_val = A_in[idx]; - int b_val = B_in[idx]; - int sum = a_val + b_val; - C_out[idx] = sum; + public: + int *A_in; + int *B_in; + int *C_out; + int len; + + void operator()() const { + for (int idx = 0; idx < len; idx++) { + int a_val = A_in[idx]; + int b_val = B_in[idx]; + int sum = a_val + b_val; + C_out[idx] = sum; + } } - } }; #define VECT_SIZE 256 int main() { - bool passed = false; + bool passed = false; - try { + try { // This design is tested with 2023.0, but also accounts for a syntax change in // 2023.1 #if __INTEL_CLANG_COMPILER >= 20230100 #if FPGA_SIMULATOR - std::cout << "using FPGA Simulator." << std::endl; - sycl::queue q(sycl::ext::intel::fpga_simulator_selector_v); + std::cout << "using FPGA Simulator." << std::endl; + auto selector = sycl::ext::intel::fpga_simulator_selector_v; #elif FPGA_HARDWARE - std::cout << "using FPGA Hardware." << std::endl; - sycl::queue q(sycl::ext::intel::fpga_selector_v); -#else // #if FPGA_EMULATOR - std::cout << "using FPGA Emulator." << std::endl; - sycl::queue q(sycl::ext::intel::fpga_emulator_selector_v); + std::cout << "using FPGA Hardware." << std::endl; + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + std::cout << "using FPGA Emulator." << std::endl; + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif #elif __INTEL_CLANG_COMPILER >= 20230000 #if FPGA_SIMULATOR - std::cout << "using FPGA Simulator." << std::endl; - sycl::queue q(sycl::ext::intel::fpga_simulator_selector{}); + std::cout << "using FPGA Simulator." << std::endl; + auto selector = sycl::ext::intel::fpga_simulator_selector{}; #elif FPGA_HARDWARE - std::cout << "using FPGA Hardware." << std::endl; - sycl::queue q(sycl::ext::intel::fpga_selector{}); -#else // #if FPGA_EMULATOR - std::cout << "using FPGA Emulator." << std::endl; - sycl::queue q(sycl::ext::intel::fpga_emulator_selector{}); + std::cout << "using FPGA Hardware." << std::endl; + auto selector = sycl::ext::intel::fpga_selector{}; +#else // #if FPGA_EMULATOR + std::cout << "using FPGA Emulator." << std::endl; + auto selector = sycl::ext::intel::fpga_emulator_selector{}; #endif #else - assert(false) && "this design requires oneAPI 2023.0 or 2023.1!" + assert(false) && "this design requires oneAPI 2023.0 or 2023.1!" #endif - int count = VECT_SIZE; // pass array size by value - - // declare arrays and fill them - // allocate in shared memory so the kernel can see them - int *A = sycl::malloc_shared(count, q); - int *B = sycl::malloc_shared(count, q); - int *C = sycl::malloc_shared(count, q); - for (int i = 0; i < count; i++) { - A[i] = i; - B[i] = (count - i); - } - - std::cout << "add two vectors of size " << count << std::endl; - - q.single_task(vector_add{A, B, C, count}).wait(); - - // verify that VC is correct - passed = true; - for (int i = 0; i < count; i++) { - int expected = A[i] + B[i]; - if (C[i] != expected) { - std::cout << "idx=" << i << ": result " << C[i] << ", expected (" - << expected << ") A=" << A[i] << " + B=" << B[i] << std::endl; - passed = false; - } - } - - std::cout << (passed ? "PASSED" : "FAILED") << std::endl; - - sycl::free(A, q); - sycl::free(B, q); - sycl::free(C, q); - - } catch (sycl::exception const &e) { - // Catches exceptions in the host code. - std::cerr << "Caught a SYCL host exception:\n" << e.what() << "\n"; - - // Most likely the runtime couldn't find FPGA hardware! - if (e.code().value() == CL_DEVICE_NOT_FOUND) { - std::cerr << "If you are targeting an FPGA, please ensure that your " - "system has a correctly configured FPGA board.\n"; - std::cerr << "Run sys_check in the oneAPI root directory to verify.\n"; - std::cerr << "If you are targeting the FPGA emulator, compile with " - "-DFPGA_EMULATOR.\n"; + sycl::queue q(selector, fpga_tools::exception_handler, + sycl::property::queue::enable_profiling{}); + + int count = VECT_SIZE; // pass array size by value + + // declare arrays and fill them + // allocate in shared memory so the kernel can see them + int *A = sycl::malloc_shared(count, q); + int *B = sycl::malloc_shared(count, q); + int *C = sycl::malloc_shared(count, q); + for (int i = 0; i < count; i++) { + A[i] = i; + B[i] = (count - i); + } + + std::cout << "add two vectors of size " << count << std::endl; + + q.single_task(vector_add{A, B, C, count}).wait(); + + // verify that VC is correct + passed = true; + for (int i = 0; i < count; i++) { + int expected = A[i] + B[i]; + if (C[i] != expected) { + std::cout << "idx=" << i << ": result " << C[i] << ", expected (" + << expected << ") A=" << A[i] << " + B=" << B[i] << std::endl; + passed = false; + } + } + + std::cout << (passed ? "PASSED" : "FAILED") << std::endl; + + sycl::free(A, q); + sycl::free(B, q); + sycl::free(C, q); + } catch (sycl::exception const &e) { + // Catches exceptions in the host code. + std::cerr << "Caught a SYCL host exception:\n" + << e.what() << "\n"; + + // Most likely the runtime couldn't find FPGA hardware! + if (e.code().value() == CL_DEVICE_NOT_FOUND) { + std::cerr << "If you are targeting an FPGA, please ensure that your " + "system has a correctly configured FPGA board.\n"; + std::cerr << "Run sys_check in the oneAPI root directory to verify.\n"; + std::cerr << "If you are targeting the FPGA emulator, compile with " + "-DFPGA_EMULATOR.\n"; + } + std::terminate(); } - std::terminate(); - } - return passed ? EXIT_SUCCESS : EXIT_FAILURE; + return passed ? EXIT_SUCCESS : EXIT_FAILURE; } \ No newline at end of file From 593508d381c3595a9ad6557729cbef41eaefeb8b Mon Sep 17 00:00:00 2001 From: "White, Paul" Date: Wed, 18 Jan 2023 01:43:59 -0800 Subject: [PATCH 13/22] minor readme tweaks --- .../GettingStarted/experimental/fpga_template/README.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md index 6767895347..a2764aee73 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md @@ -31,7 +31,7 @@ Use this project as a starting point when you build designs for the Intel® oneA |:--- |:--- | `USER_HARDWARE_FLAGS` | This space-separated list of flags applies only to flows that generate FPGA hardware (i.e. report, simulation, hardware). You can specify flags such as `-Xsclock` or `-Xshyper-optimized-handshaking=off` | `USER_FLAGS` | This space-separated list of flags applies to all flows, including emulation. You can specify flags such as `-v` or define macros such as `-DYOUR_OWN_MACRO=3` -| `USER_INCLUDE_PATHS` | This space-separated list of include paths applies to all flows, including emulation. Specify include paths relative to the `src/CMakeLists.txt` file, or using absolute paths in the filesystem. +| `USER_INCLUDE_PATHS` | This semicolon-separated list of include paths applies to all flows, including emulation. Specify include paths relative to the `src/CMakeLists.txt` file, or using absolute paths in the filesystem. ```bash ############################################################################### @@ -135,6 +135,7 @@ This design uses CMake to generate a build script for GNU/make. | `make report` | Minutes | RTL + FPGA reports | Compiles the FPGA device code to RTL and generates an optimization report that describes the structures generated on the FPGA, identifies performance bottlenecks, and estimates resource utilization. This report will include the interfaces defined in your selected Board Support Package. | `make fpga_sim` | Minutes | RTL + FPGA reports + x86-64 binary | Compiles the FPGA device code to RTL and generates a simulation testbench. Use the Questa*-Intel® FPGA Edition simulator to verify your design. | `make fpga` | Multiple Hours | Quartus Place & Route (Full accelerator) + FPGA reports + x86-64 host binary | Compiles the FPGA device code to RTL and generate an FPGA image that you can run on a supported accelerator board. + | `make fpga_ip_export` | Minutes | RTL + FPGA reports | Compiles the FPGA device code to RTL that may be exported to Intel® Quartus Prime software The `fpga_emu`, `fpga_sim` and `fpga` targets produce binaries that you can run. The executables will be called `TARGET_NAME.fpga_emu`, `TARGET_NAME.fpga_sim`, and `TARGET_NAME.fpga`, where `TARGET_NAME` is the value you specify in `src/CMakeLists.txt`. @@ -171,6 +172,7 @@ This design uses CMake to generate a build script for `nmake`. | `nmake report` | Minutes | RTL + FPGA reports | Compiles the FPGA device code to RTL and generates an optimization report that describes the structures generated on the FPGA, identifies performance bottlenecks, and estimates resource utilization. This report will include the interfaces defined in your selected Board Support Package. | `nmake fpga_sim` | Minutes | RTL + FPGA reports + x86-64 binary | Compiles the FPGA device code to RTL and generates a simulation testbench. Use the Questa*-Intel® FPGA Edition simulator to verify your design. | `nmake fpga` | Multiple Hours | Quartus Place & Route (Full accelerator) + FPGA reports + x86-64 host binary | Compiles the FPGA device code to RTL and generate an FPGA image that you can run on a supported accelerator board. + | `nmake fpga_ip_export` | Minutes | RTL + FPGA reports | Compiles the FPGA device code to RTL that may be exported to Intel® Quartus Prime software The `fpga_emu`, `fpga_sim`, and `fpga` targets also produce binaries that you can run. The executables will be called `TARGET_NAME.fpga_emu.exe`, `TARGET_NAME.fpga_sim.exe`, and `TARGET_NAME.fpga.exe`, where `TARGET_NAME` is the value you specify in `src/CMakeLists.txt`. From b04e525fb63e0f69b115d9d96ea43d084e6e7926 Mon Sep 17 00:00:00 2001 From: "White, Paul" Date: Thu, 19 Jan 2023 03:13:07 -0800 Subject: [PATCH 14/22] Yohann's changes --- .../experimental/fpga_template/CMakeLists.txt | 4 +- .../experimental/fpga_template/README.md | 92 +++++----- .../experimental/fpga_template/sample.json | 29 +-- .../fpga_template/src/fpga_template.cpp | 167 +++++++++--------- 4 files changed, 128 insertions(+), 164 deletions(-) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/CMakeLists.txt index f0f11a6356..aed11e6649 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/CMakeLists.txt @@ -82,10 +82,10 @@ message(STATUS "Additional USER_LIB_PATHS=${USER_LIB_PATHS}") link_libraries(${USER_LIBS}) message(STATUS "Additional USER_LIBS=${USER_LIBS}") -# This is a Windows-specific flag that enables exception handling in host code if(WIN32) - # add qactypes to link command on Windows only + # add qactypes for Windows set(QACTYPES "-Qactypes") + # This is a Windows-specific flag that enables exception handling in host code set(WIN_FLAG "/EHsc") else() # add qactypes for Linux diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md index a2764aee73..12220c8242 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md @@ -21,9 +21,32 @@ This project serves as a template for Intel® oneAPI FPGA designs. > **Note**: In oneAPI full systems, kernels that use SYCL Unified Shared Memory (USM) host allocations or USM shared allocations (and therefore the code in this tutorial) are only supported by Board Support Packages (BSPs) with USM support (e.g. the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) `intel_s10sx_pac:pac_s10_usm`). Kernels that use these types of allocations can always be used to generate standalone IPs. +## Prerequisites + +This sample is part of the FPGA code samples. +It is categorized as a Tier 1 sample that helps you getting started. + +```mermaid +flowchart LR + tier1("Tier 1: Get Started") + tier2("Tier 2: Explore the Fundamentals") + tier3("Tier 3: Explore the Advanced Techniques") + tier4("Tier 4: Explore the Reference Designs") + + tier1 --> tier2 --> tier3 --> tier4 + + style tier1 fill:#f96,stroke:#333,stroke-width:1px,color:#fff + style tier2 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff + style tier3 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff + style tier4 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff +``` + +Find more information about how to navigate this part of the code samples in the [FPGA top-level README.md](/DirectProgramming/DPC++FPGA/README.md). +You can also find more information about [troubleshooting build errors](/DirectProgramming/DPC++FPGA/README.md#troubleshooting), [running the sample on the Intel® DevCloud](/DirectProgramming/DPC++FPGA/README.md#build-and-run-the-samples-on-intel-devcloud-optional), [using Visual Studio Code with the code samples](/DirectProgramming/DPC++FPGA/README.md#use-visual-studio-code-vs-code-optional), [links to selected documentation](/DirectProgramming/DPC++FPGA/README.md#documentation), etc. + ## Purpose -Use this project as a starting point when you build designs for the Intel® oneAPI FPGA compiler. It includes a CMake build system to automate selecting the various command-line flags for the oneAPI FPGA compiler, and a simple single-source design to serve as an example. You can customize the build flags by modifying the top part of `src/CMakeLists.txt`: if you want to pass additional flags to the Intel® oneAPI FPGA compiler, you can change the `USER_FLAGS` and `USER_HARDWARE_FLAGS` variables defined in `src/CMakeLists.txt`. Similarly, you can add additional include paths to the `USER_INCLUDE_PATHS` variable. You can also explictly define these variables at the command-line if you don't want to make change to the CMake build system. +Use this project as a starting point when you build designs for the Intel® oneAPI DPC++/C++ compiler when targeting FPGAs. It includes a CMake build system to automate selecting the various command-line flags for the oneAPI DPC++/C++ compiler, and a simple single-source design to serve as an example. You can customize the build flags by modifying the top part of `CMakeLists.txt`: if you want to pass additional flags to the Intel® oneAPI DPC++/C++ compiler, you can change the `USER_FLAGS` and `USER_HARDWARE_FLAGS` variables defined in `CMakeLists.txt`. Similarly, you can add additional include paths to the `USER_INCLUDE_PATHS` variable. You can also explicitly define these variables at the command-line if you don't want to make change to the CMake build system. > **Note**: The code sample in this design only uses USM for improved code simplicity as compared with buffers/accessors. The included CMake build system can also be used for designs that do not use USM. @@ -31,7 +54,7 @@ Use this project as a starting point when you build designs for the Intel® oneA |:--- |:--- | `USER_HARDWARE_FLAGS` | This space-separated list of flags applies only to flows that generate FPGA hardware (i.e. report, simulation, hardware). You can specify flags such as `-Xsclock` or `-Xshyper-optimized-handshaking=off` | `USER_FLAGS` | This space-separated list of flags applies to all flows, including emulation. You can specify flags such as `-v` or define macros such as `-DYOUR_OWN_MACRO=3` -| `USER_INCLUDE_PATHS` | This semicolon-separated list of include paths applies to all flows, including emulation. Specify include paths relative to the `src/CMakeLists.txt` file, or using absolute paths in the filesystem. +| `USER_INCLUDE_PATHS` | This semicolon-separated list of include paths applies to all flows, including emulation. Specify include paths relative to the `CMakeLists.txt` file, or using absolute paths in the filesystem. ```bash ############################################################################### @@ -68,7 +91,7 @@ set(USER_FLAGS ${USER_FLAGS}) set(USER_INCLUDE_PATHS ../../../../include;${USER_INCLUDE_PATHS}) ``` -Everything below this in the `src/CMakeLists.txt` is necessary for selecting the compiler flags that are necessary to support the build targets specified below, and should not need to be modified. +Everything below this in the `CMakeLists.txt` is necessary for selecting the compiler flags that are necessary to support the build targets specified below, and should not need to be modified. ## Building the `fpga_template` Tutorial @@ -86,21 +109,6 @@ Everything below this in the `src/CMakeLists.txt` is necessary for selecting the > >For more information on environment variables, see **Use the setvars Script** for [Linux or macOS](https://www.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/oneapi-development-environment-setup/use-the-setvars-script-with-linux-or-macos.html), or [Windows](https://www.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/oneapi-development-environment-setup/use-the-setvars-script-with-windows.html). -### Running Samples in Intel® DevCloud -If running a sample in the Intel® DevCloud, remember that you must specify the type of compute node and whether to run in batch or interactive mode. Compiles to FPGA are only supported on fpga_compile nodes. Executing programs on FPGA hardware is only supported on fpga_runtime nodes of the appropriate type, such as fpga_runtime:arria10 or fpga_runtime:stratix10. Neither compiling nor executing programs on FPGA hardware are supported on the login nodes. For more information, see the Intel® oneAPI Base Toolkit Get Started Guide ([https://devcloud.intel.com/oneapi/documentation/base-toolkit/](https://devcloud.intel.com/oneapi/documentation/base-toolkit/)). -When compiling for FPGA hardware, it is recommended to increase the job timeout to 12h. -### Using Visual Studio Code* (Optional) -You can use Visual Studio Code (VS Code) extensions to set your environment, create launch configurations, -and browse and download samples. -The basic steps to build and run a sample using VS Code include: - - Download a sample using the extension **Code Sample Browser for Intel® oneAPI Toolkits**. - - Configure the oneAPI environment with the extension **Environment Configurator for Intel® oneAPI Toolkits**. - - Open a Terminal in VS Code (**Terminal>New Terminal**). - - Run the sample in the VS Code terminal using the instructions below. - - (Linux only) Debug your GPU application with GDB for Intel® oneAPI toolkits using the **Generate Launch Configurations** extension. -To learn more about the extensions, see the -[Using Visual Studio Code with Intel® oneAPI Toolkits User Guide](https://www.intel.com/content/www/us/en/develop/documentation/using-vs-code-with-intel-oneapi/top.html). - Use these commands to run the design, depending on your OS. ### On a Linux* System @@ -134,10 +142,10 @@ This design uses CMake to generate a build script for GNU/make. | `make fpga_emu` | Seconds | x86-64 binary | Compiles the FPGA device code to the CPU. Use the Intel® FPGA Emulation Platform for OpenCL™ software to verify your SYCL code’s functional correctness. | `make report` | Minutes | RTL + FPGA reports | Compiles the FPGA device code to RTL and generates an optimization report that describes the structures generated on the FPGA, identifies performance bottlenecks, and estimates resource utilization. This report will include the interfaces defined in your selected Board Support Package. | `make fpga_sim` | Minutes | RTL + FPGA reports + x86-64 binary | Compiles the FPGA device code to RTL and generates a simulation testbench. Use the Questa*-Intel® FPGA Edition simulator to verify your design. - | `make fpga` | Multiple Hours | Quartus Place & Route (Full accelerator) + FPGA reports + x86-64 host binary | Compiles the FPGA device code to RTL and generate an FPGA image that you can run on a supported accelerator board. + | `make fpga` | Multiple Hours | Quartus Place & Route (Full accelerator) + FPGA reports + x86-64 host binary | Compiles the FPGA device code to RTL and compiles the generated RTL using Intel® Quartus® Prime. If you specified a BSP with `FPGA_DEVICE`, this will generate an FPGA image that you can run on the corresponding accelerator board. | `make fpga_ip_export` | Minutes | RTL + FPGA reports | Compiles the FPGA device code to RTL that may be exported to Intel® Quartus Prime software - The `fpga_emu`, `fpga_sim` and `fpga` targets produce binaries that you can run. The executables will be called `TARGET_NAME.fpga_emu`, `TARGET_NAME.fpga_sim`, and `TARGET_NAME.fpga`, where `TARGET_NAME` is the value you specify in `src/CMakeLists.txt`. + The `fpga_emu`, `fpga_sim` and `fpga` targets produce binaries that you can run. The executables will be called `TARGET_NAME.fpga_emu`, `TARGET_NAME.fpga_sim`, and `TARGET_NAME.fpga`, where `TARGET_NAME` is the value you specify in `CMakeLists.txt`. ### On a Windows* System This design uses CMake to generate a build script for `nmake`. @@ -161,9 +169,6 @@ This design uses CMake to generate a build script for `nmake`. cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: ``` - > **NOTE**: This design will **not** work on the Intel® PAC with Intel Arria® 10 GX FPGA, because the design depends on USM. - - 2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: | Target | Expected Time | Output | Description @@ -174,34 +179,12 @@ This design uses CMake to generate a build script for `nmake`. | `nmake fpga` | Multiple Hours | Quartus Place & Route (Full accelerator) + FPGA reports + x86-64 host binary | Compiles the FPGA device code to RTL and generate an FPGA image that you can run on a supported accelerator board. | `nmake fpga_ip_export` | Minutes | RTL + FPGA reports | Compiles the FPGA device code to RTL that may be exported to Intel® Quartus Prime software - The `fpga_emu`, `fpga_sim`, and `fpga` targets also produce binaries that you can run. The executables will be called `TARGET_NAME.fpga_emu.exe`, `TARGET_NAME.fpga_sim.exe`, and `TARGET_NAME.fpga.exe`, where `TARGET_NAME` is the value you specify in `src/CMakeLists.txt`. + The `fpga_emu`, `fpga_sim`, and `fpga` targets also produce binaries that you can run. The executables will be called `TARGET_NAME.fpga_emu.exe`, `TARGET_NAME.fpga_sim.exe`, and `TARGET_NAME.fpga.exe`, where `TARGET_NAME` is the value you specify in `CMakeLists.txt`. > **Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. > **Note**: If you encounter any issues with long paths when compiling under Windows*, you may have to create your ‘build’ directory in a shorter path, for example c:\samples\build. You can then run cmake from that directory, and provide cmake with the full path to your sample directory. -### Additional Documentation -- [Explore SYCL* Through Intel® FPGA Code Samples](https://software.intel.com/content/www/us/en/develop/articles/explore-dpcpp-through-intel-fpga-code-samples.html) helps you to navigate the samples and build your knowledge of FPGAs and SYCL. -- [FPGA Optimization Guide for Intel® oneAPI Toolkits](https://software.intel.com/content/www/us/en/develop/documentation/oneapi-fpga-optimization-guide) helps you understand how to target FPGAs using SYCL and Intel® oneAPI Toolkits. -- [Intel® oneAPI Programming Guide](https://software.intel.com/en-us/oneapi-programming-guide) helps you understand target-independent, SYCL-compliant programming using Intel® oneAPI Toolkits. - -### Troubleshooting -If an error occurs, you can get more details by running `make` with the `VERBOSE=1` argument (on Windows use `nmake` instead): - -``` -make VERBOSE=1 -``` - -``` -nmake VERBOSE=1 -``` - -For more comprehensive troubleshooting, use the Diagnostics Utility for Intel® oneAPI Toolkits, which provides system checks to find missing dependencies and permissions errors. [Learn more](https://www.intel.com/content/www/us/en/develop/documentation/diagnostic-utility-user-guide/top.html). - -### In Third-Party Integrated Development Environments (IDEs) - -You can compile and run this tutorial in the Eclipse* IDE (in Linux*) and the Visual Studio* IDE (in Windows*). For instructions, refer to the following link: [FPGA Workflows on Third-Party IDEs for Intel® oneAPI Toolkits](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-oneapi-dpcpp-fpga-workflow-on-ide.html). - ## Running the Sample 1. Run the sample on the FPGA emulator (the kernel executes on the CPU): @@ -213,12 +196,17 @@ You can compile and run this tutorial in the Eclipse* IDE (in Linux*) and the Vi 2. Run the sample on the FPGA simulator device: - > **NOTE**: you need to define the `CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 environment variable in oneAPI 2023.1 - - ``` - CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./fpga_template.fpga_sim (Linux) - cmd /V /C "set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1&& fpga_template.fpga_sim.exe" (Windows) - ``` + * On Linux + ```bash + CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./fpga_template.fpga_sim + ``` + + * On Windows + ```bash + set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 + fpga_template.fpga_sim.exe + set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= + ``` 3. Run the sample on the FPGA device: ``` diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/sample.json b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/sample.json index 748e9e594a..61bc3e08e2 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/sample.json +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/sample.json @@ -1,9 +1,9 @@ { "guid": "418AA4D8-0A61-4FDB-845A-CDA4DA0655E7", "name": "FPGA Template", - "categories": ["Toolkit/oneAPI Direct Programming/DPC++ FPGA/Getting Started Tutorials"], - "description": "This project serves as a template for Intel® oneAPI FPGA designs. ", - "toolchain": ["dpcpp"], + "categories": ["Toolkit/oneAPI Direct Programming/C++SYCL FPGA/Getting Started Tutorials"], + "description": "This project serves as a template for Intel® oneAPI DPC++/C++ designs targeting FPGAs. ", + "toolchain": ["icpx"], "os": ["linux", "windows"], "targetDevice": ["FPGA"], "builder": ["cmake"], @@ -39,17 +39,6 @@ "cmake ..", "make report" ] - }, - { - "id": "fpga_sim", - "steps": [ - "dpcpp --version", - "mkdir build", - "cd build", - "cmake ..", - "make fpga_sim", - "./fpga_template.fpga_sim" - ] } ], "windows": [ @@ -75,18 +64,6 @@ "cmake -G \"NMake Makefiles\" ../Tutorials/GettingStarted/experimental/fpga_template", "nmake report" ] - }, - { - "id": "fpga_sim", - "steps": [ - "dpcpp --version", - "cd ../../../..", - "mkdir build", - "cd build", - "cmake -G \"NMake Makefiles\" ../Tutorials/GettingStarted/experimental/fpga_template", - "nmake fpga_sim", - "fpga_template.fpga_sim.exe" - ] } ] }, diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/fpga_template.cpp b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/fpga_template.cpp index 7057d8dab9..8e0ca69dcc 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/fpga_template.cpp +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/fpga_template.cpp @@ -1,115 +1,114 @@ #include // oneAPI headers -#include "exception_handler.hpp" #include #include +#include "exception_handler.hpp" + // Forward declare the kernel name in the global scope. This is an FPGA best // practice that reduces name mangling in the optimization reports. -class vector_add_ID; - -class vector_add { - public: - int *A_in; - int *B_in; - int *C_out; - int len; - - void operator()() const { - for (int idx = 0; idx < len; idx++) { - int a_val = A_in[idx]; - int b_val = B_in[idx]; - int sum = a_val + b_val; - C_out[idx] = sum; - } +class VectorAddID; + +class VectorAdd { + public: + int *a_in; + int *b_in; + int *c_out; + int len; + + void operator()() const { + for (int idx = 0; idx < len; idx++) { + int a_val = a_in[idx]; + int b_val = b_in[idx]; + int sum = a_val + b_val; + c_out[idx] = sum; } + } }; #define VECT_SIZE 256 int main() { - bool passed = false; + bool passed = false; - try { + try { // This design is tested with 2023.0, but also accounts for a syntax change in // 2023.1 #if __INTEL_CLANG_COMPILER >= 20230100 #if FPGA_SIMULATOR - std::cout << "using FPGA Simulator." << std::endl; - auto selector = sycl::ext::intel::fpga_simulator_selector_v; + auto selector = sycl::ext::intel::fpga_simulator_selector_v; #elif FPGA_HARDWARE - std::cout << "using FPGA Hardware." << std::endl; - auto selector = sycl::ext::intel::fpga_selector_v; -#else // #if FPGA_EMULATOR - std::cout << "using FPGA Emulator." << std::endl; - auto selector = sycl::ext::intel::fpga_emulator_selector_v; + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif #elif __INTEL_CLANG_COMPILER >= 20230000 #if FPGA_SIMULATOR - std::cout << "using FPGA Simulator." << std::endl; - auto selector = sycl::ext::intel::fpga_simulator_selector{}; + auto selector = sycl::ext::intel::fpga_simulator_selector{}; #elif FPGA_HARDWARE - std::cout << "using FPGA Hardware." << std::endl; - auto selector = sycl::ext::intel::fpga_selector{}; -#else // #if FPGA_EMULATOR - std::cout << "using FPGA Emulator." << std::endl; - auto selector = sycl::ext::intel::fpga_emulator_selector{}; + auto selector = sycl::ext::intel::fpga_selector{}; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector{}; #endif #else - assert(false) && "this design requires oneAPI 2023.0 or 2023.1!" + assert(false) && "this design requires oneAPI 2023.0 or 2023.1!" #endif - sycl::queue q(selector, fpga_tools::exception_handler, - sycl::property::queue::enable_profiling{}); - - int count = VECT_SIZE; // pass array size by value - - // declare arrays and fill them - // allocate in shared memory so the kernel can see them - int *A = sycl::malloc_shared(count, q); - int *B = sycl::malloc_shared(count, q); - int *C = sycl::malloc_shared(count, q); - for (int i = 0; i < count; i++) { - A[i] = i; - B[i] = (count - i); - } - - std::cout << "add two vectors of size " << count << std::endl; - - q.single_task(vector_add{A, B, C, count}).wait(); - - // verify that VC is correct - passed = true; - for (int i = 0; i < count; i++) { - int expected = A[i] + B[i]; - if (C[i] != expected) { - std::cout << "idx=" << i << ": result " << C[i] << ", expected (" - << expected << ") A=" << A[i] << " + B=" << B[i] << std::endl; - passed = false; - } - } - - std::cout << (passed ? "PASSED" : "FAILED") << std::endl; - - sycl::free(A, q); - sycl::free(B, q); - sycl::free(C, q); - } catch (sycl::exception const &e) { - // Catches exceptions in the host code. - std::cerr << "Caught a SYCL host exception:\n" - << e.what() << "\n"; - - // Most likely the runtime couldn't find FPGA hardware! - if (e.code().value() == CL_DEVICE_NOT_FOUND) { - std::cerr << "If you are targeting an FPGA, please ensure that your " - "system has a correctly configured FPGA board.\n"; - std::cerr << "Run sys_check in the oneAPI root directory to verify.\n"; - std::cerr << "If you are targeting the FPGA emulator, compile with " - "-DFPGA_EMULATOR.\n"; - } - std::terminate(); + sycl::queue q(selector, fpga_tools::exception_handler, + sycl::property::queue::enable_profiling{}); + + auto device = q.get_device(); + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + + int count = VECT_SIZE; // pass array size by value + + // declare arrays and fill them + // allocate in shared memory so the kernel can see them + int *a = sycl::malloc_shared(count, q); + int *b = sycl::malloc_shared(count, q); + int *c = sycl::malloc_shared(count, q); + for (int i = 0; i < count; i++) { + a[i] = i; + b[i] = (count - i); + } + + std::cout << "add two vectors of size " << count << std::endl; + + q.single_task(VectorAdd{a, b, c, count}).wait(); + + // verify that VC is correct + passed = true; + for (int i = 0; i < count; i++) { + int expected = a[i] + b[i]; + if (c[i] != expected) { + std::cout << "idx=" << i << ": result " << c[i] << ", expected (" + << expected << ") A=" << a[i] << " + B=" << b[i] << std::endl; + passed = false; + } + } + + std::cout << (passed ? "PASSED" : "FAILED") << std::endl; + + sycl::free(a, q); + sycl::free(b, q); + sycl::free(c, q); + } catch (sycl::exception const &e) { + // Catches exceptions in the host code. + std::cerr << "Caught a SYCL host exception:\n" << e.what() << "\n"; + + // Most likely the runtime couldn't find FPGA hardware! + if (e.code().value() == CL_DEVICE_NOT_FOUND) { + std::cerr << "If you are targeting an FPGA, please ensure that your " + "system has a correctly configured FPGA board.\n"; + std::cerr << "Run sys_check in the oneAPI root directory to verify.\n"; + std::cerr << "If you are targeting the FPGA emulator, compile with " + "-DFPGA_EMULATOR.\n"; } + std::terminate(); + } - return passed ? EXIT_SUCCESS : EXIT_FAILURE; + return passed ? EXIT_SUCCESS : EXIT_FAILURE; } \ No newline at end of file From 9dc212e672533bd08c6cc6d04664cad8a654de4f Mon Sep 17 00:00:00 2001 From: "White, Paul" Date: Fri, 20 Jan 2023 10:52:11 -0800 Subject: [PATCH 15/22] move out of experimental dir --- .../{experimental => }/fpga_template/CMakeLists.txt | 2 +- .../{experimental => }/fpga_template/README.md | 0 .../{experimental => }/fpga_template/sample.json | 6 +++--- .../{experimental => }/fpga_template/src/fpga_template.cpp | 0 4 files changed, 4 insertions(+), 4 deletions(-) rename DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/{experimental => }/fpga_template/CMakeLists.txt (99%) rename DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/{experimental => }/fpga_template/README.md (100%) rename DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/{experimental => }/fpga_template/sample.json (92%) rename DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/{experimental => }/fpga_template/src/fpga_template.cpp (100%) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/CMakeLists.txt similarity index 99% rename from DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/CMakeLists.txt rename to DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/CMakeLists.txt index aed11e6649..6be94e3467 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/CMakeLists.txt @@ -47,7 +47,7 @@ set(USER_FLAGS ${USER_FLAGS}) # Use cmake -DUSER_INCLUDE_PATHS= to set extra paths for general # compilation. -set(USER_INCLUDE_PATHS ../../../../include;${USER_INCLUDE_PATHS}) +set(USER_INCLUDE_PATHS ../../../include;${USER_INCLUDE_PATHS}) ############################################################################### ### no changes after here diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/README.md similarity index 100% rename from DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/README.md rename to DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/README.md diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/sample.json b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/sample.json similarity index 92% rename from DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/sample.json rename to DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/sample.json index 61bc3e08e2..9627694c9e 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/sample.json +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/sample.json @@ -12,7 +12,7 @@ "base": "../../..", "include": [ "README.md", - "Tutorials/GettingStarted/experimental/fpga_template", + "Tutorials/GettingStarted/fpga_template", "include" ], "exclude": [] @@ -49,7 +49,7 @@ "cd ../../../..", "mkdir build", "cd build", - "cmake -G \"NMake Makefiles\" ../Tutorials/GettingStarted/experimental/fpga_template", + "cmake -G \"NMake Makefiles\" ../Tutorials/GettingStarted/fpga_template", "nmake fpga_emu", "fpga_template.fpga_emu.exe" ] @@ -61,7 +61,7 @@ "cd ../../../..", "mkdir build", "cd build", - "cmake -G \"NMake Makefiles\" ../Tutorials/GettingStarted/experimental/fpga_template", + "cmake -G \"NMake Makefiles\" ../Tutorials/GettingStarted/fpga_template", "nmake report" ] } diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/fpga_template.cpp b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp similarity index 100% rename from DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/experimental/fpga_template/src/fpga_template.cpp rename to DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp From f242ce9495fc81dd66fc92147e5e15a26ac3b56a Mon Sep 17 00:00:00 2001 From: "White, Paul" Date: Mon, 23 Jan 2023 06:18:41 -0800 Subject: [PATCH 16/22] minor edits from yohann's code review --- .../GettingStarted/fpga_template/README.md | 21 ++++++++++--------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/README.md index 12220c8242..5820e35bd5 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/README.md @@ -52,8 +52,8 @@ Use this project as a starting point when you build designs for the Intel® oneA | Variable | Description |:--- |:--- -| `USER_HARDWARE_FLAGS` | This space-separated list of flags applies only to flows that generate FPGA hardware (i.e. report, simulation, hardware). You can specify flags such as `-Xsclock` or `-Xshyper-optimized-handshaking=off` -| `USER_FLAGS` | This space-separated list of flags applies to all flows, including emulation. You can specify flags such as `-v` or define macros such as `-DYOUR_OWN_MACRO=3` +| `USER_HARDWARE_FLAGS` | This semicolon-separated list of flags applies only to flows that generate FPGA hardware (i.e. report, simulation, hardware). You can specify flags such as `-Xsclock` or `-Xshyper-optimized-handshaking=off` +| `USER_FLAGS` | This semicolon-separated list of flags applies to all flows, including emulation. You can specify flags such as `-v` or define macros such as `-DYOUR_OWN_MACRO=3` | `USER_INCLUDE_PATHS` | This semicolon-separated list of include paths applies to all flows, including emulation. Specify include paths relative to the `CMakeLists.txt` file, or using absolute paths in the filesystem. ```bash @@ -95,19 +95,20 @@ Everything below this in the `CMakeLists.txt` is necessary for selecting the com ## Building the `fpga_template` Tutorial -> **Note**: If you have not already done so, set up your CLI -> environment by sourcing the `setvars` script located in -> the root of your oneAPI installation. +> **Note**: When working with the command-line interface (CLI), you should configure the oneAPI toolkits using environment variables. +> Set up your CLI environment by sourcing the `setvars` script located in the root of your oneAPI installation every time you open a new terminal window. +> This practice ensures that your compiler, libraries, and tools are ready for development. > > Linux*: -> - For system wide installations: `/opt/intel/oneapi/setvars.sh` -> - For private installations: `~/intel/oneapi/setvars.sh` +> - For system wide installations: `. /opt/intel/oneapi/setvars.sh` +> - For private installations: ` . ~/intel/oneapi/setvars.sh` +> - For non-POSIX shells, like csh, use the following command: `bash -c 'source /setvars.sh ; exec csh'` > > Windows*: > - `C:\Program Files(x86)\Intel\oneAPI\setvars.bat` -> - For PowerShell*, use the following command: `cmd.exe "/K" '"C:\Program Files (x86)\Intel\oneAPI\setvars.bat" && powershell'` +> - Windows PowerShell*, use the following command: `cmd.exe "/K" '"C:\Program Files (x86)\Intel\oneAPI\setvars.bat" && powershell'` > ->For more information on environment variables, see **Use the setvars Script** for [Linux or macOS](https://www.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/oneapi-development-environment-setup/use-the-setvars-script-with-linux-or-macos.html), or [Windows](https://www.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/oneapi-development-environment-setup/use-the-setvars-script-with-windows.html). +> For more information on configuring environment variables, see [Use the setvars Script with Linux* or macOS*](https://www.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/oneapi-development-environment-setup/use-the-setvars-script-with-linux-or-macos.html) or [Use the setvars Script with Windows*](https://www.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/oneapi-development-environment-setup/use-the-setvars-script-with-windows.html). Use these commands to run the design, depending on your OS. @@ -176,7 +177,7 @@ This design uses CMake to generate a build script for `nmake`. | `nmake fpga_emu` | Seconds | x86-64 binary | Compiles the FPGA device code to the CPU. Use the Intel® FPGA Emulation Platform for OpenCL™ software to verify your SYCL code’s functional correctness. | `nmake report` | Minutes | RTL + FPGA reports | Compiles the FPGA device code to RTL and generates an optimization report that describes the structures generated on the FPGA, identifies performance bottlenecks, and estimates resource utilization. This report will include the interfaces defined in your selected Board Support Package. | `nmake fpga_sim` | Minutes | RTL + FPGA reports + x86-64 binary | Compiles the FPGA device code to RTL and generates a simulation testbench. Use the Questa*-Intel® FPGA Edition simulator to verify your design. - | `nmake fpga` | Multiple Hours | Quartus Place & Route (Full accelerator) + FPGA reports + x86-64 host binary | Compiles the FPGA device code to RTL and generate an FPGA image that you can run on a supported accelerator board. + | `nmake fpga` | Multiple Hours | Quartus Place & Route (Full accelerator) + FPGA reports + x86-64 host binary | Compiles the FPGA device code to RTL and compiles the generated RTL using Intel® Quartus® Prime. If you specified a BSP with `FPGA_DEVICE`, this will generate an FPGA image that you can run on the corresponding accelerator board. | `nmake fpga_ip_export` | Minutes | RTL + FPGA reports | Compiles the FPGA device code to RTL that may be exported to Intel® Quartus Prime software The `fpga_emu`, `fpga_sim`, and `fpga` targets also produce binaries that you can run. The executables will be called `TARGET_NAME.fpga_emu.exe`, `TARGET_NAME.fpga_sim.exe`, and `TARGET_NAME.fpga.exe`, where `TARGET_NAME` is the value you specify in `CMakeLists.txt`. From dd174e31e11011cf3de45c71361e2e2672725a73 Mon Sep 17 00:00:00 2001 From: Paul White Date: Mon, 23 Jan 2023 08:53:29 -0600 Subject: [PATCH 17/22] Update DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/README.md formatting Co-authored-by: yuguen-intel --- .../Tutorials/GettingStarted/fpga_template/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/README.md index 5820e35bd5..2baa3b34a6 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/README.md @@ -1,4 +1,4 @@ -# FPGA Template +# `FPGA Template` Sample This project serves as a template for Intel® oneAPI FPGA designs. From 0fb00aad5f7434f482d65876645797d59b4111e9 Mon Sep 17 00:00:00 2001 From: "White, Paul" Date: Tue, 24 Jan 2023 05:39:53 -0800 Subject: [PATCH 18/22] fix flag outputs for `fpga` target --- .../GettingStarted/fpga_template/CMakeLists.txt | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/CMakeLists.txt index 6be94e3467..bf8590091c 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/CMakeLists.txt @@ -106,8 +106,8 @@ set(REPORT_COMPILE_FLAGS -DFPGA_HARDWARE) set(REPORT_LINK_FLAGS -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_FPGA_FLAGS} -fsycl-link=early) set(SIMULATOR_COMPILE_FLAGS -Xssimulation -DFPGA_SIMULATOR) set(SIMULATOR_LINK_FLAGS -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_FPGA_FLAGS} -reuse-exe=${CMAKE_BINARY_DIR}/${SIMULATOR_OUTPUT_NAME}) -set(HARDWARE_COMPILE_FLAGS -DFPGA_HARDWARE) -set(HARDWARE_LINK_FLAGS -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_FPGA_FLAGS} -reuse-exe=${CMAKE_BINARY_DIR}/${FPGA_OUTPUT_NAME}) +set(FPGA_COMPILE_FLAGS -DFPGA_HARDWARE) +set(FPGA_LINK_FLAGS -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_FPGA_FLAGS} -reuse-exe=${CMAKE_BINARY_DIR}/${FPGA_OUTPUT_NAME}) # get rid of this once host pipes work properly set(IP_EXPORT_COMPILE_FLAGS -DFPGA_HARDWARE) set(IP_EXPORT_LINK_FLAGS -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_FPGA_FLAGS} -fsycl-link=early -fsycl-device-code-split=per_kernel) @@ -152,9 +152,9 @@ set_target_properties(${REPORT_TARGET} PROPERTIES OUTPUT_NAME ${REPORT_OUTPUT_NA ############################################################################### add_executable(${FPGA_TARGET} EXCLUDE_FROM_ALL ${SOURCE_FILES}) target_compile_options(${FPGA_TARGET} PRIVATE ${COMMON_COMPILE_FLAGS}) -target_compile_options(${FPGA_TARGET} PRIVATE ${HARDWARE_COMPILE_FLAGS}) +target_compile_options(${FPGA_TARGET} PRIVATE ${FPGA_COMPILE_FLAGS}) target_link_libraries(${FPGA_TARGET} ${COMMON_LINK_FLAGS}) -target_link_libraries(${FPGA_TARGET} ${HARDWARE_LINK_FLAGS}) +target_link_libraries(${FPGA_TARGET} ${FPGA_LINK_FLAGS}) set_target_properties(${FPGA_TARGET} PROPERTIES OUTPUT_NAME ${FPGA_OUTPUT_NAME}) ############################################################################### @@ -172,7 +172,6 @@ target_link_libraries(${IP_EXPORT_TARGET} ${MODIFIED_COMMON_LINK_FLAGS_EXPORT}) target_link_libraries(${IP_EXPORT_TARGET} ${IP_EXPORT_LINK_FLAGS}) set_target_properties(${IP_EXPORT_TARGET} PROPERTIES OUTPUT_NAME ${IP_EXPORT_OUTPUT_NAME}) - ############################################################################### ### This part only manipulates cmake variables to print the commands to the user ############################################################################### @@ -318,4 +317,4 @@ getCompileCommands("${COMMON_COMPILE_FLAGS}" "${FPGA_COMPILE_FLAGS}" "${COMMON_L add_custom_target( displayFPGACompileCommands ALL ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" COMMENT "To compile manually:\n${COMPILE_COMMAND}\nTo link manually:\n${LINK_COMMAND}") -add_dependencies(${FPGA_TARGET} displayFPGACompileCommands) \ No newline at end of file +add_dependencies(${FPGA_TARGET} displayFPGACompileCommands) From 5bbf85dc01c295926a927d9ca9e112c90bb790fb Mon Sep 17 00:00:00 2001 From: "White, Paul" Date: Mon, 30 Jan 2023 12:34:53 -0800 Subject: [PATCH 19/22] code style improvements --- .../fpga_template/src/fpga_template.cpp | 26 +++++++++---------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp index 8e0ca69dcc..1166aaf3ee 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp @@ -27,7 +27,7 @@ class VectorAdd { } }; -#define VECT_SIZE 256 +constexpr int kVectSize = 256; int main() { bool passed = false; @@ -37,11 +37,11 @@ int main() { // 2023.1 #if __INTEL_CLANG_COMPILER >= 20230100 #if FPGA_SIMULATOR - auto selector = sycl::ext::intel::fpga_simulator_selector_v; + auto selector = sycl::ext::intel::fpga_simulator_selector_v; #elif FPGA_HARDWARE - auto selector = sycl::ext::intel::fpga_selector_v; + auto selector = sycl::ext::intel::fpga_selector_v; #else // #if FPGA_EMULATOR - auto selector = sycl::ext::intel::fpga_emulator_selector_v; + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif #elif __INTEL_CLANG_COMPILER >= 20230000 #if FPGA_SIMULATOR @@ -63,25 +63,23 @@ int main() { << device.get_info().c_str() << std::endl; - int count = VECT_SIZE; // pass array size by value - // declare arrays and fill them // allocate in shared memory so the kernel can see them - int *a = sycl::malloc_shared(count, q); - int *b = sycl::malloc_shared(count, q); - int *c = sycl::malloc_shared(count, q); - for (int i = 0; i < count; i++) { + int *a = sycl::malloc_shared(kVectSize, q); + int *b = sycl::malloc_shared(kVectSize, q); + int *c = sycl::malloc_shared(kVectSize, q); + for (int i = 0; i < kVectSize; i++) { a[i] = i; - b[i] = (count - i); + b[i] = (kVectSize - i); } - std::cout << "add two vectors of size " << count << std::endl; + std::cout << "add two vectors of size " << kVectSize << std::endl; - q.single_task(VectorAdd{a, b, c, count}).wait(); + q.single_task(VectorAdd{a, b, c, kVectSize}).wait(); // verify that VC is correct passed = true; - for (int i = 0; i < count; i++) { + for (int i = 0; i < kVectSize; i++) { int expected = a[i] + b[i]; if (c[i] != expected) { std::cout << "idx=" << i << ": result " << c[i] << ", expected (" From f19a5718a9a79622ebfd40c588ed644346c9f59e Mon Sep 17 00:00:00 2001 From: "White, Paul" Date: Wed, 1 Feb 2023 07:55:05 -0800 Subject: [PATCH 20/22] =?UTF-8?q?update=20readme=20to=20be=20compliant=20w?= =?UTF-8?q?ith=20IPA/Intel=C2=AE=20Agilex=C2=AE=20defaults?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../GettingStarted/fpga_template/README.md | 122 ++++++++++-------- 1 file changed, 67 insertions(+), 55 deletions(-) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/README.md index 2baa3b34a6..0353f9edc5 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/README.md @@ -5,7 +5,7 @@ This project serves as a template for Intel® oneAPI FPGA designs. | Optimized for | Description |:--- |:--- | OS | Linux* Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX)
Intel® FPGA 3rd party / custom platforms with oneAPI support (and SYCL USM support) Note: Intel® FPGA PAC hardware is only compatible with Ubuntu 18.04* +| Hardware | Intel® Agilex™, Arria® 10, and Stratix® 10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler | What you will learn | Best practices for creating and managing a oneAPI FPGA project | Time to complete | 10 minutes @@ -17,7 +17,9 @@ This project serves as a template for Intel® oneAPI FPGA designs. > - Questa*-Intel® FPGA Starter Edition > - ModelSim® SE > -> To use the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> :warning: Make sure you add the device files associated with the FPGA that you are targeting to your Intel® Quartus® Prime installation. > **Note**: In oneAPI full systems, kernels that use SYCL Unified Shared Memory (USM) host allocations or USM shared allocations (and therefore the code in this tutorial) are only supported by Board Support Packages (BSPs) with USM support (e.g. the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) `intel_s10sx_pac:pac_s10_usm`). Kernels that use these types of allocations can always be used to generate standalone IPs. @@ -115,28 +117,29 @@ Use these commands to run the design, depending on your OS. ### On a Linux* System This design uses CMake to generate a build script for GNU/make. -1. Generate the `Makefile` by running `cmake`. +1. Change to the sample directory. + +2. Configure the build system for the Agilex™ device family, which is the default. - ```bash + ``` mkdir build cd build - ``` - - To compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - - ```bash cmake .. ``` - You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - - ``` - cmake .. -DFPGA_DEVICE=: - ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. - > **NOTE**: This design will **not** work on the Intel® PAC with Intel Arria® 10 GX FPGA, because the design depends on USM. - -2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: +3. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: | Target | Expected Time | Output | Description |:--- |:--- |:--- |:--- @@ -151,26 +154,28 @@ This design uses CMake to generate a build script for GNU/make. ### On a Windows* System This design uses CMake to generate a build script for `nmake`. -1. Generate the `Makefile` by running `cmake`. +1. Change to the sample directory. - ```bash +2. Configure the build system for the Agilex™ device family, which is the default. + ``` mkdir build cd build - ``` - - To compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - - ```bash cmake -G "NMake Makefiles" .. ``` - You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: - ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. -2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: +3. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: | Target | Expected Time | Output | Description |:--- |:--- |:--- |:--- @@ -182,39 +187,46 @@ This design uses CMake to generate a build script for `nmake`. The `fpga_emu`, `fpga_sim`, and `fpga` targets also produce binaries that you can run. The executables will be called `TARGET_NAME.fpga_emu.exe`, `TARGET_NAME.fpga_sim.exe`, and `TARGET_NAME.fpga.exe`, where `TARGET_NAME` is the value you specify in `CMakeLists.txt`. - > **Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - > **Note**: If you encounter any issues with long paths when compiling under Windows*, you may have to create your ‘build’ directory in a shorter path, for example c:\samples\build. You can then run cmake from that directory, and provide cmake with the full path to your sample directory. -## Running the Sample - -1. Run the sample on the FPGA emulator (the kernel executes on the CPU): +## Run the `fpga_template` Executable +### On Linux +1. Run the sample on the FPGA emulator (the kernel executes on the CPU). ``` - ./fpga_template.fpga_emu (Linux) - fpga_template.fpga_emu.exe (Windows) + ./fpga_template.fpga_emu ``` - -2. Run the sample on the FPGA simulator device: - - * On Linux - ```bash - CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./fpga_template.fpga_sim - ``` - - * On Windows - ```bash - set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 - fpga_template.fpga_sim.exe - set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= - ``` - -3. Run the sample on the FPGA device: +2. Run the sample on the FPGA simulator device. + ``` + CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./fpga_template.fpga_sim + ``` +3. Alternatively, run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). + ``` + ./fpga_template.fpga ``` - ./fpga_template.fpga (Linux) - fpga_template.fpga.exe (Windows) +### On Windows +1. Run the sample on the FPGA emulator (the kernel executes on the CPU). ``` + fpga_template.fpga_emu.exe + ``` +2. Run the sample on the FPGA simulator device. + ``` + set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 + fpga_template.fpga_sim.exe + set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= + ``` +3. Alternatively, run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). + ``` + fpga_template.fpga.exe + ``` + +## Example Output +``` +Running on device: Intel(R) FPGA Emulation Device +add two vectors of size 256 +PASSED +``` ## License Code samples are licensed under the MIT license. See [License.txt](https://github.com/oneapi-src/oneAPI-samples/blob/master/License.txt) for details. From cdcf2f1931b0cedce0cbf2759c3d828f80f0a9a1 Mon Sep 17 00:00:00 2001 From: "White, Paul" Date: Fri, 3 Feb 2023 07:44:51 -0800 Subject: [PATCH 21/22] simplify as per Paul Pedersen's feedback --- .../GettingStarted/fpga_template/src/fpga_template.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp index 1166aaf3ee..02198ce0f1 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp @@ -10,11 +10,11 @@ // practice that reduces name mangling in the optimization reports. class VectorAddID; -class VectorAdd { +struct VectorAdd { public: - int *a_in; - int *b_in; - int *c_out; + int *const a_in; + int *const b_in; + int *const c_out; int len; void operator()() const { From bd67843c2e9e8467c0bf0c8e8d98dfb9b97152df Mon Sep 17 00:00:00 2001 From: "White, Paul" Date: Tue, 7 Feb 2023 06:06:37 -0800 Subject: [PATCH 22/22] remove redundant 'public' --- .../Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp index 02198ce0f1..e40cb39698 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp @@ -11,7 +11,6 @@ class VectorAddID; struct VectorAdd { - public: int *const a_in; int *const b_in; int *const c_out;