From 898c01aae5d80ad4342fb6996938562b804146df Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Thu, 8 Dec 2022 11:53:16 +0000 Subject: [PATCH 01/38] add sim to simple and vector add Signed-off-by: Yohann Uguen --- .../DenseLinearAlgebra/simple-add/README.md | 43 +++++++++++++++---- .../simple-add/src/CMakeLists.txt | 20 ++++++++- .../simple-add/src/simple-add-buffers.cpp | 5 ++- .../simple-add/src/simple-add-usm.cpp | 5 ++- .../DenseLinearAlgebra/vector-add/README.md | 43 +++++++++++++++---- .../vector-add/src/CMakeLists.txt | 19 +++++++- .../vector-add/src/vector-add-buffers.cpp | 5 ++- .../vector-add/src/vector-add-usm.cpp | 5 ++- 8 files changed, 121 insertions(+), 24 deletions(-) diff --git a/DirectProgramming/DPC++/DenseLinearAlgebra/simple-add/README.md b/DirectProgramming/DPC++/DenseLinearAlgebra/simple-add/README.md index f986e0c499..9cbc198275 100644 --- a/DirectProgramming/DPC++/DenseLinearAlgebra/simple-add/README.md +++ b/DirectProgramming/DPC++/DenseLinearAlgebra/simple-add/README.md @@ -25,6 +25,15 @@ USM, buffer, accessor, kernel, and command groups. | Hardware | GEN9 or newer
Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA (Intel® PAC with Intel® Arria® 10 GX FPGA) | Software | Intel® oneAPI DPC++/C++ Compiler +> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for CPU, GPU, FPGA emulation, generating FPGA reports and generating RTL for FPGAs, there are extra software requirements for the FPGA simulation flow and FPGA compiles. +> +> For using the simulator flow, one of the following simulators must be installed and accessible through your PATH: +> - Questa*-Intel® FPGA Edition +> - Questa*-Intel® FPGA Starter Edition +> - ModelSim® SE +> +> When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. + ## Key Implementation Details This sample provides examples of both buffers and USM implementations for simple side-by-side comparison. @@ -111,19 +120,23 @@ To learn more about the extensions and how to configure the oneAPI environment, ``` make fpga_emu ``` -2. Generate HTML performance reports. +2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + make fpga_sim + ``` +3. Generate HTML performance reports. ``` make report ``` The reports reside at `simple-add_report.prj/reports/report.html`. -3. Compile the program for FPGA hardware. (Compiling for hardware can take a long +4. Compile the program for FPGA hardware. (Compiling for hardware can take a long time.) ``` make fpga ``` -4. Clean the program. (Optional) +5. Clean the program. (Optional) ``` make clean ``` @@ -168,19 +181,23 @@ time.) ``` nmake fpga_emu ``` -2. Generate HTML performance reports. +2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + nmake fpga_sim + ``` +3. Generate HTML performance reports. ``` nmake report ``` The reports reside at `simple-add_report.prj/reports/report.html`. -3. Compile the program for FPGA hardware. (Compiling for hardware can take a long +4. Compile the program for FPGA hardware. (Compiling for hardware can take a long time.) ``` nmake fpga ``` -4. Clean the program. (Optional) +5. Clean the program. (Optional) ``` nmake clean ``` @@ -216,7 +233,12 @@ If you receive an error message, troubleshoot the problem using the **Diagnostic ./simple-add-buffers.fpga_emu ./simple-add-usm.fpga_emu ``` -3. Run on FPGA hardware. +3. Run on FPGA simulator. + ``` + ./simple-add-buffers.fpga_sim + ./simple-add-usm.fpga_sim + ``` +4. Run on FPGA hardware. ``` ./simple-add-buffers.fpga ./simple-add-usm.fpga @@ -243,7 +265,12 @@ If you receive an error message, troubleshoot the problem using the **Diagnostic simple-add-buffers.fpga_emu.exe simple-add-usm.fpga_emu.exe ``` -3. Run on FPGA hardware. +3. Run on FPGA simulator. + ``` + simple-add-buffers.fpga_sim + simple-add-usm.fpga_sim + ``` +4. Run on FPGA hardware. ``` simple-add-buffers.fpga.exe simple-add-usm.fpga.exe diff --git a/DirectProgramming/DPC++/DenseLinearAlgebra/simple-add/src/CMakeLists.txt b/DirectProgramming/DPC++/DenseLinearAlgebra/simple-add/src/CMakeLists.txt index e40f21c606..0391722f12 100755 --- a/DirectProgramming/DPC++/DenseLinearAlgebra/simple-add/src/CMakeLists.txt +++ b/DirectProgramming/DPC++/DenseLinearAlgebra/simple-add/src/CMakeLists.txt @@ -57,15 +57,18 @@ else() endif() set(EMULATOR_TARGET ${TARGET_NAME}.fpga_emu) +set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) set(FPGA_TARGET ${TARGET_NAME}.fpga) # A DPC++ ahead-of-time (AoT) compile processes the device code in two stages. # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -Wall -fintelfpga ${WIN_FLAG} -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(HARDWARE_COMPILE_FLAGS "-fsycl -Wall -fintelfpga ${WIN_FLAG}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation @@ -82,6 +85,19 @@ set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_CO set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS}") add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET}) +############################################################################### +### FPGA Simulator +############################################################################### +# To compile in a single command: +# icpx -fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget= -DFPGA_SIMULATOR .cpp -o .fpga_sim +# CMake executes: +# [compile] icpx -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR -o .cpp.o -c .cpp +# [link] icpx -fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget= .cpp.o -o .fpga_sim +add_executable(${SIMULATOR_TARGET} ${SOURCE_FILE}) +set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${SIMULATOR_COMPILE_FLAGS}") +set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${SIMULATOR_LINK_FLAGS}") +add_custom_target(fpga_sim DEPENDS ${SIMULATOR_TARGET}) + ############################################################################### ### Generate Report ############################################################################### diff --git a/DirectProgramming/DPC++/DenseLinearAlgebra/simple-add/src/simple-add-buffers.cpp b/DirectProgramming/DPC++/DenseLinearAlgebra/simple-add/src/simple-add-buffers.cpp index 19c2b81f13..2369eb6b9a 100644 --- a/DirectProgramming/DPC++/DenseLinearAlgebra/simple-add/src/simple-add-buffers.cpp +++ b/DirectProgramming/DPC++/DenseLinearAlgebra/simple-add/src/simple-add-buffers.cpp @@ -23,7 +23,7 @@ #include #include -#if FPGA || FPGA_EMULATOR +#if FPGA || FPGA_EMULATOR || FPGA_SIMULATOR #include #endif @@ -85,6 +85,9 @@ int main() { #if FPGA_EMULATOR // Intel extension: FPGA emulator selector on systems without FPGA card. ext::intel::fpga_emulator_selector d_selector; +#elif FPGA_SIMULATOR + // Intel extension: FPGA simulator selector on systems without FPGA card. + ext::intel::fpga_simulator_selector selector; #elif FPGA // Intel extension: FPGA selector on systems with FPGA card. ext::intel::fpga_selector d_selector; diff --git a/DirectProgramming/DPC++/DenseLinearAlgebra/simple-add/src/simple-add-usm.cpp b/DirectProgramming/DPC++/DenseLinearAlgebra/simple-add/src/simple-add-usm.cpp index 2cc1e441b9..b0fc0d2ed6 100644 --- a/DirectProgramming/DPC++/DenseLinearAlgebra/simple-add/src/simple-add-usm.cpp +++ b/DirectProgramming/DPC++/DenseLinearAlgebra/simple-add/src/simple-add-usm.cpp @@ -23,7 +23,7 @@ #include #include -#if FPGA || FPGA_EMULATOR +#if FPGA || FPGA_EMULATOR || FPGA_SIMULATOR #include #endif @@ -76,6 +76,9 @@ int main() { #if FPGA_EMULATOR // Intel extension: FPGA emulator selector on systems without FPGA card. ext::intel::fpga_emulator_selector selector; +#elif FPGA_SIMULATOR + // Intel extension: FPGA simulator selector on systems without FPGA card. + ext::intel::fpga_simulator_selector selector; #elif FPGA // Intel extension: FPGA selector on systems with FPGA card. ext::intel::fpga_selector selector; diff --git a/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/README.md b/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/README.md index 0e723987b5..7dbfe0c055 100755 --- a/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/README.md +++ b/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/README.md @@ -28,6 +28,15 @@ This sample provides example implementations of both Unified Shared Memory (USM) | Hardware | GEN9 or newer
Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA (Intel® PAC with Intel® Arria® 10 GX FPGA) | Software | Intel® oneAPI DPC++/C++ Compiler +> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for CPU, GPU, FPGA emulation, generating FPGA reports and generating RTL for FPGAs, there are extra software requirements for the FPGA simulation flow and FPGA compiles. +> +> For using the simulator flow, one of the following simulators must be installed and accessible through your PATH: +> - Questa*-Intel® FPGA Edition +> - Questa*-Intel® FPGA Starter Edition +> - ModelSim® SE +> +> When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. + ## Key Implementation Details The basic SYCL implementation explained in the code includes device selector, USM, buffer, accessor, kernel, and command groups. @@ -111,19 +120,23 @@ To learn more about the extensions and how to configure the oneAPI environment, ``` make fpga_emu ``` -2. Generate HTML performance reports. +2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + make fpga_sim + ``` +3. Generate HTML performance reports. ``` make report ``` The reports reside at `simple-add_report.prj/reports/report.html`. -3. Compile the program for FPGA hardware. (Compiling for hardware can take a long +4. Compile the program for FPGA hardware. (Compiling for hardware can take a long time.) ``` make fpga ``` -4. Clean the program. (Optional) +5. Clean the program. (Optional) ``` make clean ``` @@ -168,19 +181,23 @@ time.) ``` nmake fpga_emu ``` -2. Generate HTML performance reports. +2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + nmake fpga_sim + ``` +3. Generate HTML performance reports. ``` nmake report ``` The reports reside at `simple-add_report.prj/reports/report.html`. -3. Compile the program for FPGA hardware. (Compiling for hardware can take a long +4. Compile the program for FPGA hardware. (Compiling for hardware can take a long time.) ``` nmake fpga ``` -4. Clean the program. (Optional) +5. Clean the program. (Optional) ``` nmake clean ``` @@ -221,7 +238,12 @@ The source files (`vector-add-buffers.cpp` and `vector-add-usm.cpp`) specify the ./vector-add-buffers.fpga_emu ./vector-add-usm.fpga_emu ``` -3. Run on FPGA hardware. +3. Run on FPGA simulator. + ``` + ./vector-add-buffers.fpga_sim + ./vector-add-usm.fpga_sim + ``` +4. Run on FPGA hardware. ``` ./vector-add-buffers.fpga ./vector-add-usm.fpga @@ -248,7 +270,12 @@ The source files (`vector-add-buffers.cpp` and `vector-add-usm.cpp`) specify the vector-add-buffers.fpga_emu.exe vector-add-usm.fpga_emu.exe ``` -3. Run on FPGA hardware. +3. Run on FPGA simulator. + ``` + vector-add-buffers.fpga_sim + vector-add-usm.fpga_sim + ``` +4. Run on FPGA hardware. ``` vector-add-buffers.fpga.exe vector-add-usm.fpga.exe diff --git a/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src/CMakeLists.txt b/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src/CMakeLists.txt index d88bf5b824..f614ecbfb7 100755 --- a/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src/CMakeLists.txt +++ b/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src/CMakeLists.txt @@ -63,9 +63,11 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -Wall -fintelfpga -DFPGA_EMULATOR ${WIN_FLAG}") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(HARDWARE_COMPILE_FLAGS "-fsycl -Wall -fintelfpga -DFPGA ${WIN_FLAG}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation @@ -82,6 +84,19 @@ set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_CO set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS}") add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET}) +############################################################################### +### FPGA Simulator +############################################################################### +# To compile in a single command: +# icpx -fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget= -DFPGA_SIMULATOR .cpp -o .fpga_sim +# CMake executes: +# [compile] icpx -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR -o .cpp.o -c .cpp +# [link] icpx -fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget= .cpp.o -o .fpga_sim +add_executable(${SIMULATOR_TARGET} ${SOURCE_FILE}) +set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${SIMULATOR_COMPILE_FLAGS}") +set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${SIMULATOR_LINK_FLAGS}") +add_custom_target(fpga_sim DEPENDS ${SIMULATOR_TARGET}) + ############################################################################### ### Generate Report ############################################################################### diff --git a/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src/vector-add-buffers.cpp b/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src/vector-add-buffers.cpp index 4c895637b5..53463e2f03 100755 --- a/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src/vector-add-buffers.cpp +++ b/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src/vector-add-buffers.cpp @@ -23,7 +23,7 @@ #include #include #include -#if FPGA || FPGA_EMULATOR +#if FPGA || FPGA_EMULATOR || FPGA_SIMULATOR #include #endif @@ -110,6 +110,9 @@ int main(int argc, char* argv[]) { #if FPGA_EMULATOR // Intel extension: FPGA emulator selector on systems without FPGA card. ext::intel::fpga_emulator_selector d_selector; +#elif FPGA_SIMULATOR + // Intel extension: FPGA simulator selector on systems without FPGA card. + ext::intel::fpga_simulator_selector selector; #elif FPGA // Intel extension: FPGA selector on systems with FPGA card. ext::intel::fpga_selector d_selector; diff --git a/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src/vector-add-usm.cpp b/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src/vector-add-usm.cpp index d4b4648831..67d057a01d 100755 --- a/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src/vector-add-usm.cpp +++ b/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src/vector-add-usm.cpp @@ -23,7 +23,7 @@ #include #include #include -#if FPGA || FPGA_EMULATOR +#if FPGA || FPGA_EMULATOR || FPGA_SIMULATOR #include #endif @@ -84,6 +84,9 @@ int main(int argc, char* argv[]) { #if FPGA_EMULATOR // Intel extension: FPGA emulator selector on systems without FPGA card. ext::intel::fpga_emulator_selector d_selector; +#elif FPGA_SIMULATOR + // Intel extension: FPGA simulator selector on systems without FPGA card. + ext::intel::fpga_simulator_selector selector; #elif FPGA // Intel extension: FPGA selector on systems with FPGA card. ext::intel::fpga_selector d_selector; From cc41ceb147c48f4fc988c9de53b94e6952616e5e Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Thu, 8 Dec 2022 11:59:53 +0000 Subject: [PATCH 02/38] update selector names Signed-off-by: Yohann Uguen --- .../simple-add/src/simple-add-buffers.cpp | 8 ++++---- .../vector-add/src/vector-add-buffers.cpp | 8 ++++---- .../DenseLinearAlgebra/vector-add/src/vector-add-usm.cpp | 8 ++++---- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/DirectProgramming/DPC++/DenseLinearAlgebra/simple-add/src/simple-add-buffers.cpp b/DirectProgramming/DPC++/DenseLinearAlgebra/simple-add/src/simple-add-buffers.cpp index 2369eb6b9a..2f8a7f7413 100644 --- a/DirectProgramming/DPC++/DenseLinearAlgebra/simple-add/src/simple-add-buffers.cpp +++ b/DirectProgramming/DPC++/DenseLinearAlgebra/simple-add/src/simple-add-buffers.cpp @@ -84,16 +84,16 @@ int main() { // Create device selector for the device of your interest. #if FPGA_EMULATOR // Intel extension: FPGA emulator selector on systems without FPGA card. - ext::intel::fpga_emulator_selector d_selector; + ext::intel::fpga_emulator_selector selector; #elif FPGA_SIMULATOR // Intel extension: FPGA simulator selector on systems without FPGA card. ext::intel::fpga_simulator_selector selector; #elif FPGA // Intel extension: FPGA selector on systems with FPGA card. - ext::intel::fpga_selector d_selector; + ext::intel::fpga_selector selector; #else // The default device selector will select the most performant device. - auto d_selector{default_selector_v}; + auto selector{default_selector_v}; #endif // Create array objects with "array_size" to store data. @@ -104,7 +104,7 @@ int main() { for (size_t i = 0; i < sequential.size(); i++) sequential[i] = value + i; try { - queue q(d_selector, exception_handler); + queue q(selector, exception_handler); // Print out the device information used for the kernel code. cout << "Running on device: " diff --git a/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src/vector-add-buffers.cpp b/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src/vector-add-buffers.cpp index 53463e2f03..cde7553ce0 100755 --- a/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src/vector-add-buffers.cpp +++ b/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src/vector-add-buffers.cpp @@ -109,16 +109,16 @@ int main(int argc, char* argv[]) { // Create device selector for the device of your interest. #if FPGA_EMULATOR // Intel extension: FPGA emulator selector on systems without FPGA card. - ext::intel::fpga_emulator_selector d_selector; + ext::intel::fpga_emulator_selector selector; #elif FPGA_SIMULATOR // Intel extension: FPGA simulator selector on systems without FPGA card. ext::intel::fpga_simulator_selector selector; #elif FPGA // Intel extension: FPGA selector on systems with FPGA card. - ext::intel::fpga_selector d_selector; + ext::intel::fpga_selector selector; #else // The default device selector will select the most performant device. - auto d_selector{default_selector_v}; + auto selector{default_selector_v}; #endif // Create vector objects with "vector_size" to store the input and output data. @@ -133,7 +133,7 @@ int main(int argc, char* argv[]) { InitializeVector(b); try { - queue q(d_selector, exception_handler); + queue q(selector, exception_handler); // Print out the device information used for the kernel code. std::cout << "Running on device: " diff --git a/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src/vector-add-usm.cpp b/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src/vector-add-usm.cpp index 67d057a01d..076902ab42 100755 --- a/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src/vector-add-usm.cpp +++ b/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src/vector-add-usm.cpp @@ -83,20 +83,20 @@ int main(int argc, char* argv[]) { // Create device selector for the device of your interest. #if FPGA_EMULATOR // Intel extension: FPGA emulator selector on systems without FPGA card. - ext::intel::fpga_emulator_selector d_selector; + ext::intel::fpga_emulator_selector selector; #elif FPGA_SIMULATOR // Intel extension: FPGA simulator selector on systems without FPGA card. ext::intel::fpga_simulator_selector selector; #elif FPGA // Intel extension: FPGA selector on systems with FPGA card. - ext::intel::fpga_selector d_selector; + ext::intel::fpga_selector selector; #else // The default device selector will select the most performant device. - auto d_selector{default_selector_v}; + auto selector{default_selector_v}; #endif try { - queue q(d_selector, exception_handler); + queue q(selector, exception_handler); // Print out the device information used for the kernel code. std::cout << "Running on device: " From f5213102f7cbdfaf24bda6d6770a58ed9089596a Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Fri, 9 Dec 2022 08:44:31 +0000 Subject: [PATCH 03/38] fix default usm board in simple_add Signed-off-by: Yohann Uguen --- .../DenseLinearAlgebra/simple-add/src/CMakeLists.txt | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/DirectProgramming/DPC++/DenseLinearAlgebra/simple-add/src/CMakeLists.txt b/DirectProgramming/DPC++/DenseLinearAlgebra/simple-add/src/CMakeLists.txt index 0391722f12..a264f709a3 100755 --- a/DirectProgramming/DPC++/DenseLinearAlgebra/simple-add/src/CMakeLists.txt +++ b/DirectProgramming/DPC++/DenseLinearAlgebra/simple-add/src/CMakeLists.txt @@ -48,10 +48,16 @@ add_custom_target(cpu-gpu DEPENDS ${TARGET_NAME}) # FPGA device selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + if(DEFINED USM AND (NOT(USM EQUAL 0))) + set(FPGA_DEVICE "intel_s10sx_pac:pac_s10_usm") + set(DEFAULT_BOARD_STR "Intel Stratix(R) 10 SX with USM support") + else() + set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(DEFAULT_BOARD_STR "Intel Arria(R) 10 GX") + endif() message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA device ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on device selection.") + \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with ${DEFAULT_BOARD_STR} FPGA). \ + \nPlease refer to the README for information on board selection.") else() message(STATUS "Configuring the design to run on FPGA device ${FPGA_DEVICE}") endif() From 66d2beaf9c71722bd2f8f03d56e4705ae40ec3fe Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Fri, 9 Dec 2022 10:19:57 +0000 Subject: [PATCH 04/38] fixing default board for vector add usm Signed-off-by: Yohann Uguen --- .../vector-add/src/CMakeLists.txt | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src/CMakeLists.txt b/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src/CMakeLists.txt index f614ecbfb7..da9678c045 100755 --- a/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src/CMakeLists.txt +++ b/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src/CMakeLists.txt @@ -48,15 +48,23 @@ add_custom_target(cpu-gpu DEPENDS ${TARGET_NAME}) # FPGA device selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + if(DEFINED USM AND (NOT(USM EQUAL 0))) + set(FPGA_DEVICE "intel_s10sx_pac:pac_s10_usm") + set(DEFAULT_BOARD_STR "Intel Stratix(R) 10 SX with USM support") + else() + set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(DEFAULT_BOARD_STR "Intel Arria(R) 10 GX") + endif() message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA device ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on device selection.") + \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with ${DEFAULT_BOARD_STR} FPGA). \ + \nPlease refer to the README for information on board selection.") else() message(STATUS "Configuring the design to run on FPGA device ${FPGA_DEVICE}") endif() + set(EMULATOR_TARGET ${TARGET_NAME}.fpga_emu) +set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) set(FPGA_TARGET ${TARGET_NAME}.fpga) # A DPC++ ahead-of-time (AoT) compile processes the device code in two stages. From 26cf6facad5843e163cdde6a50a69d0d1de59f1c Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Mon, 12 Dec 2022 02:39:16 -0800 Subject: [PATCH 05/38] add sim support to buffered_host_streaming Signed-off-by: Yohann Uguen --- .../buffered_host_streaming/README.md | 26 +++++++++++++++---- .../src/CMakeLists.txt | 17 ++++++++++++ .../src/buffered_host_streaming.cpp | 9 ++++++- 3 files changed, 46 insertions(+), 6 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/buffered_host_streaming/README.md b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/buffered_host_streaming/README.md index 9de3f715c9..aee89ba724 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/buffered_host_streaming/README.md +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/buffered_host_streaming/README.md @@ -112,13 +112,17 @@ To learn more about the extensions and how to configure the oneAPI environment, ``` make fpga_emu ``` - 2. Generate HTML performance report. + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + make fpga_sim + ``` + 3. Generate HTML performance report. ``` make report ``` The report resides at `buffered_host_streaming_report.prj/reports/report.html`. - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). ``` make fpga ``` @@ -148,7 +152,11 @@ To learn more about the extensions and how to configure the oneAPI environment, ``` nmake fpga_emu ``` - 2. Generate HTML performance report. + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + nmake fpga_sim + ``` + 3. Generate HTML performance report. ``` nmake report ``` @@ -179,7 +187,11 @@ If you receive an error message, troubleshoot the problem using the **Diagnostic ``` ./buffered_host_streaming.fpga_emu ``` -2. Run the sample on the FPGA device: +2. Run the sample on the FPGA simulator device: + ``` + ./buffered_host_streaming.fpga_sim + ``` +3. Run the sample on the FPGA device: ``` ./buffered_host_streaming.fpga ``` @@ -190,7 +202,11 @@ If you receive an error message, troubleshoot the problem using the **Diagnostic ``` buffered_host_streaming.fpga_emu.exe ``` -2. Run the sample on the FPGA device: +2. Run the sample on the FPGA simulator device: + ``` + buffered_host_streaming.fpga_sim.exe + ``` +3. Run the sample on the FPGA device: ``` buffered_host_streaming.fpga.exe ``` diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/CMakeLists.txt index 147378eb9d..c6eca9599d 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/CMakeLists.txt @@ -1,6 +1,7 @@ set(SOURCE_FILE buffered_host_streaming.cpp) set(TARGET_NAME buffered_host_streaming) set(EMULATOR_TARGET ${TARGET_NAME}.fpga_emu) +set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) set(FPGA_TARGET ${TARGET_NAME}.fpga) set(REPORTS_TARGET ${TARGET_NAME}_report) @@ -37,6 +38,8 @@ endif() # For this reason, FPGA backend flags must be passed as link flags in CMake. set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${THREAD_FLAG}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} ${THREAD_FLAG}") set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga ${THREAD_FLAG} -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation @@ -55,6 +58,20 @@ set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_CO set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS}") add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET}) +############################################################################### +### FPGA Simulator +############################################################################### +# To compile in a single command: +# icpx -fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget= -DFPGA_SIMULATOR .cpp -o .fpga_sim +# CMake executes: +# [compile] icpx -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR -o .cpp.o -c .cpp +# [link] icpx -fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget= .cpp.o -o .fpga_sim +add_executable(${SIMULATOR_TARGET} ${SOURCE_FILE}) +target_include_directories(${SIMULATOR_TARGET} PRIVATE ../../../../include) +set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${SIMULATOR_COMPILE_FLAGS}") +set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${SIMULATOR_LINK_FLAGS}") +add_custom_target(fpga_sim DEPENDS ${SIMULATOR_TARGET}) + ############################################################################### ### Generate Report ############################################################################### diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/buffered_host_streaming.cpp b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/buffered_host_streaming.cpp index 510806efaf..a5c9d6474e 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/buffered_host_streaming.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/buffered_host_streaming.cpp @@ -36,6 +36,10 @@ int main(int argc, char* argv[]) { size_t reps = 20; size_t buffer_count = 1 << 12; // 4096 size_t iterations = 2; +#elif defined(FPGA_SIMULATOR) + size_t reps = 2; + size_t buffer_count = 1 << 8; // 256 + size_t iterations = 2; #else size_t reps = 200; size_t buffer_count = 1 << 19; // 524388 @@ -123,9 +127,12 @@ int main(int argc, char* argv[]) { bool passed = true; try { - // device selector #if defined(FPGA_EMULATOR) + // the device selector ext::intel::fpga_emulator_selector selector; +#elif defined(FPGA_SIMULATOR) + // the device simulator + ext::intel::fpga_simulator_selector selector; #else ext::intel::fpga_selector selector; #endif From e5b3ad2687ca66c2bd386fd640a59d55fb3c08dc Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Mon, 12 Dec 2022 04:47:52 -0800 Subject: [PATCH 06/38] add sim to anr - 153min Signed-off-by: Yohann Uguen --- .../DPC++FPGA/ReferenceDesigns/anr/README.md | 40 +++++++++++++------ .../ReferenceDesigns/anr/src/CMakeLists.txt | 16 +++++++- .../ReferenceDesigns/anr/src/main.cpp | 10 ++++- 3 files changed, 50 insertions(+), 16 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/README.md b/DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/README.md index 7486ae435e..a976695906 100755 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/README.md +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/README.md @@ -166,13 +166,17 @@ The design uses the following generic header files. ``` make fpga_emu ``` - 2. Generate HTML performance report. + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + make fpga_sim + ``` + 3. Generate HTML performance report. ``` make report ``` The report resides at `anr_report.prj/reports/report.html`. - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). ``` make fpga ``` @@ -201,13 +205,17 @@ The design uses the following generic header files. ``` nmake fpga_emu ``` - 2. Generate HTML performance report. + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + nmake fpga_sim + ``` + 3. Generate HTML performance report. ``` nmake report ``` The report resides at `anr_report.prj/reports/report.html`. - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). ``` nmake fpga ``` @@ -218,10 +226,14 @@ The design uses the following generic header files. ### On Linux 1. Run the sample on the FPGA emulator (the kernel executes on the CPU). - ``` - ./anr.fpga_emu - ``` -2. Alternatively, run the sample on the FPGA device. + ``` + ./anr.fpga_emu + ``` +2. Run the sample on the FPGA simulator device: + ``` + ./anr.fpga_sim + ``` +3. Alternatively, run the sample on the FPGA device. ``` ./anr.fpga ``` @@ -229,10 +241,14 @@ The design uses the following generic header files. ### On Windows 1. Run the sample on the FPGA emulator (the kernel executes on the CPU). - ``` - anr.fpga_emu.exe - ``` -2. Alternatively, run the sample on the FPGA device. + ``` + anr.fpga_emu.exe + ``` +2. Run the sample on the FPGA simulator device: + ``` + anr.fpga_sim.exe + ``` +3. Alternatively, run the sample on the FPGA device. ``` anr.fpga.exe ``` diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/CMakeLists.txt index f91fc6fa33..35d3150422 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/CMakeLists.txt @@ -1,6 +1,7 @@ set(TARGET_NAME anr) set(SOURCE_FILE main.cpp) set(EMULATOR_TARGET ${TARGET_NAME}.fpga_emu) +set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection @@ -119,10 +120,12 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} -fsycl -fintelfpga ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} -fsycl -fintelfpga ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -Xshardware ${PROFILE_FLAG} ${FLAT_COMPILE_FLAG} -Xsparallel=2 ${SEED_FLAG} -Xstarget=${FPGA_DEVICE} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} ${IP_MODE_FLAG} ${USER_HARDWARE_FLAGS}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG}") set(HARDWARE_LINK_FLAGS "${REPORT_LINK_FLAGS} ${AC_TYPES_FLAG}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation @@ -135,6 +138,15 @@ set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_CO set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS}") add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET}) +############################################################################### +### FPGA Simulator +############################################################################### +add_executable(${SIMULATOR_TARGET} ${SOURCE_FILE}) +target_include_directories(${SIMULATOR_TARGET} PRIVATE ../../../include) +set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${SIMULATOR_COMPILE_FLAGS}") +set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${SIMULATOR_LINK_FLAGS}") +add_custom_target(fpga_sim DEPENDS ${SIMULATOR_TARGET}) + ############################################################################### ### Generate Report ############################################################################### diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/main.cpp b/DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/main.cpp index cb06fdc758..195795bd02 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/main.cpp +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/main.cpp @@ -42,9 +42,12 @@ int main(int argc, char* argv[]) { // reading and validating the command line arguments std::string data_dir = "../test_data"; bool passed = true; -#ifdef FPGA_EMULATOR +#if defined(FPGA_EMULATOR) int runs = 2; int frames = 2; +#elif defined(FPGA_SIMULATOR) + int runs = 2; + int frames = 1; #else int runs = 2; int frames = 8; @@ -78,9 +81,12 @@ int main(int argc, char* argv[]) { } ///////////////////////////////////////////////////////////// +#if defined(FPGA_EMULATOR) // the device selector -#ifdef FPGA_EMULATOR ext::intel::fpga_emulator_selector selector; +#elif defined(FPGA_SIMULATOR) + // the device simulator + ext::intel::fpga_simulator_selector selector; #else ext::intel::fpga_selector selector; #endif From e87ab50df7e9b40878540bafd72990b864238676 Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Mon, 12 Dec 2022 05:53:20 -0800 Subject: [PATCH 07/38] add db and decompress sim support Signed-off-by: Yohann Uguen --- .../DPC++FPGA/ReferenceDesigns/db/README.md | 102 ++++++++++-------- .../ReferenceDesigns/db/src/CMakeLists.txt | 18 +++- .../DPC++FPGA/ReferenceDesigns/db/src/db.cpp | 18 +++- .../ReferenceDesigns/db/src/dbdata.hpp | 2 +- .../ReferenceDesigns/decompress/README.md | 100 +++++++++-------- 5 files changed, 144 insertions(+), 96 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/db/README.md b/DirectProgramming/DPC++FPGA/ReferenceDesigns/db/README.md index a7d665a768..b76ee7e475 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/db/README.md +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/db/README.md @@ -146,22 +146,25 @@ Query 12 showcases the `MergeJoin` database operator. The block diagram of the d 3. Compile the design. (The provided targets match the recommended development flow.) - 1. Compile for emulation (fast compile time, targets emulated FPGA device). - ``` - make fpga_emu - ``` - 2. Generate HTML performance report. - ``` - make report - ``` - The report resides at `db_report.prj/reports/report.html`. - - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). - - ``` - make fpga - ``` - When building for hardware, the default scale factor is **1**. To use the smaller scale factor of 0.01, add the flag `-DSF_SMALL=1` to the original `cmake` command. For example: `cmake .. -DQUERY=11 -DSF_SMALL=1`. See the [Database files](#database-files) for more information. + 1. Compile for emulation (fast compile time, targets emulated FPGA device). + ``` + make fpga_emu + ``` + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + make fpga_sim + ``` + 3. Generate HTML performance report. + ``` + make report + ``` + The report resides at `db_report.prj/reports/report.html`. + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). + + ``` + make fpga + ``` + When building for hardware, the default scale factor is **1**. To use the smaller scale factor of 0.01, add the flag `-DSF_SMALL=1` to the original `cmake` command. For example: `cmake .. -DQUERY=11 -DSF_SMALL=1`. See the [Database files](#database-files) for more information. (Optional) The hardware compile may take several hours to complete. You can download a pre-compiled binary (compatible with Linux* Ubuntu* 18.04) for an Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) from [https://iotdk.intel.com/fpga-precompiled-binaries/latest/db.fpga.tar.gz](https://iotdk.intel.com/fpga-precompiled-binaries/latest/db.fpga.tar.gz). @@ -180,21 +183,24 @@ Query 12 showcases the `MergeJoin` database operator. The block diagram of the d 3. Compile the design. (The provided targets match the recommended development flow.) - 1. Compile for emulation (fast compile time, targets emulated FPGA device). - - ``` - nmake fpga_emu - ``` - 2. Generate HTML performance report. - ``` - nmake report - ``` - The report resides at `db_report.prj/reports/report.html` directory. - - 3. Compile for FPGA hardware (longer compile time, targets FPGA device): - ``` - nmake fpga - ``` + 1. Compile for emulation (fast compile time, targets emulated FPGA device). + ``` + nmake fpga_emu + ``` + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + nmake fpga_sim + ``` + 3. Generate HTML performance report. + ``` + nmake report + ``` + The report resides at `db_report.prj/reports/report.html` directory. + + 4. Compile for FPGA hardware (longer compile time, targets FPGA device): + ``` + nmake fpga + ``` >**Note**: If you encounter any issues with long paths when compiling under Windows*, you may have to create your ‘build’ directory in a shorter path, for example `C:\samples\build`. You can then run cmake from that directory, and provide cmake with the full path to your sample directory. ## Run the `DB` Reference Design @@ -212,26 +218,32 @@ Query 12 showcases the `MergeJoin` database operator. The block diagram of the d ### On Linux - 1. Run the design on the FPGA emulator (the kernel executes on the CPU). - ``` - ./db.fpga_emu --dbroot=../data/sf0.01 --test - ``` - (Optional) Run the design for queries `11` and `12`. - -2. Run the design on an FPGA device. +1. Run the design on the FPGA emulator (the kernel executes on the CPU). + ``` + ./db.fpga_emu --dbroot=../data/sf0.01 --test + ``` + (Optional) Run the design for queries `11` and `12`. +2. Run the sample on the FPGA simulator device: + ``` + ./db.fpga_sim --dbroot=../data/sf0.01 --test + ``` +3. Run the design on an FPGA device. ``` ./db.fpga --dbroot=../data/sf1 --test ``` ### On Windows - 1. Run the sample on the FPGA emulator (the kernel executes on the CPU). - ``` - db.fpga_emu.exe --dbroot=../data/sf0.01 --test - ``` - (Optional) Run the design for queries `11` and `12`. - -2. Run the sample on an FPGA device. +1. Run the sample on the FPGA emulator (the kernel executes on the CPU). + ``` + db.fpga_emu.exe --dbroot=../data/sf0.01 --test + ``` + (Optional) Run the design for queries `11` and `12`. +2. Run the sample on the FPGA simulator device: + ``` + db.fpga_sim.exe --dbroot=../data/sf0.01 --test + ``` +3. Run the sample on an FPGA device. ``` db.fpga.exe --dbroot=../data/sf1 --test ``` diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/CMakeLists.txt index e422c9f428..86367c441b 100755 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/CMakeLists.txt @@ -1,6 +1,7 @@ set(TARGET_NAME db) set(SOURCE_FILE db.cpp dbdata.cpp) set(EMULATOR_TARGET ${TARGET_NAME}.fpga_emu) +set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) set(FPGA_TARGET ${TARGET_NAME}.fpga) # which query are we doing? @@ -120,11 +121,13 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DQUERY=${QUERY} ${SF_SMALL_ARG} ${AC_TYPES_FLAG} -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DQUERY=${QUERY} ${SF_SMALL_ARG} ${AC_TYPES_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga -DQUERY=${QUERY} ${SF_SMALL_ARG} ${AC_TYPES_FLAG}") -set(REPORT_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DQUERY=${QUERY} ${SF_SMALL_ARG} ${AC_TYPES_FLAG}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DQUERY=${QUERY} ${SF_SMALL_ARG} ${AC_TYPES_FLAG} -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} -DQUERY=${QUERY} ${SF_SMALL_ARG} ${USER_HARDWARE_FLAGS} ${AC_TYPES_FLAG}") +set(REPORT_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DQUERY=${QUERY} ${SF_SMALL_ARG} ${AC_TYPES_FLAG}") set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xsparallel=2 -Xsseed=2 -Xstarget=${FPGA_DEVICE} -DQUERY=${QUERY} ${SF_SMALL_ARG} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DQUERY=${QUERY} ${SF_SMALL_ARG} ${AC_TYPES_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DQUERY=${QUERY} ${SF_SMALL_ARG} ${AC_TYPES_FLAG}") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xsparallel=2 ${SEED} -Xstarget=${FPGA_DEVICE} -DQUERY=${QUERY} ${SF_SMALL_ARG} ${USER_HARDWARE_FLAGS} ${AC_TYPES_FLAG}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation @@ -137,6 +140,15 @@ set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_CO set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS}") add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET}) +############################################################################### +### FPGA Simulator +############################################################################### +add_executable(${SIMULATOR_TARGET} ${SOURCE_FILE} ${DEVICE_SOURCE}) +target_include_directories(${SIMULATOR_TARGET} PRIVATE ../../../include) +set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${SIMULATOR_COMPILE_FLAGS}") +set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${SIMULATOR_LINK_FLAGS}") +add_custom_target(fpga_sim DEPENDS ${SIMULATOR_TARGET}) + ############################################################################### ### Generate Report ############################################################################### diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/db.cpp b/DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/db.cpp index d41a3bf1e3..8f5c9289d8 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/db.cpp +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/db.cpp @@ -119,10 +119,12 @@ int main(int argc, char* argv[]) { std::string args = ""; unsigned int query = QUERY; bool test_query = false; -#ifndef FPGA_EMULATOR - unsigned int runs = 5; -#else +#if defined(FPGA_EMULATOR) unsigned int runs = 1; +#elif defined(FPGA_SIMULATOR) + unsigned int runs = 1; +#else + unsigned int runs = 5; #endif bool print_result = false; bool need_help = false; @@ -152,7 +154,8 @@ int main(int argc, char* argv[]) { // a 'warmup' iteration runs = std::max(2, atoi(str_after_equals.c_str()) + 1); #else - // for emulation, allow a single iteration and don't add a 'warmup' run + // for emulation and simulation, allow a single iteration and + // don't add a 'warmup' run runs = std::max(1, atoi(str_after_equals.c_str())); #endif } else { @@ -186,9 +189,12 @@ int main(int argc, char* argv[]) { // queue properties to enable profiling auto props = property_list{property::queue::enable_profiling()}; +#if defined(FPGA_EMULATOR) // the device selector -#ifdef FPGA_EMULATOR ext::intel::fpga_emulator_selector selector; +#elif defined(FPGA_SIMULATOR) + // the device simulator + ext::intel::fpga_simulator_selector selector; #else ext::intel::fpga_selector selector; #endif @@ -280,6 +286,8 @@ int main(int argc, char* argv[]) { "system has a correctly configured FPGA board.\n"; std::cout << "If you are targeting the FPGA emulator, compile with " "-DFPGA_EMULATOR.\n"; + std::cout << "If you are targeting the FPGA simulator, compile with " + "-DFPGA_SIMULATOR.\n"; } std::terminate(); } diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/dbdata.hpp b/DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/dbdata.hpp index 3fb9a3852c..6b3fc14e16 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/dbdata.hpp +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/dbdata.hpp @@ -24,7 +24,7 @@ using DBDate = unsigned int; // The default scale factor for hardware is 1. However, // the SF_SMALL flag allows the hardware design to be compiled // with a scale factor of 0.01 -#if defined(FPGA_EMULATOR) || defined(SF_SMALL) +#if defined(FPGA_EMULATOR) || defined(FPGA_SIMULATOR) || defined(SF_SMALL) constexpr float kSF = 0.01f; #else constexpr float kSF = 1.0f; diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/README.md b/DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/README.md index e275c9568e..ffa2f2e17c 100755 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/README.md +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/README.md @@ -320,20 +320,24 @@ For `constexpr_math.hpp`, `memory_utils.hpp`, `metaprogramming_utils.hpp`, `tupl 3. Compile the design. (The provided targets match the recommended development flow.) - 1. Compile for emulation (fast compile time, targets emulated FPGA device). - ``` - make fpga_emu - ``` - 2. Generate the HTML performance report. - ``` - make report - ``` - The report resides at `decompression type>_report.prj/reports/report/report.html`. - - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). - ``` - make fpga - ``` + 1. Compile for emulation (fast compile time, targets emulated FPGA device). + ``` + make fpga_emu + ``` + 2. Generate the HTML performance report. + ``` + make report + ``` + The report resides at `decompression type>_report.prj/reports/report/report.html`. + + 3. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + make fpga_sim + ``` + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). + ``` + make fpga + ``` (Optional) The hardware compiles listed above can take several hours to complete; alternatively, you can download FPGA precompiled binaries (compatible with Linux* Ubuntu* 18.04) from [https://iotdk.intel.com/fpga-precompiled-binaries/latest/decompress.fpga.tar.gz](https://iotdk.intel.com/fpga-precompiled-binaries/latest/decompress.fpga.tar.gz). @@ -359,20 +363,24 @@ For `constexpr_math.hpp`, `memory_utils.hpp`, `metaprogramming_utils.hpp`, `tupl ``` 3. Compile the design. (The provided targets match the recommended development flow.) - 1. Compile for emulation (fast compile time, targets emulated FPGA device). - ``` - nmake fpga_emu - ``` - 2. Generate the HTML performance report. - ``` - nmake report - ``` - The report resides at `_report.a.prj/reports/report/report.html`. - - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). - ``` - nmake fpga - ``` + 1. Compile for emulation (fast compile time, targets emulated FPGA device). + ``` + nmake fpga_emu + ``` + 2. Generate the HTML performance report. + ``` + nmake report + ``` + The report resides at `_report.a.prj/reports/report/report.html`. + + 3. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + nmake fpga_sim + ``` + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). + ``` + nmake fpga + ``` > **Note**: If you encounter any issues with long paths when compiling under Windows*, you may have to create your ‘build’ directory in a shorter path, for example `c:\samples\build`. You can then run cmake from that directory, and provide cmake with the full path to your sample directory. ## Run the `Decompression` Program @@ -380,24 +388,32 @@ For `constexpr_math.hpp`, `memory_utils.hpp`, `metaprogramming_utils.hpp`, `tupl ### On Linux 1. Run the sample on the FPGA emulator (the kernel executes on the CPU). - ``` - ./decompress.fpga_emu - ``` -2. Run the sample on the FPGA device. - ``` - ./decompress.fpga - ``` + ``` + ./decompress.fpga_emu + ``` +2. Run the sample on the FPGA simulator device: + ``` + ./decompress.fpga_sim + ``` +3. Run the sample on the FPGA device. + ``` + ./decompress.fpga + ``` ### On Windows 1. Run the sample on the FPGA emulator (the kernel executes on the CPU). - ``` - decompress.fpga_emu.exe - ``` -2. Run the sample on the FPGA device. - ``` - decompress.fpga.exe - ``` + ``` + decompress.fpga_emu.exe + ``` +2. Run the sample on the FPGA simulator device: + ``` + decompress.fpga_sim.exe + ``` +3. Run the sample on the FPGA device. + ``` + decompress.fpga.exe + ``` ## Example Output From c6648304bacfcd342c97bb68c638e6769c107b15 Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Mon, 12 Dec 2022 08:34:51 -0800 Subject: [PATCH 08/38] add sim support to explicit data movement: Signed-off-by: Yohann Uguen --- .../explicit_data_movement/README.md | 28 +++++++++++++++---- .../explicit_data_movement/src/CMakeLists.txt | 21 ++++++++++++-- .../src/explicit_data_movement.cpp | 10 +++++-- 3 files changed, 49 insertions(+), 10 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/explicit_data_movement/README.md b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/explicit_data_movement/README.md index 1f69b09f8b..7c0427d7f8 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/explicit_data_movement/README.md +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/explicit_data_movement/README.md @@ -132,13 +132,17 @@ To learn more about the extensions and how to configure the oneAPI environment, ``` make fpga_emu ``` - 2. Generate HTML performance report. + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + make fpga_sim + ``` + 3. Generate HTML performance report. ``` make report ``` The report resides at `explicit_data_movement.prj/reports/report.html`. Note that because the optimization occurs at the *runtime* level, the FPGA compiler report will not show a difference between the optimized and unoptimized cases. - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). ``` make fpga ``` @@ -172,13 +176,17 @@ To learn more about the extensions and how to configure the oneAPI environment, ``` nmake fpga_emu ``` - 2. Generate HTML performance report. + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + nmake fpga_sim + ``` + 3. Generate HTML performance report. ``` nmake report ``` The report resides at `explicit_data_movement.prj.a/reports/report.html`. - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). ``` nmake fpga ``` @@ -202,7 +210,11 @@ If you receive an error message, troubleshoot the problem using the **Diagnostic ``` ./explicit_data_movement.fpga_emu ``` -2. Run the sample on the FPGA device. +2. Run the sample on the FPGA simulator device: + ``` + ./explicit_data_movement.fpga_sim + ``` +3. Run the sample on the FPGA device. ``` ./explicit_data_movement.fpga ``` @@ -213,7 +225,11 @@ If you receive an error message, troubleshoot the problem using the **Diagnostic ``` explicit_data_movement.fpga_emu.exe ``` -2. Run the sample on the FPGA device. +2. Run the sample on the FPGA simulator device: + ``` + explicit_data_movement.fpga_sim.exe + ``` +3. Run the sample on the FPGA device. ``` explicit_data_movement.fpga.exe ``` diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/CMakeLists.txt index 81659781b9..adc66d8de3 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/CMakeLists.txt @@ -1,6 +1,7 @@ set(SOURCE_FILE explicit_data_movement.cpp) set(TARGET_NAME explicit_data_movement) set(EMULATOR_TARGET ${TARGET_NAME}.fpga_emu) +set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection @@ -22,9 +23,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG}") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation @@ -42,6 +45,20 @@ set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_CO set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS}") add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET}) +############################################################################### +### FPGA Simulator +############################################################################### +# To compile in a single command: +# icpx -fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget= -DFPGA_SIMULATOR .cpp -o .fpga_sim +# CMake executes: +# [compile] icpx -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR -o .cpp.o -c .cpp +# [link] icpx -fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget= .cpp.o -o .fpga_sim +add_executable(${SIMULATOR_TARGET} ${SOURCE_FILE}) +target_include_directories(${SIMULATOR_TARGET} PRIVATE ../../../../include) +set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${SIMULATOR_COMPILE_FLAGS}") +set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${SIMULATOR_LINK_FLAGS}") +add_custom_target(fpga_sim DEPENDS ${SIMULATOR_TARGET}) + ############################################################################### ### Generate Report ############################################################################### diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/explicit_data_movement.cpp b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/explicit_data_movement.cpp index c63ee1186f..7f63936263 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/explicit_data_movement.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/explicit_data_movement.cpp @@ -142,6 +142,9 @@ int main(int argc, char *argv[]) { #if defined(FPGA_EMULATOR) size_t size = 10000; size_t iters = 1; +#elif defined(FPGA_SIMULATOR) + size_t size = 100; + size_t iters = 1; #else size_t size = 100000000; size_t iters = 5; @@ -159,9 +162,12 @@ int main(int argc, char *argv[]) { } try { - // device selector #if defined(FPGA_EMULATOR) + // the device selector ext::intel::fpga_emulator_selector selector; +#elif defined(FPGA_SIMULATOR) + // the device simulator + ext::intel::fpga_simulator_selector selector; #else ext::intel::fpga_selector selector; #endif @@ -236,7 +242,7 @@ int main(int argc, char *argv[]) { if (passed) { // The emulator does not accurately represent real hardware performance. // Therefore, we don't show performance results when running in emulation. -#ifndef FPGA_EMULATOR +#if !defined(FPGA_EMULATOR) && !defined(FPGA_SIMULATOR) double implicit_avg_lat = std::accumulate(implicit_kernel_latency.begin() + 1, implicit_kernel_latency.end(), 0.0) From 05a8c3fa3cf79308a099e5304088be1d842ef885 Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Mon, 12 Dec 2022 08:35:20 -0800 Subject: [PATCH 09/38] update decompress readme Signed-off-by: Yohann Uguen --- .../ReferenceDesigns/decompress/README.md | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/README.md b/DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/README.md index ffa2f2e17c..da762444d7 100755 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/README.md +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/README.md @@ -324,16 +324,16 @@ For `constexpr_math.hpp`, `memory_utils.hpp`, `metaprogramming_utils.hpp`, `tupl ``` make fpga_emu ``` - 2. Generate the HTML performance report. + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + make fpga_sim + ``` + 3. Generate the HTML performance report. ``` make report ``` The report resides at `decompression type>_report.prj/reports/report/report.html`. - 3. Compile for simulation (fast compile time, targets simulator FPGA device): - ``` - make fpga_sim - ``` 4. Compile for FPGA hardware (longer compile time, targets FPGA device). ``` make fpga @@ -367,16 +367,16 @@ For `constexpr_math.hpp`, `memory_utils.hpp`, `metaprogramming_utils.hpp`, `tupl ``` nmake fpga_emu ``` - 2. Generate the HTML performance report. + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + nmake fpga_sim + ``` + 3. Generate the HTML performance report. ``` nmake report ``` The report resides at `_report.a.prj/reports/report/report.html`. - 3. Compile for simulation (fast compile time, targets simulator FPGA device): - ``` - nmake fpga_sim - ``` 4. Compile for FPGA hardware (longer compile time, targets FPGA device). ``` nmake fpga From 965988144f470b99247385eb49a9a0297e35c1f8 Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Tue, 13 Dec 2022 01:40:01 -0800 Subject: [PATCH 10/38] sim support to compute_units Signed-off-by: Yohann Uguen --- .../DesignPatterns/compute_units/README.md | 28 +++++++++++++++---- .../compute_units/src/CMakeLists.txt | 24 ++++++++++++---- .../compute_units/src/compute_units.cpp | 10 +++++-- 3 files changed, 48 insertions(+), 14 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/README.md b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/README.md index 2bf83cdd88..900893d77c 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/README.md +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/README.md @@ -157,13 +157,17 @@ To learn more about the extensions and how to configure the oneAPI environment, ``` make fpga_emu ``` - 2. Generate HTML performance report. + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + make fpga_sim + ``` + 3. Generate HTML performance report. ``` make report ``` The report resides at `compute_units_report.prj/reports/report.html`. You can visualize the kernels and pipes generated by looking at the "System Viewer" section of the report. Note that each compute unit is shown as a unique kernel in the reports, with names `ChainComputeUnit<0>`, `ChainComputeUnit<1>`, and so on. - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). ``` make fpga ``` @@ -197,13 +201,17 @@ To learn more about the extensions and how to configure the oneAPI environment, ``` nmake fpga_emu ``` - 2. Generate HTML performance report. + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + nmake fpga_sim + ``` + 3. Generate HTML performance report. ``` nmake report ``` The report resides at `compute_units_report.prj.a/reports/report.html`. You can visualize the kernels and pipes generated by looking at the "System Viewer" section of the report. Note that each compute unit is shown as a unique kernel in the reports, with names `ChainComputeUnit<0>`, `ChainComputeUnit<1>`, and so on. - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). ``` nmake fpga ``` @@ -228,7 +236,11 @@ If you receive an error message, troubleshoot the problem using the **Diagnostic ``` ./compute_units.fpga_emu ``` -2. Run the sample on the FPGA device. +2. Run the sample on the FPGA simulator device: + ``` + ./compute_units.fpga_sim + ``` +3. Run the sample on the FPGA device. ``` ./compute_units.fpga ``` @@ -238,7 +250,11 @@ If you receive an error message, troubleshoot the problem using the **Diagnostic ``` compute_units.fpga_emu.exe ``` -2. Run the sample on the FPGA device. +2. Run the sample on the FPGA simulator device: + ``` + compute_units.fpga_sim.exe + ``` +3. Run the sample on the FPGA device. ``` compute_units.fpga.exe ``` diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/src/CMakeLists.txt index d263b824a5..acbec04fdb 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/src/CMakeLists.txt @@ -1,6 +1,7 @@ set(SOURCE_FILE compute_units.cpp) set(TARGET_NAME compute_units) set(EMULATOR_TARGET ${TARGET_NAME}.fpga_emu) +set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection @@ -22,9 +23,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG}") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation @@ -38,11 +41,24 @@ set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} # [link] icpx -fsycl -fintelfpga compute_units.cpp.o -o compute_units.fpga_emu add_executable(${EMULATOR_TARGET} ${SOURCE_FILE}) # CMake automatically adds #include'd headers to the dependency list target_include_directories(${EMULATOR_TARGET} PRIVATE ../../../../include) -target_include_directories(${EMULATOR_TARGET} PRIVATE ../../../../include) set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_COMPILE_FLAGS}") set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS}") add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET}) +############################################################################### +### FPGA Simulator +############################################################################### +# To compile in a single command: +# icpx -fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget= -DFPGA_SIMULATOR .cpp -o .fpga_sim +# CMake executes: +# [compile] icpx -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR -o .cpp.o -c .cpp +# [link] icpx -fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget= .cpp.o -o .fpga_sim +add_executable(${SIMULATOR_TARGET} ${SOURCE_FILE}) +target_include_directories(${SIMULATOR_TARGET} PRIVATE ../../../../include) +set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${SIMULATOR_COMPILE_FLAGS}") +set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${SIMULATOR_LINK_FLAGS}") +add_custom_target(fpga_sim DEPENDS ${SIMULATOR_TARGET}) + ############################################################################### ### Generate Report ############################################################################### @@ -52,7 +68,6 @@ set(FPGA_EARLY_IMAGE ${TARGET_NAME}_report.a) # The compile output is not an executable, but an intermediate compilation result unique to SYCL. add_executable(${FPGA_EARLY_IMAGE} ${SOURCE_FILE}) target_include_directories(${FPGA_EARLY_IMAGE} PRIVATE ../../../../include) -target_include_directories(${FPGA_EARLY_IMAGE} PRIVATE ../../../../include) add_custom_target(report DEPENDS ${FPGA_EARLY_IMAGE}) set_target_properties(${FPGA_EARLY_IMAGE} PROPERTIES COMPILE_FLAGS "${HARDWARE_COMPILE_FLAGS}") set_target_properties(${FPGA_EARLY_IMAGE} PROPERTIES LINK_FLAGS "${HARDWARE_LINK_FLAGS} -fsycl-link=early") @@ -68,7 +83,6 @@ set_target_properties(${FPGA_EARLY_IMAGE} PROPERTIES LINK_FLAGS "${HARDWARE_LINK # [link] icpx -fsycl -fintelfpga -Xshardware -Xstarget= compute_units.cpp.o -o compute_units.fpga add_executable(${FPGA_TARGET} EXCLUDE_FROM_ALL ${SOURCE_FILE}) target_include_directories(${FPGA_TARGET} PRIVATE ../../../../include) -target_include_directories(${FPGA_TARGET} PRIVATE ../../../../include) add_custom_target(fpga DEPENDS ${FPGA_TARGET}) set_target_properties(${FPGA_TARGET} PROPERTIES COMPILE_FLAGS "${HARDWARE_COMPILE_FLAGS}") set_target_properties(${FPGA_TARGET} PROPERTIES LINK_FLAGS "${HARDWARE_LINK_FLAGS} -reuse-exe=${CMAKE_BINARY_DIR}/${FPGA_TARGET}") diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/src/compute_units.cpp b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/src/compute_units.cpp index e6ea72df7e..1137b4e200 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/src/compute_units.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/src/compute_units.cpp @@ -44,15 +44,19 @@ void SinkKernel(queue &q, float &out_data) { int main() { #if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector device_selector; + // the device selector + ext::intel::fpga_emulator_selector selector; +#elif defined(FPGA_SIMULATOR) + // the device simulator + ext::intel::fpga_simulator_selector selector; #else - ext::intel::fpga_selector device_selector; + ext::intel::fpga_selector selector; #endif float out_data = 0; try { - queue q(device_selector, fpga_tools::exception_handler); + queue q(selector, fpga_tools::exception_handler); // Enqueue the Source kernel SourceKernel(q, kTestData); From 03634adc9b569edc911a3f154dc439d0c826bb79 Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Tue, 13 Dec 2022 01:40:22 -0800 Subject: [PATCH 11/38] sim support to fast_recompile Signed-off-by: Yohann Uguen --- .../GettingStarted/fast_recompile/README.md | 65 +++++++++++-------- .../fast_recompile/src/CMakeLists.txt | 21 +++++- .../fast_recompile/src/host.cpp | 12 ++-- 3 files changed, 66 insertions(+), 32 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fast_recompile/README.md b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fast_recompile/README.md index 8d2d7945e6..22517132e1 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fast_recompile/README.md +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fast_recompile/README.md @@ -189,14 +189,18 @@ After learning how to use the extensions for Intel oneAPI Toolkits, return to th **NOTE:** For the FPGA emulator target and the FPGA target, the device link method is used. 2. Compile the design through the generated `Makefile`. The following build targets are provided: - * Compile for emulation (fast compile time, targets emulated FPGA device): - ``` - make fpga_emu - ``` - * Compile for FPGA hardware (longer compile time, targets FPGA device): - ``` - make fpga - ``` + * Compile for emulation (fast compile time, targets emulated FPGA device): + ``` + make fpga_emu + ``` + * Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + make fpga_sim + ``` + * Compile for FPGA hardware (longer compile time, targets FPGA device): + ``` + make fpga + ``` 3. (Optional) As the above hardware compile may take several hours to complete, FPGA precompiled binaries (compatible with Linux* Ubuntu* 18.04) can be downloaded here. ### On a Windows* System @@ -222,14 +226,18 @@ After learning how to use the extensions for Intel oneAPI Toolkits, return to th 2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: - * Compile for emulation (fast compile time, targets emulated FPGA device): - ``` - nmake fpga_emu - ``` - * Compile for FPGA hardware (longer compile time, targets FPGA device): - ``` - nmake fpga - ``` + * Compile for emulation (fast compile time, targets emulated FPGA device): + ``` + nmake fpga_emu + ``` + * Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + nmake fpga_sim + ``` + * Compile for FPGA hardware (longer compile time, targets FPGA device): + ``` + nmake fpga + ``` > **Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. @@ -252,16 +260,21 @@ You can compile and run this tutorial in the Eclipse* IDE (in Linux*) and the Vi ## Running the Sample - 1. Run the sample on the FPGA emulator (the kernel executes on the CPU): - ``` - ./fast_recompile.fpga_emu (Linux) - fast_recompile.fpga_emu.exe (Windows) - ``` -2. Run the sample on the FPGA device: - ``` - ./fast_recompile.fpga (Linux) - fast_recompile.fpga.exe (Windows) - ``` +1. Run the sample on the FPGA emulator (the kernel executes on the CPU): + ``` + ./fast_recompile.fpga_emu (Linux) + fast_recompile.fpga_emu.exe (Windows) + ``` +2. Run the sample on the FPGA simulator device: + ``` + ./fast_recompile.fpga_sim (Linux) + fast_recompile.fpga_sim.exe (Windows) + ``` +3. Run the sample on the FPGA device: + ``` + ./fast_recompile.fpga (Linux) + fast_recompile.fpga.exe (Windows) + ``` ### Example of Output ``` diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fast_recompile/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fast_recompile/src/CMakeLists.txt index 03169876b6..2b17485521 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fast_recompile/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fast_recompile/src/CMakeLists.txt @@ -3,6 +3,7 @@ set(KERNEL_HEADER_FILE kernel.hpp) set(HOST_SOURCE_FILE host.cpp) set(TARGET_NAME fast_recompile) set(EMULATOR_TARGET ${TARGET_NAME}.fpga_emu) +set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection @@ -24,9 +25,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG}") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation @@ -45,6 +48,20 @@ set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_CO set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS}") add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET}) +############################################################################### +### FPGA Simulator +############################################################################### +# To compile in a single command: +# icpx -fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget= -DFPGA_SIMULATOR .cpp -o .fpga_sim +# CMake executes: +# [compile] icpx -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR -o .cpp.o -c .cpp +# [link] icpx -fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget= .cpp.o -o .fpga_sim +add_executable(${SIMULATOR_TARGET} ${HOST_SOURCE_FILE} ${DEVICE_SOURCE_FILE}) +target_include_directories(${SIMULATOR_TARGET} PRIVATE ../../../../include) +set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${SIMULATOR_COMPILE_FLAGS}") +set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${SIMULATOR_LINK_FLAGS}") +add_custom_target(fpga_sim DEPENDS ${SIMULATOR_TARGET}) + ############################################################################### ### Generate Report ############################################################################### diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fast_recompile/src/host.cpp b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fast_recompile/src/host.cpp index fb979c35b4..1e63ac2ca3 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fast_recompile/src/host.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fast_recompile/src/host.cpp @@ -40,18 +40,22 @@ int main() { vec_b[i] = rand() / (float)RAND_MAX; } - // Select either the FPGA emulator or FPGA device + // Select either the FPGA emulator, FPGA simulator or FPGA device #if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector device_selector; + // the device selector + ext::intel::fpga_emulator_selector selector; +#elif defined(FPGA_SIMULATOR) + // the device simulator + ext::intel::fpga_simulator_selector selector; #else - ext::intel::fpga_selector device_selector; + ext::intel::fpga_selector selector; #endif try { // Create a queue bound to the chosen device. // If the device is unavailable, a SYCL runtime exception is thrown. - queue q(device_selector, fpga_tools::exception_handler); + queue q(selector, fpga_tools::exception_handler); // create the device buffers buffer device_a(vec_a); From 9884b974f85a389b2f93b95c62aef3fccc48faf5 Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Tue, 13 Dec 2022 01:40:39 -0800 Subject: [PATCH 12/38] sim support to fpga_compile Signed-off-by: Yohann Uguen --- .../GettingStarted/fpga_compile/README.md | 155 ++++++++++-------- .../fpga_compile/src/CMakeLists.txt | 17 ++ .../fpga_compile/src/fpga_compile.cpp | 9 +- 3 files changed, 109 insertions(+), 72 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fpga_compile/README.md b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fpga_compile/README.md index 205705397b..7f29edf6e2 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fpga_compile/README.md +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fpga_compile/README.md @@ -49,7 +49,11 @@ The typical FPGA development workflow is to iterate in each of these stages, ref The FPGA emulator is the fastest method to verify the correctness of your code. The FPGA emulator executes the SYCL* device code on the CPU. The emulator is similar to the SYCL* host device, but unlike the host device, the FPGA emulator device supports FPGA extensions such as FPGA pipes and `fpga_reg`. -There are two important caveats to remember when using the FPGA emulator. +#### FPGA Simulator + +The FPGA simulator is the fastest method to verify the correctness of the gerenated RTL. The FPGA simulator executes the SYCL* device code in an RTL simulator (e.g. Questa*). The host code still runs on the CPU as it would when targetting an FPGA. When using this flow, the generated exectuable will launch the simulator and inject the obtained results in the host execution. + +There are two important caveats to remember when using the FPGA emulator and the FPGA simulator. * **Performance is not representative.** _Never_ draw inferences about FPGA performance from the FPGA emulator. The FPGA emulator's timing behavior is uncorrelated to that of the physical FPGA hardware. For example, an optimization that yields a 100x performance improvement on the FPGA may show no impact on the emulator performance. It may show an unrelated increase or even a decrease. * **Undefined behavior may differ.** If your code produces different results when compiled for the FPGA emulator versus FPGA hardware, your code most likely exercises undefined behavior. By definition, undefined behavior is not specified by the language specification and may manifest differently on different targets. @@ -177,75 +181,83 @@ To learn more about the extensions, see the ### On a Linux* System 1. Generate the `Makefile` by running `cmake`. - ``` - mkdir build - cd build - ``` - To compile for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: - ``` - cmake .. - ``` - Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - - ``` - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - ``` - cmake .. -DFPGA_DEVICE=: - ``` + ``` + mkdir build + cd build + ``` + To compile for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: + ``` + cmake .. + ``` + Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: + + ``` + cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 + ``` + You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: + ``` + cmake .. -DFPGA_DEVICE=: + ``` 2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: - * Compile for [emulation](#fpga-emulator) (compiles quickly, targets emulated FPGA device): - ``` - make fpga_emu - ``` - * Generate the [optimization report](#optimization-report): - ``` - make report - ``` - * Compile for [FPGA hardware](#fpga-hardware) (takes longer to compile, targets FPGA device): - ``` - make fpga - ``` + * Compile for [emulation](#fpga-emulator) (compiles quickly, targets emulated FPGA device): + ``` + make fpga_emu + ``` + * Compile for [simulation](#fpga-simulator) (fast compile time, targets simulator FPGA device): + ``` + make fpga_sim + ``` + * Generate the [optimization report](#optimization-report): + ``` + make report + ``` + * Compile for [FPGA hardware](#fpga-hardware) (takes longer to compile, targets FPGA device): + ``` + make fpga + ``` 3. (Optional) As the above hardware compile may take several hours to complete, FPGA precompiled binaries (compatible with Linux* Ubuntu* 18.04) can be downloaded here. ### On a Windows* System 1. Generate the `Makefile` by running `cmake`. - ``` - mkdir build - cd build - ``` - To compile for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: - ``` - cmake -G "NMake Makefiles" .. - ``` - Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: - ``` + ``` + mkdir build + cd build + ``` + To compile for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: + ``` + cmake -G "NMake Makefiles" .. + ``` + Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: + + ``` + cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 + ``` + You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: + ``` + cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + ``` 2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: - * Compile for emulation (compiles quickly, targets emulated FPGA device): - ``` - nmake fpga_emu - ``` - * Generate the optimization report: - ``` - nmake report - ``` - * Compile for FPGA hardware (longer compile time, targets FPGA device): - ``` - nmake fpga - ``` + * Compile for [emulation](#fpga-emulator) (compiles quickly, targets emulated FPGA device): + ``` + nmake fpga_emu + ``` + * Compile for [simulation](#fpga-simulator) (fast compile time, targets simulator FPGA device): + ``` + nmake fpga_sim + ``` + * Generate the [optimization report](#optimization-report): + ``` + nmake report + ``` + * Compile for [FPGA hardware](#fpga-hardware) (takes longer to compile, targets FPGA device): + ``` + nmake fpga + ``` > **Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. @@ -273,16 +285,21 @@ Browse the reports that were generated for the `VectorAdd` kernel's FPGA early i ## Running the Sample - 1. Run the sample on the FPGA emulator (the kernel executes on the CPU): - ``` - ./fpga_compile.fpga_emu (Linux) - fpga_compile.fpga_emu.exe (Windows) - ``` -2. Run the sample on the FPGA device: - ``` - ./fpga_compile.fpga (Linux) - fpga_compile.fpga.exe (Windows) - ``` +1. Run the sample on the FPGA emulator (the kernel executes on the CPU): + ``` + ./fpga_compile.fpga_emu (Linux) + fpga_compile.fpga_emu.exe (Windows) + ``` +2. Run the sample on the FPGA simulator device (the kernel executes in the simulator): + ``` + ./fpga_compile.fpga_sim (Linux) + fpga_compile.fpga_sim.exe (Windows) + ``` +3. Run the sample on the FPGA device: + ``` + ./fpga_compile.fpga (Linux) + fpga_compile.fpga.exe (Windows) + ``` ### Example of Output ``` diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fpga_compile/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fpga_compile/src/CMakeLists.txt index 90bac33a26..1da0751bc3 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fpga_compile/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fpga_compile/src/CMakeLists.txt @@ -1,6 +1,7 @@ set(SOURCE_FILE fpga_compile.cpp) set(TARGET_NAME fpga_compile) set(EMULATOR_TARGET ${TARGET_NAME}.fpga_emu) +set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA device selection @@ -24,6 +25,8 @@ endif() # For this reason, FPGA backend flags must be passed as link flags in CMake. set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation @@ -42,6 +45,20 @@ set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_CO set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS}") add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET}) +############################################################################### +### FPGA Simulator +############################################################################### +# To compile in a single command: +# icpx -fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget= -DFPGA_SIMULATOR .cpp -o .fpga_sim +# CMake executes: +# [compile] icpx -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR -o .cpp.o -c .cpp +# [link] icpx -fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget= .cpp.o -o .fpga_sim +add_executable(${SIMULATOR_TARGET} ${SOURCE_FILE}) +target_include_directories(${SIMULATOR_TARGET} PRIVATE ../../../../include) +set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${SIMULATOR_COMPILE_FLAGS}") +set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${SIMULATOR_LINK_FLAGS}") +add_custom_target(fpga_sim DEPENDS ${SIMULATOR_TARGET}) + ############################################################################### ### Generate Report ############################################################################### diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fpga_compile/src/fpga_compile.cpp b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fpga_compile/src/fpga_compile.cpp index 1a1523632a..69b3eac86f 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fpga_compile/src/fpga_compile.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fpga_compile/src/fpga_compile.cpp @@ -32,18 +32,21 @@ int main() { // Select either: // - the FPGA emulator device (CPU emulation of the FPGA) + // - the FPGA simulator // - the FPGA device (a real FPGA) #if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector device_selector; + ext::intel::fpga_emulator_selector selector; +#elif defined(FPGA_SIMULATOR) + ext::intel::fpga_simulator_selector selector; #else - ext::intel::fpga_selector device_selector; + ext::intel::fpga_selector selector; #endif try { // Create a queue bound to the chosen device. // If the device is unavailable, a SYCL runtime exception is thrown. - queue q(device_selector, fpga_tools::exception_handler); + queue q(selector, fpga_tools::exception_handler); // Print out the device information. std::cout << "Running on device: " From 0d29c71b07200a0d308bd9210ebd3c39e5ccf879 Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Tue, 13 Dec 2022 02:51:34 -0800 Subject: [PATCH 13/38] sim support to io_streaming Signed-off-by: Yohann Uguen --- .../DesignPatterns/io_streaming/README.md | 30 ++++++++++++++----- .../io_streaming/src/CMakeLists.txt | 21 +++++++++++-- .../io_streaming/src/io_streaming.cpp | 4 +++ 3 files changed, 46 insertions(+), 9 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/io_streaming/README.md b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/io_streaming/README.md index 4762b9be2f..5e0b8a8c11 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/io_streaming/README.md +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/io_streaming/README.md @@ -18,7 +18,7 @@ The purpose of this code sample is to demonstrate how to do trivial I/O streamin |:--- |:--- | OS | Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 | Hardware | Intel® Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA
FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX)
FPGA third-party/custom platforms with oneAPI support -| Software | Intel® oneAPI DPC++/C++ Compiler
Intel® FPGA Add-On for oneAPI Base Toolkit +| Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. > @@ -156,13 +156,17 @@ To learn more about the extensions and how to configure the oneAPI environment, ``` make fpga_emu ``` - 2. Generate HTML performance report. + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + make fpga_sim + ``` + 3. Generate HTML performance report. ``` make report ``` The report resides at `io_streaming_report.prj/reports/report.html`. - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). ``` make fpga ``` @@ -195,13 +199,17 @@ To learn more about the extensions and how to configure the oneAPI environment, ``` nmake fpga_emu ``` - 2. Generate HTML performance report. + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + nmake fpga_sim + ``` + 3. Generate HTML performance report. ``` nmake report ``` The report resides at `io_streaming_report.prj.a/reports/report.html`. - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). ``` nmake fpga ``` @@ -225,7 +233,11 @@ If you receive an error message, troubleshoot the problem using the **Diagnostic ``` ./io_streaming.fpga_emu ``` -2. Run the sample on the FPGA device. +2. Run the sample on the FPGA simulator device: + ``` + ./io_streaming.fpga_sim + ``` +3. Run the sample on the FPGA device. ``` ./io_streaming.fpga ``` @@ -236,7 +248,11 @@ If you receive an error message, troubleshoot the problem using the **Diagnostic ``` io_streaming.fpga_emu.exe ``` -2. Run the sample on the FPGA device. +2. Run the sample on the FPGA simulator device: + ``` + io_streaming.fpga_sim.exe + ``` +3. Run the sample on the FPGA device. ``` io_streaming.fpga.exe ``` diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/io_streaming/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/io_streaming/src/CMakeLists.txt index a0ec86ff7a..6b8610239c 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/io_streaming/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/io_streaming/src/CMakeLists.txt @@ -1,6 +1,7 @@ set(SOURCE_FILE io_streaming.cpp) set(TARGET_NAME io_streaming) set(EMULATOR_TARGET ${TARGET_NAME}.fpga_emu) +set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection @@ -28,9 +29,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR ${USM_HOST_ALLOCATIONS}") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR ${USM_HOST_ALLOCATIONS}") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga ${USM_HOST_ALLOCATIONS}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR ${USM_HOST_ALLOCATIONS}") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${USM_HOST_ALLOCATIONS}") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation @@ -48,6 +51,20 @@ set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_CO set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS}") add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET}) +############################################################################### +### FPGA Simulator +############################################################################### +# To compile in a single command: +# icpx -fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget= -DFPGA_SIMULATOR .cpp -o .fpga_sim +# CMake executes: +# [compile] icpx -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR -o .cpp.o -c .cpp +# [link] icpx -fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget= .cpp.o -o .fpga_sim +add_executable(${SIMULATOR_TARGET} ${SOURCE_FILE}) +target_include_directories(${SIMULATOR_TARGET} PRIVATE ../../../../include) +set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${SIMULATOR_COMPILE_FLAGS}") +set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${SIMULATOR_LINK_FLAGS}") +add_custom_target(fpga_sim DEPENDS ${SIMULATOR_TARGET}) + ############################################################################### ### Generate Report ############################################################################### diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/io_streaming/src/io_streaming.cpp b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/io_streaming/src/io_streaming.cpp index 54b2287f9d..c97a6f4b89 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/io_streaming/src/io_streaming.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/io_streaming/src/io_streaming.cpp @@ -32,6 +32,8 @@ int main() { #if defined(FPGA_EMULATOR) size_t count = 1 << 12; +#elif defined(FPGA_SIMULATOR) + size_t count = 1 << 5; #else size_t count = 1 << 24; #endif @@ -40,6 +42,8 @@ int main() { // device selector #if defined(FPGA_EMULATOR) ext::intel::fpga_emulator_selector selector; +#elif defined(FPGA_SIMULATOR) + ext::intel::fpga_simulator_selector selector; #else ext::intel::fpga_selector selector; #endif From 117b3c50f392abde8cf680b480ce921b88d38a07 Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Tue, 13 Dec 2022 02:52:02 -0800 Subject: [PATCH 14/38] sim support to shannonization Signed-off-by: Yohann Uguen --- .../DesignPatterns/shannonization/README.md | 17 ++++++++++++-- .../shannonization/src/CMakeLists.txt | 22 +++++++++++++++++-- .../shannonization/src/shannonization.cpp | 14 +++++++----- 3 files changed, 43 insertions(+), 10 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/README.md b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/README.md index 0508dd4d94..6852c4a1db 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/README.md +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/README.md @@ -188,6 +188,10 @@ To learn more about the extensions and how to configure the oneAPI environment, ``` make fpga_emu ``` + * Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + make fpga_sim + ``` * Generate the optimization report: ``` make report @@ -225,6 +229,10 @@ To learn more about the extensions and how to configure the oneAPI environment, ``` nmake fpga_emu ``` + * Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + nmake fpga_sim + ``` * Generate the optimization report: ``` nmake report @@ -330,12 +338,17 @@ As a consequence of the fabric architecture of the Intel Stratix® 10 SX FPGA ## Running the Sample - 1. Run the sample on the FPGA emulator (the kernel executes on the CPU): +1. Run the sample on the FPGA emulator (the kernel executes on the CPU): ``` ./shannonization.fpga_emu (Linux) shannonization.fpga_emu.exe (Windows) ``` -2. Run the sample on the FPGA device: +2. Run the sample on the FPGA simulator device: + ``` + ./shannonization.fpga_sim (Linux) + shannonization.fpga_sim.exe (Windows) + ``` +3. Run the sample on the FPGA device: ``` ./shannonization.fpga (Linux) shannonization.fpga.exe (Windows) diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/src/CMakeLists.txt index 145cfee6d7..9003ca978a 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/src/CMakeLists.txt @@ -1,6 +1,7 @@ set(SOURCE_FILE shannonization.cpp) set(TARGET_NAME shannonization) set(EMULATOR_TARGET ${TARGET_NAME}.fpga_emu) +set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) set(FPGA_TARGET ${TARGET_NAME}.fpga) set(REPORTS_TARGET ${TARGET_NAME}_report) @@ -36,14 +37,17 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR ${DEVICE_FLAG}") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR ${DEVICE_FLAG}") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga ${DEVICE_FLAG}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR ${DEVICE_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${DEVICE_FLAG}") if(FPGA_DEVICE MATCHES ".s10.*") # hyper-optimized-handshaking only applies to Intel Stratix® 10 FPGAs set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xshyper-optimized-handshaking=off -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") + set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xshyper-optimized-handshaking=off -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") else() set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") + set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") endif() # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation @@ -61,6 +65,20 @@ set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_CO set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS}") add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET}) +############################################################################### +### FPGA Simulator +############################################################################### +# To compile in a single command: +# icpx -fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget= -DFPGA_SIMULATOR .cpp -o .fpga_sim +# CMake executes: +# [compile] icpx -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR -o .cpp.o -c .cpp +# [link] icpx -fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget= .cpp.o -o .fpga_sim +add_executable(${SIMULATOR_TARGET} ${SOURCE_FILE}) +target_include_directories(${SIMULATOR_TARGET} PRIVATE ../../../../include) +set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${SIMULATOR_COMPILE_FLAGS}") +set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${SIMULATOR_LINK_FLAGS}") +add_custom_target(fpga_sim DEPENDS ${SIMULATOR_TARGET}) + ############################################################################### ### Generate Report ############################################################################### diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/src/shannonization.cpp b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/src/shannonization.cpp index a65de9d1e5..961e9dc79f 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/src/shannonization.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/src/shannonization.cpp @@ -124,7 +124,7 @@ bool Intersection(queue& q, std::vector& a, // For emulation, just do a single iteration. // For hardware, perform multiple iterations for a more // accurate throughput measurement -#if defined(FPGA_EMULATOR) +#if defined(FPGA_EMULATOR) || defined(FPGA_SIMULATOR) int iterations = 1; #else int iterations = 5; @@ -163,7 +163,7 @@ bool Intersection(queue& q, std::vector& a, // The FPGA emulator does not accurately represent the hardware performance // so we don't print performance results when running with the emulator if (success) { -#ifndef FPGA_EMULATOR +#if !defined(FPGA_EMULATOR) && !defined(FPGA_SIMULATOR) // Compute the average throughput across all iterations. // We use the first iteration as a 'warmup' for the FPGA, // so we ignore its results. @@ -187,7 +187,7 @@ bool Intersection(queue& q, std::vector& a, int main(int argc, char** argv) { // parse the command line arguments -#if defined(FPGA_EMULATOR) +#if defined(FPGA_EMULATOR) || defined(FPGA_SIMULATOR) unsigned int a_size = 128; unsigned int b_size = 256; #else @@ -257,13 +257,15 @@ int main(int argc, char** argv) { // the device selector #ifdef FPGA_EMULATOR - ext::intel::fpga_emulator_selector device_selector; + ext::intel::fpga_emulator_selector selector; +#elif defined(FPGA_SIMULATOR) + ext::intel::fpga_simulator_selector selector; #else - ext::intel::fpga_selector device_selector; + ext::intel::fpga_selector selector; #endif // create the device queue - queue q(device_selector, props); + queue q(selector, props); bool success = true; From 6c07970b188eeb8258de963a1684db611803387a Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Tue, 13 Dec 2022 03:14:47 -0800 Subject: [PATCH 15/38] sim support to merge_sort Signed-off-by: Yohann Uguen --- .../ReferenceDesigns/merge_sort/README.md | 46 +++++++++++++------ .../merge_sort/src/CMakeLists.txt | 16 ++++++- .../ReferenceDesigns/merge_sort/src/main.cpp | 11 ++++- 3 files changed, 55 insertions(+), 18 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/README.md b/DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/README.md index 8b853fa500..ccd77eb9d4 100755 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/README.md +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/README.md @@ -133,19 +133,23 @@ For `constexpr_math.hpp`, `pipe_utils.hpp`, and `unrolled_loop.hpp` see the READ 3. Compile the design. (The provided targets match the recommended development flow.) 1. Compile for emulation (fast compile time, targets emulated FPGA device). - ``` - make fpga_emu - ``` - 2. Generate the HTML performance report. - ``` - make report - ``` + ``` + make fpga_emu + ``` + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + make fpga_sim + ``` + 3. Generate the HTML performance report. + ``` + make report + ``` The report resides at `merge_sort_report.prj/reports/report.html`. - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). - ``` - make fpga - ``` + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). + ``` + make fpga + ``` (Optional) The hardware compiles listed above can take several hours to complete; alternatively, you can download FPGA precompiled binaries (compatible with Linux* Ubuntu* 18.04) from [https://iotdk.intel.com/fpga-precompiled-binaries/latest/merge_sort.fpga.tar.gz](https://iotdk.intel.com/fpga-precompiled-binaries/latest/merge_sort.fpga.tar.gz). @@ -170,13 +174,17 @@ For `constexpr_math.hpp`, `pipe_utils.hpp`, and `unrolled_loop.hpp` see the READ ``` nmake fpga_emu ``` - 2. Generate the HTML performance report. + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + nmake fpga_sim + ``` + 3. Generate the HTML performance report. ``` nmake report ``` The report resides at `merge_sort_report.a.prj/reports/report.html`. - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). ``` nmake fpga ``` @@ -190,7 +198,11 @@ For `constexpr_math.hpp`, `pipe_utils.hpp`, and `unrolled_loop.hpp` see the READ ``` ./merge_sort.fpga_emu ``` -2. Run the sample on the FPGA device. +2. Run the sample on the FPGA simulator device: + ``` + ./merge_sort.fpga_sim + ``` +3. Run the sample on the FPGA device. ``` ./merge_sort.fpga ``` @@ -200,7 +212,11 @@ For `constexpr_math.hpp`, `pipe_utils.hpp`, and `unrolled_loop.hpp` see the READ ``` merge_sort.fpga_emu.exe ``` -2. Run the sample on the FPGA device. +2. Run the sample on the FPGA simulator device: + ``` + merge_sort.fpga_sim.exe + ``` +3. Run the sample on the FPGA device. ``` merge_sort.fpga.exe ``` diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/src/CMakeLists.txt index 7bc6e10c1e..6a958d4c9c 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/src/CMakeLists.txt @@ -1,6 +1,7 @@ set(TARGET_NAME merge_sort) set(SOURCE_FILE main.cpp) set(EMULATOR_TARGET ${TARGET_NAME}.fpga_emu) +set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection @@ -65,9 +66,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG} -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG}") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG} ${USER_HARDWARE_FLAGS}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG}") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware ${PROFILE_FLAG} -Xsparallel=2 ${SEED_FLAG} -Xstarget=${FPGA_DEVICE} ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation @@ -80,6 +83,15 @@ set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_CO set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS}") add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET}) +############################################################################### +### FPGA Simulator +############################################################################### +add_executable(${SIMULATOR_TARGET} ${SOURCE_FILE}) +target_include_directories(${SIMULATOR_TARGET} PRIVATE ../../../include) +set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${SIMULATOR_COMPILE_FLAGS}") +set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${SIMULATOR_LINK_FLAGS}") +add_custom_target(fpga_sim DEPENDS ${SIMULATOR_TARGET}) + ############################################################################### ### Generate Report ############################################################################### diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/src/main.cpp b/DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/src/main.cpp index fdf25ca905..773cfbc0db 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/src/main.cpp +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/src/main.cpp @@ -34,8 +34,12 @@ constexpr bool kUseUSMHostAllocation = false; // This can be set by defining the preprocessor macro 'MERGE_UNITS' // otherwise the default value below is used. #ifndef MERGE_UNITS +#if defined(FPGA_SIMULATOR) +#define MERGE_UNITS 2 +#else #define MERGE_UNITS 8 #endif +#endif constexpr size_t kMergeUnits = MERGE_UNITS; static_assert(kMergeUnits > 0); static_assert(fpga_tools::IsPow2(kMergeUnits)); @@ -73,9 +77,12 @@ int main(int argc, char *argv[]) { // reading and validating the command line arguments // defaults bool passed = true; -#ifdef FPGA_EMULATOR +#if defined(FPGA_EMULATOR) IndexT count = 128; int runs = 2; +#elif defined(FPGA_SIMULATOR) + IndexT count = 16; + int runs = 2; #else IndexT count = 1 << 24; int runs = 17; @@ -120,6 +127,8 @@ int main(int argc, char *argv[]) { // the device selector #ifdef FPGA_EMULATOR ext::intel::fpga_emulator_selector selector; +#elif defined(FPGA_SIMULATOR) + ext::intel::fpga_simulator_selector selector; #else ext::intel::fpga_selector selector; #endif From d2bc81088a1bd6b6f567157fa0173e93aa31b95a Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Tue, 13 Dec 2022 03:36:47 -0800 Subject: [PATCH 16/38] fix existing READMEs with sim support Signed-off-by: Yohann Uguen --- .../ReferenceDesigns/cholesky/README.md | 28 ++++++++--- .../cholesky_inversion/README.md | 46 +++++++++++++------ .../DPC++FPGA/ReferenceDesigns/qrd/README.md | 32 +++++++++++-- .../DPC++FPGA/ReferenceDesigns/qri/README.md | 32 +++++++++++-- 4 files changed, 109 insertions(+), 29 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky/README.md b/DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky/README.md index d8206494c2..0386ac8c95 100755 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky/README.md +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky/README.md @@ -161,13 +161,17 @@ For `constexpr_math.hpp`, `memory_utils.hpp`, `metaprogramming_utils.hpp`, and ` ``` make fpga_emu ``` - 2. Generate the HTML performance report. + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + make fpga_sim + ``` + 3. Generate the HTML performance report. ``` make report ``` The report resides at `cholesky_report.prj/reports/report.html`. - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). ``` make fpga ``` @@ -194,11 +198,15 @@ For `constexpr_math.hpp`, `memory_utils.hpp`, `metaprogramming_utils.hpp`, and ` ``` nmake fpga_emu ``` - 2. Generate the HTML performance report. + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + nmake fpga_sim + ``` + 3. Generate the HTML performance report. ``` nmake report ``` - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). ``` nmake fpga ``` @@ -224,7 +232,11 @@ You can apply the Cholesky decomposition to a number of matrices, as shown below ``` ./cholesky.fpga_emu ``` -2. Run the sample on the FPGA device. +2. Run the sample on the FPGA simulator. + ``` + ./cholesky.fpga_sim + ``` +3. Run the sample on the FPGA device. ``` ./cholesky.fpga ``` @@ -235,7 +247,11 @@ You can apply the Cholesky decomposition to a number of matrices, as shown below ``` cholesky.fpga_emu.exe ``` -2. Run the sample on the FPGA device. +2. Run the sample on the FPGA simulator. + ``` + cholesky.fpga_sim.exe + ``` +3. Run the sample on the FPGA device. ``` cholesky.fpga.exe ``` diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky_inversion/README.md b/DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky_inversion/README.md index b163328a3b..d6f1a51f72 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky_inversion/README.md +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky_inversion/README.md @@ -180,19 +180,23 @@ Additionaly, the cmake build system can be configured using the following parame 3. Compile the design. (The provided targets match the recommended development flow.) 1. Compile for emulation (fast compile time, targets emulated FPGA device). - ``` - make fpga_emu - ``` - 2. Generate the HTML performance report. - ``` - make report - ``` + ``` + make fpga_emu + ``` + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + make fpga_sim + ``` + 3. Generate the HTML performance report. + ``` + make report + ``` The report resides at `cholesky_inversion_report.prj/reports/report.html`. - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). - ``` - make fpga - ``` + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). + ``` + make fpga + ``` (Optional) The hardware compiles listed above can take several hours to complete; alternatively, you can download FPGA precompiled binaries (compatible with Linux* Ubuntu* 18.04) from [https://iotdk.intel.com/fpga-precompiled-binaries/latest/cholesky_inversion.fpga.tar.gz](https://iotdk.intel.com/fpga-precompiled-binaries/latest/cholesky_inversion.fpga.tar.gz). @@ -218,13 +222,17 @@ Additionaly, the cmake build system can be configured using the following parame ``` nmake fpga_emu ``` - 2. Generate the HTML performance report. + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + nmake fpga_sim + ``` + 3. Generate the HTML performance report. ``` nmake report ``` The report resides at `cholesky_inversion_report.a.prj/reports/report.html`. - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). ``` nmake fpga ``` @@ -251,7 +259,11 @@ You can apply the Cholesky-based inversion to 8 matrices repeated a number of ti ``` ./cholesky_inversion.fpga_emu ``` -2. Run on the FPGA device. +2. Run the sample on the FPGA simulator. + ``` + ./cholesky_inversion.fpga_sim + ``` +3. Run on the FPGA device. ``` ./cholesky_inversion.fpga ``` @@ -262,7 +274,11 @@ You can apply the Cholesky-based inversion to 8 matrices repeated a number of ti ``` cholesky_inversion.fpga_emu.exe ``` -2. Run on the FPGA device. +2. Run the sample on the FPGA simulator. + ``` + cholesky_inversion.fpga_sim.exe + ``` +3. Run on the FPGA device. ``` cholesky_inversion.fpga.exe ``` diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/qrd/README.md b/DirectProgramming/DPC++FPGA/ReferenceDesigns/qrd/README.md index 922b663389..dfb66d70b6 100755 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/qrd/README.md +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/qrd/README.md @@ -152,13 +152,17 @@ Additionaly, the cmake build system can be configured using the following parame ``` make fpga_emu ``` - 2. Generate HTML performance report. + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + make fpga_sim + ``` + 3. Generate HTML performance report. ``` make report ``` The report resides at `qrd_report/reports/report.html`. - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). ``` make fpga ``` @@ -187,13 +191,17 @@ Additionaly, the cmake build system can be configured using the following parame ``` nmake fpga_emu ``` - 2. Generate HTML performance report. + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + nmake fpga_sim + ``` + 3. Generate HTML performance report. ``` nmake report ``` The report resides at `qrd_report.a.prj/reports/report.html`. - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). ``` nmake fpga ``` @@ -222,6 +230,14 @@ You can perform the QR decomposition of the set of matrices repeatedly. This ste export CL_CONFIG_CPU_FORCE_PRIVATE_MEM_SIZE=32MB ./qrd.fpga_emu ``` + +#### Run on FPGA Simulator + +1. Run the sample on the FPGA simulator. + ``` + ./qrd.fpga_sim + ``` + #### Run on FPGA 1. Run the sample on the FPGA device. @@ -239,6 +255,14 @@ You can perform the QR decomposition of the set of matrices repeatedly. This ste set CL_CONFIG_CPU_FORCE_PRIVATE_MEM_SIZE=32MB qrd.fpga_emu.exe ``` + +#### Run on FPGA Simulator + +1. Run the sample on the FPGA simulator. + ``` + qrd.fpga_sim.exe + ``` + #### Run on FPGA 1. Run the sample on the FPGA device. diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/qri/README.md b/DirectProgramming/DPC++FPGA/ReferenceDesigns/qri/README.md index cb3070c081..fbb461c663 100755 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/qri/README.md +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/qri/README.md @@ -144,13 +144,17 @@ Additionaly, the cmake build system can be configured using the following parame ``` make fpga_emu ``` - 2. Generate HTML performance report. + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + make fpga_sim + ``` + 3. Generate HTML performance report. ``` make report ``` The report resides at `qri_report/reports/report.html`. - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). ``` make fpga ``` @@ -179,13 +183,17 @@ Additionaly, the cmake build system can be configured using the following parame ``` nmake fpga_emu ``` - 2. Generate HTML performance report. + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + nmake fpga_sim + ``` + 3. Generate HTML performance report. ``` nmake report ``` The report resides at `qri_report.a.prj/reports/report.html`. - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). ``` nmake fpga ``` @@ -215,6 +223,14 @@ You can perform the QR-based inversion of the set of matrices repeatedly, as sho export CL_CONFIG_CPU_FORCE_PRIVATE_MEM_SIZE=32MB ./qri.fpga_emu ``` + +#### Run on FPGA Simulator + +1. Run the sample on the FPGA simulator. + ``` + ./qri.fpga_sim + ``` + #### Run on FPGA 1. Run the sample on the FPGA device. @@ -232,6 +248,14 @@ You can perform the QR-based inversion of the set of matrices repeatedly, as sho set CL_CONFIG_CPU_FORCE_PRIVATE_MEM_SIZE=32MB qri.fpga_emu.exe ``` + +#### Run on FPGA Simulator + +1. Run the sample on the FPGA simulator. + ``` + qri.fpga_sim.exe + ``` + #### Run on FPGA 1. Run the sample on the FPGA device. From 6b607008123654408b0ae348ad818e2f76524720 Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Tue, 13 Dec 2022 05:35:07 -0800 Subject: [PATCH 17/38] sim support for mvdr Signed-off-by: Yohann Uguen --- .../mvdr_beamforming/README.md | 54 ++++++++++++------- .../mvdr_beamforming/src/CMakeLists.txt | 10 ++-- .../mvdr_beamforming/src/mvdr_beamforming.cpp | 6 +++ 3 files changed, 46 insertions(+), 24 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/README.md b/DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/README.md index 3e089f7159..c506b420aa 100755 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/README.md +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/README.md @@ -132,19 +132,23 @@ The `DataProducer` kernel replaces the input IO pipe in the first image. The spl 3. Compile the design. (The provided targets match the recommended development flow.) 1. Compile for emulation (fast compile time, targets emulated FPGA device). - ``` - make fpga_emu - ``` - 2. Generate the HTML performance report. - ``` - make report - ``` + ``` + make fpga_emu + ``` + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + make fpga_sim + ``` + 3. Generate the HTML performance report. + ``` + make report + ``` The report resides at `mvdr_beamforming_report.prj/reports/report.html`. - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). - ``` - make fpga - ``` + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). + ``` + make fpga + ``` (Optional) The hardware compiles listed above can take several hours to complete; alternatively, you can download FPGA precompiled binaries (compatible with Linux* Ubuntu* 18.04) from [https://iotdk.intel.com/fpga-precompiled-binaries/latest/mvdr_beamforming.fpga.tar.gz](https://iotdk.intel.com/fpga-precompiled-binaries/latest/mvdr_beamforming.fpga.tar.gz). @@ -169,13 +173,17 @@ The `DataProducer` kernel replaces the input IO pipe in the first image. The spl ``` nmake fpga_emu ``` - 2. Generate the HTML performance report. + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + nmake fpga_sim + ``` + 3. Generate the HTML performance report. ``` nmake report ``` The report resides at `mvdr_beamforming_report.a.prj/reports/report.html`. - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). ``` nmake fpga ``` @@ -196,11 +204,15 @@ The general syntax for running the program is shown below and the table describe | 2 | The output directory (default=`.`) ### On Linux - 1. Run the sample on the FPGA emulator (the kernel executes on the CPU). - ``` - ./mvdr_beamforming.fpga_emu 1024 ../data . - ``` -2. Run the sample on the FPGA device. +1. Run the sample on the FPGA emulator (the kernel executes on the CPU). + ``` + ./mvdr_beamforming.fpga_emu 1024 ../data . + ``` +2. Run the sample on the FPGA simulator device: + ``` + ./mvdr_beamforming.fpga_sim 1024 ../data . + ``` +3. Run the sample on the FPGA device. ``` ./mvdr_beamforming.fpga 1024 ../data . ``` @@ -211,7 +223,11 @@ The general syntax for running the program is shown below and the table describe ``` mvdr_beamforming.fpga_emu.exe 1024 ../data . ``` -2. Run the sample on the FPGA device. +2. Run the sample on the FPGA simulator device: + ``` + mvdr_beamforming.fpga_sim.exe ../data . + ``` +3. Run the sample on the FPGA device. ``` mvdr_beamforming.fpga.exe 1024 ../data . ``` diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/src/CMakeLists.txt index e475353d44..0bec59a4ba 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/src/CMakeLists.txt @@ -86,12 +86,12 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -fbracket-depth=512 ${AC_TYPES_FLAG} ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${STREAMING_PIPE_WIDTH_FLAG} -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -fbracket-depth=512 ${AC_TYPES_FLAG} ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${STREAMING_PIPE_WIDTH_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} ${ENABLE_USM}") -set(SIMULATOR_COMPILE_FLAGS "${WIN_FLAG} -Wall -fsycl -fintelfpga -fbracket-depth=512 ${AC_TYPES_FLAG} ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${STREAMING_PIPE_WIDTH_FLAG} -DFPGA_SIMULATOR") -set(HARDWARE_COMPILE_FLAGS "${WIN_FLAG} -fbracket-depth=512 -fsycl -fintelfpga ${AC_TYPES_FLAG} ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${REAL_IO_PIPES_FLAG} ${STREAMING_PIPE_WIDTH_FLAG}") -set(REPORT_LINK_FLAGS "-Wall -fsycl -fintelfpga -Xshardware -fbracket-depth=512 ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${REAL_IO_PIPES_FLAG} ${STREAMING_PIPE_WIDTH_FLAG} ${PROFILE_FLAG} -Xsparallel=2 -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} ${UDP_LINK_FLAGS}") -set(SIMULATOR_LINK_FLAGS "${REPORT_LINK_FLAGS} ${AC_TYPES_FLAG} -Xssimulation -Xsghdl") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -fbracket-depth=512 ${AC_TYPES_FLAG} ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${STREAMING_PIPE_WIDTH_FLAG} -DFPGA_SIMULATOR") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Wall -fbracket-depth=512 ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${REAL_IO_PIPES_FLAG} ${STREAMING_PIPE_WIDTH_FLAG} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} ${UDP_LINK_FLAGS} ${AC_TYPES_FLAG} -Xssimulation -Xsghdl") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga ${WIN_FLAG} -fbracket-depth=512 ${AC_TYPES_FLAG} ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${REAL_IO_PIPES_FLAG} ${STREAMING_PIPE_WIDTH_FLAG}") +set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -Wall -Xshardware -fbracket-depth=512 ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${REAL_IO_PIPES_FLAG} ${STREAMING_PIPE_WIDTH_FLAG} ${PROFILE_FLAG} -Xsparallel=2 -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} ${UDP_LINK_FLAGS}") set(HARDWARE_LINK_FLAGS "${REPORT_LINK_FLAGS} ${AC_TYPES_FLAG}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/src/mvdr_beamforming.cpp b/DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/src/mvdr_beamforming.cpp index e50ddb9012..7266389bff 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/src/mvdr_beamforming.cpp +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/src/mvdr_beamforming.cpp @@ -154,7 +154,11 @@ void PrintUsage(); // the main function int main(int argc, char *argv[]) { UDPArgs udp_args; +#if defined(FPGA_SIMULATOR) + int num_matrix_copies = 2; +#else int num_matrix_copies = 1024; +#endif std::string in_dir = "../data"; std::string out_dir = "."; @@ -222,6 +226,8 @@ int main(int argc, char *argv[]) { // device selector #if defined(FPGA_EMULATOR) ext::intel::fpga_emulator_selector selector; +#elif defined(FPGA_SIMULATOR) + ext::intel::fpga_simulator_selector selector; #else ext::intel::fpga_selector selector; #endif From 421dbf961cf1fc6d97a2cc68911396f0650d0acb Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Tue, 13 Dec 2022 07:04:35 -0800 Subject: [PATCH 18/38] reducing decompress time Signed-off-by: Yohann Uguen --- .../ReferenceDesigns/decompress/src/main.cpp | 20 ++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/main.cpp b/DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/main.cpp index a15df060fa..35132404d2 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/main.cpp +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/main.cpp @@ -185,6 +185,7 @@ bool RunGzipTest(sycl::queue& q, GzipDecompressorT decompressor, std::string dynamic_compress_filename = test_dir + "/dynamic_compressed.gz"; std::string tp_test_filename = test_dir + "/tp_test.gz"; +#ifndef FPGA_SIMULATOR std::cout << ">>>>> Uncompressed File Test <<<<<" << std::endl; bool uncompressed_test_pass = decompressor.DecompressFile( q, uncompressed_filename, "", 1, false, false); @@ -196,6 +197,12 @@ bool RunGzipTest(sycl::queue& q, GzipDecompressorT decompressor, q, static_compress_filename, "", 1, false, false); PrintTestResults("Statically Compressed File Test", static_test_pass); std::cout << std::endl; +#else + std::cout << "Only running the Dynamically Compressed File Test when using " + "the simulator flow to reduce execution time." << std::endl; + bool uncompressed_test_pass = true; + bool static_test_pass = true; +#endif std::cout << ">>>>> Dynamically Compressed File Test <<<<<" << std::endl; bool dynamic_test_pass = decompressor.DecompressFile( @@ -203,12 +210,17 @@ bool RunGzipTest(sycl::queue& q, GzipDecompressorT decompressor, PrintTestResults("Dynamically Compressed File Test", dynamic_test_pass); std::cout << std::endl; + +#ifndef FPGA_SIMULATOR std::cout << ">>>>> Throughput Test <<<<<" << std::endl; constexpr int kTPTestRuns = 5; bool tp_test_pass = decompressor.DecompressFile(q, tp_test_filename, "", kTPTestRuns, true, false); PrintTestResults("Throughput Test", tp_test_pass); std::cout << std::endl; +#else + bool tp_test_pass = true; +#endif return uncompressed_test_pass && static_test_pass && dynamic_test_pass && tp_test_pass; @@ -231,6 +243,7 @@ bool RunSnappyTest(sycl::queue& q, SnappyDecompressorT decompressor, PrintTestResults("Alice In Wonderland Test", alice_test_pass); std::cout << std::endl; +#ifndef FPGA_SIMULATOR std::cout << ">>>>> Only Literal Strings Test <<<<<" << std::endl; auto test1_bytes = GenerateSnappyCompressedData(333, 3, 0, 0, 3); auto test1_ret = decompressor.DecompressBytes(q, test1_bytes, 1, false); @@ -265,6 +278,11 @@ bool RunSnappyTest(sycl::queue& q, SnappyDecompressorT decompressor, PrintTestResults("Throughput Test", test_tp_pass); std::cout << std::endl; - return test1_pass && test2_pass && test3_pass && test_tp_pass; + return alice_test_pass && test1_pass && test2_pass && test3_pass && + test_tp_pass; +#else + return alice_test_pass; +#endif + } #endif From db66fedd2d2714ddb276a3a3907e8bec5353e1a8 Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Tue, 13 Dec 2022 08:21:19 -0800 Subject: [PATCH 19/38] update selectors on ref designs Signed-off-by: Yohann Uguen --- .../ReferenceDesigns/anr/src/CMakeLists.txt | 2 +- .../ReferenceDesigns/anr/src/main.cpp | 21 ++++++++------ .../board_test/src/CMakeLists.txt | 4 +-- .../board_test/src/board_test.cpp | 15 ++++++---- .../cholesky/src/CMakeLists.txt | 4 +-- .../cholesky/src/cholesky_demo.cpp | 23 +++++++-------- .../cholesky_inversion/src/CMakeLists.txt | 4 +-- .../src/cholesky_inversion_demo.cpp | 23 +++++++-------- .../ReferenceDesigns/crr/src/CMakeLists.txt | 16 +++++++++-- .../ReferenceDesigns/crr/src/main.cpp | 28 +++++++++++-------- .../ReferenceDesigns/db/src/CMakeLists.txt | 4 +-- .../DPC++FPGA/ReferenceDesigns/db/src/db.cpp | 20 +++++++------ .../decompress/src/CMakeLists.txt | 6 ++-- .../ReferenceDesigns/decompress/src/main.cpp | 19 ++++++++----- .../ReferenceDesigns/gzip/src/CMakeLists.txt | 6 ++-- .../ReferenceDesigns/gzip/src/gzip.cpp | 23 +++++++++------ .../ReferenceDesigns/gzip/src/gzip_ll.cpp | 23 +++++++++------ .../merge_sort/src/CMakeLists.txt | 2 +- .../ReferenceDesigns/merge_sort/src/main.cpp | 22 +++++++++------ .../mvdr_beamforming/src/CMakeLists.txt | 2 +- .../mvdr_beamforming/src/mvdr_beamforming.cpp | 18 ++++++++---- .../ReferenceDesigns/qrd/src/CMakeLists.txt | 4 +-- .../ReferenceDesigns/qrd/src/qrd_demo.cpp | 19 +++++++------ .../ReferenceDesigns/qri/src/CMakeLists.txt | 4 +-- .../ReferenceDesigns/qri/src/qri_demo.cpp | 20 +++++++------ 25 files changed, 195 insertions(+), 137 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/CMakeLists.txt index 35d3150422..84e197a7d2 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/CMakeLists.txt @@ -125,7 +125,7 @@ set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} -Xssimulation -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -Xshardware ${PROFILE_FLAG} ${FLAT_COMPILE_FLAG} -Xsparallel=2 ${SEED_FLAG} -Xstarget=${FPGA_DEVICE} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} ${IP_MODE_FLAG} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "${REPORT_LINK_FLAGS} ${AC_TYPES_FLAG}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/main.cpp b/DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/main.cpp index 195795bd02..e0f9931946 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/main.cpp +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/main.cpp @@ -81,14 +81,12 @@ int main(int argc, char* argv[]) { } ///////////////////////////////////////////////////////////// -#if defined(FPGA_EMULATOR) - // the device selector - ext::intel::fpga_emulator_selector selector; -#elif defined(FPGA_SIMULATOR) - // the device simulator - ext::intel::fpga_simulator_selector selector; -#else - ext::intel::fpga_selector selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif // create the device queue @@ -102,6 +100,13 @@ int main(int argc, char* argv[]) { std::terminate(); } + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + + // parse the input files int cols, rows, pixel_count; ANRParams params; diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/board_test/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/ReferenceDesigns/board_test/src/CMakeLists.txt index 5bcccb66c5..00ec0ad4b6 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/board_test/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/board_test/src/CMakeLists.txt @@ -30,9 +30,9 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "${PLATFORM_SPECIFIC_COMPILE_FLAGS} -fsycl -fintelfpga -DFPGA_EMULATOR -Wformat-security -Werror=format-security -Wall") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -DFPGA_EMULATOR -Wformat-security -Werror=format-security -Wall") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "${PLATFORM_SPECIFIC_COMPILE_FLAGS} -fsycl -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -DFPGA_HARDWARE") # By default oneAPI compiler burst interleaves across same memory type, # -Xsno-interleaving is used to disable burst interleaving and test each memory bank independently # Refer to https://www.intel.com/content/www/us/en/develop/documentation/oneapi-fpga-optimization-guide/top/flags-attr-prag-ext/optimization-flags/disabl-burst-int.html for more information diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/board_test/src/board_test.cpp b/DirectProgramming/DPC++FPGA/ReferenceDesigns/board_test/src/board_test.cpp index cb011358cc..ad9a244d9a 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/board_test/src/board_test.cpp +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/board_test/src/board_test.cpp @@ -49,10 +49,10 @@ int main(int argc, char* argv[]) { // - the FPGA emulator device (CPU emulation of the FPGA) using FPGA_EMULATOR // macro // - the FPGA device (a real FPGA) -#if defined(FPGA_EMULATOR) - sycl::ext::intel::fpga_emulator_selector device_selector; -#else - sycl::ext::intel::fpga_selector device_selector; +#if FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif // Variable ORed with result of each test @@ -66,11 +66,14 @@ int main(int argc, char* argv[]) { // Create a queue bound to the chosen device // If the device is unavailable, a SYCL runtime exception is thrown - sycl::queue q(device_selector, fpga_tools::exception_handler, q_prop_list); + sycl::queue q(selector, fpga_tools::exception_handler, q_prop_list); + + auto device = q.get_device(); // Print out the device information. std::cout << "Running on device: " - << q.get_device().get_info() << "\n"; + << device.get_info() + << std::endl; // Create a oneAPI Shim object ShimMetrics hldshim(q); diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky/src/CMakeLists.txt index 9b00cb0c1e..eaccfce68f 100755 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky/src/CMakeLists.txt @@ -79,11 +79,11 @@ message(STATUS "SEED=${SEED}") # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fbracket-depth=512 -fsycl -fintelfpga -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS}") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -DFPGA_SIMULATOR -fbracket-depth=512 -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -Xsfp-relaxed ${USER_SIMULATOR_FLAGS}") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} -Xssimulation -Xsghdl -Xsclock=${CLOCK_TARGET} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} -Xsfp-relaxed") -set(HARDWARE_COMPILE_FLAGS "-Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fsycl -fintelfpga -fbracket-depth=512 -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -Xsfp-relaxed") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -Xsfp-relaxed -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} -Xshardware -Xsclock=${CLOCK_TARGET} -Xsparallel=2 ${SEED} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} -Xsfp-relaxed") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky/src/cholesky_demo.cpp b/DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky/src/cholesky_demo.cpp index 68d0507265..e1a7414a75 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky/src/cholesky_demo.cpp +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky/src/cholesky_demo.cpp @@ -87,23 +87,24 @@ int main(int argc, char *argv[]) { } try { - // SYCL boilerplate -#if defined(FPGA_EMULATOR) - sycl::ext::intel::fpga_emulator_selector device_selector; -#elif defined(FPGA_SIMULATOR) - sycl::ext::intel::fpga_simulator_selector device_selector; -#else - sycl::ext::intel::fpga_selector device_selector; + +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif // Enable the queue profiling to time the execution sycl::queue q = sycl::queue( - device_selector, fpga_tools::exception_handler, + selector, fpga_tools::exception_handler, sycl::property_list{sycl::property::queue::enable_profiling()}); sycl::device device = q.get_device(); - std::cout << "Device name: " - << device.get_info().c_str() - << std::endl; + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; // Select a type for this compile depending on the value of COMPLEX using T = std::conditional_t, float>; diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky_inversion/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky_inversion/src/CMakeLists.txt index f06916cfba..3b7ab5af32 100755 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky_inversion/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky_inversion/src/CMakeLists.txt @@ -88,11 +88,11 @@ message(STATUS "SEED=${SEED}") # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fbracket-depth=512 -fsycl -fintelfpga -DFIXED_ITERATIONS_DECOMPOSITION=${FIXED_ITERATIONS_DECOMPOSITION} -DFIXED_ITERATIONS_INVERSION=${FIXED_ITERATIONS_INVERSION} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS_DECOMPOSITION=${FIXED_ITERATIONS_DECOMPOSITION} -DFIXED_ITERATIONS_INVERSION=${FIXED_ITERATIONS_INVERSION} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS}") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -DFPGA_SIMULATOR -DFIXED_ITERATIONS_DECOMPOSITION=${FIXED_ITERATIONS_DECOMPOSITION} -DFIXED_ITERATIONS_INVERSION=${FIXED_ITERATIONS_INVERSION} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -Xsfp-relaxed ${USER_HARDWARE_FLAGS}") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} -Xssimulation -Xsghdl -Xsclock=${CLOCK_TARGET} -Xstarget=${FPGA_DEVICE} ${USER_SIMULATOR_FLAGS} -Xsfp-relaxed") -set(HARDWARE_COMPILE_FLAGS "-Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fsycl -fintelfpga -fbracket-depth=512 -DFIXED_ITERATIONS_DECOMPOSITION=${FIXED_ITERATIONS_DECOMPOSITION} -DFIXED_ITERATIONS_INVERSION=${FIXED_ITERATIONS_INVERSION} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -Xsfp-relaxed") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS_DECOMPOSITION=${FIXED_ITERATIONS_DECOMPOSITION} -DFIXED_ITERATIONS_INVERSION=${FIXED_ITERATIONS_INVERSION} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -Xsfp-relaxed -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} -Xshardware -Xsclock=${CLOCK_TARGET} -Xsparallel=2 ${SEED} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} -Xsfp-relaxed") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky_inversion/src/cholesky_inversion_demo.cpp b/DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky_inversion/src/cholesky_inversion_demo.cpp index 4b1b166bcc..1b3cf218e2 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky_inversion/src/cholesky_inversion_demo.cpp +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky_inversion/src/cholesky_inversion_demo.cpp @@ -357,23 +357,24 @@ int main(int argc, char *argv[]) { } try { - // SYCL boilerplate -#if defined(FPGA_EMULATOR) - sycl::ext::intel::fpga_emulator_selector device_selector; -#elif defined(FPGA_SIMULATOR) - sycl::ext::intel::fpga_simulator_selector device_selector; -#else - sycl::ext::intel::fpga_selector device_selector; + +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif // Enable the queue profiling to time the execution sycl::queue q = sycl::queue( - device_selector, fpga_tools::exception_handler, + selector, fpga_tools::exception_handler, sycl::property_list{sycl::property::queue::enable_profiling()}); sycl::device device = q.get_device(); - std::cout << "Device name: " - << device.get_info().c_str() - << std::endl; + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; // Select a type for this compile depending on the value of COMPLEX using T = std::conditional_t, float>; diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/CMakeLists.txt index 4035ba1c89..cd32206f06 100755 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/CMakeLists.txt @@ -1,6 +1,7 @@ set(TARGET_NAME crr) set(SOURCE_FILE main.cpp) set(EMULATOR_TARGET ${TARGET_NAME}.fpga_emu) +set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection @@ -53,9 +54,11 @@ message(STATUS "OUTER_UNROLL_POW2=${OUTER_UNROLL_POW2}") # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DOUTER_UNROLL=${OUTER_UNROLL} -DINNER_UNROLL=${INNER_UNROLL} -DOUTER_UNROLL_POW2=${OUTER_UNROLL_POW2} -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DOUTER_UNROLL=${OUTER_UNROLL} -DINNER_UNROLL=${INNER_UNROLL} -DOUTER_UNROLL_POW2=${OUTER_UNROLL_POW2} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga -DOUTER_UNROLL=${OUTER_UNROLL} -DINNER_UNROLL=${INNER_UNROLL} -DOUTER_UNROLL_POW2=${OUTER_UNROLL_POW2}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DOUTER_UNROLL=${OUTER_UNROLL} -DINNER_UNROLL=${INNER_UNROLL} -DOUTER_UNROLL_POW2=${OUTER_UNROLL_POW2}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DOUTER_UNROLL=${OUTER_UNROLL} -DINNER_UNROLL=${INNER_UNROLL} -DOUTER_UNROLL_POW2=${OUTER_UNROLL_POW2} -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} -Xsdaz -Xsrounding=faithful -DOUTER_UNROLL=${OUTER_UNROLL} -DINNER_UNROLL=${INNER_UNROLL} -DOUTER_UNROLL_POW2=${OUTER_UNROLL_POW2} ${USER_HARDWARE_FLAGS}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DOUTER_UNROLL=${OUTER_UNROLL} -DINNER_UNROLL=${INNER_UNROLL} -DOUTER_UNROLL_POW2=${OUTER_UNROLL_POW2} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xsdaz -Xsrounding=faithful -Xsparallel=2 ${SEED} -Xstarget=${FPGA_DEVICE} -DOUTER_UNROLL=${OUTER_UNROLL} -DINNER_UNROLL=${INNER_UNROLL} -DOUTER_UNROLL_POW2=${OUTER_UNROLL_POW2} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation @@ -71,6 +74,15 @@ set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_CO set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS}") add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET}) +############################################################################### +### FPGA Simulator +############################################################################### +add_executable(${SIMULATOR_TARGET} ${SOURCE_FILE}) +target_include_directories(${SIMULATOR_TARGET} PRIVATE ../../../include) +set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${SIMULATOR_COMPILE_FLAGS}") +set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${SIMULATOR_LINK_FLAGS}") +add_custom_target(fpga_sim DEPENDS ${SIMULATOR_TARGET}) + ############################################################################### ### Generate Report ############################################################################### diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/main.cpp b/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/main.cpp index 099bf45125..39a3cb3fe2 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/main.cpp +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/main.cpp @@ -732,20 +732,22 @@ int main(int argc, char *argv[]) { } try { -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector device_selector; -#else - ext::intel::fpga_selector device_selector; -#endif - queue q(device_selector, fpga_tools::exception_handler); +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; +#endif - std::cout << "Running on device: " - << q.get_device().get_info().c_str() << "\n"; + queue q(selector, fpga_tools::exception_handler); device device = q.get_device(); - std::cout << "Device name: " - << device.get_info().c_str() << "\n \n \n"; + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; vector inp; @@ -788,9 +790,9 @@ int main(int argc, char *argv[]) { ReadInputFromFile(inputFile, inp); // Get the number of data from the input file -// Emulator mode only goes through one input (or through OUTER_UNROLL inputs) to +// Emulator and simulator modes only goes through one input (or through OUTER_UNROLL inputs) to // ensure fast runtime -#if defined(FPGA_EMULATOR) +#if defined(FPGA_EMULATOR) || defined(FPGA_SIMULATOR) int temp_crrs = 1; #else int temp_crrs = inp.size(); @@ -860,6 +862,8 @@ int main(int argc, char *argv[]) { "set up correctly\n"; std::cerr << " If you are targeting the FPGA emulator, compile with " "-DFPGA_EMULATOR\n"; + std::cerr << " If you are targeting the FPGA simulator, compile with " + "-DFPGA_SIMULATOR\n"; return 1; } return 0; diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/CMakeLists.txt index 86367c441b..7b644ff8a0 100755 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/CMakeLists.txt @@ -125,9 +125,9 @@ set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DQUERY=${QUERY set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga -DQUERY=${QUERY} ${SF_SMALL_ARG} ${AC_TYPES_FLAG}") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DQUERY=${QUERY} ${SF_SMALL_ARG} ${AC_TYPES_FLAG} -Xssimulation -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} -DQUERY=${QUERY} ${SF_SMALL_ARG} ${USER_HARDWARE_FLAGS} ${AC_TYPES_FLAG}") -set(REPORT_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DQUERY=${QUERY} ${SF_SMALL_ARG} ${AC_TYPES_FLAG}") +set(REPORT_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DQUERY=${QUERY} ${SF_SMALL_ARG} ${AC_TYPES_FLAG} -DFPGA_HARDWARE") set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xsparallel=2 -Xsseed=2 -Xstarget=${FPGA_DEVICE} -DQUERY=${QUERY} ${SF_SMALL_ARG} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DQUERY=${QUERY} ${SF_SMALL_ARG} ${AC_TYPES_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DQUERY=${QUERY} ${SF_SMALL_ARG} ${AC_TYPES_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xsparallel=2 ${SEED} -Xstarget=${FPGA_DEVICE} -DQUERY=${QUERY} ${SF_SMALL_ARG} ${USER_HARDWARE_FLAGS} ${AC_TYPES_FLAG}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/db.cpp b/DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/db.cpp index 8f5c9289d8..0b8849e5e8 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/db.cpp +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/db.cpp @@ -189,19 +189,23 @@ int main(int argc, char* argv[]) { // queue properties to enable profiling auto props = property_list{property::queue::enable_profiling()}; -#if defined(FPGA_EMULATOR) - // the device selector - ext::intel::fpga_emulator_selector selector; -#elif defined(FPGA_SIMULATOR) - // the device simulator - ext::intel::fpga_simulator_selector selector; -#else - ext::intel::fpga_selector selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif // create the device queue queue q(selector, fpga_tools::exception_handler, props); + device device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + // parse the database files located in the 'db_root_dir' directory bool success = dbinfo.Parse(db_root_dir); if (!success) { diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/CMakeLists.txt index 5d79b8ac07..51f7f13fd0 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/CMakeLists.txt @@ -94,11 +94,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} -fsycl -fintelfpga ${AC_TYPES_FLAG} ${LITERALS_PER_CYCLE_FLAG} ${DECOMPRESS_FORMAT_FLAG} -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${LITERALS_PER_CYCLE_FLAG} ${DECOMPRESS_FORMAT_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG}") -set(SIMULATOR_COMPILE_FLAGS "-Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} -fsycl -fintelfpga ${AC_TYPES_FLAG} ${LITERALS_PER_CYCLE_FLAG} ${DECOMPRESS_FORMAT_FLAG} -DFPGA_SIMULATOR") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${LITERALS_PER_CYCLE_FLAG} ${DECOMPRESS_FORMAT_FLAG} -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} -fsycl -fintelfpga ${AC_TYPES_FLAG} ${LITERALS_PER_CYCLE_FLAG} ${DECOMPRESS_FORMAT_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${LITERALS_PER_CYCLE_FLAG} ${DECOMPRESS_FORMAT_FLAG} -DFPGA_HARDWARE") set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -Xshardware ${PROFILE_FLAG} ${FLAT_COMPILE_FLAG} -Xsparallel=2 ${SEED_FLAG} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") set(HARDWARE_LINK_FLAGS "${REPORT_LINK_FLAGS} ${AC_TYPES_FLAG}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/main.cpp b/DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/main.cpp index 35132404d2..f4dca99219 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/main.cpp +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/main.cpp @@ -124,18 +124,23 @@ int main(int argc, char* argv[]) { std::cout << "Using " << decompressor_name << " decompression\n"; std::cout << std::endl; - // the device selector -#if defined(FPGA_EMULATOR) - sycl::ext::intel::fpga_emulator_selector selector; -#elif defined(FPGA_SIMULATOR) - sycl::ext::intel::fpga_simulator_selector selector; -#else - sycl::ext::intel::fpga_selector selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif // create the device queue queue q(selector, fpga_tools::exception_handler); + device device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + // create the decompressor based on which decompression version we are using #if defined(GZIP) GzipDecompressorT decompressor; diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/src/CMakeLists.txt index 95b610cb5e..d8ff2e0637 100755 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/src/CMakeLists.txt @@ -100,11 +100,11 @@ message(STATUS "NUM_REORDER=${NUM_REORDER}") # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DNUM_ENGINES=${NUM_ENGINES} -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DNUM_ENGINES=${NUM_ENGINES} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga -DNUM_ENGINES=${NUM_ENGINES}") -set(SIMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -Xssimulation -DNUM_ENGINES=${NUM_ENGINES} -DFPGA_SIMULATOR") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DNUM_ENGINES=${NUM_ENGINES} -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} -DNUM_ENGINES=${NUM_ENGINES} ${USER_SIMULATOR_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DNUM_ENGINES=${NUM_ENGINES}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DNUM_ENGINES=${NUM_ENGINES} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xsparallel=2 -Xsopt-arg=\"-nocaching\" -Xstarget=${FPGA_DEVICE} -DNUM_ENGINES=${NUM_ENGINES} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/src/gzip.cpp b/DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/src/gzip.cpp index 183e6732e1..fe4e825334 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/src/gzip.cpp +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/src/gzip.cpp @@ -120,18 +120,23 @@ int main(int argc, char *argv[]) { } try { -#ifdef FPGA_EMULATOR - ext::intel::fpga_emulator_selector device_selector; -#elif FPGA_SIMULATOR - ext::intel::fpga_simulator_selector device_selector; -#else - ext::intel::fpga_selector device_selector; + +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif + auto prop_list = property_list{property::queue::enable_profiling()}; - queue q(device_selector, fpga_tools::exception_handler, prop_list); + queue q(selector, fpga_tools::exception_handler, prop_list); + + auto device = q.get_device(); - std::cout << "Running on device: " - << q.get_device().get_info().c_str() << "\n"; + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; if (infilename == "") { std::cout << "Must specify a filename to compress\n\n"; diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/src/gzip_ll.cpp b/DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/src/gzip_ll.cpp index fac52dcd3d..b73a13d2e7 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/src/gzip_ll.cpp +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/src/gzip_ll.cpp @@ -125,18 +125,23 @@ int main(int argc, char *argv[]) { } try { -#ifdef FPGA_EMULATOR - ext::intel::fpga_emulator_selector device_selector; -#elif FPGA_SIMULATOR - ext::intel::fpga_simulator_selector device_selector; -#else - ext::intel::fpga_selector device_selector; + +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif + auto prop_list = property_list{property::queue::enable_profiling()}; - queue q(device_selector, fpga_tools::exception_handler, prop_list); + queue q(selector, fpga_tools::exception_handler, prop_list); + + auto device = q.get_device(); - std::cout << "Running on device: " - << q.get_device().get_info().c_str() << "\n"; + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; if (infilename == "") { std::cout << "Must specify a filename to compress\n\n"; diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/src/CMakeLists.txt index 6a958d4c9c..1c77de9388 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/src/CMakeLists.txt @@ -70,7 +70,7 @@ set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${ENABLE_USM} $ set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG}") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG}") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware ${PROFILE_FLAG} -Xsparallel=2 ${SEED_FLAG} -Xstarget=${FPGA_DEVICE} ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/src/main.cpp b/DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/src/main.cpp index 773cfbc0db..1f09fe81c8 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/src/main.cpp +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/src/main.cpp @@ -125,33 +125,37 @@ int main(int argc, char *argv[]) { ///////////////////////////////////////////////////////////// // the device selector -#ifdef FPGA_EMULATOR - ext::intel::fpga_emulator_selector selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector selector; -#else - ext::intel::fpga_selector selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif // create the device queue queue q(selector, fpga_tools::exception_handler); // make sure the device supports USM device allocations - auto d = q.get_device(); - if (!q.get_device().has(aspect::usm_device_allocations)) { + auto device = q.get_device(); + if (!device.has(aspect::usm_device_allocations)) { std::cerr << "ERROR: The selected device does not support USM device" << " allocations\n"; std::terminate(); } // make sure the device support USM host allocations if we chose to use them - if (!q.get_device().has(aspect::usm_host_allocations) && + if (!device.has(aspect::usm_host_allocations) && kUseUSMHostAllocation) { std::cerr << "ERROR: The selected device does not support USM host" << " allocations\n"; std::terminate(); } + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + // the input, output, and reference data std::vector in_vec(count), out_vec(count), ref(count); diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/src/CMakeLists.txt index 0bec59a4ba..1133553196 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/src/CMakeLists.txt @@ -90,7 +90,7 @@ set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -fbracket-depth set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} ${ENABLE_USM}") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -fbracket-depth=512 ${AC_TYPES_FLAG} ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${STREAMING_PIPE_WIDTH_FLAG} -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Wall -fbracket-depth=512 ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${REAL_IO_PIPES_FLAG} ${STREAMING_PIPE_WIDTH_FLAG} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} ${UDP_LINK_FLAGS} ${AC_TYPES_FLAG} -Xssimulation -Xsghdl") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga ${WIN_FLAG} -fbracket-depth=512 ${AC_TYPES_FLAG} ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${REAL_IO_PIPES_FLAG} ${STREAMING_PIPE_WIDTH_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga ${WIN_FLAG} -fbracket-depth=512 ${AC_TYPES_FLAG} ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${REAL_IO_PIPES_FLAG} ${STREAMING_PIPE_WIDTH_FLAG} -FPGA_HARDWARE") set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -Wall -Xshardware -fbracket-depth=512 ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${REAL_IO_PIPES_FLAG} ${STREAMING_PIPE_WIDTH_FLAG} ${PROFILE_FLAG} -Xsparallel=2 -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} ${UDP_LINK_FLAGS}") set(HARDWARE_LINK_FLAGS "${REPORT_LINK_FLAGS} ${AC_TYPES_FLAG}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/src/mvdr_beamforming.cpp b/DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/src/mvdr_beamforming.cpp index 7266389bff..8ac7e1da6c 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/src/mvdr_beamforming.cpp +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/src/mvdr_beamforming.cpp @@ -224,12 +224,12 @@ int main(int argc, char *argv[]) { try { // device selector -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector selector; -#else - ext::intel::fpga_selector selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif // create the device queue @@ -239,6 +239,12 @@ int main(int argc, char *argv[]) { queue q(selector, fpga_tools::exception_handler); #endif + device device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + // initialize the producers and consumers #if not defined(REAL_IO_PIPES) DataProducer::Init(q, kInputDataSize * num_matrix_copies); diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/qrd/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/ReferenceDesigns/qrd/src/CMakeLists.txt index 4c9271565a..31c3710bd4 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/qrd/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/qrd/src/CMakeLists.txt @@ -93,11 +93,11 @@ message(STATUS "SEED=${SEED}") # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} ${AC_TYPES_COMPILE_FLAG} -Wformat-security -Werror=format-security -fbracket-depth=512 -fsycl -fintelfpga -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DROWS_COMPONENT=${ROWS_COMPONENT} -DCOLS_COMPONENT=${COLS_COMPONENT} -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} ${AC_TYPES_COMPILE_FLAG} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DROWS_COMPONENT=${ROWS_COMPONENT} -DCOLS_COMPONENT=${COLS_COMPONENT} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} ${STACK_FLAG} ${AC_TYPES_LINK_FLAG}") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} ${AC_TYPES_COMPILE_FLAG} -DFPGA_SIMULATOR -fbracket-depth=512 -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DROWS_COMPONENT=${ROWS_COMPONENT} -DCOLS_COMPONENT=${COLS_COMPONENT} ${USER_HARDWARE_FLAGS}") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} ${STACK_FLAG} -Xssimulation -Xsghdl -Xsclock=${CLOCK_TARGET} -Xstarget=${FPGA_DEVICE} ${USER_SIMULATOR_FLAGS} ${AC_TYPES_LINK_FLAG}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} ${AC_TYPES_COMPILE_FLAG} -Wformat-security -Werror=format-security -fsycl -fintelfpga -fbracket-depth=512 -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DROWS_COMPONENT=${ROWS_COMPONENT} -DCOLS_COMPONENT=${COLS_COMPONENT}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} ${AC_TYPES_COMPILE_FLAG} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DROWS_COMPONENT=${ROWS_COMPONENT} -DCOLS_COMPONENT=${COLS_COMPONENT} -DFPGA_HARDWARE") set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -Xshardware ${PLATFORM_SPECIFIC_LINK_FLAGS} -Xsclock=${CLOCK_TARGET} -Xsparallel=2 ${SEED} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} ${AC_TYPES_LINK_FLAG}") set(HARDWARE_LINK_FLAGS "${REPORT_LINK_FLAGS} ${STACK_FLAG}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/qrd/src/qrd_demo.cpp b/DirectProgramming/DPC++FPGA/ReferenceDesigns/qrd/src/qrd_demo.cpp index 57487846a4..e34447d1b1 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/qrd/src/qrd_demo.cpp +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/qrd/src/qrd_demo.cpp @@ -112,24 +112,25 @@ int main(int argc, char *argv[]) { #endif try { - // SYCL boilerplate -#if defined(FPGA_EMULATOR) - sycl::ext::intel::fpga_emulator_selector device_selector; -#elif defined(FPGA_SIMULATOR) - sycl::ext::intel::fpga_simulator_selector device_selector; -#else - sycl::ext::intel::fpga_selector device_selector; + +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif // Enable the queue profiling to time the execution sycl::property_list queue_properties{sycl::property::queue::enable_profiling()}; - sycl::queue q = sycl::queue(device_selector, + sycl::queue q = sycl::queue(selector, fpga_tools::exception_handler, queue_properties); sycl::device device = q.get_device(); - std::cout << "Device name: " + + std::cout << "Running on device: " << device.get_info().c_str() << std::endl; diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/qri/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/ReferenceDesigns/qri/src/CMakeLists.txt index 601b0921a2..3c73b2eedc 100755 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/qri/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/qri/src/CMakeLists.txt @@ -94,11 +94,11 @@ message(STATUS "SEED=${SEED}") # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fbracket-depth=512 -fsycl -fintelfpga -DFIXED_ITERATIONS_QRD=${FIXED_ITERATIONS_QRD} -DFIXED_ITERATIONS_QRI=${FIXED_ITERATIONS_QRI} -DCOMPLEX=${COMPLEX} -DROWS_COMPONENT=${ROWS_COMPONENT} -DCOLS_COMPONENT=${COLS_COMPONENT} -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS_QRD=${FIXED_ITERATIONS_QRD} -DFIXED_ITERATIONS_QRI=${FIXED_ITERATIONS_QRI} -DCOMPLEX=${COMPLEX} -DROWS_COMPONENT=${ROWS_COMPONENT} -DCOLS_COMPONENT=${COLS_COMPONENT} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS}") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -DFPGA_SIMULATOR -fbracket-depth=512 -DFIXED_ITERATIONS_QRD=${FIXED_ITERATIONS_QRD} -DFIXED_ITERATIONS_QRI=${FIXED_ITERATIONS_QRI} -DCOMPLEX=${COMPLEX} -DROWS_COMPONENT=${ROWS_COMPONENT} -DCOLS_COMPONENT=${COLS_COMPONENT} -Xsfp-relaxed ${USER_HARDWARE_FLAGS}") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} -Xssimulation -Xsghdl -Xsclock=${CLOCK_TARGET} -Xstarget=${FPGA_DEVICE} ${USER_SIMULATOR_FLAGS} -Xsfp-relaxed") -set(HARDWARE_COMPILE_FLAGS "${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fsycl -fintelfpga -fbracket-depth=512 -DFIXED_ITERATIONS_QRD=${FIXED_ITERATIONS_QRD} -DFIXED_ITERATIONS_QRI=${FIXED_ITERATIONS_QRI} -DCOMPLEX=${COMPLEX} -DROWS_COMPONENT=${ROWS_COMPONENT} -DCOLS_COMPONENT=${COLS_COMPONENT} -Xsfp-relaxed") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS_QRD=${FIXED_ITERATIONS_QRD} -DFIXED_ITERATIONS_QRI=${FIXED_ITERATIONS_QRI} -DCOMPLEX=${COMPLEX} -DROWS_COMPONENT=${ROWS_COMPONENT} -DCOLS_COMPONENT=${COLS_COMPONENT} -Xsfp-relaxed -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} -Xshardware -Xsclock=${CLOCK_TARGET} -Xsparallel=2 ${SEED} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} -Xsfp-relaxed") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/qri/src/qri_demo.cpp b/DirectProgramming/DPC++FPGA/ReferenceDesigns/qri/src/qri_demo.cpp index 5b1e25b979..b343b70aac 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/qri/src/qri_demo.cpp +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/qri/src/qri_demo.cpp @@ -212,24 +212,26 @@ int main(int argc, char *argv[]) { } try { - // SYCL boilerplate -#if defined(FPGA_EMULATOR) - sycl::ext::intel::fpga_emulator_selector device_selector; -#elif defined(FPGA_SIMULATOR) - sycl::ext::intel::fpga_simulator_selector device_selector; -#else - sycl::ext::intel::fpga_selector device_selector; + +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif + // Enable the queue profiling to time the execution sycl::property_list queue_properties{sycl::property::queue::enable_profiling()}; - sycl::queue q = sycl::queue(device_selector, + sycl::queue q = sycl::queue(selector, fpga_tools::exception_handler, queue_properties); sycl::device device = q.get_device(); - std::cout << "Device name: " + + std::cout << "Running on device: " << device.get_info().c_str() << std::endl; From a6c10a7757e667cfd3dd6e5c65968005951db3c7 Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Wed, 14 Dec 2022 00:44:54 -0800 Subject: [PATCH 20/38] updating selectors in Design patterns Signed-off-by: Yohann Uguen --- .../ReferenceDesigns/qri/src/qri_demo.cpp | 1 - .../DesignPatterns/autorun/src/CMakeLists.txt | 2 +- .../DesignPatterns/autorun/src/autorun.cpp | 24 +++++++----- .../src/CMakeLists.txt | 4 +- .../src/buffered_host_streaming.cpp | 22 ++++++----- .../compute_units/src/CMakeLists.txt | 2 +- .../compute_units/src/compute_units.cpp | 20 ++++++---- .../double_buffering/src/CMakeLists.txt | 6 +-- .../double_buffering/src/double_buffering.cpp | 38 ++++++++++--------- .../explicit_data_movement/src/CMakeLists.txt | 2 +- .../src/explicit_data_movement.cpp | 23 ++++++----- .../io_streaming/src/CMakeLists.txt | 2 +- .../io_streaming/src/io_streaming.cpp | 18 ++++++--- .../src/CMakeLists.txt | 6 +-- .../src/loop_carried_dependency.cpp | 27 ++++++++----- .../n_way_buffering/src/CMakeLists.txt | 12 +++--- .../n_way_buffering/src/n_way_buffering.cpp | 34 ++++++++--------- .../onchip_memory_cache/src/CMakeLists.txt | 8 ++-- .../src/onchip_memory_cache.cpp | 36 +++++++++--------- .../optimize_inner_loop/src/CMakeLists.txt | 2 +- .../src/optimize_inner_loop.cpp | 18 ++++++--- .../pipe_array/src/CMakeLists.txt | 6 +-- .../pipe_array/src/pipe_array.cpp | 20 ++++++---- .../shannonization/src/CMakeLists.txt | 2 +- .../shannonization/src/shannonization.cpp | 18 ++++++--- .../simple_host_streaming/src/CMakeLists.txt | 6 +-- .../src/simple_host_streaming.cpp | 20 ++++++---- .../triangular_loop/src/CMakeLists.txt | 6 +-- .../triangular_loop/src/triangular_loop.cpp | 23 +++++------ .../src/CMakeLists.txt | 6 +-- .../src/zero_copy_data_transfer.cpp | 20 ++++++---- 31 files changed, 244 insertions(+), 190 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/qri/src/qri_demo.cpp b/DirectProgramming/DPC++FPGA/ReferenceDesigns/qri/src/qri_demo.cpp index b343b70aac..bea198e997 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/qri/src/qri_demo.cpp +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/qri/src/qri_demo.cpp @@ -221,7 +221,6 @@ int main(int argc, char *argv[]) { auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif - // Enable the queue profiling to time the execution sycl::property_list queue_properties{sycl::property::queue::enable_profiling()}; diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/autorun/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/autorun/src/CMakeLists.txt index aff8c213d7..dbfb02daef 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/autorun/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/autorun/src/CMakeLists.txt @@ -27,7 +27,7 @@ set(EMULATOR_COMPILE_FLAGS "-fsycl -Wall ${WIN_FLAG} -fintelfpga -DFPGA_EMULATOR set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") set(SIMULATOR_COMPILE_FLAGS "-fsycl -Wall ${WIN_FLAG} -fintelfpga -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -Wall ${WIN_FLAG} -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -Wall ${WIN_FLAG} -fintelfpga -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/autorun/src/autorun.cpp b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/autorun/src/autorun.cpp index 324d67a2e7..82843deb02 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/autorun/src/autorun.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/autorun/src/autorun.cpp @@ -13,12 +13,12 @@ using namespace sycl; // choose the device selector based on emulation or actual hardware // we make this a global variable so it can be used by the autorun kernels -#if defined(FPGA_EMULATOR) -ext::intel::fpga_emulator_selector ds; -#elif defined(FPGA_SIMULATOR) -ext::intel::fpga_simulator_selector ds; -#else -ext::intel::fpga_selector ds; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif // declare the kernel names globally to reduce name mangling @@ -55,7 +55,7 @@ struct MyAutorun { // declaring a global instance of this class causes the constructor to be called // before main() starts, and the constructor launches the kernel. -fpga_tools::Autorun ar_kernel{ds, MyAutorun{}}; +fpga_tools::Autorun ar_kernel{selector, MyAutorun{}}; //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// @@ -73,7 +73,7 @@ struct MyAutorunForever { // declaring a global instance of this class causes the constructor to be called // before main() starts, and the constructor launches the kernel. fpga_tools::AutorunForever ar_forever_kernel{ - ds, MyAutorunForever{}}; + selector, MyAutorunForever{}}; //////////////////////////////////////////////////////////////////////////////// // @@ -120,7 +120,13 @@ int main() { try { // create the queue - queue q(ds, fpga_tools::exception_handler); + queue q(selector, fpga_tools::exception_handler); + + sycl::device device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; // stream data through the Autorun kernel std::cout << "Running the Autorun kernel test\n"; diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/CMakeLists.txt index c6eca9599d..59a073f4c4 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/CMakeLists.txt @@ -36,11 +36,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${THREAD_FLAG}") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} ${THREAD_FLAG}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga ${THREAD_FLAG} -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/buffered_host_streaming.cpp b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/buffered_host_streaming.cpp index a5c9d6474e..14601fb769 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/buffered_host_streaming.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/buffered_host_streaming.cpp @@ -127,14 +127,12 @@ int main(int argc, char* argv[]) { bool passed = true; try { -#if defined(FPGA_EMULATOR) - // the device selector - ext::intel::fpga_emulator_selector selector; -#elif defined(FPGA_SIMULATOR) - // the device simulator - ext::intel::fpga_simulator_selector selector; -#else - ext::intel::fpga_selector selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif // queue properties to enable profiling @@ -144,13 +142,17 @@ int main(int argc, char* argv[]) { queue q(selector, fpga_tools::exception_handler, prop_list); // make sure the device supports USM host allocations - device d = q.get_device(); - if (!d.get_info()) { + auto device = q.get_device(); + if (!device.get_info()) { std::cerr << "ERROR: The selected device does not support USM host" << " allocations\n"; std::terminate(); } + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + /////////////////////////////////////////////////////////////////////////// // find the bandwidth of each processing component in our design std::cout << "Running the roofline analysis\n"; diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/src/CMakeLists.txt index acbec04fdb..92c30e5b18 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/src/CMakeLists.txt @@ -27,7 +27,7 @@ set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall -Xssimulation -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/src/compute_units.cpp b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/src/compute_units.cpp index 1137b4e200..5e75922f30 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/src/compute_units.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/src/compute_units.cpp @@ -43,14 +43,12 @@ void SinkKernel(queue &q, float &out_data) { int main() { -#if defined(FPGA_EMULATOR) - // the device selector - ext::intel::fpga_emulator_selector selector; -#elif defined(FPGA_SIMULATOR) - // the device simulator - ext::intel::fpga_simulator_selector selector; -#else - ext::intel::fpga_selector selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif float out_data = 0; @@ -58,6 +56,12 @@ int main() { try { queue q(selector, fpga_tools::exception_handler); + sycl::device device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + // Enqueue the Source kernel SourceKernel(q, kTestData); diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/double_buffering/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/double_buffering/src/CMakeLists.txt index ae12f0a3d3..d60ea53ba0 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/double_buffering/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/double_buffering/src/CMakeLists.txt @@ -23,11 +23,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR ${MATH_FLAGS}") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR ${MATH_FLAGS}") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR ${MATH_FLAGS}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR ${MATH_FLAGS}") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga ${MATH_FLAGS}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${MATH_FLAGS} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA simulator and backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/double_buffering/src/double_buffering.cpp b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/double_buffering/src/double_buffering.cpp index 10ee9d1230..157858162f 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/double_buffering/src/double_buffering.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/double_buffering/src/double_buffering.cpp @@ -203,34 +203,36 @@ void ProcessInput(buffer &buf) { } int main() { -// Create queue, get platform and device -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector device_selector; - std::cout << "\nEmulator output does not demonstrate true hardware " - "performance. The design may need to run on actual hardware " - "to observe the performance benefit of the optimization " - "exemplified in this tutorial.\n\n"; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector device_selector; - std::cout << "\nSimulator output does not demonstrate true hardware " - "performance. The design may need to run on actual hardware " - "to observe the performance benefit of the optimization " - "exemplified in this tutorial.\n\n"; -#else - ext::intel::fpga_selector device_selector; + +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; +#endif + +#ifndef FPGA_HARDWARE + std::cout << "\nEmulator and simualtor outputs do not demonstrate " + "true hardware performance. The design may need to run " + "on actual hardware to observe the performance benefit " + "of the optimization exemplified in this tutorial.\n\n"; #endif try { auto prop_list = property_list{property::queue::enable_profiling()}; - sycl::queue q(device_selector, fpga_tools::exception_handler, prop_list); + sycl::queue q(selector, fpga_tools::exception_handler, prop_list); platform platform = q.get_context().get_platform(); device device = q.get_device(); + std::cout << "Platform name: " << platform.get_info().c_str() << "\n"; - std::cout << "Device name: " - << device.get_info().c_str() << "\n\n\n"; + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; std::cout << "Executing kernel " << kTimes << " times in each round.\n\n"; diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/CMakeLists.txt index adc66d8de3..ba99098740 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/CMakeLists.txt @@ -27,7 +27,7 @@ set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/explicit_data_movement.cpp b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/explicit_data_movement.cpp index 7f63936263..18c2dafbe2 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/explicit_data_movement.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/explicit_data_movement.cpp @@ -162,14 +162,13 @@ int main(int argc, char *argv[]) { } try { -#if defined(FPGA_EMULATOR) - // the device selector - ext::intel::fpga_emulator_selector selector; -#elif defined(FPGA_SIMULATOR) - // the device simulator - ext::intel::fpga_simulator_selector selector; -#else - ext::intel::fpga_selector selector; + +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif // queue properties to enable profiling @@ -179,13 +178,17 @@ int main(int argc, char *argv[]) { queue q(selector, fpga_tools::exception_handler, prop_list); // make sure the device supports USM device allocations - device d = q.get_device(); - if (!d.get_info()) { + auto device = q.get_device(); + if (!device.get_info()) { std::cerr << "ERROR: The selected device does not support USM device" << " allocations\n"; return 1; } + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + // input and output data std::vector in(size); std::vector out_gold(size), out_implicit(size), out_explicit(size); diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/io_streaming/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/io_streaming/src/CMakeLists.txt index 6b8610239c..026c8fdc7f 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/io_streaming/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/io_streaming/src/CMakeLists.txt @@ -33,7 +33,7 @@ set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR ${USM_HOST_ALLOCATIONS}") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${USM_HOST_ALLOCATIONS}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${USM_HOST_ALLOCATIONS} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/io_streaming/src/io_streaming.cpp b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/io_streaming/src/io_streaming.cpp index c97a6f4b89..c57207dd0c 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/io_streaming/src/io_streaming.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/io_streaming/src/io_streaming.cpp @@ -40,12 +40,12 @@ int main() { try { // device selector -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector selector; -#else - ext::intel::fpga_selector selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif // queue properties to enable SYCL profiling of kernels @@ -54,6 +54,12 @@ int main() { // create the device queue queue q(selector, fpga_tools::exception_handler, prop_list); + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + // run the loopback example system // see 'LoopbackTest.hpp' std::cout << "Running loopback test\n"; diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/loop_carried_dependency/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/loop_carried_dependency/src/CMakeLists.txt index 49db05f730..91f811ad2f 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/loop_carried_dependency/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/loop_carried_dependency/src/CMakeLists.txt @@ -23,11 +23,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-Wall -fsycl -fintelfpga ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/loop_carried_dependency/src/loop_carried_dependency.cpp b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/loop_carried_dependency/src/loop_carried_dependency.cpp index bae49a1fe6..fb2844cf5e 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/loop_carried_dependency/src/loop_carried_dependency.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/loop_carried_dependency/src/loop_carried_dependency.cpp @@ -128,16 +128,19 @@ int main(int argc, char *argv[]) { // Initialize queue with device selector and enabling profiling // Create queue, get platform and device -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector selector; - cout << "\nEmulator output does not demonstrate true hardware " - "performance. The design may need to run on actual hardware " - "to observe the performance benefit of the optimization " +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; +#endif + +#ifndef FPGA_HARDWARE + cout << "\nEmulator and simulator outputs do not demonstrate true " + "hardware performance. The design may need to run on actual " + "hardware to observe the performance benefit of the optimization " "exemplified in this tutorial.\n\n"; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector selector; -#else - ext::intel::fpga_selector selector; #endif double unopt_sum = -1, opt_sum = -1; @@ -147,6 +150,12 @@ int main(int argc, char *argv[]) { queue q(selector, fpga_tools::exception_handler, property::queue::enable_profiling{}); + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + // compute result on device PrintTime(Unoptimized(q, vec_a, vec_b, unopt_sum, n), q, "Unoptimized"); PrintTime(Optimized(q, vec_a, vec_b, opt_sum, n), q, "Optimized"); diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/n_way_buffering/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/n_way_buffering/src/CMakeLists.txt index 12544d0faa..643a391c53 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/n_way_buffering/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/n_way_buffering/src/CMakeLists.txt @@ -29,12 +29,12 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") -set(EMULATOR_LINK_FLAGS "${THREAD_LIB} -fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR") -set(SIMULATOR_LINK_FLAGS "${THREAD_LIB} -fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga") -set(HARDWARE_LINK_FLAGS "${THREAD_LIB} -fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") +set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${THREAD_LIB}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${THREAD_LIB} -Xssimulation -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") +set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga ${THREAD_LIB} -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA simulator and backend compilation ############################################################################### diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/n_way_buffering/src/n_way_buffering.cpp b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/n_way_buffering/src/n_way_buffering.cpp index 891e901935..f6feb80b0b 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/n_way_buffering/src/n_way_buffering.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/n_way_buffering/src/n_way_buffering.cpp @@ -214,33 +214,33 @@ void ProcessInput(buffer &buf, std::vector ©) { int main() { // Create queue, get platform and device -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector device_selector; - std::cout << "\nEmulator output does not demonstrate true hardware " - "performance. The design may need to run on actual hardware " - "to observe the performance benefit of the optimization " - "exemplified in this tutorial.\n\n"; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector device_selector; - std::cout << "\nSimulator output does not demonstrate true hardware " - "performance. The design may need to run on actual hardware " - "to observe the performance benefit of the optimization " - "exemplified in this tutorial.\n\n"; -#else - ext::intel::fpga_selector device_selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; +#endif + +#ifndef FPGA_HARDWARE + std::cout << "\nEmulator and simualtor outputs do not demonstrate " + "true hardware performance. The design may need to run " + "on actual hardware to observe the performance benefit " + "of the optimization exemplified in this tutorial.\n\n"; #endif try { auto prop_list = property_list{property::queue::enable_profiling()}; - sycl::queue q(device_selector, fpga_tools::exception_handler, prop_list); + sycl::queue q(selector, fpga_tools::exception_handler, prop_list); platform platform = q.get_context().get_platform(); device device = q.get_device(); std::cout << "Platform name: " << platform.get_info().c_str() << "\n"; - std::cout << "Device name: " - << device.get_info().c_str() << "\n\n\n"; + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; std::cout << "Executing kernel " << kTimes << " times in each round.\n\n"; diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/onchip_memory_cache/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/onchip_memory_cache/src/CMakeLists.txt index 1387a68cd6..f9c8cadd60 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/onchip_memory_cache/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/onchip_memory_cache/src/CMakeLists.txt @@ -38,12 +38,12 @@ set(CACHE_DEPTH_FLAG "-DMAX_CACHE_DEPTH=${MAX_CACHE_DEPTH} -DMIN_CACHE_DEPTH=${M # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} ${CACHE_DEPTH_FLAG} ${AC_TYPES_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") -set(EMULATOR_LINK_FLAGS "${AC_TYPES_FLAG} -fsycl -fintelfpga") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${CACHE_DEPTH_FLAG} ${AC_TYPES_FLAG} -DFPGA_EMULATOR") +set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG}") set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${CACHE_DEPTH_FLAG} ${USER_HARDWARE_FLAGS}") -set(SIMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} ${CACHE_DEPTH_FLAG} ${AC_TYPES_FLAG} -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${CACHE_DEPTH_FLAG} ${AC_TYPES_FLAG} -Xssimulation -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} ${CACHE_DEPTH_FLAG} ${USER_HARDWARE_FLAGS} ${AC_TYPES_FLAG}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} ${CACHE_DEPTH_FLAG} ${AC_TYPES_FLAG} -fsycl -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${CACHE_DEPTH_FLAG} ${AC_TYPES_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${CACHE_DEPTH_FLAG} ${USER_HARDWARE_FLAGS} ${AC_TYPES_FLAG}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/onchip_memory_cache/src/onchip_memory_cache.cpp b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/onchip_memory_cache/src/onchip_memory_cache.cpp index 5340993786..62fe06bc70 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/onchip_memory_cache/src/onchip_memory_cache.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/onchip_memory_cache/src/onchip_memory_cache.cpp @@ -73,35 +73,35 @@ int main() { double time_kernel; // Create queue, get platform and device -#if defined(FPGA_EMULATOR) - sycl::ext::intel::fpga_emulator_selector device_selector; - std::cout << "\nEmulator output does not demonstrate true hardware " - "performance. The design may need to run on actual hardware " - "to observe the performance benefit of the optimization " - "exemplified in this tutorial.\n\n"; -#elif defined(FPGA_SIMULATOR) - sycl::ext::intel::fpga_simulator_selector device_selector; - std::cout << "\nSimulator output does not demonstrate true hardware " - "performance. The design may need to run on actual hardware " - "to observe the performance benefit of the optimization " - "exemplified in this tutorial.\n\n"; -#else - sycl::ext::intel::fpga_selector device_selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; +#endif + +#ifndef FPGA_HARDWARE + std::cout << "\nEmulator and simualtor outputs do not demonstrate " + "true hardware performance. The design may need to run " + "on actual hardware to observe the performance benefit " + "of the optimization exemplified in this tutorial.\n\n"; #endif + try { auto prop_list = sycl::property_list{sycl::property::queue::enable_profiling()}; - sycl::queue q(device_selector, fpga_tools::exception_handler, prop_list); + sycl::queue q(selector, fpga_tools::exception_handler, prop_list); sycl::platform platform = q.get_context().get_platform(); sycl::device device = q.get_device(); std::cout << "Platform name: " << platform.get_info().c_str() << "\n"; - std::cout << "Device name: " - << device.get_info().c_str() - << "\n\n\n"; + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; std::cout << "\nNumber of inputs: " << kInitNumInputs << "\n"; std::cout << "Number of outputs: " << kNumOutputs << "\n\n"; diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/optimize_inner_loop/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/optimize_inner_loop/src/CMakeLists.txt index e222fb28d1..b9eb2182c0 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/optimize_inner_loop/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/optimize_inner_loop/src/CMakeLists.txt @@ -28,7 +28,7 @@ set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") set(SIMULATOR_COMPILE_FLAGS "-fsycl -Wall -fintelfpga ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR ${USER_SIMULATOR_FLAGS}") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} ${USER_SIMULATOR_FLAGS}") # use cmake -D USER_SIMULATOR_FLAGS= to set extra flags for FPGA simulator compilation -set(HARDWARE_COMPILE_FLAGS "-fsycl -Wall -fintelfpga ${WIN_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -Wall -fintelfpga ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/optimize_inner_loop/src/optimize_inner_loop.cpp b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/optimize_inner_loop/src/optimize_inner_loop.cpp index e27a8f3495..470f2b9d4e 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/optimize_inner_loop/src/optimize_inner_loop.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/optimize_inner_loop/src/optimize_inner_loop.cpp @@ -60,12 +60,12 @@ void SubmitKernels(std::vector &in, int &res, double &kernel_time_ms) { static_assert(spec_iters >= 0, "spec_iters must be positive"); // the device selector -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector selector; -#else - ext::intel::fpga_selector selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif // the pipe @@ -79,6 +79,12 @@ void SubmitKernels(std::vector &in, int &res, double &kernel_time_ms) { auto prop_list = property_list{property::queue::enable_profiling()}; queue q(selector, fpga_tools::exception_handler, prop_list); + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + // The input data buffer buffer in_buf(in); diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/pipe_array/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/pipe_array/src/CMakeLists.txt index 012c689c05..0f31aca395 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/pipe_array/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/pipe_array/src/CMakeLists.txt @@ -23,11 +23,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/pipe_array/src/pipe_array.cpp b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/pipe_array/src/pipe_array.cpp index 76820f1655..2d91df08a4 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/pipe_array/src/pipe_array.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/pipe_array/src/pipe_array.cpp @@ -119,16 +119,22 @@ int main(int argc, char *argv[]) { for (size_t i = 0; i < array_size; i++) producer_input[i] = i; -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector device_selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector device_selector; -#else - ext::intel::fpga_selector device_selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif try { - queue q(device_selector, fpga_tools::exception_handler); + queue q(selector, fpga_tools::exception_handler); + + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; // Enqueue producer buffer producer_buffer(producer_input); diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/src/CMakeLists.txt index 9003ca978a..21b5359f59 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/src/CMakeLists.txt @@ -40,7 +40,7 @@ endif() set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR ${DEVICE_FLAG}") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR ${DEVICE_FLAG}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${DEVICE_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${DEVICE_FLAG} -DFPGA_HARDWARE") if(FPGA_DEVICE MATCHES ".s10.*") # hyper-optimized-handshaking only applies to Intel Stratix® 10 FPGAs set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xshyper-optimized-handshaking=off -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/src/shannonization.cpp b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/src/shannonization.cpp index 961e9dc79f..23e7cabee9 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/src/shannonization.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/src/shannonization.cpp @@ -256,17 +256,23 @@ int main(int argc, char** argv) { auto props = property_list{property::queue::enable_profiling()}; // the device selector -#ifdef FPGA_EMULATOR - ext::intel::fpga_emulator_selector selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector selector; -#else - ext::intel::fpga_selector selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif // create the device queue queue q(selector, props); + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + bool success = true; // Instantiate multiple versions of the kernel diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/simple_host_streaming/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/simple_host_streaming/src/CMakeLists.txt index fbb0515511..b2422700ff 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/simple_host_streaming/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/simple_host_streaming/src/CMakeLists.txt @@ -35,11 +35,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -Wall -DFPGA_EMULATOR ${DEVICE_FLAG}") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR ${DEVICE_FLAG}") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -Wall -Xssimulation -DFPGA_SIMULATOR ${DEVICE_FLAG}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR ${DEVICE_FLAG}") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Wall -Xssimulation -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga ${DEVICE_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${DEVICE_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Wall -Xshardware -Xshyper-optimized-handshaking=off -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA simulator and backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/simple_host_streaming/src/simple_host_streaming.cpp b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/simple_host_streaming/src/simple_host_streaming.cpp index 7cefd6ba3a..558fc69863 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/simple_host_streaming/src/simple_host_streaming.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/simple_host_streaming/src/simple_host_streaming.cpp @@ -140,12 +140,12 @@ int main(int argc, char* argv[]) { try { // device selector -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector selector; -#else - ext::intel::fpga_selector selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif // queue properties to enable profiling @@ -155,13 +155,17 @@ int main(int argc, char* argv[]) { queue q(selector, fpga_tools::exception_handler, prop_list); // make sure the device supports USM host allocations - device d = q.get_device(); - if (!d.get_info()) { + auto device = q.get_device(); + if (!device.get_info()) { std::cerr << "ERROR: The selected device does not support USM host" << " allocations\n"; std::terminate(); } + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + // the USM input and output data Type *in, *out; if ((in = malloc_host(total_count, q)) == nullptr) { diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/triangular_loop/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/triangular_loop/src/CMakeLists.txt index 487fe6c83c..cd099c5c9b 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/triangular_loop/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/triangular_loop/src/CMakeLists.txt @@ -23,11 +23,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-Wall -fsycl -fintelfpga ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/triangular_loop/src/triangular_loop.cpp b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/triangular_loop/src/triangular_loop.cpp index 3a846a5bfa..1ebf3c9486 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/triangular_loop/src/triangular_loop.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/triangular_loop/src/triangular_loop.cpp @@ -126,30 +126,27 @@ int main() { ulong t1_kernel, t2_kernel; double time_kernel; // Create queue, get platform and device -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector device_selector; - std::cout << "\nEmulator output does not demonstrate true hardware " - "performance. The design may need to run on actual hardware " - "to observe the performance benefit of the optimization " - "exemplified in this tutorial.\n\n"; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector device_selector; -#else - ext::intel::fpga_selector device_selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif try { auto prop_list = property_list{property::queue::enable_profiling()}; - sycl::queue q(device_selector, fpga_tools::exception_handler, prop_list); + sycl::queue q(selector, fpga_tools::exception_handler, prop_list); platform platform = q.get_context().get_platform(); device device = q.get_device(); std::cout << "Platform name: " << platform.get_info().c_str() << "\n"; - std::cout << "Device name: " - << device.get_info().c_str() << "\n\n\n"; + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; // Create input and output buffers auto input_buf = buffer(range<1>(kSize)); diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/src/CMakeLists.txt index 681da3a8c2..f914a23efb 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/src/CMakeLists.txt @@ -35,11 +35,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -Wall -DFPGA_EMULATOR ${DEVICE_FLAG}") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Wall -DFPGA_EMULATOR ${DEVICE_FLAG}") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -Xssimulation -Wall -DFPGA_SIMULATOR ${DEVICE_FLAG}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -Wall -DFPGA_SIMULATOR ${DEVICE_FLAG}") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xshyper-optimized-handshaking=off -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_SIMULATOR_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -Wall ${DEVICE_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Wall ${DEVICE_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xshyper-optimized-handshaking=off -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/src/zero_copy_data_transfer.cpp b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/src/zero_copy_data_transfer.cpp index 7df84b69f1..2da35473d8 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/src/zero_copy_data_transfer.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/src/zero_copy_data_transfer.cpp @@ -48,25 +48,29 @@ int main(int argc, char* argv[]) { try { // device selector -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector selector; -#elif FPGA_SIMULATOR - ext::intel::fpga_simulator_selector selector; -#else - ext::intel::fpga_selector selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif // create the device queue queue q(selector, fpga_tools::exception_handler); // make sure the device supports USM host allocations - device d = q.get_device(); - if (!d.get_info()) { + auto device = q.get_device(); + if (!device.get_info()) { std::cerr << "ERROR: The selected device does not support USM host" << " allocations\n"; return 1; } + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + // the golden output std::vector out_gold(size); From f62c0f0d696b29c12fef237ec288fede69e1fa39 Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Wed, 14 Dec 2022 01:35:27 -0800 Subject: [PATCH 21/38] updated selectors to part of the Features Signed-off-by: Yohann Uguen --- .../ReferenceDesigns/crr/src/CMakeLists.txt | 1 + .../ReferenceDesigns/crr/src/main.cpp | 12 ++++++++--- .../Features/ac_fixed/src/CMakeLists.txt | 2 +- .../Features/ac_fixed/src/ac_fixed.cpp | 20 ++++++++++++------- .../Features/ac_int/src/CMakeLists.txt | 2 +- .../Tutorials/Features/ac_int/src/ac_int.cpp | 20 ++++++++++++------- .../Features/dsp_control/src/CMakeLists.txt | 2 +- .../Features/dsp_control/src/dsp_control.cpp | 20 ++++++++++++------- 8 files changed, 52 insertions(+), 27 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/CMakeLists.txt index cd32206f06..448a5a0769 100755 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/CMakeLists.txt @@ -64,6 +64,7 @@ set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xsdaz -Xsrounding=faith # Copy input data configure_file("data/ordered_inputs.csv" "data/ordered_inputs.csv" COPYONLY) +configure_file("data/ordered_inputs.csv" "data/small_ordered_inputs.csv" COPYONLY) ############################################################################### ### FPGA Emulator diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/main.cpp b/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/main.cpp index 39a3cb3fe2..14f22e87c7 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/main.cpp +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/main.cpp @@ -716,7 +716,11 @@ int main(int argc, char *argv[]) { string infilename = ""; string outfilename = ""; +#ifdef FPGA_HARDWARE const string default_ifile = "src/data/ordered_inputs.csv"; +#else + const string default_ifile = "src/data/small_ordered_inputs.csv"; +#endif const string default_ofile = "src/data/ordered_outputs.csv"; char str_buffer[kMaxStringLen] = {0}; @@ -822,17 +826,19 @@ int main(int argc, char *argv[]) { vector in_buff_params(n_crrs * 3); vector in_buff2_params(n_crrs * 3); - vector res_params(n_crrs * 3); - vector res_params_dummy(n_crrs * 3); - // Prepare metadata as input to kernel PrepareKernelData(in_params, array_params, in_buff_params, in_buff2_params, n_crrs); +#ifdef FPGA_HARDWARE // warmup run - use this run to warmup accelerator + vector res_params_dummy(n_crrs * 3); CrrSolver(n_crrs, in_buff_params, res_params_dummy, in_buff2_params, q); +#endif + // Timed run - profile performance + vector res_params(n_crrs * 3); double time = CrrSolver(n_crrs, in_buff_params, res_params, in_buff2_params, q); bool pass = true; diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_fixed/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_fixed/src/CMakeLists.txt index bded938873..6f308d5d08 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_fixed/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_fixed/src/CMakeLists.txt @@ -32,7 +32,7 @@ set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} -DFPGA_EMULATOR set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG}") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} -DFPGA_SIMULATOR -Wall ${WIN_FLAG}") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} -Wall ${WIN_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_fixed/src/ac_fixed.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_fixed/src/ac_fixed.cpp index 76b2d11992..2a94fe35b1 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_fixed/src/ac_fixed.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_fixed/src/ac_fixed.cpp @@ -109,17 +109,23 @@ void TestCalculateWithACFixed(queue &q, const fixed_10_3_t &x, } int main() { -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector device_selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector device_selector; -#else - ext::intel::fpga_selector device_selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif try { // Create the SYCL device queue - queue q(device_selector, fpga_tools::exception_handler); + queue q(selector, fpga_tools::exception_handler); + + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; // I. Constructing `ac_fixed` Numbers std::cout << "1. Testing Constructing ac_fixed from float or ac_fixed:\n"; diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_int/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_int/src/CMakeLists.txt index 00e2c2ed85..38712b22ae 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_int/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_int/src/CMakeLists.txt @@ -33,7 +33,7 @@ set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG}") # simulator compilation set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} -DFPGA_SIMULATOR -Wall ${WIN_FLAG}") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${AC_TYPES_FLAG} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} -Wall ${WIN_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # We do not need to supply the AC_TYPES_FLAG for the 'report' target's linking stage. set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_int/src/ac_int.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_int/src/ac_int.cpp index 13950552fd..de6e478922 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_int/src/ac_int.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_int/src/ac_int.cpp @@ -113,18 +113,24 @@ MyInt14 TestBitAccess(queue &q, const MyInt14 &a) { } int main() { -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector device_selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector device_selector; -#else - ext::intel::fpga_selector device_selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif bool passed = true; try { - queue q(device_selector, fpga_tools::exception_handler); + queue q(selector, fpga_tools::exception_handler); + + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; constexpr int kVal1 = 1000, kVal2 = 2; diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/dsp_control/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/dsp_control/src/CMakeLists.txt index ac3675dcda..84e1f1e9be 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/dsp_control/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/dsp_control/src/CMakeLists.txt @@ -27,7 +27,7 @@ set(EMULATOR_COMPILE_FLAGS "-fsycl -Wall ${WIN_FLAG} -fintelfpga -DFPGA_EMULATOR set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") set(SIMULATOR_COMPILE_FLAGS "-fsycl -Wall ${WIN_FLAG} -fintelfpga -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} -Xsdsp-mode=prefer-softlogic ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -Wall ${WIN_FLAG} -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -Wall ${WIN_FLAG} -fintelfpga -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} -Xsdsp-mode=prefer-softlogic ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/dsp_control/src/dsp_control.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Features/dsp_control/src/dsp_control.cpp index c5df12f451..1b04a4f24c 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/dsp_control/src/dsp_control.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/dsp_control/src/dsp_control.cpp @@ -23,19 +23,25 @@ void KernelRun(const std::vector &input_data, std::vector &output_data_add, std::vector &output_data_sub) { -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector device_selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector device_selector; -#else - ext::intel::fpga_selector device_selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif try { // Create the SYCL device queue. - queue q(device_selector, fpga_tools::exception_handler, + queue q(selector, fpga_tools::exception_handler, property::queue::enable_profiling{}); + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + buffer input_buffer(input_data); buffer output_add_buffer(output_data_add); buffer output_sub_buffer(output_data_sub); From b00c9c7459cd4a73c89dc8883f91e72fd4efedfc Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Wed, 14 Dec 2022 03:04:17 -0800 Subject: [PATCH 22/38] updated selectors on all remaining samples Signed-off-by: Yohann Uguen --- .../DPC++FPGA/ReferenceDesigns/crr/README.md | 77 +++++++++++------- .../crr/src/data/small_ordered_inputs.csv | 1 + .../ReferenceDesigns/crr/src/main.cpp | 8 +- .../double_buffering/src/double_buffering.cpp | 2 +- .../n_way_buffering/src/n_way_buffering.cpp | 2 +- .../src/onchip_memory_cache.cpp | 2 +- .../Features/experimental/hostpipes/README.md | 80 +++++++++++-------- .../experimental/hostpipes/src/CMakeLists.txt | 24 +++++- .../experimental/hostpipes/src/hostpipes.cpp | 19 +++-- .../latency_control/src/CMakeLists.txt | 6 +- .../latency_control/src/latency_control.cpp | 21 +++-- .../Features/fpga_reg/src/CMakeLists.txt | 6 +- .../Features/fpga_reg/src/fpga_reg.cpp | 18 +++-- .../kernel_args_restrict/src/CMakeLists.txt | 6 +- .../src/kernel_args_restrict.cpp | 20 +++-- .../Features/loop_coalesce/src/CMakeLists.txt | 6 +- .../loop_coalesce/src/loop_coalesce.cpp | 20 +++-- .../Features/loop_fusion/src/CMakeLists.txt | 6 +- .../Features/loop_fusion/src/loop_fusion.cpp | 18 +++-- .../src/CMakeLists.txt | 6 +- .../src/loop_initiation_interval.cpp | 18 +++-- .../Features/loop_ivdep/src/CMakeLists.txt | 6 +- .../Features/loop_ivdep/src/loop_ivdep.cpp | 18 +++-- .../Features/loop_unroll/src/CMakeLists.txt | 6 +- .../Features/loop_unroll/src/loop_unroll.cpp | 21 +++-- .../Features/lsu_control/src/CMakeLists.txt | 6 +- .../Features/lsu_control/src/lsu_control.cpp | 20 +++-- .../max_interleaving/src/CMakeLists.txt | 6 +- .../max_interleaving/src/max_interleaving.cpp | 18 +++-- .../Features/mem_channel/src/CMakeLists.txt | 6 +- .../Features/mem_channel/src/mem_channel.cpp | 21 +++-- .../memory_attributes/src/CMakeLists.txt | 21 ++++- .../src/memory_attributes.cpp | 28 +++++-- .../Features/pipes/src/CMakeLists.txt | 6 +- .../Tutorials/Features/pipes/src/pipes.cpp | 20 +++-- .../Features/printf/src/CMakeLists.txt | 6 +- .../Tutorials/Features/printf/src/printf.cpp | 21 +++-- .../private_copies/src/CMakeLists.txt | 4 +- .../private_copies/src/private_copies.cpp | 21 +++-- .../read_only_cache/src/CMakeLists.txt | 6 +- .../read_only_cache/src/read_only_cache.cpp | 21 +++-- .../scheduler_target_fmax/src/CMakeLists.txt | 6 +- .../src/scheduler_target_fmax.cpp | 20 +++-- .../speculated_iterations/src/CMakeLists.txt | 6 +- .../src/speculated_iterations.cpp | 29 ++++--- .../Features/stall_enable/src/CMakeLists.txt | 6 +- .../stall_enable/src/stall_enable.cpp | 18 +++-- .../fast_recompile/src/CMakeLists.txt | 2 +- .../fast_recompile/src/host.cpp | 20 +++-- .../fpga_compile/src/CMakeLists.txt | 4 +- .../fpga_compile/src/fpga_compile.cpp | 17 ++-- .../Tools/dynamic_profiler/src/CMakeLists.txt | 6 +- .../dynamic_profiler/src/dynamic_profiler.cpp | 22 +++-- .../Tools/system_profiling/src/CMakeLists.txt | 6 +- .../system_profiling/src/double_buffering.cpp | 32 ++++---- .../Tools/use_library/src/CMakeLists.txt | 2 +- .../Tools/use_library/src/use_library.cpp | 20 +++-- 57 files changed, 546 insertions(+), 318 deletions(-) create mode 100755 DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/data/small_ordered_inputs.csv diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/README.md b/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/README.md index 6925a71127..d8ded4d251 100755 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/README.md +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/README.md @@ -167,13 +167,17 @@ This design measures the FPGA performance to determine how many assets can be pr ``` make fpga_emu ``` - 2. Generate the HTML performance report. - ``` - make report - ``` + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + make fpga_sim + ``` + 3. Generate the HTML performance report. + ``` + make report + ``` The report resides at `/reports/report.html`. - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). ``` make fpga ``` @@ -202,13 +206,17 @@ This design measures the FPGA performance to determine how many assets can be pr ``` nmake fpga_emu ``` - 2. Generate the HTML performance report. + 2. Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + nmake fpga_sim + ``` + 3. Generate the HTML performance report. ``` nmake report ``` The report resides at `.a.prj/reports/report.html`. - 3. Compile for FPGA hardware (longer compile time, targets FPGA device). + 4. Compile for FPGA hardware (longer compile time, targets FPGA device). ``` nmake fpga ``` @@ -218,33 +226,40 @@ This design measures the FPGA performance to determine how many assets can be pr ### On Linux - 1. Run the sample on the FPGA emulator (the kernel executes on the CPU). - ``` - ./crr.fpga_emu [-o=] - ``` - where: - - `` is an **optional** argument to specify the input data file name. The default input file is `/data/ordered_inputs.csv`. - - `-o=` is an **optional** argument to specify the name of the output file. The default name of the output file is `ordered_outputs.csv`. - - 2. Run the sample on the FPGA device. - ``` - ./crr.fpga [-o=] - ``` +1. Run the sample on the FPGA emulator (the kernel executes on the CPU). + ``` + ./crr.fpga_emu [-o=] + ``` + where: + - `` is an **optional** argument to specify the input data file name. The default input file is `/data/ordered_inputs.csv`. + - `-o=` is an **optional** argument to specify the name of the output file. The default name of the output file is `ordered_outputs.csv`. +2. Run the sample on the FPGA simulator. + ``` + ./crr.fpga_sim [-o=] + ``` +3. Run the sample on the FPGA device. + ``` + ./crr.fpga [-o=] + ``` ### On Windows - 1. Run the sample on the FPGA emulator (the kernel executes on the CPU). - ``` - crr.fpga_emu.exe [-o=] - ``` - where: - - `` is an **optional** argument to specify the input data file name. The default input file is `/data/ordered_inputs.csv`. - - `-o=` is an **optional** argument to specify the name of the output file. The default name of the output file is `ordered_outputs.csv`. - - 2. Run the sample on the FPGA device. - ``` - crr.fpga.exe [-o=] - ``` +1. Run the sample on the FPGA emulator (the kernel executes on the CPU). + ``` + crr.fpga_emu.exe [-o=] + ``` + where: + - `` is an **optional** argument to specify the input data file name. The default input file is `/data/ordered_inputs.csv`. + - `-o=` is an **optional** argument to specify the name of the output file. The default name of the output file is `ordered_outputs.csv`. +2. Run the sample on the FPGA simulator. + ``` + crr.fpga_sim.exe [-o=] + ``` + +3. Run the sample on the FPGA device. + ``` + crr.fpga.exe [-o=] + ``` ## Example Output diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/data/small_ordered_inputs.csv b/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/data/small_ordered_inputs.csv new file mode 100755 index 0000000000..ff5745eaef --- /dev/null +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/data/small_ordered_inputs.csv @@ -0,0 +1 @@ +8189,-1,37.5,37.50112053,85,0.4,0.99997012,0.011952191 diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/main.cpp b/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/main.cpp index 14f22e87c7..c5208e3c46 100644 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/main.cpp +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/main.cpp @@ -250,8 +250,8 @@ double CrrSolver(const int n_items, vector &in_params, // Update optval[] -- calculate each level of the binomial tree. // reg[] helps to achieve updating INNER_UNROLL elements in optval[] // simultaneously. - [[intel::disable_loop_pipelining]] for (short t = 0; - t <= steps - 1; ++t) { + [[intel::disable_loop_pipelining]] // NO-FORMAT: Attribute + for (short t = 0; t <= steps - 1; ++t) { [[intel::fpga_register]] double reg[INNER_UNROLL + 1][OUTER_UNROLL]; double val_1, val_2; @@ -264,8 +264,8 @@ double CrrSolver(const int n_items, vector &in_params, // L4: // Calculate all the elements in optval[] -- all the tree nodes // for one level of the tree - [[intel::ivdep]] for (int n = 0; n <= steps - 1 - t; - n += INNER_UNROLL) { + [[intel::ivdep]] // NO-FORMAT: Attribute + for (int n = 0; n <= steps - 1 - t; n += INNER_UNROLL) { #pragma unroll for (short ic = 0; ic < OUTER_UNROLL; ++ic) { diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/double_buffering/src/double_buffering.cpp b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/double_buffering/src/double_buffering.cpp index 157858162f..5d120e5ae0 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/double_buffering/src/double_buffering.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/double_buffering/src/double_buffering.cpp @@ -213,7 +213,7 @@ int main() { #endif #ifndef FPGA_HARDWARE - std::cout << "\nEmulator and simualtor outputs do not demonstrate " + std::cout << "\nEmulator and simulator outputs do not demonstrate " "true hardware performance. The design may need to run " "on actual hardware to observe the performance benefit " "of the optimization exemplified in this tutorial.\n\n"; diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/n_way_buffering/src/n_way_buffering.cpp b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/n_way_buffering/src/n_way_buffering.cpp index f6feb80b0b..f6ef224450 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/n_way_buffering/src/n_way_buffering.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/n_way_buffering/src/n_way_buffering.cpp @@ -223,7 +223,7 @@ int main() { #endif #ifndef FPGA_HARDWARE - std::cout << "\nEmulator and simualtor outputs do not demonstrate " + std::cout << "\nEmulator and simulator outputs do not demonstrate " "true hardware performance. The design may need to run " "on actual hardware to observe the performance benefit " "of the optimization exemplified in this tutorial.\n\n"; diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/onchip_memory_cache/src/onchip_memory_cache.cpp b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/onchip_memory_cache/src/onchip_memory_cache.cpp index 62fe06bc70..5ff9199a9c 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/onchip_memory_cache/src/onchip_memory_cache.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/onchip_memory_cache/src/onchip_memory_cache.cpp @@ -82,7 +82,7 @@ int main() { #endif #ifndef FPGA_HARDWARE - std::cout << "\nEmulator and simualtor outputs do not demonstrate " + std::cout << "\nEmulator and simulator outputs do not demonstrate " "true hardware performance. The design may need to run " "on actual hardware to observe the performance benefit " "of the optimization exemplified in this tutorial.\n\n"; diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/experimental/hostpipes/README.md b/DirectProgramming/DPC++FPGA/Tutorials/Features/experimental/hostpipes/README.md index 94efb50244..796c117897 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/experimental/hostpipes/README.md +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/experimental/hostpipes/README.md @@ -316,18 +316,22 @@ After learning how to use the extensions for Intel oneAPI Toolkits, return to th 2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: - * Compile for emulation (fast compile time, targets emulated FPGA device): - ``` - make fpga_emu - ``` - * Generate the optimization report: - ``` - make report - ``` - * Compile for FPGA hardware (longer compile time, targets FPGA device): - ``` - make fpga - ``` + * Compile for emulation (fast compile time, targets emulated FPGA device): + ``` + make fpga_emu + ``` + * Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + make fpga_sim + ``` + * Generate the optimization report: + ``` + make report + ``` + * Compile for FPGA hardware (longer compile time, targets FPGA device): + ``` + make fpga + ``` 3. (Optional) As the above hardware compile may take several hours to complete, FPGA precompiled binaries (compatible with Linux* Ubuntu* 18.04) can be downloaded here. ### On a Windows* System @@ -349,18 +353,22 @@ After learning how to use the extensions for Intel oneAPI Toolkits, return to th 2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: - * Compile for emulation (fast compile time, targets emulated FPGA device): - ``` - nmake fpga_emu - ``` - * Generate the optimization report: - ``` - nmake report - ``` - * Compile for FPGA hardware (longer compile time, targets FPGA device): - ``` - nmake fpga - ``` + * Compile for emulation (fast compile time, targets emulated FPGA device): + ``` + nmake fpga_emu + ``` + * Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + nmake fpga_sim + ``` + * Generate the optimization report: + ``` + nmake report + ``` + * Compile for FPGA hardware (longer compile time, targets FPGA device): + ``` + nmake fpga + ``` >*Note:* The Intel® FPGA PAC D5005 with Intel Stratix® 10 SX does not support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support.
@@ -413,15 +421,21 @@ using D2HPipe = cl::sycl::ext::intel::prototype::pipe< ## Running the Sample - 1. Run the sample on the FPGA emulator (the kernel executes on the CPU): - ``` - ./hostpipes.fpga_emu (Linux) - hostpipes.fpga_emu.exe (Windows) - ``` -2. Run the sample on the FPGA device: - ``` - ./hostpipes.fpga (Linux) - ``` +1. Run the sample on the FPGA emulator (the kernel executes on the CPU): + ``` + ./hostpipes.fpga_emu (Linux) + hostpipes.fpga_emu.exe (Windows) + ``` +2. Run the sample on the FPGA simulator. + ``` + ./hostpipes.fpga_sim [-o=] (Linux) + hostpipes.fpga_sim.exe [-o=] (Windows) + ``` +3. Run the sample on the FPGA device: + ``` + ./hostpipes.fpga (Linux) + hostpipes.fpga.exe (Windows) + ``` ### Example of Output diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/experimental/hostpipes/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/experimental/hostpipes/src/CMakeLists.txt index 347005905d..a95a554227 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/experimental/hostpipes/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/experimental/hostpipes/src/CMakeLists.txt @@ -1,6 +1,7 @@ set(SOURCE_FILE hostpipes.cpp) set(TARGET_NAME hostpipes) set(EMULATOR_TARGET ${TARGET_NAME}.fpga_emu) +set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA device selection @@ -40,9 +41,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -Wall ${WIN_FLAG} -fintelfpga -DFPGA_EMULATOR -I${SDK_ROOT_PATH}/include -I${SDK_ROOT_PATH}/include/sycl/ext/intel/prototype") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR -I${SDK_ROOT_PATH}/include -I${SDK_ROOT_PATH}/include/sycl/ext/intel/prototype") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(HARDWARE_COMPILE_FLAGS "-fsycl -Wall ${WIN_FLAG} -fintelfpga -I${SDK_ROOT_PATH}/include -I${SDK_ROOT_PATH}/include/sycl/ext/intel/prototype") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -I${SDK_ROOT_PATH}/include -I${SDK_ROOT_PATH}/include/sycl/ext/intel/prototype -DFPGA_SIMULATOR") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} -Xsdsp-mode=prefer-softlogic ${USER_HARDWARE_FLAGS}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -I${SDK_ROOT_PATH}/include -I${SDK_ROOT_PATH}/include/sycl/ext/intel/prototype -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xsboard=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation @@ -60,6 +63,23 @@ set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_CO set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS}") add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET}) +############################################################################### +### FPGA Simulator +############################################################################### +# To compile in a single command: +# icpx -fsycl -fintelfpga -DFPGA_SIMULATOR -Xssimulation -Xsghdl -Xstarget= -Xsdsp-mode=prefer-softlogic dsp_control.cpp -o dsp_control.fpga +# CMake executes: +# [compile] icpx -fsycl -fintelfpga -DFPGA_SIMULATOR -o dsp_control.cpp.o -c dsp_control.cpp +# [link] icpx -fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget= -Xsdsp-mode=prefer-softlogic dsp_control.cpp.o -o dsp_control.fpga +add_executable(${SIMULATOR_TARGET} EXCLUDE_FROM_ALL ${SOURCE_FILE}) +target_include_directories(${SIMULATOR_TARGET} PRIVATE ../../../../../include) +add_custom_target(fpga_sim DEPENDS ${SIMULATOR_TARGET}) +set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${SIMULATOR_COMPILE_FLAGS}") +set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${SIMULATOR_LINK_FLAGS} -reuse-exe=${CMAKE_BINARY_DIR}/${SIMULATOR_TARGET}") +# The -reuse-exe flag enables rapid recompilation of host-only code changes. +# See DPC++FPGA/GettingStarted/fast_recompile for details. + + ############################################################################### ### Generate Report ############################################################################### diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/experimental/hostpipes/src/hostpipes.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Features/experimental/hostpipes/src/hostpipes.cpp index 2c77d7b0dc..b9a11a4671 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/experimental/hostpipes/src/hostpipes.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/experimental/hostpipes/src/hostpipes.cpp @@ -62,10 +62,12 @@ ValueT SomethingComplicated(ValueT val) { return (ValueT)(val * sqrt(val)); } ///////////////////////////////////////// int main(int argc, char* argv[]) { -#if defined(FPGA_EMULATOR) - sycl::ext::intel::fpga_emulator_selector selector; -#else - sycl::ext::intel::fpga_selector selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif bool passed = true; @@ -90,13 +92,18 @@ int main(int argc, char* argv[]) { sycl::property::queue::enable_profiling{}); // make sure the device supports USM device allocations - sycl::device d = q.get_device(); - if (!d.has(sycl::aspect::usm_host_allocations)) { + auto device = q.get_device(); + if (!device.has(sycl::aspect::usm_host_allocations)) { std::cerr << "ERROR: The selected device does not support USM host" << " allocations" << std::endl; return 1; } + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + + // create input and golden output data std::vector in(count), out(count), golden(count); std::generate(in.begin(), in.end(), [] { return ValueT(rand() % 77); }); diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/experimental/latency_control/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/experimental/latency_control/src/CMakeLists.txt index 2f9bdab7a3..9d0f1d3205 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/experimental/latency_control/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/experimental/latency_control/src/CMakeLists.txt @@ -31,11 +31,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -Wall ${WIN_FLAG} -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-fsycl -Wall ${WIN_FLAG} -fintelfpga -DFPGA_SIMULATOR") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl ${HANDSHAKING} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -Wall ${WIN_FLAG} -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware ${HANDSHAKING} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/experimental/latency_control/src/latency_control.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Features/experimental/latency_control/src/latency_control.cpp index b97121b2d6..af8ac46605 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/experimental/latency_control/src/latency_control.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/experimental/latency_control/src/latency_control.cpp @@ -17,20 +17,25 @@ class LatencyControl; // Runs the Kernel. void KernelRun(const std::vector &in_data, std::vector &out_data, const size_t &size) { -#if defined(FPGA_EMULATOR) - sycl::ext::intel::fpga_emulator_selector device_selector; -#elif defined(FPGA_SIMULATOR) - sycl::ext::intel::fpga_simulator_selector device_selector; -#else - sycl::ext::intel::fpga_selector device_selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif - try { // Create the SYCL device queue. - sycl::queue q(device_selector, fpga_tools::exception_handler, + sycl::queue q(selector, fpga_tools::exception_handler, sycl::property::queue::enable_profiling{}); + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + sycl::buffer in_buffer(in_data); sycl::buffer out_buffer(out_data); diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/fpga_reg/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/fpga_reg/src/CMakeLists.txt index 3d5aa18193..b336c2a8a1 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/fpga_reg/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/fpga_reg/src/CMakeLists.txt @@ -26,11 +26,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -Wall ${WIN_FLAG} -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-fsycl -Wall ${WIN_FLAG} -fintelfpga -DFPGA_SIMULATOR") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -Wall ${WIN_FLAG} -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/fpga_reg/src/fpga_reg.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Features/fpga_reg/src/fpga_reg.cpp index 2cb0c3b764..55e3d0400e 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/fpga_reg/src/fpga_reg.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/fpga_reg/src/fpga_reg.cpp @@ -73,12 +73,12 @@ void RunKernel(const std::vector &vec_a, std::vector &vec_r) { // Run the kernel on either the FPGA emulator, or FPGA simulator, or FPGA // hardware -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector selector; -#else - ext::intel::fpga_selector selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif size_t input_size = vec_a.size(); @@ -87,6 +87,12 @@ void RunKernel(const std::vector &vec_a, queue q(selector, fpga_tools::exception_handler, property::queue::enable_profiling{}); + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + buffer device_a(vec_a); buffer device_r(vec_r); diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/kernel_args_restrict/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/kernel_args_restrict/src/CMakeLists.txt index 13a445ccee..df3670f1da 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/kernel_args_restrict/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/kernel_args_restrict/src/CMakeLists.txt @@ -23,12 +23,12 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -Wall ${WIN_FLAG} -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA simulator compilation -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/kernel_args_restrict/src/kernel_args_restrict.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Features/kernel_args_restrict/src/kernel_args_restrict.cpp index d2559fc079..ca4ca27cb6 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/kernel_args_restrict/src/kernel_args_restrict.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/kernel_args_restrict/src/kernel_args_restrict.cpp @@ -29,18 +29,24 @@ double GetExecutionTime(const event &e) { void RunKernels(size_t size, std::vector &in, std::vector &nr_out, std::vector &r_out) { -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector device_selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector device_selector; -#else - ext::intel::fpga_selector device_selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif try { // create the SYCL device queue - queue q(device_selector, fpga_tools::exception_handler, + queue q(selector, fpga_tools::exception_handler, property::queue::enable_profiling{}); + + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; buffer in_buf(in); buffer nr_out_buf(nr_out); diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_coalesce/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_coalesce/src/CMakeLists.txt index a543abc34f..2b9a317acc 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_coalesce/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_coalesce/src/CMakeLists.txt @@ -23,11 +23,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-Wall -fsycl -fintelfpga ${WIN_FLAG} -DFPGA_SIMULATOR") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_coalesce/src/loop_coalesce.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_coalesce/src/loop_coalesce.cpp index 984f1d306c..86bc3da8f6 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_coalesce/src/loop_coalesce.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_coalesce/src/loop_coalesce.cpp @@ -33,18 +33,26 @@ void MatrixMultiply(const std::vector &matrix_a, const std::vector &matrix_b, std::vector &res) { double kernel_time = 0.0; -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector selector; -#else - ext::intel::fpga_selector selector; + +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif + try { auto prop_list = property_list{property::queue::enable_profiling()}; queue q(selector, fpga_tools::exception_handler, prop_list); + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + buffer buffer_in_a(matrix_a); buffer buffer_in_b(matrix_b); buffer buffer_out(res); diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_fusion/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_fusion/src/CMakeLists.txt index d5e8ad6b7a..fbca480ece 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_fusion/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_fusion/src/CMakeLists.txt @@ -23,12 +23,12 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -Wall -fintelfpga ${WIN_FLAG} -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-fsycl -Wall -fintelfpga ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR ${USER_SIMULATOR_FLAGS}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR ${USER_SIMULATOR_FLAGS}") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} ${USER_SIMULATOR_FLAGS}") # use cmake -D USER_SIMULATOR_FLAGS= to set extra flags for FPGA simulator compilation -set(HARDWARE_COMPILE_FLAGS "-fsycl -Wall -fintelfpga ${WIN_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_fusion/src/loop_fusion.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_fusion/src/loop_fusion.cpp index 407ee9a7b1..f88daddb4b 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_fusion/src/loop_fusion.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_fusion/src/loop_fusion.cpp @@ -29,12 +29,12 @@ class NoFusionKernel; class DefaultNoFusionKernel; class FusionFunctionKernel; -#if defined(FPGA_EMULATOR) -ext::intel::fpga_emulator_selector selector; -#elif defined(FPGA_SIMULATOR) -ext::intel::fpga_simulator_selector selector; -#else -ext::intel::fpga_selector selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif // Handles error reporting @@ -68,6 +68,12 @@ void DefaultFusion(FixedArray &m_array_1, FixedArray &m_array_2) { queue q(selector, fpga_tools::exception_handler, property::queue::enable_profiling{}); + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + buffer buff_1(m_array_1); buffer buff_2(m_array_2); diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_initiation_interval/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_initiation_interval/src/CMakeLists.txt index 6b4baf3b0d..97bc25315d 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_initiation_interval/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_initiation_interval/src/CMakeLists.txt @@ -40,11 +40,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR ${DEVICE_FLAG}") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR ${DEVICE_FLAG}") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_SIMULATOR ${DEVICE_FLAG}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_SIMULATOR ${DEVICE_FLAG}") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga ${DEVICE_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${DEVICE_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_initiation_interval/src/loop_initiation_interval.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_initiation_interval/src/loop_initiation_interval.cpp index ca84263753..9b2daf26e5 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_initiation_interval/src/loop_initiation_interval.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_initiation_interval/src/loop_initiation_interval.cpp @@ -68,12 +68,12 @@ double GetExecutionTime(const event &e) { } void RunKernel(std::vector &in, std::vector &out) { -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector selector; -#else - ext::intel::fpga_selector selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif try { @@ -81,6 +81,12 @@ void RunKernel(std::vector &in, std::vector &out) { queue q(selector, fpga_tools::exception_handler, property::queue::enable_profiling{}); + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + buffer in_buf(in); buffer out_buf(out); diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_ivdep/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_ivdep/src/CMakeLists.txt index ec91929dc7..c31d9d796c 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_ivdep/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_ivdep/src/CMakeLists.txt @@ -23,11 +23,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA simulator compilation and backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_ivdep/src/loop_ivdep.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_ivdep/src/loop_ivdep.cpp index 89584370d5..6466c7fc55 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_ivdep/src/loop_ivdep.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_ivdep/src/loop_ivdep.cpp @@ -28,12 +28,12 @@ template class KernelCompute; template void TransposeAndFold(const std::array &m_input, std::array &m_output) { -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector selector; -#else - ext::intel::fpga_selector selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif double kernel_time = 0; @@ -41,6 +41,12 @@ void TransposeAndFold(const std::array &m_input, queue q(selector, fpga_tools::exception_handler, property::queue::enable_profiling{}); + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + buffer buffer_input(m_input); buffer buffer_output(m_output); diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/src/CMakeLists.txt index 91f8949f66..e786aee5be 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/src/CMakeLists.txt @@ -23,11 +23,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA simulator compilation and backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/src/loop_unroll.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/src/loop_unroll.cpp index d94c07124c..ecbeaf5c18 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/src/loop_unroll.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/src/loop_unroll.cpp @@ -26,19 +26,24 @@ void VecAdd(const std::vector &summands1, const std::vector &summands2, std::vector &sum, size_t array_size) { - -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector device_selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector device_selector; -#else - ext::intel::fpga_selector device_selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif try { - queue q(device_selector, fpga_tools::exception_handler, + queue q(selector, fpga_tools::exception_handler, property::queue::enable_profiling{}); + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + buffer buffer_summands1(summands1); buffer buffer_summands2(summands2); buffer buffer_sum(sum); diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/lsu_control/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/lsu_control/src/CMakeLists.txt index 6b23dfd38c..13ac86c5ba 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/lsu_control/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/lsu_control/src/CMakeLists.txt @@ -23,11 +23,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA simulator compilation -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") if(FPGA_DEVICE STREQUAL "intel_a10gx_pac:pac_a10") # hyper-optimized-handshaking does not apply to Intel Arria 10® FPGAs set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/lsu_control/src/lsu_control.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Features/lsu_control/src/lsu_control.cpp index 6121b098b3..77ef29ee38 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/lsu_control/src/lsu_control.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/lsu_control/src/lsu_control.cpp @@ -51,19 +51,25 @@ void KernelRun(const std::vector &input_data, const size_t &input_size, const size_t &output_size, std::vector &output_data) { std::fill(output_data.begin(), output_data.end(), -1); -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector device_selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector device_selector; -#else - ext::intel::fpga_selector device_selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif try { // create the SYCL device queue - queue q(device_selector, fpga_tools::exception_handler, + queue q(selector, fpga_tools::exception_handler, property::queue::enable_profiling{}); + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + buffer output_buffer(output_data); buffer input_buffer(input_data); diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/max_interleaving/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/max_interleaving/src/CMakeLists.txt index 66862e2e59..c33636326f 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/max_interleaving/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/max_interleaving/src/CMakeLists.txt @@ -23,11 +23,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA simulator compilation and backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/max_interleaving/src/max_interleaving.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Features/max_interleaving/src/max_interleaving.cpp index 0519bfec2b..84ce3962ae 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/max_interleaving/src/max_interleaving.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/max_interleaving/src/max_interleaving.cpp @@ -36,12 +36,12 @@ class KernelCompute; template void Transform(const TwoDimFloatArray &array_a, const FloatArray &array_b, FloatArray &array_r) { -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector selector; -#else - ext::intel::fpga_selector selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif double kernel_time = 0.0; @@ -50,6 +50,12 @@ void Transform(const TwoDimFloatArray &array_a, const FloatArray &array_b, queue q(selector, fpga_tools::exception_handler, property::queue::enable_profiling{}); + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + buffer array_a_buffer(array_a); buffer array_b_buffer(array_b); buffer array_r_buffer(array_r); diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/mem_channel/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/mem_channel/src/CMakeLists.txt index f7c650661b..8ab8bfa7e3 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/mem_channel/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/mem_channel/src/CMakeLists.txt @@ -24,12 +24,12 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA simulator compilation -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/mem_channel/src/mem_channel.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Features/mem_channel/src/mem_channel.cpp index 49130ba0b0..245d99b63f 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/mem_channel/src/mem_channel.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/mem_channel/src/mem_channel.cpp @@ -78,18 +78,25 @@ int main() { std::iota(c.begin(), c.end(), 0); // Create queue, get platform and device -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector device_selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector device_selector; -#else - ext::intel::fpga_selector device_selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif + try { auto prop_list = sycl::property_list{sycl::property::queue::enable_profiling()}; - sycl::queue q(device_selector, fpga_tools::exception_handler, prop_list); + sycl::queue q(selector, fpga_tools::exception_handler, prop_list); + + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; std::cout << "\nVector size: " << vector_size << "\n"; diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/memory_attributes/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/memory_attributes/src/CMakeLists.txt index 0f69d424c1..49920e28d9 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/memory_attributes/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/memory_attributes/src/CMakeLists.txt @@ -1,6 +1,7 @@ set(SOURCE_FILE memory_attributes.cpp) set(TARGET_NAME memory_attributes) set(EMULATOR_TARGET ${TARGET_NAME}.fpga_emu) +set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection @@ -22,9 +23,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation @@ -42,6 +45,20 @@ set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_CO set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS}") add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET}) +############################################################################### +### FPGA Simulator +############################################################################### +# To compile in a single command: +# icpx -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR mem_channel.cpp -o mem_channel.fpga_sim +# CMake executes: +# [compile] icpx -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR -o mem_channel.cpp.o -c mem_channel.cpp +# [link] icpx -fsycl -fintelfpga -Xssimulation mem_channel.cpp.o -o mem_channel.fpga_sim +add_executable(${SIMULATOR_TARGET} ${SOURCE_FILE}) +target_include_directories(${SIMULATOR_TARGET} PRIVATE ../../../../include) +set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${SIMULATOR_COMPILE_FLAGS}") +set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${SIMULATOR_LINK_FLAGS}") +add_custom_target(fpga_sim DEPENDS ${SIMULATOR_TARGET}) + ############################################################################### ### Generate Report ############################################################################### diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/memory_attributes/src/memory_attributes.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Features/memory_attributes/src/memory_attributes.cpp index 004b3ab66d..da6ad25c43 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/memory_attributes/src/memory_attributes.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/memory_attributes/src/memory_attributes.cpp @@ -164,18 +164,29 @@ event submitKernel<2>(queue& q, unsigned init, buffer& d_buf, return e; } -template -unsigned RunKernel(unsigned init, const unsigned dict_offset_init[]) { +template +unsigned RunKernel(unsigned init, const unsigned dict_offset_init[], + bool first_run = false) { unsigned result = 0; -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector device_selector; -#else - ext::intel::fpga_selector device_selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif try { - queue q(device_selector, fpga_tools::exception_handler); + queue q(selector, fpga_tools::exception_handler); + + if (first_run){ + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + } // Flatten the 2D array to a 1D buffer, because the // buffer constructor requires a pointer to input data @@ -236,7 +247,8 @@ int main() { unsigned golden_result = GoldenRun(init, dict_offset_init); // run the kernel with 'singlepump' memory attribute - unsigned result_sp = RunKernel<1>(init, dict_offset_init); + bool first_run = j==0; + unsigned result_sp = RunKernel<1>(init, dict_offset_init, first_run); if (!(result_sp == golden_result)) { passed = false; diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/pipes/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/pipes/src/CMakeLists.txt index cde55441cd..5b288364fa 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/pipes/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/pipes/src/CMakeLists.txt @@ -23,11 +23,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/pipes/src/pipes.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Features/pipes/src/pipes.cpp index bbd08e0279..4bad87e149 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/pipes/src/pipes.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/pipes/src/pipes.cpp @@ -104,12 +104,12 @@ int main(int argc, char *argv[]) { producer_input[i] = rand() % max_val; } -#if defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector device_selector; -#elif defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector device_selector; -#else - ext::intel::fpga_selector device_selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif event producer_event, consumer_event; @@ -119,7 +119,13 @@ int main(int argc, char *argv[]) { auto props = property_list{property::queue::enable_profiling()}; // create the device queue with SYCL profiling enabled - queue q(device_selector, fpga_tools::exception_handler, props); + queue q(selector, fpga_tools::exception_handler, props); + + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; // create the producer and consumer buffers buffer producer_buffer(producer_input); diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/printf/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/printf/src/CMakeLists.txt index f3aa07fd46..1f6d21a129 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/printf/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/printf/src/CMakeLists.txt @@ -23,11 +23,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "${WIN_FLAG} -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "${WIN_FLAG} -fsycl -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA simulator and backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/printf/src/printf.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Features/printf/src/printf.cpp index 805292db22..e3d063d89e 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/printf/src/printf.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/printf/src/printf.cpp @@ -24,15 +24,22 @@ using namespace sycl; class BasicKernel; int main(int argc, char* argv[]) { -#ifdef FPGA_EMULATOR - ext::intel::fpga_emulator_selector device_selector; -#elif FPGA_SIMULATOR - ext::intel::fpga_simulator_selector device_selector; -#else - ext::intel::fpga_selector device_selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif - queue q(device_selector); + queue q(selector); + + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + // Create some kernel arguments for printing. int x = 123; float y = 1.0f; diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/private_copies/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/private_copies/src/CMakeLists.txt index af1961c59c..68745f9968 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/private_copies/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/private_copies/src/CMakeLists.txt @@ -22,9 +22,9 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/private_copies/src/private_copies.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Features/private_copies/src/private_copies.cpp index 2f95bbeb1b..ce7d020e2b 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/private_copies/src/private_copies.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/private_copies/src/private_copies.cpp @@ -30,12 +30,13 @@ template class Kernel; // Launch a kernel on the device specified by selector. // The kernel's functionality is designed to show the // performance impact of the private_copies attribute. -template +template void SimpleMathWithShift(const IntArray &array, int shift, IntScalar &result) { -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector selector; -#else - ext::intel::fpga_selector selector; + +#if FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif double kernel_time = 0.0; @@ -44,6 +45,14 @@ void SimpleMathWithShift(const IntArray &array, int shift, IntScalar &result) { queue q(selector, fpga_tools::exception_handler, property::queue::enable_profiling{}); + if constexpr (first_call){ + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + } + buffer buffer_array(array); buffer buffer_result(result.data(), 1); @@ -135,7 +144,7 @@ int main() { // Run the kernel with different values of the private_copies // attribute to determine the optimal private_copies number. - SimpleMathWithShift<0>(a, shift, R0); + SimpleMathWithShift<0, true>(a, shift, R0); SimpleMathWithShift<1>(a, shift, R1); SimpleMathWithShift<2>(a, shift, R2); SimpleMathWithShift<3>(a, shift, R3); diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/read_only_cache/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/read_only_cache/src/CMakeLists.txt index 710d0ef047..056cc71b59 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/read_only_cache/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/read_only_cache/src/CMakeLists.txt @@ -24,11 +24,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/read_only_cache/src/read_only_cache.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Features/read_only_cache/src/read_only_cache.cpp index 688bdeb929..4f265feac0 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/read_only_cache/src/read_only_cache.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/read_only_cache/src/read_only_cache.cpp @@ -82,18 +82,25 @@ int main() { } // Create queue, get platform and device -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector device_selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector device_selector; -#else - ext::intel::fpga_selector device_selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif + try { auto prop_list = sycl::property_list{sycl::property::queue::enable_profiling()}; - sycl::queue q(device_selector, fpga_tools::exception_handler, prop_list); + sycl::queue q(selector, fpga_tools::exception_handler, prop_list); + + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; std::cout << "\nSQRT LUT size: " << kLUTSize << "\n"; std::cout << "Number of outputs: " << kNumOutputs << "\n"; diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/scheduler_target_fmax/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/scheduler_target_fmax/src/CMakeLists.txt index f62844f198..c289ffa077 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/scheduler_target_fmax/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/scheduler_target_fmax/src/CMakeLists.txt @@ -23,11 +23,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -Wall ${WIN_FLAG} -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-fsycl -Wall ${WIN_FLAG} -fintelfpga -DFPGA_SIMULATOR") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -Wall ${WIN_FLAG} -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/scheduler_target_fmax/src/scheduler_target_fmax.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Features/scheduler_target_fmax/src/scheduler_target_fmax.cpp index 6b56b201f5..906c132eb4 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/scheduler_target_fmax/src/scheduler_target_fmax.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/scheduler_target_fmax/src/scheduler_target_fmax.cpp @@ -22,19 +22,25 @@ class Fmax240II; // Runs the Kernel void KernelRun(size_t size, const std::vector &input_data, std::vector &output_data) { -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector device_selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector device_selector; -#else - ext::intel::fpga_selector device_selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif try { // create the SYCL device queue - queue q(device_selector, fpga_tools::exception_handler, + queue q(selector, fpga_tools::exception_handler, property::queue::enable_profiling{}); + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + buffer input_buffer(input_data); buffer output_buffer(output_data); diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/speculated_iterations/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/speculated_iterations/src/CMakeLists.txt index b7f5d7f099..7b6c638d74 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/speculated_iterations/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/speculated_iterations/src/CMakeLists.txt @@ -38,11 +38,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR ${DEVICE_FLAG}") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR ${DEVICE_FLAG}") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_SIMULATOR ${DEVICE_FLAG}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_SIMULATOR ${DEVICE_FLAG}") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga ${DEVICE_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${DEVICE_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/speculated_iterations/src/speculated_iterations.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Features/speculated_iterations/src/speculated_iterations.cpp index ccd896e515..623297055a 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/speculated_iterations/src/speculated_iterations.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/speculated_iterations/src/speculated_iterations.cpp @@ -34,21 +34,30 @@ using namespace sycl; // This FPGA best practice reduces name mangling in the optimization reports. template class KernelCompute; -template +template void ComplexExit(float bound, int &res) { -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector selector; -#else - ext::intel::fpga_selector selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif + double kernel_time_ms = 0.0; try { // create the device queue with profiling enabled auto prop_list = property_list{property::queue::enable_profiling()}; queue q(selector, fpga_tools::exception_handler, prop_list); + if constexpr (first_call){ + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + } + // The scalar inputs are passed to the kernel using the lambda capture, // but a SYCL buffer must be used to return a scalar from the kernel. buffer buffer_res(&res, 1); @@ -120,15 +129,15 @@ int main(int argc, char *argv[]) { // This reflects compute latency differences on different hardware // architectures, and is a low-level optimization. #if defined(A10) - ComplexExit<0>(bound, r0); + ComplexExit<0, true>(bound, r0); ComplexExit<10>(bound, r1); ComplexExit<27>(bound, r2); #elif defined(S10) - ComplexExit<0>(bound, r0); + ComplexExit<0, true>(bound, r0); ComplexExit<10>(bound, r1); ComplexExit<54>(bound, r2); #elif defined(Agilex) - ComplexExit<0>(bound, r0); + ComplexExit<0, true>(bound, r0); ComplexExit<10>(bound, r1); ComplexExit<50>(bound, r2); #else diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/stall_enable/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/stall_enable/src/CMakeLists.txt index b239a35b5e..d3ec031d23 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/stall_enable/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/stall_enable/src/CMakeLists.txt @@ -34,11 +34,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} ${HYPER_FLAG} -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${HYPER_FLAG} -Xssimulation -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} ${HYPER_FLAG} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} ${HYPER_FLAG} -fsycl -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${HYPER_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${HYPER_FLAG} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/stall_enable/src/stall_enable.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Features/stall_enable/src/stall_enable.cpp index 019d10af4e..5c225ba2b4 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/stall_enable/src/stall_enable.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/stall_enable/src/stall_enable.cpp @@ -49,12 +49,12 @@ static void Work(const ReadAccessor &vec_a, const ReadAccessor &vec_b, } void DoSomeWork(const WorkVec &vec_a, const WorkVec &vec_b, WorkVec &res) { -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector selector; -#else - ext::intel::fpga_selector selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif double kernel_time = 0.0; @@ -63,6 +63,12 @@ void DoSomeWork(const WorkVec &vec_a, const WorkVec &vec_b, WorkVec &res) { queue q(selector, fpga_tools::exception_handler, prop_list); + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + buffer buffer_in_a(vec_a); buffer buffer_in_b(vec_b); buffer buffer_out(res); diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fast_recompile/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fast_recompile/src/CMakeLists.txt index 2b17485521..98b8729f61 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fast_recompile/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fast_recompile/src/CMakeLists.txt @@ -29,7 +29,7 @@ set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall -Xssimulation -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fast_recompile/src/host.cpp b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fast_recompile/src/host.cpp index 1e63ac2ca3..f404d2cf24 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fast_recompile/src/host.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fast_recompile/src/host.cpp @@ -41,14 +41,12 @@ int main() { } // Select either the FPGA emulator, FPGA simulator or FPGA device -#if defined(FPGA_EMULATOR) - // the device selector - ext::intel::fpga_emulator_selector selector; -#elif defined(FPGA_SIMULATOR) - // the device simulator - ext::intel::fpga_simulator_selector selector; -#else - ext::intel::fpga_selector selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif try { @@ -57,6 +55,12 @@ int main() { // If the device is unavailable, a SYCL runtime exception is thrown. queue q(selector, fpga_tools::exception_handler); + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + // create the device buffers buffer device_a(vec_a); buffer device_b(vec_b); diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fpga_compile/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fpga_compile/src/CMakeLists.txt index 1da0751bc3..489eb79d84 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fpga_compile/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fpga_compile/src/CMakeLists.txt @@ -23,11 +23,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall -Xssimulation -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fpga_compile/src/fpga_compile.cpp b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fpga_compile/src/fpga_compile.cpp index 69b3eac86f..d36bc48454 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fpga_compile/src/fpga_compile.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/GettingStarted/fpga_compile/src/fpga_compile.cpp @@ -34,12 +34,12 @@ int main() { // - the FPGA emulator device (CPU emulation of the FPGA) // - the FPGA simulator // - the FPGA device (a real FPGA) -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector selector; -#else - ext::intel::fpga_selector selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif try { @@ -49,8 +49,11 @@ int main() { queue q(selector, fpga_tools::exception_handler); // Print out the device information. + auto device = q.get_device(); + std::cout << "Running on device: " - << q.get_device().get_info() << "\n"; + << device.get_info().c_str() + << std::endl; { // Create buffers to share data between host and device. diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Tools/dynamic_profiler/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Tools/dynamic_profiler/src/CMakeLists.txt index fb66c9ef8f..99eab3f2c8 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Tools/dynamic_profiler/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Tools/dynamic_profiler/src/CMakeLists.txt @@ -18,11 +18,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall -fsycl -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-Wall -fsycl -fintelfpga -DFPGA_SIMULATOR") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} -Xsprofile ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-Wall -fsycl -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} -Xsprofile ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Tools/dynamic_profiler/src/dynamic_profiler.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Tools/dynamic_profiler/src/dynamic_profiler.cpp index 4cf464438f..17b1dc6539 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Tools/dynamic_profiler/src/dynamic_profiler.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Tools/dynamic_profiler/src/dynamic_profiler.cpp @@ -188,19 +188,27 @@ bool ProcessOutput(buffer &input_buf, buffer &output_buf) { int main() { // Create queue, get platform and device -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector device_selector; + +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; std::cout << "\nThe Dynamic Profiler cannot be used in the emulator " "flow. Please compile to FPGA hardware or simulator flow " "to collect dynamic profiling data. \n\n"; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector device_selector; -#else - ext::intel::fpga_selector device_selector; #endif + try { - queue q(device_selector, fpga_tools::exception_handler); + queue q(selector, fpga_tools::exception_handler); + + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; std::vector producer_input(kSize, -1); std::vector consumer_output_before(kSize, -1); diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Tools/system_profiling/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Tools/system_profiling/src/CMakeLists.txt index 4b6fa1c277..14c2c78e13 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/Tools/system_profiling/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Tools/system_profiling/src/CMakeLists.txt @@ -18,11 +18,11 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall -fsycl -fintelfpga -DFPGA_EMULATOR") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall -DFPGA_EMULATOR") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-Wall -fsycl -fintelfpga -DFPGA_SIMULATOR") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} -Xsprofile ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-Wall -fsycl -fintelfpga") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Tools/system_profiling/src/double_buffering.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Tools/system_profiling/src/double_buffering.cpp index efee6f717c..235e33f593 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Tools/system_profiling/src/double_buffering.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Tools/system_profiling/src/double_buffering.cpp @@ -204,30 +204,34 @@ void ProcessInput(buffer &buf) { int main() { // Create queue, get platform and device -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector device_selector; - std::cout << "\nEmulator output does not demonstrate true hardware " - "performance. The design may need to run on actual hardware " - "to observe the performance benefit of the optimization " - "exemplified in this tutorial.\n\n"; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector device_selector; -#else - ext::intel::fpga_selector device_selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif +#ifndef FPGA_HARDWARE + std::cout << "\nEmulator and simulator outputs do not demonstrate " + "true hardware performance. The design may need to run " + "on actual hardware to observe the performance benefit " + "of the optimization exemplified in this tutorial.\n\n"; +#endif + + try { auto prop_list = property_list{property::queue::enable_profiling()}; - sycl::queue q(device_selector, fpga_tools::exception_handler, prop_list); + sycl::queue q(selector, fpga_tools::exception_handler, prop_list); platform platform = q.get_context().get_platform(); device device = q.get_device(); std::cout << "Platform name: " << platform.get_info().c_str() << "\n"; - std::cout << "Device name: " - << device.get_info().c_str() << "\n\n\n"; - + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; std::cout << "Executing kernel " << kTimes << " times in each round.\n\n"; // Create a vector to store the input/output SYCL buffers diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Tools/use_library/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Tools/use_library/src/CMakeLists.txt index 1fc6b64323..dc262a2f94 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Tools/use_library/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Tools/use_library/src/CMakeLists.txt @@ -38,7 +38,7 @@ set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_EMULATOR ${WIN_FLAG}") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -DFPGA_SIMULATOR ${WIN_FLAG}") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga ${WIN_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Tools/use_library/src/use_library.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Tools/use_library/src/use_library.cpp index fde6239935..4d1fc95749 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Tools/use_library/src/use_library.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Tools/use_library/src/use_library.cpp @@ -21,16 +21,22 @@ int main() { unsigned result = 0; // Select the FPGA emulator (CPU), FPGA simulator, or FPGA device -#if defined(FPGA_EMULATOR) - sycl::ext::intel::fpga_emulator_selector device_selector; -#elif defined(FPGA_SIMULATOR) - sycl::ext::intel::fpga_simulator_selector device_selector; -#else - sycl::ext::intel::fpga_selector device_selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif try { - sycl::queue q(device_selector, fpga_tools::exception_handler); + sycl::queue q(selector, fpga_tools::exception_handler); + + auto device = q.get_device(); + + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; // The scalar inputs are passed to the kernel using the lambda capture, // but a SYCL buffer must be used to return a scalar from the kernel. From b811f0377a42b7220e1096ea4ec4970f6d915a44 Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Wed, 14 Dec 2022 05:25:13 -0800 Subject: [PATCH 23/38] ac_fixed readme update Signed-off-by: Yohann Uguen --- .../Tutorials/Features/ac_fixed/README.md | 74 ++++++++----------- 1 file changed, 30 insertions(+), 44 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_fixed/README.md b/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_fixed/README.md index 4f437d9bc3..d53e416e21 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_fixed/README.md +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_fixed/README.md @@ -19,6 +19,29 @@ This FPGA tutorial demonstrates how to use the Algorithmic C (AC) data type `ac_ > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +## Prerequisites + +This sample is part of the FPGA code samples. +It is categorized as a Tier 2 sample: Explore the Fundamentals. + +```mermaid +flowchart LR + tier1("Tier 1: Get Started") + tier2("Tier 2: Explore the Fundamentals") + tier3("Tier 3: Explore the Advanced Techniques") + tier4("Tier 4: Explore the Reference Designs") + + tier1 --> tier2 --> tier3 --> tier4 + + style tier1 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff + style tier2 fill:#f96,stroke:#333,stroke-width:1px,color:#fff + style tier3 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff + style tier4 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff +``` + +Find more information about how to navigate this part of the code samples in the [FPGA top-level README.md](/DirectProgramming/DPC++FPGA/README.md). +You can also find more information about [troubleshooting build errors](/DirectProgramming/DPC++FPGA/README.md#troubleshooting), [running the sample on the Intel® DevCloud](/DirectProgramming/DPC++FPGA/README.md#build-and-run-the-samples-on-intel-devcloud-optional), [using Visual Studio Code with the code samples](/DirectProgramming/DPC++FPGA/README.md#use-visual-studio-code-vs-code-optional), [links to selected documentation](/DirectProgramming/DPC++FPGA/README.md#documentation), etc. + ## Purpose This FPGA tutorial shows you how to use the `ac_fixed` type to perform fixed-point arithmetic and includes some simple examples. @@ -111,12 +134,6 @@ When you use the `ac_fixed` library, keep the following points in mind: Due to the differences in the internal math implementations, the results from `ac_fixed` math functions in emulation and FPGA hardware might not always be bit-accurate. This tutorial shows how to build and run the sample for emulation and FPGA hardware so you can observe the difference. -### Additional Documentation - -- [Explore SYCL* Through Intel® FPGA Code Samples](https://software.intel.com/content/www/us/en/develop/articles/explore-dpcpp-through-intel-fpga-code-samples.html) helps you to navigate the samples and build your knowledge of FPGAs and SYCL. -- [FPGA Optimization Guide for Intel® oneAPI Toolkits](https://software.intel.com/content/www/us/en/develop/documentation/oneapi-fpga-optimization-guide) helps you understand how to target FPGAs using SYCL and Intel® oneAPI Toolkits. -- [Intel® oneAPI Programming Guide](https://software.intel.com/en-us/oneapi-programming-guide) helps you understand target-independent, SYCL-compliant programming using Intel® oneAPI Toolkits. - ## Key Concepts - Constructing an `ac_fixed` from a `float` or `double` value is much more area intensive than constructing one from another `ac_fixed`. @@ -126,46 +143,20 @@ When you use the `ac_fixed` library, keep the following points in mind: ## Building the `ac_fixed` Tutorial -> **Note**: If you have not already done so, set up your CLI -> environment by sourcing the `setvars` script located in -> the root of your oneAPI installation. +> **Note**: When working with the command-line interface (CLI), you should configure the oneAPI toolkits using environment variables. +> Set up your CLI environment by sourcing the `setvars` script located in the root of your oneAPI installation every time you open a new terminal window. +> This practice ensures that your compiler, libraries, and tools are ready for development. > > Linux*: -> > - For system wide installations: `. /opt/intel/oneapi/setvars.sh` -> - For private installations: `. ~/intel/oneapi/setvars.sh` +> - For private installations: ` . ~/intel/oneapi/setvars.sh` +> - For non-POSIX shells, like csh, use the following command: `bash -c 'source /setvars.sh ; exec csh'` > > Windows*: -> > - `C:\Program Files(x86)\Intel\oneAPI\setvars.bat` +> - Windows PowerShell*, use the following command: `cmd.exe "/K" '"C:\Program Files (x86)\Intel\oneAPI\setvars.bat" && powershell'` > ->For more information on environment variables, see **Use the setvars Script** for [Linux or macOS](https://www.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/oneapi-development-environment-setup/use-the-setvars-script-with-linux-or-macos.html), or [Windows](https://www.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/oneapi-development-environment-setup/use-the-setvars-script-with-windows.html). - -### Running Samples in Intel® DevCloud - -If you are running a sample in the Intel® DevCloud, remember that you must specify the type of compute node and whether to run in batch or interactive mode: - -- Compiles to FPGA are supported only on `fpga_compile` nodes. -- Executing programs on FPGA hardware is supported only on `fpga_runtime` nodes of the appropriate type, such as `fpga_runtime:arria10` or `fpga_runtime:stratix10`. - -On the login nodes, you cannot compile or execute programs on FPGA hardware. For more information, see the Intel® oneAPI Base Toolkit Get Started Guide ([https://devcloud.intel.com/oneapi/documentation/base-toolkit/](https://devcloud.intel.com/oneapi/documentation/base-toolkit/)). - -When compiling for FPGA hardware, increase the job timeout to 12h. - -### Using Visual Studio Code* (Optional) - -You can use Visual Studio Code (VS Code) extensions to set your environment, create launch configurations, -and browse and download samples. - -The basic steps to build and run a sample using VS Code include: - -- Download a sample using the extension **Code Sample Browser for Intel® oneAPI Toolkits**. -- Configure the oneAPI environment with the extension **Environment Configurator for Intel® oneAPI Toolkits**. -- Open a Terminal in VS Code (**Terminal>New Terminal**). -- Run the sample in the VS Code terminal using the instructions below. - -To learn more about the extensions and how to configure the oneAPI environment, see the -[Using Visual Studio Code with Intel® oneAPI Toolkits User Guide](https://software.intel.com/content/www/us/en/develop/documentation/using-vs-code-with-intel-oneapi/top.html). +> For more information on configuring environment variables, see [Use the setvars Script with Linux* or macOS*](https://www.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/oneapi-development-environment-setup/use-the-setvars-script-with-linux-or-macos.html) or [Use the setvars Script with Windows*](https://www.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/oneapi-development-environment-setup/use-the-setvars-script-with-windows.html). ### On a Linux* System @@ -279,11 +270,6 @@ To learn more about the extensions and how to configure the oneAPI environment, > **Note**: If you encounter any issues with long paths when compiling under Windows*, you might have to create your `build` directory in a shorter path, for example `c:\samples\build`. You can then run `cmake` from that directory, and provide `cmake` with the full path to your sample directory. -### In Third-Party Integrated Development Environments (IDEs) - -You can compile and run this tutorial in the Eclipse*IDE (in Linux*) and the Visual Studio*IDE (in Windows*). -For instructions, refer to [FPGA Workflows on Third-Party IDEs for Intel® oneAPI Toolkits](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-oneapi-dpcpp-fpga-workflow-on-ide.html). - ## Examining the Reports Locate the pair of `report.html` files in either: From e6acaf8273b88bac6046a7687c2bede68a998d28 Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Wed, 14 Dec 2022 05:55:18 -0800 Subject: [PATCH 24/38] simplify Features readmes Signed-off-by: Yohann Uguen --- .../Tutorials/Features/ac_fixed/README.md | 2 +- .../Tutorials/Features/ac_int/README.md | 79 ++++++--------- .../Tutorials/Features/dsp_control/README.md | 78 ++++++--------- .../Features/experimental/hostpipes/README.md | 96 ++++++++----------- .../experimental/latency_control/README.md | 88 +++++++---------- .../Tutorials/Features/fpga_reg/README.md | 88 +++++++---------- .../Features/kernel_args_restrict/README.md | 84 +++++++--------- .../Features/loop_coalesce/README.md | 79 ++++++--------- .../Tutorials/Features/loop_fusion/README.md | 81 +++++++--------- .../loop_initiation_interval/README.md | 76 ++++++--------- .../Tutorials/Features/loop_ivdep/README.md | 77 ++++++--------- .../Tutorials/Features/loop_unroll/README.md | 84 +++++++--------- .../Tutorials/Features/lsu_control/README.md | 81 +++++++--------- .../Features/max_interleaving/README.md | 83 +++++++--------- .../Tutorials/Features/mem_channel/README.md | 84 ++++++---------- .../Features/memory_attributes/README.md | 83 +++++++--------- .../Tutorials/Features/pipes/README.md | 81 +++++++--------- .../Tutorials/Features/printf/README.md | 82 +++++++--------- .../Features/private_copies/README.md | 84 +++++++--------- .../Features/read_only_cache/README.md | 91 +++++++----------- .../Features/scheduler_target_fmax/README.md | 89 +++++++---------- .../Features/speculated_iterations/README.md | 84 +++++++--------- .../Tutorials/Features/stall_enable/README.md | 78 ++++++--------- 23 files changed, 717 insertions(+), 1115 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_fixed/README.md b/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_fixed/README.md index d53e416e21..7e07ef9a1d 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_fixed/README.md +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_fixed/README.md @@ -22,7 +22,7 @@ This FPGA tutorial demonstrates how to use the Algorithmic C (AC) data type `ac_ ## Prerequisites This sample is part of the FPGA code samples. -It is categorized as a Tier 2 sample: Explore the Fundamentals. +It is categorized as a Tier 2 sample that demonstatres a compiler feature. ```mermaid flowchart LR diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_int/README.md b/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_int/README.md index b93299129e..5668a8bc09 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_int/README.md +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/ac_int/README.md @@ -19,6 +19,29 @@ This FPGA tutorial demonstrates how to use the Algorithmic C (AC) data type `ac_ > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +## Prerequisites + +This sample is part of the FPGA code samples. +It is categorized as a Tier 2 sample that demonstatres a compiler feature. + +```mermaid +flowchart LR + tier1("Tier 1: Get Started") + tier2("Tier 2: Explore the Fundamentals") + tier3("Tier 3: Explore the Advanced Techniques") + tier4("Tier 4: Explore the Reference Designs") + + tier1 --> tier2 --> tier3 --> tier4 + + style tier1 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff + style tier2 fill:#f96,stroke:#333,stroke-width:1px,color:#fff + style tier3 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff + style tier4 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff +``` + +Find more information about how to navigate this part of the code samples in the [FPGA top-level README.md](/DirectProgramming/DPC++FPGA/README.md). +You can also find more information about [troubleshooting build errors](/DirectProgramming/DPC++FPGA/README.md#troubleshooting), [running the sample on the Intel® DevCloud](/DirectProgramming/DPC++FPGA/README.md#build-and-run-the-samples-on-intel-devcloud-optional), [using Visual Studio Code with the code samples](/DirectProgramming/DPC++FPGA/README.md#use-visual-studio-code-vs-code-optional), [links to selected documentation](/DirectProgramming/DPC++FPGA/README.md#documentation), etc. + ## Purpose This FPGA tutorial shows how to use the `ac_int` data type with some simple examples. @@ -92,12 +115,6 @@ Kernel `ShiftOps` contains an `ac_int` left-shifter and an `ac_int` right-shifte Kernel `BitOps` demonstrates bit operations with bit select operator `[]` and bit slice operations `slc` and `set_slc`. -### Additional Documentation - -- [Explore SYCL* Through Intel® FPGA Code Samples](https://software.intel.com/content/www/us/en/develop/articles/explore-dpcpp-through-intel-fpga-code-samples.html) helps you to navigate the samples and build your knowledge of FPGAs and SYCL. -- [FPGA Optimization Guide for Intel® oneAPI Toolkits](https://software.intel.com/content/www/us/en/develop/documentation/oneapi-fpga-optimization-guide) helps you understand how to target FPGAs using SYCL and Intel® oneAPI Toolkits. -- [Intel® oneAPI Programming Guide](https://software.intel.com/en-us/oneapi-programming-guide) helps you understand target-independent, SYCL-compliant programming using Intel® oneAPI Toolkits. - ## Key Concepts - The `ac_int` data type can be used to generate hardware for only as many bits as are needed by your application. Native integer types must generate hardware for only 8, 16, 32, or 64 bits. @@ -106,41 +123,20 @@ Kernel `BitOps` demonstrates bit operations with bit select operator `[]` and bi ## Building the `ac_int` Tutorial -> **Note**: If you have not already done so, set up your CLI -> environment by sourcing the `setvars` script located in -> the root of your oneAPI installation. +> **Note**: When working with the command-line interface (CLI), you should configure the oneAPI toolkits using environment variables. +> Set up your CLI environment by sourcing the `setvars` script located in the root of your oneAPI installation every time you open a new terminal window. +> This practice ensures that your compiler, libraries, and tools are ready for development. > > Linux*: -> > - For system wide installations: `. /opt/intel/oneapi/setvars.sh` -> - For private installations: `. ~/intel/oneapi/setvars.sh` +> - For private installations: ` . ~/intel/oneapi/setvars.sh` +> - For non-POSIX shells, like csh, use the following command: `bash -c 'source /setvars.sh ; exec csh'` > > Windows*: -> > - `C:\Program Files(x86)\Intel\oneAPI\setvars.bat` +> - Windows PowerShell*, use the following command: `cmd.exe "/K" '"C:\Program Files (x86)\Intel\oneAPI\setvars.bat" && powershell'` > ->For more information on environment variables, see **Use the setvars Script** for [Linux or macOS](https://www.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/oneapi-development-environment-setup/use-the-setvars-script-with-linux-or-macos.html), or [Windows](https://www.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/oneapi-development-environment-setup/use-the-setvars-script-with-windows.html). - -### Running Samples in Intel® DevCloud - -If running a sample in the Intel® DevCloud, remember that you must specify the type of compute node and whether to run in batch or interactive mode. Compiles to FPGA are only supported on fpga_compile nodes. Executing programs on FPGA hardware is only supported on fpga_runtime nodes of the appropriate type, such as fpga_runtime:arria10 or fpga_runtime:stratix10. Neither compiling nor executing programs on FPGA hardware are supported on the login nodes. For more information, see the Intel® oneAPI Base Toolkit Get Started Guide ([https://devcloud.intel.com/oneapi/documentation/base-toolkit/](https://devcloud.intel.com/oneapi/documentation/base-toolkit/)). - -When compiling for FPGA hardware, it is recommended to increase the job timeout to 12h. - -### Using Visual Studio Code* (Optional) - -You can use Visual Studio Code (VS Code) extensions to set your environment, create launch configurations, -and browse and download samples. - -The basic steps to build and run a sample using VS Code include: - -- Download a sample using the extension **Code Sample Browser for Intel® oneAPI Toolkits**. -- Configure the oneAPI environment with the extension **Environment Configurator for Intel® oneAPI Toolkits**. -- Open a Terminal in VS Code (**Terminal>New Terminal**). -- Run the sample in the VS Code terminal using the instructions below. - -To learn more about the extensions and how to configure the oneAPI environment, see the -[Using Visual Studio Code with Intel® oneAPI Toolkits User Guide](https://software.intel.com/content/www/us/en/develop/documentation/using-vs-code-with-intel-oneapi/top.html). +> For more information on configuring environment variables, see [Use the setvars Script with Linux* or macOS*](https://www.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/oneapi-development-environment-setup/use-the-setvars-script-with-linux-or-macos.html) or [Use the setvars Script with Windows*](https://www.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/oneapi-development-environment-setup/use-the-setvars-script-with-windows.html). ### On a Linux* System @@ -261,21 +257,6 @@ directory in a shorter path, for example c:\samples\build. You can then run cmake from that directory, and provide cmake with the full path to your sample directory. -### Troubleshooting - -If an error occurs, you can get more details by running `make` with -the `VERBOSE=1` argument: -``make VERBOSE=1`` -For more comprehensive troubleshooting, use the Diagnostics Utility for -Intel® oneAPI Toolkits, which provides system checks to find missing -dependencies and permissions errors. -[Learn more](https://software.intel.com/content/www/us/en/develop/documentation/diagnostic-utility-user-guide/top.html). - -### In Third-Party Integrated Development Environments (IDEs) - -You can compile and run this tutorial in the Eclipse*IDE (in Linux*) and the Visual Studio*IDE (in Windows*). -For instructions, refer to the following link: [FPGA Workflows on Third-Party IDEs for Intel® oneAPI Toolkits](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-oneapi-dpcpp-fpga-workflow-on-ide.html) - ## Examining the Reports Locate `report.html` in the `ac_int_report.prj/reports/` directory. Open the report in any of Chrome*, Firefox*, Edge*, or Internet Explorer*. diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/dsp_control/README.md b/DirectProgramming/DPC++FPGA/Tutorials/Features/dsp_control/README.md index 12fd54ef1a..786e492212 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/dsp_control/README.md +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/dsp_control/README.md @@ -19,6 +19,29 @@ This FPGA tutorial demonstrates how to set the implementation preference for cer > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +## Prerequisites + +This sample is part of the FPGA code samples. +It is categorized as a Tier 3 sample that demonstatres a compiler feature. + +```mermaid +flowchart LR + tier1("Tier 1: Get Started") + tier2("Tier 2: Explore the Fundamentals") + tier3("Tier 3: Explore the Advanced Techniques") + tier4("Tier 4: Explore the Reference Designs") + + tier1 --> tier2 --> tier3 --> tier4 + + style tier1 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff + style tier2 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff + style tier3 fill:#f96,stroke:#333,stroke-width:1px,color:#fff + style tier4 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff +``` + +Find more information about how to navigate this part of the code samples in the [FPGA top-level README.md](/DirectProgramming/DPC++FPGA/README.md). +You can also find more information about [troubleshooting build errors](/DirectProgramming/DPC++FPGA/README.md#troubleshooting), [running the sample on the Intel® DevCloud](/DirectProgramming/DPC++FPGA/README.md#build-and-run-the-samples-on-intel-devcloud-optional), [using Visual Studio Code with the code samples](/DirectProgramming/DPC++FPGA/README.md#use-visual-studio-code-vs-code-optional), [links to selected documentation](/DirectProgramming/DPC++FPGA/README.md#documentation), etc. + ## Purpose This tutorial shows how to apply global and local controls to set the implementation preference between DSPs and soft-logic for certain math operations. The global control is applied using a command-line flag and affects applicable math operations in all kernels. The local control is applied as a library function and affects math operations in a block scope in a single kernel. Both global and local controls only affect math operations that support DSP control (see table below). @@ -64,12 +87,6 @@ The second template argument `Propagate::