From 1cee70e4d7dffc868c57b5b04d73a2a574168e12 Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Thu, 12 Jan 2023 02:33:34 -0800 Subject: [PATCH 01/22] set Agilex as default target in all cmakes Signed-off-by: Yohann Uguen --- .../ReferenceDesigns/anr/src/CMakeLists.txt | 35 +++++++++---- .../board_test/src/CMakeLists.txt | 13 +++-- .../cholesky/src/CMakeLists.txt | 51 ++++++++++--------- .../cholesky_inversion/src/CMakeLists.txt | 49 ++++++++++-------- .../ReferenceDesigns/crr/src/CMakeLists.txt | 29 ++++++++--- .../ReferenceDesigns/db/src/CMakeLists.txt | 46 ++++++++--------- .../decompress/src/CMakeLists.txt | 29 ++++++++--- .../ReferenceDesigns/gzip/src/CMakeLists.txt | 38 +++++++++++--- .../merge_sort/src/CMakeLists.txt | 9 ++-- .../mvdr_beamforming/src/CMakeLists.txt | 8 +-- .../ReferenceDesigns/qrd/src/CMakeLists.txt | 48 ++++++++++------- .../ReferenceDesigns/qri/src/CMakeLists.txt | 49 +++++++++++------- .../DesignPatterns/autorun/src/CMakeLists.txt | 8 +-- .../src/CMakeLists.txt | 18 +++++-- .../compute_units/src/CMakeLists.txt | 8 +-- .../double_buffering/src/CMakeLists.txt | 8 +-- .../explicit_data_movement/src/CMakeLists.txt | 9 ++-- .../io_streaming/src/CMakeLists.txt | 8 +-- .../src/CMakeLists.txt | 8 +-- .../n_way_buffering/src/CMakeLists.txt | 9 ++-- .../onchip_memory_cache/src/CMakeLists.txt | 8 +-- .../optimize_inner_loop/src/CMakeLists.txt | 9 ++-- .../shannonization/src/CMakeLists.txt | 27 +++++----- .../simple_host_streaming/src/CMakeLists.txt | 8 +-- .../triangular_loop/src/CMakeLists.txt | 8 +-- .../src/CMakeLists.txt | 18 +++++-- .../Features/ac_fixed/src/CMakeLists.txt | 8 +-- .../Features/ac_int/src/CMakeLists.txt | 8 +-- .../Features/dsp_control/src/CMakeLists.txt | 8 +-- .../experimental/hostpipes/src/CMakeLists.txt | 10 ++-- .../latency_control/src/CMakeLists.txt | 8 +-- .../Features/fpga_reg/src/CMakeLists.txt | 8 +-- .../kernel_args_restrict/src/CMakeLists.txt | 8 +-- .../Features/loop_coalesce/src/CMakeLists.txt | 8 +-- .../Features/loop_fusion/src/CMakeLists.txt | 8 +-- .../src/CMakeLists.txt | 23 +++++---- .../Features/loop_ivdep/src/CMakeLists.txt | 8 +-- .../Features/loop_unroll/src/CMakeLists.txt | 8 +-- .../Features/lsu_control/src/CMakeLists.txt | 8 +-- .../max_interleaving/src/CMakeLists.txt | 8 +-- .../Features/mem_channel/src/CMakeLists.txt | 8 +-- .../memory_attributes/src/CMakeLists.txt | 8 +-- .../Features/pipes/src/CMakeLists.txt | 8 +-- .../Features/printf/src/CMakeLists.txt | 8 +-- .../private_copies/src/CMakeLists.txt | 9 ++-- .../read_only_cache/src/CMakeLists.txt | 8 +-- .../scheduler_target_fmax/src/CMakeLists.txt | 8 +-- .../speculated_iterations/src/CMakeLists.txt | 23 +++++---- .../Features/stall_enable/src/CMakeLists.txt | 8 +-- .../fast_recompile/src/CMakeLists.txt | 8 +-- .../fpga_compile/src/CMakeLists.txt | 10 ++-- .../Tools/dynamic_profiler/src/CMakeLists.txt | 8 +-- .../Tools/system_profiling/src/CMakeLists.txt | 8 +-- .../Tools/use_library/src/CMakeLists.txt | 8 +-- 54 files changed, 472 insertions(+), 345 deletions(-) diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/CMakeLists.txt index d6ee2236af..1d89d5a2ac 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/CMakeLists.txt @@ -6,12 +6,27 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") + set(DEVICE_FLAG "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + string(TOLOWER ${FPGA_DEVICE} FPGA_DEVICE_NAME) + if(FPGA_DEVICE_NAME MATCHES ".*a10.*" OR FPGA_DEVICE_NAME MATCHES ".*arria10.*") + set(DEVICE_FLAG "A10") + elseif(FPGA_DEVICE_NAME MATCHES ".*s10.*" OR FPGA_DEVICE_NAME MATCHES ".*stratix10.*") + set(DEVICE_FLAG "S10") + elseif(FPGA_DEVICE_NAME MATCHES ".*agilex.*") + set(DEVICE_FLAG "Agilex") + endif() + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") +endif() + +if(NOT DEFINED DEVICE_FLAG) + message(FATAL_ERROR "An unrecognized or custom board was passed, but DEVICE_FLAG was not specified. \ + Please make sure you have set -DDEVICE_FLAG=A10, -DDEVICE_FLAG=S10 or \ + -DDEVICE_FLAG=Agilex.") endif() # These are Windows-specific flags: @@ -46,11 +61,11 @@ endif() # e.g. cmake .. -DSEED=7 if(NOT DEFINED SEED) # the default seed - if(FPGA_DEVICE MATCHES ".*a10.*") + if(DEVICE_FLAG MATCHES "A10") set(SEED 1) - elseif(FPGA_DEVICE MATCHES ".*s10.*") + elseif(DEVICE_FLAG MATCHES "S10") set(SEED 2) - elseif(FPGA_DEVICE MATCHES ".*agilex.*") + elseif(DEVICE_FLAG MATCHES "Agilex") set(SEED 3) else() set(SEED 4) @@ -79,11 +94,11 @@ if(PIXELS_PER_CYCLE) message(STATUS "PIXELS_PER_CYCLE explicitly set to ${PIXELS_PER_CYCLE}") else() # Default PIXELS_PER_CYCLE based on the board being used - if(FPGA_DEVICE MATCHES ".*a10.*") + if(DEVICE_FLAG MATCHES "A10") set(PIXELS_PER_CYCLE 2) - elseif(FPGA_DEVICE MATCHES ".*s10.*") + elseif(DEVICE_FLAG MATCHES "S10") set(PIXELS_PER_CYCLE 2) - elseif(FPGA_DEVICE MATCHES ".*agilex.*") + elseif(DEVICE_FLAG MATCHES "Agilex") set(PIXELS_PER_CYCLE 1) else() message(WARNING "Unknown board: setting PIXELS_PER_CYCLE to 1") diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/board_test/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/board_test/src/CMakeLists.txt index e11d99f43b..c5105263ba 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/board_test/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/board_test/src/CMakeLists.txt @@ -9,14 +9,19 @@ set(FPGA_EARLY_IMAGE ${TARGET_NAME}_report.a) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_s10sx_pac:pac_s10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Stratix(R) 10 SX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() +# Check if the target is a BSP +if(NOT FPGA_DEVICE MATCHES ".*:.*") + message(STATUS "This sample is made to target BSPs as this is a benchmarking sample.") +else() + # This is a Windows-specific flag that enables error handling in host code if(WIN32) set(PLATFORM_SPECIFIC_COMPILE_FLAGS "/EHsc /Qactypes /Wall") diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/CMakeLists.txt index e52aa0d3d3..ebe3719e76 100755 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/CMakeLists.txt @@ -7,42 +7,44 @@ set(FPGA_EARLY_IMAGE ${TARGET_NAME}_report.a) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") + set(DEVICE_FLAG "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + string(TOLOWER ${FPGA_DEVICE} FPGA_DEVICE_NAME) + if(FPGA_DEVICE_NAME MATCHES ".*a10.*" OR FPGA_DEVICE_NAME MATCHES ".*arria10.*") + set(DEVICE_FLAG "A10") + elseif(FPGA_DEVICE_NAME MATCHES ".*s10.*" OR FPGA_DEVICE_NAME MATCHES ".*stratix10.*") + set(DEVICE_FLAG "S10") + elseif(FPGA_DEVICE_NAME MATCHES ".*agilex.*") + set(DEVICE_FLAG "Agilex") + endif() + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() -# This is a Windows-specific flag that enables error handling in host code -if(WIN32) - set(PLATFORM_SPECIFIC_COMPILE_FLAGS "/EHsc /Qactypes /Wall /fp:precise") - set(PLATFORM_SPECIFIC_LINK_FLAGS "/Qactypes /fp:precise") -else() - set(PLATFORM_SPECIFIC_COMPILE_FLAGS "-qactypes -Wall -fno-finite-math-only -fp-model=precise") - set(PLATFORM_SPECIFIC_LINK_FLAGS "-fp-model=precise") +if(NOT DEFINED DEVICE_FLAG) + message(FATAL_ERROR "An unrecognized or custom board was passed, but DEVICE_FLAG was not specified. \ + Please make sure you have set -DDEVICE_FLAG=A10, -DDEVICE_FLAG=S10 or \ + -DDEVICE_FLAG=Agilex.") endif() - -# A10 parameters -set(MATRIX_DIMENSION 32) -set(COMPLEX 0) -set(FIXED_ITERATIONS 39) -set(CLOCK_TARGET 360MHz) -set(SEED "-Xsseed=29") -# Overwrite design parameters according to the selected board -if(FPGA_DEVICE MATCHES ".*a10.*") +if(DEVICE_FLAG MATCHES "A10") # A10 parameters - # Nothing to do -elseif(FPGA_DEVICE MATCHES ".*s10.*") + set(MATRIX_DIMENSION 32) + set(COMPLEX 0) + set(FIXED_ITERATIONS 39) + set(CLOCK_TARGET 360MHz) + set(SEED "-Xsseed=29") +elseif(DEVICE_FLAG MATCHES "S10") # S10 parameters set(MATRIX_DIMENSION 32) set(COMPLEX 0) set(FIXED_ITERATIONS 44) set(CLOCK_TARGET 450MHz) set(SEED "-Xsseed=5") -elseif(FPGA_DEVICE MATCHES ".*agilex.*") +elseif(DEVICE_FLAG MATCHES "Agilex") # Agilex™ parameters set(MATRIX_DIMENSION 32) set(FIXED_ITERATIONS 45) @@ -50,8 +52,7 @@ elseif(FPGA_DEVICE MATCHES ".*agilex.*") set(CLOCK_TARGET 520MHz) set(SEED "-Xsseed=5") else() - message(STATUS "Unknown board ${FPGA_DEVICE}!") - message(STATUS "Using Arria 10 defaults.") + message(FATAL_ERROR "Unreachable") endif() if(IGNORE_DEFAULT_SEED) diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/CMakeLists.txt index 1b464c424e..9aa382dc12 100755 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/CMakeLists.txt @@ -7,12 +7,27 @@ set(FPGA_EARLY_IMAGE ${TARGET_NAME}_report.a) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") + set(DEVICE_FLAG "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + string(TOLOWER ${FPGA_DEVICE} FPGA_DEVICE_NAME) + if(FPGA_DEVICE_NAME MATCHES ".*a10.*" OR FPGA_DEVICE_NAME MATCHES ".*arria10.*") + set(DEVICE_FLAG "A10") + elseif(FPGA_DEVICE_NAME MATCHES ".*s10.*" OR FPGA_DEVICE_NAME MATCHES ".*stratix10.*") + set(DEVICE_FLAG "S10") + elseif(FPGA_DEVICE_NAME MATCHES ".*agilex.*") + set(DEVICE_FLAG "Agilex") + endif() + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") +endif() + +if(NOT DEFINED DEVICE_FLAG) + message(FATAL_ERROR "An unrecognized or custom board was passed, but DEVICE_FLAG was not specified. \ + Please make sure you have set -DDEVICE_FLAG=A10, -DDEVICE_FLAG=S10 or \ + -DDEVICE_FLAG=Agilex.") endif() # This is a Windows-specific flag that enables error handling in host code @@ -24,20 +39,15 @@ else() set(PLATFORM_SPECIFIC_LINK_FLAGS "-fp-model=precise ") endif() - -# A10 parameters -set(MATRIX_DIMENSION 32) -set(COMPLEX 0) -set(FIXED_ITERATIONS_DECOMPOSITION 39) -set(FIXED_ITERATIONS_INVERSION 34) -set(CLOCK_TARGET 360MHz) -set(SEED "-Xsseed=29") - -# Set design parameters according to the selected board -if(FPGA_DEVICE MATCHES ".*a10.*") +if(DEVICE_FLAG MATCHES "A10") # A10 parameters - # Nothing to do -elseif(FPGA_DEVICE MATCHES ".*s10.*") + set(MATRIX_DIMENSION 32) + set(COMPLEX 0) + set(FIXED_ITERATIONS_DECOMPOSITION 39) + set(FIXED_ITERATIONS_INVERSION 34) + set(CLOCK_TARGET 360MHz) + set(SEED "-Xsseed=29") +elseif(DEVICE_FLAG MATCHES "S10") # S10 parameters set(MATRIX_DIMENSION 32) set(COMPLEX 0) @@ -45,7 +55,7 @@ elseif(FPGA_DEVICE MATCHES ".*s10.*") set(FIXED_ITERATIONS_INVERSION 44) set(CLOCK_TARGET 450MHz) set(SEED "-Xsseed=5") -elseif(FPGA_DEVICE MATCHES ".*agilex.*") +elseif(DEVICE_FLAG MATCHES "Agilex") # Agilex™ parameters set(MATRIX_DIMENSION 32) set(FIXED_ITERATIONS_DECOMPOSITION 45) @@ -54,8 +64,7 @@ elseif(FPGA_DEVICE MATCHES ".*agilex.*") set(CLOCK_TARGET 520MHz) set(SEED "-Xsseed=5") else() - message(STATUS "Unknown board ${FPGA_DEVICE}!") - message(STATUS "Using Arria 10 defaults.") + message(FATAL_ERROR "Unreachable") endif() if(IGNORE_DEFAULT_SEED) diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/crr/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/crr/src/CMakeLists.txt index 448a5a0769..9e1667f88c 100755 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/crr/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/crr/src/CMakeLists.txt @@ -6,12 +6,27 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") + set(DEVICE_FLAG "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + string(TOLOWER ${FPGA_DEVICE} FPGA_DEVICE_NAME) + if(FPGA_DEVICE_NAME MATCHES ".*a10.*" OR FPGA_DEVICE_NAME MATCHES ".*arria10.*") + set(DEVICE_FLAG "A10") + elseif(FPGA_DEVICE_NAME MATCHES ".*s10.*" OR FPGA_DEVICE_NAME MATCHES ".*stratix10.*") + set(DEVICE_FLAG "S10") + elseif(FPGA_DEVICE_NAME MATCHES ".*agilex.*") + set(DEVICE_FLAG "Agilex") + endif() + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") +endif() + +if(NOT DEFINED DEVICE_FLAG) + message(FATAL_ERROR "An unrecognized or custom board was passed, but DEVICE_FLAG was not specified. \ + Please make sure you have set -DDEVICE_FLAG=A10, -DDEVICE_FLAG=S10 or \ + -DDEVICE_FLAG=Agilex.") endif() # This is a Windows-specific flag that enables error handling in host code @@ -20,19 +35,19 @@ if(WIN32) endif() # Set design parameters according to the selected board -if(FPGA_DEVICE MATCHES ".*a10.*") +if(DEVICE_FLAG MATCHES "A10") # A10 parameters set(OUTER_UNROLL 1) set(INNER_UNROLL 64) set(OUTER_UNROLL_POW2 1) set(SEED "-Xsseed=1") -elseif(FPGA_DEVICE MATCHES ".*s10.*") +elseif(DEVICE_FLAG MATCHES "S10") # S10 parameters set(OUTER_UNROLL 2) set(INNER_UNROLL 64) set(OUTER_UNROLL_POW2 2) set(SEED "-Xsseed=2") -elseif(FPGA_DEVICE MATCHES ".*agilex.*") +elseif(DEVICE_FLAG MATCHES "Agilex") # Agilex™ set(OUTER_UNROLL 2) set(INNER_UNROLL 64) diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/CMakeLists.txt index 339f3e0a5d..63ab8c7ed5 100755 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/CMakeLists.txt @@ -12,29 +12,29 @@ else() message(STATUS "\tQUERY=${QUERY}") endif() -# select default board based on query -if(${QUERY} EQUAL 1) - set(DEFAULT_BOARD "intel_a10gx_pac:pac_a10") - set(DEFAULT_BOARD_STR "Intel Arria(R) 10 GX") -elseif(${QUERY} EQUAL 9) - set(DEFAULT_BOARD "intel_s10sx_pac:pac_s10") - set(DEFAULT_BOARD_STR "Intel Stratix(R) 10 SX") -elseif(${QUERY} EQUAL 11) - set(DEFAULT_BOARD "intel_s10sx_pac:pac_s10") - set(DEFAULT_BOARD_STR "Intel Stratix(R) 10 SX") -elseif(${QUERY} EQUAL 12) - set(DEFAULT_BOARD "intel_a10gx_pac:pac_a10") - set(DEFAULT_BOARD_STR "Intel Arria(R) 10 GX") -endif() - # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE ${DEFAULT_BOARD}) + set(FPGA_DEVICE "Agilex") + set(DEVICE_FLAG "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with ${DEFAULT_BOARD_STR} FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + string(TOLOWER ${FPGA_DEVICE} FPGA_DEVICE_NAME) + if(FPGA_DEVICE_NAME MATCHES ".*a10.*" OR FPGA_DEVICE_NAME MATCHES ".*arria10.*") + set(DEVICE_FLAG "A10") + elseif(FPGA_DEVICE_NAME MATCHES ".*s10.*" OR FPGA_DEVICE_NAME MATCHES ".*stratix10.*") + set(DEVICE_FLAG "S10") + elseif(FPGA_DEVICE_NAME MATCHES ".*agilex.*") + set(DEVICE_FLAG "Agilex") + endif() + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") +endif() + +if(NOT DEFINED DEVICE_FLAG) + message(FATAL_ERROR "An unrecognized or custom board was passed, but DEVICE_FLAG was not specified. \ + Please make sure you have set -DDEVICE_FLAG=A10, -DDEVICE_FLAG=S10 or \ + -DDEVICE_FLAG=Agilex.") endif() # This is a Windows-specific flag that enables error handling in host code @@ -53,7 +53,7 @@ endif() # Pick the default seed if the user did not specify one to CMake. # We do a seed sweep to find a good seed by default if(NOT DEFINED SEED) - if(${FPGA_DEVICE} MATCHES ".*a10.*") + if(DEVICE_FLAG MATCHES "A10") if(${QUERY} EQUAL 1) set(SEED "-Xsseed=2") elseif(${QUERY} EQUAL 9) @@ -63,7 +63,7 @@ if(NOT DEFINED SEED) elseif(${QUERY} EQUAL 12) set(SEED "-Xsseed=2") endif() - elseif(${FPGA_DEVICE} MATCHES ".*s10.*") + elseif(DEVICE_FLAG MATCHES "S10") if(${QUERY} EQUAL 1) set(SEED "-Xsseed=3") elseif(${QUERY} EQUAL 9) @@ -73,7 +73,7 @@ if(NOT DEFINED SEED) elseif(${QUERY} EQUAL 12) set(SEED "-Xsseed=2") endif() - elseif(${FPGA_DEVICE} MATCHES ".*agilex.*") + elseif(DEVICE_FLAG MATCHES "Agilex") if(${QUERY} EQUAL 1) set(SEED "-Xsseed=2") elseif(${QUERY} EQUAL 9) @@ -93,7 +93,7 @@ if(IGNORE_DEFAULT_SEED) endif() # Error out if trying to run Q9 or Q11 on Arria 10 -if (${FPGA_DEVICE} MATCHES ".*a10.*") +if (DEVICE_FLAG MATCHES "A10") if(${QUERY} EQUAL 9 OR ${QUERY} EQUAL 11) message(FATAL_ERROR "Queries 9 and 11 are not supported on Arria 10 devices") endif() diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/CMakeLists.txt index d01e36b8cd..d85aae4282 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/CMakeLists.txt @@ -6,12 +6,27 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") + set(DEVICE_FLAG "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + string(TOLOWER ${FPGA_DEVICE} FPGA_DEVICE_NAME) + if(FPGA_DEVICE_NAME MATCHES ".*a10.*" OR FPGA_DEVICE_NAME MATCHES ".*arria10.*") + set(DEVICE_FLAG "A10") + elseif(FPGA_DEVICE_NAME MATCHES ".*s10.*" OR FPGA_DEVICE_NAME MATCHES ".*stratix10.*") + set(DEVICE_FLAG "S10") + elseif(FPGA_DEVICE_NAME MATCHES ".*agilex.*") + set(DEVICE_FLAG "Agilex") + endif() + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") +endif() + +if(NOT DEFINED DEVICE_FLAG) + message(FATAL_ERROR "An unrecognized or custom board was passed, but DEVICE_FLAG was not specified. \ + Please make sure you have set -DDEVICE_FLAG=A10, -DDEVICE_FLAG=S10 or \ + -DDEVICE_FLAG=Agilex.") endif() # Select between SNAPPY and GZIP decompression @@ -68,11 +83,11 @@ if(IGNORE_DEFAULT_SEED) else() if (NOT DEFINED SEED) # the default seed for each FPGA type - if(FPGA_DEVICE MATCHES ".*a10.*") + if(DEVICE_FLAG MATCHES "A10") set(SEED 1) - elseif(FPGA_DEVICE MATCHES ".*s10.*") + elseif(DEVICE_FLAG MATCHES "S10") set(SEED 2) - elseif(FPGA_DEVICE MATCHES ".*agilex.*") + elseif(DEVICE_FLAG MATCHES "Agilex") set(SEED 3) else() message(STATUS "SEED not defined and no known seed for this board -- defaulting to SEED = 1") diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/CMakeLists.txt index 56b9aabe00..3f1809e33e 100755 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/CMakeLists.txt @@ -21,12 +21,27 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") + set(DEVICE_FLAG "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + string(TOLOWER ${FPGA_DEVICE} FPGA_DEVICE_NAME) + if(FPGA_DEVICE_NAME MATCHES ".*a10.*" OR FPGA_DEVICE_NAME MATCHES ".*arria10.*") + set(DEVICE_FLAG "A10") + elseif(FPGA_DEVICE_NAME MATCHES ".*s10.*" OR FPGA_DEVICE_NAME MATCHES ".*stratix10.*") + set(DEVICE_FLAG "S10") + elseif(FPGA_DEVICE_NAME MATCHES ".*agilex.*") + set(DEVICE_FLAG "Agilex") + endif() + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") +endif() + +if(NOT DEFINED DEVICE_FLAG) + message(FATAL_ERROR "An unrecognized or custom board was passed, but DEVICE_FLAG was not specified. \ + Please make sure you have set -DDEVICE_FLAG=A10, -DDEVICE_FLAG=S10 or \ + -DDEVICE_FLAG=Agilex.") endif() # This is a Windows-specific flag that enables error handling in host code @@ -35,7 +50,7 @@ if(WIN32) endif() # Set design parameters according to the selected chip -if(FPGA_DEVICE MATCHES ".*a10.*") +if(DEVICE_FLAG MATCHES "A10") # A10 parameters set(NUM_ENGINES 1) if(DEFINED LOW_LATENCY) @@ -45,7 +60,7 @@ if(FPGA_DEVICE MATCHES ".*a10.*") set(SEED "-Xsseed=4") set(NUM_REORDER "") endif() -elseif(FPGA_DEVICE MATCHES ".*s10.*") +elseif(DEVICE_FLAG MATCHES "S10") # S10 parameters set(NUM_ENGINES 2) if(DEFINED LOW_LATENCY) @@ -57,7 +72,7 @@ elseif(FPGA_DEVICE MATCHES ".*s10.*") # For Low Latency variant this is not necessary since only one channel of global memory is used (host memory). set(NUM_REORDER "-Xsnum-reorder=6") endif() -elseif(FPGA_DEVICE MATCHES ".*agilex.*") +elseif(DEVICE_FLAG MATCHES "Agilex") # Agilex™ set(NUM_ENGINES 2) if(DEFINED LOW_LATENCY) @@ -79,11 +94,18 @@ if(IGNORE_DEFAULT_SEED) set(SEED "") endif() +# Check if the target is a BSP +if(FPGA_DEVICE MATCHES ".*:.*") + set(IS_BSP "1") + message(STATUS "Targetting a BSP.") +else() + set(IS_BSP "0") +endif() # Presence of USM host allocations (and whether to turn on enable the low-latency target) is detected automatically by # looking at the name of the BSP, or manually by the user when running CMake. # E.g., cmake .. -DUSM_HOST_ALLOCATIONS_ENABLED=1 -if(LOW_LATENCY AND NOT FPGA_DEVICE MATCHES ".usm.*" AND (NOT DEFINED USM_HOST_ALLOCATIONS_ENABLED OR USM_HOST_ALLOCATIONS_ENABLED STREQUAL "0")) +if((IS_BSP STREQUAL "1") AND LOW_LATENCY AND NOT FPGA_DEVICE MATCHES ".usm.*" AND (NOT DEFINED USM_HOST_ALLOCATIONS_ENABLED OR USM_HOST_ALLOCATIONS_ENABLED STREQUAL "0")) # Low latency design requires USM, so error out message(FATAL_ERROR "Error: The Low Latency variant of the design requires USM host allocations") endif() diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/CMakeLists.txt index 917d1e16c9..db90e5c60e 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/CMakeLists.txt @@ -6,14 +6,15 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() + # This is a Windows-specific flag that enables error handling in host code if(WIN32) set(WIN_FLAG "/EHsc") diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/CMakeLists.txt index 514fd4e447..8e7846aff2 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # check if the BSP has USM host allocations diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/CMakeLists.txt index b909ab5663..e110721e79 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/CMakeLists.txt @@ -7,12 +7,27 @@ set(FPGA_EARLY_IMAGE ${TARGET_NAME}_report.a) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") + set(DEVICE_FLAG "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + string(TOLOWER ${FPGA_DEVICE} FPGA_DEVICE_NAME) + if(FPGA_DEVICE_NAME MATCHES ".*a10.*" OR FPGA_DEVICE_NAME MATCHES ".*arria10.*") + set(DEVICE_FLAG "A10") + elseif(FPGA_DEVICE_NAME MATCHES ".*s10.*" OR FPGA_DEVICE_NAME MATCHES ".*stratix10.*") + set(DEVICE_FLAG "S10") + elseif(FPGA_DEVICE_NAME MATCHES ".*agilex.*") + set(DEVICE_FLAG "Agilex") + endif() + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") +endif() + +if(NOT DEFINED DEVICE_FLAG) + message(FATAL_ERROR "An unrecognized or custom board was passed, but DEVICE_FLAG was not specified. \ + Please make sure you have set -DDEVICE_FLAG=A10, -DDEVICE_FLAG=S10 or \ + -DDEVICE_FLAG=Agilex.") endif() # This is a Windows-specific flag that enables error handling in host code @@ -31,18 +46,15 @@ else() endif() -# A10 parameters -set(ROWS_COMPONENT 128) -set(COLS_COMPONENT 128) -set(COMPLEX 1) -set(FIXED_ITERATIONS 64) -set(CLOCK_TARGET 360MHz) -set(SEED "-Xsseed=7") -# Overwrite design parameters according to the selected board -if(FPGA_DEVICE MATCHES ".*a10.*") +if(DEVICE_FLAG MATCHES "A10") # A10 parameters - # Nothing to do -elseif(FPGA_DEVICE MATCHES ".*s10.*") + set(ROWS_COMPONENT 128) + set(COLS_COMPONENT 128) + set(COMPLEX 1) + set(FIXED_ITERATIONS 64) + set(CLOCK_TARGET 360MHz) + set(SEED "-Xsseed=7") +elseif(FPGA_DEVICE MATCHES "S10") # S10 parameters set(ROWS_COMPONENT 256) set(COLS_COMPONENT 256) @@ -50,7 +62,7 @@ elseif(FPGA_DEVICE MATCHES ".*s10.*") set(FIXED_ITERATIONS 110) set(CLOCK_TARGET 480MHz) set(SEED "-Xsseed=9") -elseif(FPGA_DEVICE MATCHES ".*agilex.*") +elseif(FPGA_DEVICE MATCHES "Agilex") # Agilex™ parameters set(ROWS_COMPONENT 256) set(COLS_COMPONENT 256) @@ -59,10 +71,10 @@ elseif(FPGA_DEVICE MATCHES ".*agilex.*") set(CLOCK_TARGET 600MHz) set(SEED "-Xsseed=5") else() - message(STATUS "Unknown board ${FPGA_DEVICE}!") - message(STATUS "Using Arria 10 defaults.") + message(FATAL_ERROR "Unreachable") endif() + if(IGNORE_DEFAULT_SEED) set(SEED "") endif() diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/CMakeLists.txt index 0e508ebf5c..ebbbe1b14d 100755 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/CMakeLists.txt @@ -7,12 +7,27 @@ set(FPGA_EARLY_IMAGE ${TARGET_NAME}_report.a) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") + set(DEVICE_FLAG "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + string(TOLOWER ${FPGA_DEVICE} FPGA_DEVICE_NAME) + if(FPGA_DEVICE_NAME MATCHES ".*a10.*" OR FPGA_DEVICE_NAME MATCHES ".*arria10.*") + set(DEVICE_FLAG "A10") + elseif(FPGA_DEVICE_NAME MATCHES ".*s10.*" OR FPGA_DEVICE_NAME MATCHES ".*stratix10.*") + set(DEVICE_FLAG "S10") + elseif(FPGA_DEVICE_NAME MATCHES ".*agilex.*") + set(DEVICE_FLAG "Agilex") + endif() + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") +endif() + +if(NOT DEFINED DEVICE_FLAG) + message(FATAL_ERROR "An unrecognized or custom board was passed, but DEVICE_FLAG was not specified. \ + Please make sure you have set -DDEVICE_FLAG=A10, -DDEVICE_FLAG=S10 or \ + -DDEVICE_FLAG=Agilex.") endif() # This is a Windows-specific flag that enables error handling in host code @@ -24,19 +39,16 @@ else() set(PLATFORM_SPECIFIC_LINK_FLAGS "-fp-model=precise") endif() -# A10 parameters -set(ROWS_COMPONENT 32) -set(COLS_COMPONENT 32) -set(COMPLEX 0) -set(FIXED_ITERATIONS_QRD 50) -set(FIXED_ITERATIONS_QRI 36) -set(CLOCK_TARGET 360MHz) -set(SEED "-Xsseed=10") -# Overwrite design parameters according to the selected board -if(FPGA_DEVICE MATCHES ".*a10.*") +if(DEVICE_FLAG MATCHES "A10") # A10 parameters - # Nothing to do -elseif(FPGA_DEVICE MATCHES ".*s10.*") + set(ROWS_COMPONENT 32) + set(COLS_COMPONENT 32) + set(COMPLEX 0) + set(FIXED_ITERATIONS_QRD 50) + set(FIXED_ITERATIONS_QRI 36) + set(CLOCK_TARGET 360MHz) + set(SEED "-Xsseed=10") +elseif(FPGA_DEVICE MATCHES "S10") # S10 parameters set(ROWS_COMPONENT 32) set(COLS_COMPONENT 32) @@ -45,7 +57,7 @@ elseif(FPGA_DEVICE MATCHES ".*s10.*") set(FIXED_ITERATIONS_QRI 38) set(CLOCK_TARGET 450MHz) set(SEED "-Xsseed=5") -elseif(FPGA_DEVICE MATCHES ".*agilex.*") +elseif(FPGA_DEVICE MATCHES "Agilex") # Agilex™ parameters set(ROWS_COMPONENT 32) set(COLS_COMPONENT 32) @@ -55,8 +67,7 @@ elseif(FPGA_DEVICE MATCHES ".*agilex.*") set(CLOCK_TARGET 520MHz) set(SEED "-Xsseed=5") else() - message(STATUS "Unknown board ${FPGA_DEVICE}!") - message(STATUS "Using Arria 10 defaults.") + message(FATAL_ERROR "Unreachable") endif() if(IGNORE_DEFAULT_SEED) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/autorun/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/autorun/src/CMakeLists.txt index dbfb02daef..524c7c9bc7 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/autorun/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/autorun/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/CMakeLists.txt index b6c8d1ac41..81024c073e 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/buffered_host_streaming/src/CMakeLists.txt @@ -7,18 +7,26 @@ set(REPORTS_TARGET ${TARGET_NAME}_report) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_s10sx_pac:pac_s10_usm") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Stratix(R) 10 SX FPGA with USM support). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") +endif() + +# Check if the target is a BSP +if(FPGA_DEVICE MATCHES ".*:.*") + set(IS_BSP "1") + message(STATUS "Targetting a BSP.") +else() + set(IS_BSP "0") endif() # this tutorial requires USM host allocations. Check the BSP name (which should contain the text 'usm') # to ensure the BSP has the required support. Allow the user to define USM_HOST_ALLOCATIONS_ENABLED # to override this check (e.g., cmake .. -DUSM_HOST_ALLOCATIONS_ENABLED=1) -if(NOT FPGA_DEVICE MATCHES ".usm.*" AND (NOT DEFINED USM_HOST_ALLOCATIONS_ENABLED OR USM_HOST_ALLOCATIONS_ENABLED STREQUAL "0")) +if((IS_BSP STREQUAL "1") AND (NOT FPGA_DEVICE MATCHES ".usm.*") AND (NOT DEFINED USM_HOST_ALLOCATIONS_ENABLED OR USM_HOST_ALLOCATIONS_ENABLED STREQUAL "0")) message(FATAL_ERROR "ERROR: This tutorial requires a BSP that has USM host allocations enabled.") endif() diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/compute_units/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/compute_units/src/CMakeLists.txt index dfb0ca6cf9..002416d343 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/compute_units/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/compute_units/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/double_buffering/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/double_buffering/src/CMakeLists.txt index cd4b6e57de..f86ffe6ce0 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/double_buffering/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/double_buffering/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/CMakeLists.txt index 83c3f1a58a..001a1ce04a 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/CMakeLists.txt @@ -6,14 +6,15 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() + # This is a Windows-specific flag that enables exception handling in host code if(WIN32) set(WIN_FLAG "/EHsc") diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/io_streaming/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/io_streaming/src/CMakeLists.txt index 2e88ff0ff1..9ee6a58f1b 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/io_streaming/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/io_streaming/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables error handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/loop_carried_dependency/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/loop_carried_dependency/src/CMakeLists.txt index 3d52bdaf17..89db5e6cd3 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/loop_carried_dependency/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/loop_carried_dependency/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/n_way_buffering/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/n_way_buffering/src/CMakeLists.txt index 73cb4c3657..aaf3e9e6fc 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/n_way_buffering/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/n_way_buffering/src/CMakeLists.txt @@ -6,13 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") - + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/onchip_memory_cache/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/onchip_memory_cache/src/CMakeLists.txt index eafb0596e4..9eef332a47 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/onchip_memory_cache/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/onchip_memory_cache/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/optimize_inner_loop/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/optimize_inner_loop/src/CMakeLists.txt index 57737c59e6..3957592d27 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/optimize_inner_loop/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/optimize_inner_loop/src/CMakeLists.txt @@ -6,14 +6,15 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() + # This is a Windows-specific flag that enables exception handling in host code if(WIN32) set(WIN_FLAG "/EHsc") diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/shannonization/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/shannonization/src/CMakeLists.txt index edbf970b18..3dcef8d3d9 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/shannonization/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/shannonization/src/CMakeLists.txt @@ -7,27 +7,30 @@ set(REPORTS_TARGET ${TARGET_NAME}_report) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") - set(DEVICE_FLAG "-DA10") + set(FPGA_DEVICE "Agilex") + set(DEVICE_FLAG "-DAgilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - if(FPGA_DEVICE MATCHES ".*a10.*") - set(DEVICE_FLAG "-DA10") - elseif(FPGA_DEVICE MATCHES ".*s10.*") - set(DEVICE_FLAG "-DS10") - elseif(FPGA_DEVICE MATCHES ".*agilex.*") - set(DEVICE_FLAG "-DAgilex") + string(TOLOWER ${FPGA_DEVICE} FPGA_DEVICE_NAME) + if(FPGA_DEVICE_NAME MATCHES ".*a10.*" OR FPGA_DEVICE_NAME MATCHES ".*arria10.*") + set(DEVICE_FLAG "A10") + elseif(FPGA_DEVICE_NAME MATCHES ".*s10.*" OR FPGA_DEVICE_NAME MATCHES ".*stratix10.*") + set(DEVICE_FLAG "S10") + elseif(FPGA_DEVICE_NAME MATCHES ".*agilex.*") + set(DEVICE_FLAG "Agilex") endif() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() if(NOT DEFINED DEVICE_FLAG) message(FATAL_ERROR "An unrecognized or custom board was passed, but DEVICE_FLAG was not specified. \ - Please make sure you have set -DDEVICE_FLAG=-DA10 or -DDEVICE_FLAG=-DS10.") + Please make sure you have set -DDEVICE_FLAG=-DA10, -DDEVICE_FLAG=-DS10 or \ + -DDEVICE_FLAG=-DAgilex.") endif() + # This is a Windows-specific flag that enables exception handling in host code if(WIN32) set(WIN_FLAG "/EHsc") diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/simple_host_streaming/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/simple_host_streaming/src/CMakeLists.txt index 457b6b5fa5..021940f4db 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/simple_host_streaming/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/simple_host_streaming/src/CMakeLists.txt @@ -7,12 +7,12 @@ set(REPORTS_TARGET ${TARGET_NAME}_report) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_s10sx_pac:pac_s10_usm") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Stratix(R) 10 SX FPGA with USM support). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # this tutorial requires USM host allocations. Check the BSP name (which should contain the text 'usm') diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/triangular_loop/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/triangular_loop/src/CMakeLists.txt index 47cb4fb14f..98ea0fc38c 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/triangular_loop/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/triangular_loop/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/src/CMakeLists.txt index 55245b4cc6..be28c1e347 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/src/CMakeLists.txt @@ -7,18 +7,26 @@ set(REPORTS_TARGET ${TARGET_NAME}_report) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_s10sx_pac:pac_s10_usm") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Stratix(R) 10 SX FPGA with USM support). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") +endif() + +# Check if the target is a BSP +if(FPGA_DEVICE MATCHES ".*:.*") + set(IS_BSP "1") + message(STATUS "Targetting a BSP.") +else() + set(IS_BSP "0") endif() # this tutorial requires USM host allocations. Check the BSP name (which should contain the text 'usm') # to ensure the BSP has the required support. Allow the user to define USM_HOST_ALLOCATIONS_ENABLED # to override this check (e.g., cmake .. -DUSM_HOST_ALLOCATIONS_ENABLED=1) -if(NOT FPGA_DEVICE MATCHES ".usm.*" AND (NOT DEFINED USM_HOST_ALLOCATIONS_ENABLED OR USM_HOST_ALLOCATIONS_ENABLED STREQUAL "0")) +if((IS_BSP STREQUAL "1") AND (NOT FPGA_DEVICE MATCHES ".usm.*") AND (NOT DEFINED USM_HOST_ALLOCATIONS_ENABLED OR USM_HOST_ALLOCATIONS_ENABLED STREQUAL "0")) message(FATAL_ERROR "ERROR: This tutorial requires a BSP that has USM host allocations enabled.") endif() diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/src/CMakeLists.txt index 06249e736b..feae4be3d9 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # These are Windows-specific flags: diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_int/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_int/src/CMakeLists.txt index 0d127d1e79..aebece6e88 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_int/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_int/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # These are Windows-specific flags: diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/dsp_control/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/dsp_control/src/CMakeLists.txt index c98c81e1f1..1f15368ee8 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/dsp_control/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/dsp_control/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/hostpipes/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/hostpipes/src/CMakeLists.txt index 53caac3055..eb5920954a 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/hostpipes/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/hostpipes/src/CMakeLists.txt @@ -4,14 +4,14 @@ set(EMULATOR_TARGET ${TARGET_NAME}.fpga_emu) set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) set(FPGA_TARGET ${TARGET_NAME}.fpga) -# FPGA device selection +# FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_s10sx_pac:pac_s10_usm") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA device ${FPGA_DEVICE} (Intel(R) PAC with Intel Stratix(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA device ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # this tutorial requires USM host allocations. Check the BSP name (which should contain the text 'usm') diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/latency_control/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/latency_control/src/CMakeLists.txt index a4c8f0ac3e..6206c41231 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/latency_control/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/latency_control/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/fpga_reg/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/fpga_reg/src/CMakeLists.txt index b336c2a8a1..9ae86277b5 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/fpga_reg/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/fpga_reg/src/CMakeLists.txt @@ -9,12 +9,12 @@ set(FPGA_TARGET_REG ${TARGET_NAME_REG}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/kernel_args_restrict/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/kernel_args_restrict/src/CMakeLists.txt index df3670f1da..3912093a48 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/kernel_args_restrict/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/kernel_args_restrict/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_coalesce/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_coalesce/src/CMakeLists.txt index 511ff9ffa1..5da31ab70d 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_coalesce/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_coalesce/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_fusion/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_fusion/src/CMakeLists.txt index 9c96136833..da4a27dba8 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_fusion/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_fusion/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_initiation_interval/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_initiation_interval/src/CMakeLists.txt index 0edcd66110..d04dbae79b 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_initiation_interval/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_initiation_interval/src/CMakeLists.txt @@ -9,20 +9,21 @@ set(FPGA_TARGET_ENABLE_II ${TARGET_NAME_ENABLE_II}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") - set(DEVICE_FLAG "-DA10") + set(FPGA_DEVICE "Agilex") + set(DEVICE_FLAG "-DAgilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - if(FPGA_DEVICE MATCHES ".*a10.*") - set(DEVICE_FLAG "-DA10") - elseif(FPGA_DEVICE MATCHES ".*s10.*") - set(DEVICE_FLAG "-DS10") - elseif(FPGA_DEVICE MATCHES ".*agilex.*") - set(DEVICE_FLAG "-DAgilex") + string(TOLOWER ${FPGA_DEVICE} FPGA_DEVICE_NAME) + if(FPGA_DEVICE_NAME MATCHES ".*a10.*" OR FPGA_DEVICE_NAME MATCHES ".*arria10.*") + set(DEVICE_FLAG "A10") + elseif(FPGA_DEVICE_NAME MATCHES ".*s10.*" OR FPGA_DEVICE_NAME MATCHES ".*stratix10.*") + set(DEVICE_FLAG "S10") + elseif(FPGA_DEVICE_NAME MATCHES ".*agilex.*") + set(DEVICE_FLAG "Agilex") endif() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() if(NOT DEFINED DEVICE_FLAG) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_ivdep/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_ivdep/src/CMakeLists.txt index 0fc1c1b48c..eb9955faa5 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_ivdep/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_ivdep/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_unroll/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_unroll/src/CMakeLists.txt index c2b0721827..5318284578 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_unroll/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_unroll/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/lsu_control/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/lsu_control/src/CMakeLists.txt index ac998976c1..e8e38ecffd 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/lsu_control/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/lsu_control/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/max_interleaving/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/max_interleaving/src/CMakeLists.txt index 1db78888f6..5743e83faa 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/max_interleaving/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/max_interleaving/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/mem_channel/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/mem_channel/src/CMakeLists.txt index 665dbb08d0..b0571c60ae 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/mem_channel/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/mem_channel/src/CMakeLists.txt @@ -7,12 +7,12 @@ set(FPGA_TARGET_NO_INTERLEAVING ${TARGET_NAME}_no_interleaving.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/memory_attributes/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/memory_attributes/src/CMakeLists.txt index 0f384c52eb..647989136f 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/memory_attributes/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/memory_attributes/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/pipes/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/pipes/src/CMakeLists.txt index 1026ff96ec..3b804fccc1 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/pipes/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/pipes/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/printf/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/printf/src/CMakeLists.txt index 226a20fa79..bba5f32ab2 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/printf/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/printf/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/private_copies/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/private_copies/src/CMakeLists.txt index a0288d5568..c8a85d65f8 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/private_copies/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/private_copies/src/CMakeLists.txt @@ -5,14 +5,13 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() - # This is a Windows-specific flag that enables exception handling in host code if(WIN32) set(WIN_FLAG "/EHsc") diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/read_only_cache/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/read_only_cache/src/CMakeLists.txt index 819d2289df..f14e770976 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/read_only_cache/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/read_only_cache/src/CMakeLists.txt @@ -7,12 +7,12 @@ set(FPGA_TARGET_CACHE_ENABLED ${TARGET_NAME}_enabled.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/scheduler_target_fmax/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/scheduler_target_fmax/src/CMakeLists.txt index b50820cb05..3687be9be6 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/scheduler_target_fmax/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/scheduler_target_fmax/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/speculated_iterations/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/speculated_iterations/src/CMakeLists.txt index 269b1a800e..bb4641a808 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/speculated_iterations/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/speculated_iterations/src/CMakeLists.txt @@ -7,20 +7,21 @@ set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") - set(DEVICE_FLAG "-DA10") + set(FPGA_DEVICE "Agilex") + set(DEVICE_FLAG "-DAgilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - if(FPGA_DEVICE MATCHES ".*a10*") - set(DEVICE_FLAG "-DA10") - elseif(FPGA_DEVICE MATCHES ".*s10*") - set(DEVICE_FLAG "-DS10") - elseif(FPGA_DEVICE MATCHES ".*agilex*") - set(DEVICE_FLAG "-DAgilex") + string(TOLOWER ${FPGA_DEVICE} FPGA_DEVICE_NAME) + if(FPGA_DEVICE_NAME MATCHES ".*a10.*" OR FPGA_DEVICE_NAME MATCHES ".*arria10.*") + set(DEVICE_FLAG "A10") + elseif(FPGA_DEVICE_NAME MATCHES ".*s10.*" OR FPGA_DEVICE_NAME MATCHES ".*stratix10.*") + set(DEVICE_FLAG "S10") + elseif(FPGA_DEVICE_NAME MATCHES ".*agilex.*") + set(DEVICE_FLAG "Agilex") endif() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() if(NOT DEFINED DEVICE_FLAG) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/stall_enable/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/stall_enable/src/CMakeLists.txt index e4bf730be9..223d1bb40e 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/stall_enable/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/stall_enable/src/CMakeLists.txt @@ -12,12 +12,12 @@ set(FPGA_TARGET_STALL_FREE ${STALL_FREE_TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # Allow disabling of hyper-optimization for S10 diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/src/CMakeLists.txt index 2262a5bd4a..a2df4f2fe7 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/src/CMakeLists.txt @@ -8,12 +8,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/src/CMakeLists.txt index c7b9d10532..373504a091 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/src/CMakeLists.txt @@ -4,14 +4,14 @@ set(EMULATOR_TARGET ${TARGET_NAME}.fpga_emu) set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) set(FPGA_TARGET ${TARGET_NAME}.fpga) -# FPGA device selection +# FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA device ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on device selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA device ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # This is a Windows-specific flag that enables exception handling in host code diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/dynamic_profiler/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/dynamic_profiler/src/CMakeLists.txt index 99eab3f2c8..c104768772 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/dynamic_profiler/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/dynamic_profiler/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # A DPC++ ahead-of-time (AoT) compile processes the device code in two stages. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/system_profiling/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/system_profiling/src/CMakeLists.txt index 31a6a56cb2..69a7947ecf 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/system_profiling/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/system_profiling/src/CMakeLists.txt @@ -6,12 +6,12 @@ set(FPGA_TARGET ${TARGET_NAME}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # A SYCL ahead-of-time (AoT) compile processes the device code in two stages. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/use_library/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/use_library/src/CMakeLists.txt index e292940026..5c80526a5a 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/use_library/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/use_library/src/CMakeLists.txt @@ -8,12 +8,12 @@ set(REPORT_TARGET ${TARGET_NAME}_report.a) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") + set(FPGA_DEVICE "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") + \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ + \nPlease refer to the README for information on target selection.") else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() # /EHsc This is a Windows-specific flag that enables exception handling in host code From 17bfb61da5ca3d121467bfd43bfed68841cf4c48 Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Fri, 13 Jan 2023 05:07:23 -0800 Subject: [PATCH 02/22] support IPA for selected samples Signed-off-by: Yohann Uguen --- .../ReferenceDesigns/anr/src/CMakeLists.txt | 24 +++++++++----- .../board_test/src/CMakeLists.txt | 2 +- .../cholesky/src/CMakeLists.txt | 31 +++++++++++++++---- .../cholesky/src/cholesky.hpp | 12 ++++--- .../cholesky/src/memory_transfers.hpp | 6 ++-- .../cholesky_inversion/src/CMakeLists.txt | 22 +++++++++---- .../src/cholesky_inversion.hpp | 6 ++++ .../src/memory_transfers.hpp | 12 +++---- .../ReferenceDesigns/qrd/src/CMakeLists.txt | 24 +++++++++----- .../qrd/src/memory_transfers.hpp | 12 +++---- .../ReferenceDesigns/qrd/src/qrd.hpp | 11 +++++-- .../ReferenceDesigns/qri/src/CMakeLists.txt | 22 +++++++++---- .../qri/src/memory_transfers.hpp | 12 +++---- .../ReferenceDesigns/qri/src/qri.hpp | 7 +++++ .../src/explicit_data_movement.cpp | 4 +-- .../io_streaming/src/CMakeLists.txt | 12 +++++-- .../shannonization/src/CMakeLists.txt | 16 +++++----- .../simple_host_streaming/src/CMakeLists.txt | 10 +++++- .../Features/ac_fixed/src/CMakeLists.txt | 6 ++-- .../experimental/hostpipes/src/CMakeLists.txt | 18 ++++++++--- .../src/CMakeLists.txt | 12 +++---- .../memory_attributes/src/CMakeLists.txt | 4 +-- .../Tutorials/Features/printf/README.md | 2 ++ .../Features/printf/src/CMakeLists.txt | 15 +++++++++ .../speculated_iterations/src/CMakeLists.txt | 12 +++---- 25 files changed, 212 insertions(+), 102 deletions(-) diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/CMakeLists.txt index 1d89d5a2ac..6b38376d16 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/CMakeLists.txt @@ -29,6 +29,16 @@ if(NOT DEFINED DEVICE_FLAG) -DDEVICE_FLAG=Agilex.") endif() +# Check if the target is a BSP +if(FPGA_DEVICE MATCHES ".*:.*") + set(IS_BSP "1") + message(STATUS "Targetting a BSP.") + set(BSP_FLAG "-DIS_BSP") +else() + set(IS_BSP "0") + set(BSP_FLAG "") +endif() + # These are Windows-specific flags: # 1. /EHsc This is a Windows-specific flag that enables exception handling in host code # 2. /Qactypes Include ac_types headers and link against ac_types emulation libraries @@ -135,13 +145,13 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} -DFPGA_EMULATOR") -set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG}") -set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} -Xssimulation -DFPGA_SIMULATOR") -set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -Xshardware ${PROFILE_FLAG} ${FLAT_COMPILE_FLAG} -Xsparallel=2 ${SEED_FLAG} -Xstarget=${FPGA_DEVICE} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} ${IP_MODE_FLAG} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} -DFPGA_HARDWARE") -set(HARDWARE_LINK_FLAGS "${REPORT_LINK_FLAGS} ${AC_TYPES_FLAG}") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} -DFPGA_EMULATOR ${BSP_FLAG}") +set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} ${BSP_FLAG}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} -Xssimulation -DFPGA_SIMULATOR ${BSP_FLAG}") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} ${BSP_FLAG}") +set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -Xshardware ${PROFILE_FLAG} ${FLAT_COMPILE_FLAG} -Xsparallel=2 ${SEED_FLAG} -Xstarget=${FPGA_DEVICE} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} ${IP_MODE_FLAG} ${USER_HARDWARE_FLAGS} ${BSP_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} -DFPGA_HARDWARE ${BSP_FLAG}") +set(HARDWARE_LINK_FLAGS "${REPORT_LINK_FLAGS} ${AC_TYPES_FLAG} ${BSP_FLAG}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation ############################################################################### diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/board_test/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/board_test/src/CMakeLists.txt index c5105263ba..01c6b46987 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/board_test/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/board_test/src/CMakeLists.txt @@ -20,7 +20,7 @@ endif() # Check if the target is a BSP if(NOT FPGA_DEVICE MATCHES ".*:.*") message(STATUS "This sample is made to target BSPs as this is a benchmarking sample.") -else() +endif() # This is a Windows-specific flag that enables error handling in host code if(WIN32) diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/CMakeLists.txt index ebe3719e76..00961b84ba 100755 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/CMakeLists.txt @@ -30,6 +30,16 @@ if(NOT DEFINED DEVICE_FLAG) -DDEVICE_FLAG=Agilex.") endif() +# Check if the target is a BSP +if(FPGA_DEVICE MATCHES ".*:.*") + set(IS_BSP "1") + message(STATUS "Targetting a BSP.") + set(BSP_FLAG "-DIS_BSP") +else() + set(IS_BSP "0") + set(BSP_FLAG "") +endif() + if(DEVICE_FLAG MATCHES "A10") # A10 parameters set(MATRIX_DIMENSION 32) @@ -55,6 +65,15 @@ else() message(FATAL_ERROR "Unreachable") endif() +# This is a Windows-specific flag that enables error handling in host code +if(WIN32) + set(PLATFORM_SPECIFIC_COMPILE_FLAGS "/EHsc /Qactypes /Wall /fp:precise") + set(PLATFORM_SPECIFIC_LINK_FLAGS "/Qactypes /fp:precise") +else() + set(PLATFORM_SPECIFIC_COMPILE_FLAGS "-qactypes -Wall -fno-finite-math-only -fp-model=precise") + set(PLATFORM_SPECIFIC_LINK_FLAGS "-fp-model=precise") +endif() + if(IGNORE_DEFAULT_SEED) set(SEED "") endif() @@ -80,12 +99,12 @@ message(STATUS "SEED=${SEED}") # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -DFPGA_EMULATOR") -set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS}") -set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -DFPGA_SIMULATOR -fbracket-depth=512 -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -Xsfp-relaxed ${USER_SIMULATOR_FLAGS}") -set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} -Xssimulation -Xsghdl -Xsclock=${CLOCK_TARGET} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} -Xsfp-relaxed") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -Xsfp-relaxed -DFPGA_HARDWARE") -set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} -Xshardware -Xsclock=${CLOCK_TARGET} -Xsparallel=2 ${SEED} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} -Xsfp-relaxed") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -DFPGA_EMULATOR ${BSP_FLAG}") +set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} ${BSP_FLAG}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -DFPGA_SIMULATOR -fbracket-depth=512 -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -Xsfp-relaxed ${USER_SIMULATOR_FLAGS} ${BSP_FLAG}") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} -Xssimulation -Xsghdl -Xsclock=${CLOCK_TARGET} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} -Xsfp-relaxed ${BSP_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -Xsfp-relaxed -DFPGA_HARDWARE ${BSP_FLAG}") +set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} -Xshardware -Xsclock=${CLOCK_TARGET} -Xsparallel=2 ${SEED} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} -Xsfp-relaxed ${BSP_FLAG}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/cholesky.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/cholesky.hpp index d0729d4a29..edb8881528 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/cholesky.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/cholesky.hpp @@ -54,8 +54,14 @@ void CholeskyDecompositionImpl( sycl::ext::intel::pipe; // Allocate FPGA DDR memory. +#if defined (IS_BSP) TT *a_device = sycl::malloc_device(kAMatrixSize * matrix_count, q); TT *l_device = sycl::malloc_device(kLMatrixSize * matrix_count, q); +#else + // malloc_device are not supported when targetting an FPGA part/family + TT *a_device = sycl::malloc_shared(kAMatrixSize * matrix_count, q); + TT *l_device = sycl::malloc_shared(kLMatrixSize * matrix_count, q); +#endif if ((a_device == nullptr) || (l_device == nullptr)) { std::cerr << "Error when allocating FPGA DDR" << std::endl; @@ -93,8 +99,6 @@ void CholeskyDecompositionImpl( constexpr int kLoopIter = (kLMatrixSize / kNumElementsPerDDRBurst) + kExtraIteration; - sycl::device_ptr vector_ptr_device(l_device); - // Repeat matrix_count complete L matrix pipe reads // for as many repetitions as needed // The loop coalescing directive merges the two outer loops together @@ -117,7 +121,7 @@ void CholeskyDecompositionImpl( #pragma unroll for (int k = 0; k < kNumElementsPerDDRBurst; k++) { if (((li * kNumElementsPerDDRBurst) + k) < kLMatrixSize) { - vector_ptr_device[(matrix_idx * kLMatrixSize) + + l_device[(matrix_idx * kLMatrixSize) + (li * kNumElementsPerDDRBurst) + k] = bank[k]; } } @@ -125,7 +129,7 @@ void CholeskyDecompositionImpl( // Write a burst of kNumElementsPerDDRBurst elements to DDR #pragma unroll for (int k = 0; k < kNumElementsPerDDRBurst; k++) { - vector_ptr_device[(matrix_idx * kLMatrixSize) + + l_device[(matrix_idx * kLMatrixSize) + (li * kNumElementsPerDDRBurst) + k] = bank[k]; } } diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/memory_transfers.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/memory_transfers.hpp index 6d25905d41..44bb9d8a8d 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/memory_transfers.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/memory_transfers.hpp @@ -38,8 +38,6 @@ void MatrixReadFromDDRToPipe( // Size of a full matrix constexpr int kMatrixSize = rows * columns; - sycl::device_ptr matrix_ptr_device(matrix_ptr); - // Repeatedly read matrix_count matrices from DDR and send them to the pipe for (int repetition = 0; repetition < repetitions; repetition++) { for (int matrix_index = 0; matrix_index < matrix_count; matrix_index++) { @@ -71,12 +69,12 @@ void MatrixReadFromDDRToPipe( // memory address that may be beyond the matrix last address) if (!out_of_bounds) { ddr_read.template get() = - matrix_ptr_device[matrix_index * kMatrixSize + load_index + + matrix_ptr[matrix_index * kMatrixSize + load_index + k]; } } else { ddr_read.template get() = - matrix_ptr_device[matrix_index * kMatrixSize + + matrix_ptr[matrix_index * kMatrixSize + (int)(li)*num_elem_per_bank + k]; } }); diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/CMakeLists.txt index 9aa382dc12..2c248e7a80 100755 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/CMakeLists.txt @@ -30,6 +30,16 @@ if(NOT DEFINED DEVICE_FLAG) -DDEVICE_FLAG=Agilex.") endif() +# Check if the target is a BSP +if(FPGA_DEVICE MATCHES ".*:.*") + set(IS_BSP "1") + message(STATUS "Targetting a BSP.") + set(BSP_FLAG "-DIS_BSP") +else() + set(IS_BSP "0") + set(BSP_FLAG "") +endif() + # This is a Windows-specific flag that enables error handling in host code if(WIN32) set(PLATFORM_SPECIFIC_COMPILE_FLAGS "/EHsc /Qactypes /Wall /fp:precise") @@ -97,12 +107,12 @@ message(STATUS "SEED=${SEED}") # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS_DECOMPOSITION=${FIXED_ITERATIONS_DECOMPOSITION} -DFIXED_ITERATIONS_INVERSION=${FIXED_ITERATIONS_INVERSION} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -DFPGA_EMULATOR") -set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS}") -set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -DFPGA_SIMULATOR -DFIXED_ITERATIONS_DECOMPOSITION=${FIXED_ITERATIONS_DECOMPOSITION} -DFIXED_ITERATIONS_INVERSION=${FIXED_ITERATIONS_INVERSION} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -Xsfp-relaxed ${USER_HARDWARE_FLAGS}") -set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} -Xssimulation -Xsghdl -Xsclock=${CLOCK_TARGET} -Xstarget=${FPGA_DEVICE} ${USER_SIMULATOR_FLAGS} -Xsfp-relaxed") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS_DECOMPOSITION=${FIXED_ITERATIONS_DECOMPOSITION} -DFIXED_ITERATIONS_INVERSION=${FIXED_ITERATIONS_INVERSION} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -Xsfp-relaxed -DFPGA_HARDWARE") -set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} -Xshardware -Xsclock=${CLOCK_TARGET} -Xsparallel=2 ${SEED} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} -Xsfp-relaxed") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS_DECOMPOSITION=${FIXED_ITERATIONS_DECOMPOSITION} -DFIXED_ITERATIONS_INVERSION=${FIXED_ITERATIONS_INVERSION} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -DFPGA_EMULATOR ${BSP_FLAG}") +set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} ${BSP_FLAG}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -DFPGA_SIMULATOR -DFIXED_ITERATIONS_DECOMPOSITION=${FIXED_ITERATIONS_DECOMPOSITION} -DFIXED_ITERATIONS_INVERSION=${FIXED_ITERATIONS_INVERSION} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -Xsfp-relaxed ${USER_HARDWARE_FLAGS} ${BSP_FLAG}") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} -Xssimulation -Xsghdl -Xsclock=${CLOCK_TARGET} -Xstarget=${FPGA_DEVICE} ${USER_SIMULATOR_FLAGS} -Xsfp-relaxed ${BSP_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS_DECOMPOSITION=${FIXED_ITERATIONS_DECOMPOSITION} -DFIXED_ITERATIONS_INVERSION=${FIXED_ITERATIONS_INVERSION} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -Xsfp-relaxed -DFPGA_HARDWARE ${BSP_FLAG}") +set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} -Xshardware -Xsclock=${CLOCK_TARGET} -Xsparallel=2 ${SEED} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} -Xsfp-relaxed ${BSP_FLAG}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation ############################################################################### diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/cholesky_inversion.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/cholesky_inversion.hpp index 7f67dfdc38..22e8faac39 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/cholesky_inversion.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/cholesky_inversion.hpp @@ -62,8 +62,14 @@ void CholeskyInversionImpl( sycl::ext::intel::pipe; // Allocate FPGA DDR memory. +#if defined (IS_BSP) TT *a_device = sycl::malloc_device(kAMatrixSize * matrix_count, q); TT *i_device = sycl::malloc_device(kIMatrixSize * matrix_count, q); +#else + // malloc_device are not supported when targetting an FPGA part/family + TT *a_device = sycl::malloc_shared(kAMatrixSize * matrix_count, q); + TT *i_device = sycl::malloc_shared(kIMatrixSize * matrix_count, q); +#endif if ((a_device == nullptr) || (i_device == nullptr)) { std::cerr << "Error when allocating FPGA DDR" << std::endl; diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/memory_transfers.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/memory_transfers.hpp index 1a40f3915f..1c44f3e38f 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/memory_transfers.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/memory_transfers.hpp @@ -38,8 +38,6 @@ void MatrixReadFromDDRToPipe( // Size of a full matrix constexpr int kMatrixSize = rows * columns; - sycl::device_ptr matrix_ptr_device(matrix_ptr); - // Repeatedly read matrix_count matrices from the DDR and send them to the // pipe for (int repetition = 0; repetition < repetitions; repetition++) { @@ -72,12 +70,12 @@ void MatrixReadFromDDRToPipe( // memory address that may be beyond the matrix last address) if (!out_of_bounds) { ddr_read.template get() = - matrix_ptr_device[matrix_index * kMatrixSize + load_index + + matrix_ptr[matrix_index * kMatrixSize + load_index + k]; } } else { ddr_read.template get() = - matrix_ptr_device[matrix_index * kMatrixSize + + matrix_ptr[matrix_index * kMatrixSize + (int)(li)*num_elem_per_bank + k]; } }); @@ -118,8 +116,6 @@ void VectorReadFromPipeToDDR( constexpr int kExtraIteration = kIncompleteBurst ? 1 : 0; constexpr int kLoopIter = (vector_size / num_elem_per_bank) + kExtraIteration; - sycl::device_ptr vector_ptr_device(vector_ptr); - // Repeat vector_count complete I vector pipe reads // for as many repetitions as needed for (int rep_idx = 0; rep_idx < repetitions; rep_idx++) { @@ -139,7 +135,7 @@ void VectorReadFromPipeToDDR( #pragma unroll for (int k = 0; k < num_elem_per_bank; k++) { if (((li * num_elem_per_bank) + k) < vector_size) { - vector_ptr_device[(vector_idx * vector_size) + + vector_ptr[(vector_idx * vector_size) + (li * num_elem_per_bank) + k] = bank[k]; } } @@ -147,7 +143,7 @@ void VectorReadFromPipeToDDR( // Write a burst of num_elem_per_bank elements to DDR #pragma unroll for (int k = 0; k < num_elem_per_bank; k++) { - vector_ptr_device[(vector_idx * vector_size) + + vector_ptr[(vector_idx * vector_size) + (li * num_elem_per_bank) + k] = bank[k]; } } diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/CMakeLists.txt index e110721e79..04a4c501c1 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/CMakeLists.txt @@ -30,6 +30,16 @@ if(NOT DEFINED DEVICE_FLAG) -DDEVICE_FLAG=Agilex.") endif() +# Check if the target is a BSP +if(FPGA_DEVICE MATCHES ".*:.*") + set(IS_BSP "1") + message(STATUS "Targetting a BSP.") + set(BSP_FLAG "-DIS_BSP") +else() + set(IS_BSP "0") + set(BSP_FLAG "") +endif() + # This is a Windows-specific flag that enables error handling in host code if(WIN32) set(AC_TYPES_COMPILE_FLAG "/Qactypes") @@ -105,13 +115,13 @@ message(STATUS "SEED=${SEED}") # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} ${AC_TYPES_COMPILE_FLAG} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DROWS_COMPONENT=${ROWS_COMPONENT} -DCOLS_COMPONENT=${COLS_COMPONENT} -DFPGA_EMULATOR") -set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} ${STACK_FLAG} ${AC_TYPES_LINK_FLAG}") -set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} ${AC_TYPES_COMPILE_FLAG} -DFPGA_SIMULATOR -fbracket-depth=512 -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DROWS_COMPONENT=${ROWS_COMPONENT} -DCOLS_COMPONENT=${COLS_COMPONENT} ${USER_HARDWARE_FLAGS}") -set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} ${STACK_FLAG} -Xssimulation -Xsghdl -Xsclock=${CLOCK_TARGET} -Xstarget=${FPGA_DEVICE} ${USER_SIMULATOR_FLAGS} ${AC_TYPES_LINK_FLAG}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} ${AC_TYPES_COMPILE_FLAG} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DROWS_COMPONENT=${ROWS_COMPONENT} -DCOLS_COMPONENT=${COLS_COMPONENT} -DFPGA_HARDWARE") -set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -Xshardware ${PLATFORM_SPECIFIC_LINK_FLAGS} -Xsclock=${CLOCK_TARGET} -Xsparallel=2 ${SEED} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} ${AC_TYPES_LINK_FLAG}") -set(HARDWARE_LINK_FLAGS "${REPORT_LINK_FLAGS} ${STACK_FLAG}") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} ${AC_TYPES_COMPILE_FLAG} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DROWS_COMPONENT=${ROWS_COMPONENT} -DCOLS_COMPONENT=${COLS_COMPONENT} -DFPGA_EMULATOR ${BSP_FLAG}") +set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} ${STACK_FLAG} ${AC_TYPES_LINK_FLAG} ${BSP_FLAG}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} ${AC_TYPES_COMPILE_FLAG} -DFPGA_SIMULATOR -fbracket-depth=512 -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DROWS_COMPONENT=${ROWS_COMPONENT} -DCOLS_COMPONENT=${COLS_COMPONENT} ${USER_HARDWARE_FLAGS} ${BSP_FLAG}") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} ${STACK_FLAG} -Xssimulation -Xsghdl -Xsclock=${CLOCK_TARGET} -Xstarget=${FPGA_DEVICE} ${USER_SIMULATOR_FLAGS} ${AC_TYPES_LINK_FLAG} ${BSP_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} ${AC_TYPES_COMPILE_FLAG} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DROWS_COMPONENT=${ROWS_COMPONENT} -DCOLS_COMPONENT=${COLS_COMPONENT} -DFPGA_HARDWARE ${BSP_FLAG}") +set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -Xshardware ${PLATFORM_SPECIFIC_LINK_FLAGS} -Xsclock=${CLOCK_TARGET} -Xsparallel=2 ${SEED} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} ${AC_TYPES_LINK_FLAG} ${BSP_FLAG}") +set(HARDWARE_LINK_FLAGS "${REPORT_LINK_FLAGS} ${STACK_FLAG} ${BSP_FLAG}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation ############################################################################### diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/memory_transfers.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/memory_transfers.hpp index 0e03ed62a5..35a568ac62 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/memory_transfers.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/memory_transfers.hpp @@ -37,8 +37,6 @@ void MatrixReadFromDDRToPipe( // Size of a full matrix constexpr int kMatrixSize = rows * columns; - sycl::device_ptr matrix_ptr_device(matrix_ptr); - // Repeatedly read matrix_count matrices from DDR and sends them to the pipe for (int repetition = 0; repetition < repetitions; repetition++){ @@ -72,12 +70,12 @@ void MatrixReadFromDDRToPipe( // Only perform the DDR reads that are relevant (and don't access a // memory address that may be beyond the matrix last address) if (!out_of_bounds) { - ddr_read.template get() = matrix_ptr_device + ddr_read.template get() = matrix_ptr [matrix_index * kMatrixSize + load_index + k]; } } else{ - ddr_read.template get() = matrix_ptr_device + ddr_read.template get() = matrix_ptr [matrix_index * kMatrixSize + (int)(li)*num_elem_per_bank + k]; } @@ -128,8 +126,6 @@ void MatrixReadPipeToDDR( // Size of a full matrix constexpr int kMatrixSize = rows * columns; - sycl::device_ptr matrix_ptr_device(matrix_ptr); - // Repeatedly read matrix_count matrices from the pipe and write them to DDR for (int repetition = 0; repetition < repetitions; repetition++){ @@ -161,12 +157,12 @@ void MatrixReadPipeToDDR( // Only perform the DDR writes that are relevant (and don't access a // memory address that may be beyond the buffer last address) if (!out_of_bounds) { - matrix_ptr_device[matrix_index * kMatrixSize + write_idx + k] = + matrix_ptr[matrix_index * kMatrixSize + write_idx + k] = pipe_read.template get(); } } else{ - matrix_ptr_device[matrix_index * kMatrixSize + matrix_ptr[matrix_index * kMatrixSize + int(li) * num_elem_per_bank + k] = pipe_read.template get(); } diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/qrd.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/qrd.hpp index c86e5f4e95..0adb1f3d54 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/qrd.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/qrd.hpp @@ -61,9 +61,16 @@ void QRDecompositionImpl( kNumElementsPerDDRBurst * 4>; // Allocate FPGA DDR memory. +#if defined (IS_BSP) TT *a_device = sycl::malloc_device(kAMatrixSize * matrix_count, q); TT *q_device = sycl::malloc_device(kQMatrixSize * matrix_count, q); TT *r_device = sycl::malloc_device(kRMatrixSize * matrix_count, q); +#else + // malloc_device are not supported when targetting an FPGA part/family + TT *a_device = sycl::malloc_shared(kAMatrixSize * matrix_count, q); + TT *q_device = sycl::malloc_shared(kQMatrixSize * matrix_count, q); + TT *r_device = sycl::malloc_shared(kRMatrixSize * matrix_count, q); +#endif q.memcpy(a_device, a_matrix.data(), kAMatrixSize * matrix_count * sizeof(TT)).wait(); @@ -96,8 +103,6 @@ void QRDecompositionImpl( ]() [[intel::kernel_args_restrict]] { // Read the R matrix from the RMatrixPipe pipe and copy it to the // FPGA DDR - sycl::device_ptr vector_ptr_device(r_device); - // Repeat matrix_count complete R matrix pipe reads // for as many repetitions as needed for (int repetition_index = 0; repetition_index < repetitions; @@ -106,7 +111,7 @@ void QRDecompositionImpl( [[intel::loop_coalesce(2)]] // NO-FORMAT: Attribute for (int matrix_index = 0; matrix_index < matrix_count; matrix_index++) { for (int r_idx = 0; r_idx < kRMatrixSize; r_idx++) { - vector_ptr_device[matrix_index * kRMatrixSize + r_idx] = + r_device[matrix_index * kRMatrixSize + r_idx] = RMatrixPipe::read(); } // end of r_idx } // end of repetition_index diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/CMakeLists.txt index ebbbe1b14d..bba1c7f16d 100755 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/CMakeLists.txt @@ -30,6 +30,16 @@ if(NOT DEFINED DEVICE_FLAG) -DDEVICE_FLAG=Agilex.") endif() +# Check if the target is a BSP +if(FPGA_DEVICE MATCHES ".*:.*") + set(IS_BSP "1") + message(STATUS "Targetting a BSP.") + set(BSP_FLAG "-DIS_BSP") +else() + set(IS_BSP "0") + set(BSP_FLAG "") +endif() + # This is a Windows-specific flag that enables error handling in host code if(WIN32) set(PLATFORM_SPECIFIC_COMPILE_FLAGS "/EHsc /Qactypes /Wall /fp:precise") @@ -105,12 +115,12 @@ message(STATUS "SEED=${SEED}") # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS_QRD=${FIXED_ITERATIONS_QRD} -DFIXED_ITERATIONS_QRI=${FIXED_ITERATIONS_QRI} -DCOMPLEX=${COMPLEX} -DROWS_COMPONENT=${ROWS_COMPONENT} -DCOLS_COMPONENT=${COLS_COMPONENT} -DFPGA_EMULATOR") -set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS}") -set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -DFPGA_SIMULATOR -fbracket-depth=512 -DFIXED_ITERATIONS_QRD=${FIXED_ITERATIONS_QRD} -DFIXED_ITERATIONS_QRI=${FIXED_ITERATIONS_QRI} -DCOMPLEX=${COMPLEX} -DROWS_COMPONENT=${ROWS_COMPONENT} -DCOLS_COMPONENT=${COLS_COMPONENT} -Xsfp-relaxed ${USER_HARDWARE_FLAGS}") -set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} -Xssimulation -Xsghdl -Xsclock=${CLOCK_TARGET} -Xstarget=${FPGA_DEVICE} ${USER_SIMULATOR_FLAGS} -Xsfp-relaxed") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS_QRD=${FIXED_ITERATIONS_QRD} -DFIXED_ITERATIONS_QRI=${FIXED_ITERATIONS_QRI} -DCOMPLEX=${COMPLEX} -DROWS_COMPONENT=${ROWS_COMPONENT} -DCOLS_COMPONENT=${COLS_COMPONENT} -Xsfp-relaxed -DFPGA_HARDWARE") -set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} -Xshardware -Xsclock=${CLOCK_TARGET} -Xsparallel=2 ${SEED} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} -Xsfp-relaxed") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS_QRD=${FIXED_ITERATIONS_QRD} -DFIXED_ITERATIONS_QRI=${FIXED_ITERATIONS_QRI} -DCOMPLEX=${COMPLEX} -DROWS_COMPONENT=${ROWS_COMPONENT} -DCOLS_COMPONENT=${COLS_COMPONENT} -DFPGA_EMULATOR ${BSP_FLAG}") +set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} ${BSP_FLAG}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -DFPGA_SIMULATOR -fbracket-depth=512 -DFIXED_ITERATIONS_QRD=${FIXED_ITERATIONS_QRD} -DFIXED_ITERATIONS_QRI=${FIXED_ITERATIONS_QRI} -DCOMPLEX=${COMPLEX} -DROWS_COMPONENT=${ROWS_COMPONENT} -DCOLS_COMPONENT=${COLS_COMPONENT} -Xsfp-relaxed ${USER_HARDWARE_FLAGS} ${BSP_FLAG}") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} -Xssimulation -Xsghdl -Xsclock=${CLOCK_TARGET} -Xstarget=${FPGA_DEVICE} ${USER_SIMULATOR_FLAGS} -Xsfp-relaxed ${BSP_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS_QRD=${FIXED_ITERATIONS_QRD} -DFIXED_ITERATIONS_QRI=${FIXED_ITERATIONS_QRI} -DCOMPLEX=${COMPLEX} -DROWS_COMPONENT=${ROWS_COMPONENT} -DCOLS_COMPONENT=${COLS_COMPONENT} -Xsfp-relaxed -DFPGA_HARDWARE ${BSP_FLAG}") +set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} -Xshardware -Xsclock=${CLOCK_TARGET} -Xsparallel=2 ${SEED} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} -Xsfp-relaxed ${BSP_FLAG}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation ############################################################################### diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/memory_transfers.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/memory_transfers.hpp index 0e03ed62a5..35a568ac62 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/memory_transfers.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/memory_transfers.hpp @@ -37,8 +37,6 @@ void MatrixReadFromDDRToPipe( // Size of a full matrix constexpr int kMatrixSize = rows * columns; - sycl::device_ptr matrix_ptr_device(matrix_ptr); - // Repeatedly read matrix_count matrices from DDR and sends them to the pipe for (int repetition = 0; repetition < repetitions; repetition++){ @@ -72,12 +70,12 @@ void MatrixReadFromDDRToPipe( // Only perform the DDR reads that are relevant (and don't access a // memory address that may be beyond the matrix last address) if (!out_of_bounds) { - ddr_read.template get() = matrix_ptr_device + ddr_read.template get() = matrix_ptr [matrix_index * kMatrixSize + load_index + k]; } } else{ - ddr_read.template get() = matrix_ptr_device + ddr_read.template get() = matrix_ptr [matrix_index * kMatrixSize + (int)(li)*num_elem_per_bank + k]; } @@ -128,8 +126,6 @@ void MatrixReadPipeToDDR( // Size of a full matrix constexpr int kMatrixSize = rows * columns; - sycl::device_ptr matrix_ptr_device(matrix_ptr); - // Repeatedly read matrix_count matrices from the pipe and write them to DDR for (int repetition = 0; repetition < repetitions; repetition++){ @@ -161,12 +157,12 @@ void MatrixReadPipeToDDR( // Only perform the DDR writes that are relevant (and don't access a // memory address that may be beyond the buffer last address) if (!out_of_bounds) { - matrix_ptr_device[matrix_index * kMatrixSize + write_idx + k] = + matrix_ptr[matrix_index * kMatrixSize + write_idx + k] = pipe_read.template get(); } } else{ - matrix_ptr_device[matrix_index * kMatrixSize + matrix_ptr[matrix_index * kMatrixSize + int(li) * num_elem_per_bank + k] = pipe_read.template get(); } diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/qri.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/qri.hpp index 85f4e55b43..ba0e24c4c9 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/qri.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/qri.hpp @@ -68,8 +68,15 @@ void QRIImpl( // Create buffers and allocate space for them. +#if defined (IS_BSP) TT *a_device = sycl::malloc_device(kAMatrixSize * matrix_count, q); TT *i_device = sycl::malloc_device(kInverseMatrixSize * matrix_count, q); +#else + // malloc_device are not supported when targetting an FPGA part/family + TT *a_device = sycl::malloc_shared(kAMatrixSize * matrix_count, q); + TT *i_device = sycl::malloc_shared(kInverseMatrixSize * matrix_count, q); +#endif + q.memcpy(a_device, a_matrix.data(), kAMatrixSize * matrix_count * sizeof(TT)).wait(); diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/explicit_data_movement.cpp b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/explicit_data_movement.cpp index 18c2dafbe2..a3b834433c 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/explicit_data_movement.cpp +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/explicit_data_movement.cpp @@ -97,8 +97,8 @@ double SubmitExplicitKernel(queue& q, std::vector& in, h.single_task([=]() [[intel::kernel_args_restrict]] { // create device pointers to explicitly inform the compiler these // pointer reside in the device's address space - device_ptr in_ptr_d(in_ptr); - device_ptr out_ptr_d(out_ptr); + T* in_ptr_d(in_ptr); + T* out_ptr_d(out_ptr); for (size_t i = 0; i < size; i ++) { out_ptr_d[i] = in_ptr_d[i] * i; diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/io_streaming/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/io_streaming/src/CMakeLists.txt index 9ee6a58f1b..bf2752da80 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/io_streaming/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/io_streaming/src/CMakeLists.txt @@ -19,8 +19,16 @@ if(WIN32) set(WIN_FLAG "/EHsc") endif() -# check if the BSP has USM host allocations -if(FPGA_DEVICE MATCHES ".usm.*") +# Check if the target is a BSP +if(FPGA_DEVICE MATCHES ".*:.*") + set(IS_BSP "1") + message(STATUS "Targetting a BSP.") +else() + set(IS_BSP "0") +endif() + +# Use USM host allocations if the BSP supports them or if we target an FPGA part +if((IS_BSP STREQUAL "0") OR FPGA_DEVICE MATCHES ".usm.*") set(USM_HOST_ALLOCATIONS "-DUSM_HOST_ALLOCATIONS") message(STATUS "USM host allocations are enabled") endif() diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/shannonization/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/shannonization/src/CMakeLists.txt index 3dcef8d3d9..0f7b7b0ef1 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/shannonization/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/shannonization/src/CMakeLists.txt @@ -8,7 +8,7 @@ set(REPORTS_TARGET ${TARGET_NAME}_report) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) set(FPGA_DEVICE "Agilex") - set(DEVICE_FLAG "-DAgilex") + set(DEVICE_FLAG "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ \nPlease refer to the README for information on target selection.") @@ -40,17 +40,17 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR ${DEVICE_FLAG}") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR -D${DEVICE_FLAG}") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR ${DEVICE_FLAG}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${DEVICE_FLAG} -DFPGA_HARDWARE") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR -D${DEVICE_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -D${DEVICE_FLAG} -DFPGA_HARDWARE") if(FPGA_DEVICE MATCHES ".s10.*") # hyper-optimized-handshaking only applies to Intel Stratix® 10 FPGAs - set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xshyper-optimized-handshaking=off -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") - set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xshyper-optimized-handshaking=off -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") + set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xshyper-optimized-handshaking=off -Xstarget=${FPGA_DEVICE} -D${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") + set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xshyper-optimized-handshaking=off -Xstarget=${FPGA_DEVICE} -D${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") else() - set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") - set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") + set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} -D${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") + set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} -D${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") endif() # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/simple_host_streaming/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/simple_host_streaming/src/CMakeLists.txt index 021940f4db..3ba5aa1f0d 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/simple_host_streaming/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/simple_host_streaming/src/CMakeLists.txt @@ -15,10 +15,18 @@ else() message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() +# Check if the target is a BSP +if(FPGA_DEVICE MATCHES ".*:.*") + set(IS_BSP "1") + message(STATUS "Targetting a BSP.") +else() + set(IS_BSP "0") +endif() + # this tutorial requires USM host allocations. Check the BSP name (which should contain the text 'usm') # to ensure the BSP has the required support. Allow the user to define USM_HOST_ALLOCATIONS_ENABLED # to override this check (e.g., cmake .. -DUSM_HOST_ALLOCATIONS_ENABLED=1) -if(NOT FPGA_DEVICE MATCHES ".usm.*" AND (NOT DEFINED USM_HOST_ALLOCATIONS_ENABLED OR USM_HOST_ALLOCATIONS_ENABLED STREQUAL "0")) +if((IS_BSP STREQUAL "1") AND NOT FPGA_DEVICE MATCHES ".usm.*" AND (NOT DEFINED USM_HOST_ALLOCATIONS_ENABLED OR USM_HOST_ALLOCATIONS_ENABLED STREQUAL "0")) message(FATAL_ERROR "ERROR: This tutorial requires a BSP that has USM host allocations enabled.") endif() diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/src/CMakeLists.txt index feae4be3d9..9d7c4f182a 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/src/CMakeLists.txt @@ -32,6 +32,8 @@ set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} -DFPGA_EMULATOR set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG}") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} -DFPGA_SIMULATOR -Wall ${WIN_FLAG}") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") +set(REPORT_COMPILE_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} -Wall ${WIN_FLAG} -DFPGA_REPORT") +set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} -Wall ${WIN_FLAG} -DFPGA_HARDWARE") set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation @@ -60,8 +62,8 @@ set(FPGA_EARLY_IMAGE ${TARGET_NAME}_report.a) add_executable(${FPGA_EARLY_IMAGE} ${SOURCE_FILE}) target_include_directories(${FPGA_EARLY_IMAGE} PRIVATE ../../../../include) add_custom_target(report DEPENDS ${FPGA_EARLY_IMAGE}) -set_target_properties(${FPGA_EARLY_IMAGE} PROPERTIES COMPILE_FLAGS "${HARDWARE_COMPILE_FLAGS}") -set_target_properties(${FPGA_EARLY_IMAGE} PROPERTIES LINK_FLAGS "${HARDWARE_LINK_FLAGS} -fsycl-link=early") +set_target_properties(${FPGA_EARLY_IMAGE} PROPERTIES COMPILE_FLAGS "${REPORT_COMPILE_FLAGS}") +set_target_properties(${FPGA_EARLY_IMAGE} PROPERTIES LINK_FLAGS "${REPORT_LINK_FLAGS} -fsycl-link=early") # fsycl-link=early stops the compiler after RTL generation, before invoking Quartus® ############################################################################### diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/hostpipes/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/hostpipes/src/CMakeLists.txt index eb5920954a..1ec3584420 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/hostpipes/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/hostpipes/src/CMakeLists.txt @@ -14,10 +14,18 @@ else() message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() +# Check if the target is a BSP +if(FPGA_DEVICE MATCHES ".*:.*") + set(IS_BSP "1") + message(STATUS "Targetting a BSP.") +else() + set(IS_BSP "0") +endif() + # this tutorial requires USM host allocations. Check the BSP name (which should contain the text 'usm') # to ensure the BSP has the required support. Allow the user to define USM_HOST_ALLOCATIONS_ENABLED # to override this check (e.g., cmake .. -DUSM_HOST_ALLOCATIONS_ENABLED=1) -if(NOT FPGA_DEVICE MATCHES ".usm.*" AND (NOT DEFINED USM_HOST_ALLOCATIONS_ENABLED OR USM_HOST_ALLOCATIONS_ENABLED STREQUAL "0")) +if((IS_BSP STREQUAL "1") AND NOT FPGA_DEVICE MATCHES ".usm.*" AND (NOT DEFINED USM_HOST_ALLOCATIONS_ENABLED OR USM_HOST_ALLOCATIONS_ENABLED STREQUAL "0")) message(FATAL_ERROR "ERROR: This tutorial requires a BSP that has USM host allocations enabled.") endif() @@ -46,7 +54,7 @@ set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -I${SDK_ROOT_PATH}/include -I${SDK_ROOT_PATH}/include/sycl/ext/intel/prototype -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} -Xsdsp-mode=prefer-softlogic ${USER_HARDWARE_FLAGS}") set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -I${SDK_ROOT_PATH}/include -I${SDK_ROOT_PATH}/include/sycl/ext/intel/prototype -DFPGA_HARDWARE") -set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xsboard=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") +set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation ############################################################################### @@ -84,7 +92,7 @@ set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${SIMULATOR_LIN ### Generate Report ############################################################################### # To compile manually: -# icpx -fintelfpga -Xshardware -Xsboard= -fsycl-link=early hostpipes.cpp -o hostpipes_report.a +# icpx -fintelfpga -Xshardware -Xstarget= -fsycl-link=early hostpipes.cpp -o hostpipes_report.a set(FPGA_EARLY_IMAGE ${TARGET_NAME}_report.a) # The compile output is not an executable, but an intermediate compilation result unique to SYCL. add_executable(${FPGA_EARLY_IMAGE} ${SOURCE_FILE}) @@ -98,10 +106,10 @@ set_target_properties(${FPGA_EARLY_IMAGE} PROPERTIES LINK_FLAGS "${HARDWARE_LINK ### FPGA Hardware ############################################################################### # To compile in a single command: -# icpx -fintelfpga -Xshardware -Xsboard= hostpipes.cpp -o hostpipes.fpga +# icpx -fintelfpga -Xshardware -Xstarget= hostpipes.cpp -o hostpipes.fpga # CMake executes: # [compile] icpx -fintelfpga -o hostpipes.cpp.o -c hostpipes.cpp -# [link] icpx -fintelfpga -Xshardware -Xsboard= hostpipes.cpp.o -o hostpipes.fpga +# [link] icpx -fintelfpga -Xshardware -Xstarget= hostpipes.cpp.o -o hostpipes.fpga add_executable(${FPGA_TARGET} EXCLUDE_FROM_ALL ${SOURCE_FILE}) target_include_directories(${FPGA_TARGET} PRIVATE ../../../../../include) add_custom_target(fpga DEPENDS ${FPGA_TARGET}) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_initiation_interval/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_initiation_interval/src/CMakeLists.txt index d04dbae79b..ad6da30d85 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_initiation_interval/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_initiation_interval/src/CMakeLists.txt @@ -10,7 +10,7 @@ set(FPGA_TARGET_ENABLE_II ${TARGET_NAME_ENABLE_II}.fpga) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) set(FPGA_DEVICE "Agilex") - set(DEVICE_FLAG "-DAgilex") + set(DEVICE_FLAG "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ \nPlease refer to the README for information on target selection.") @@ -41,12 +41,12 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR ${DEVICE_FLAG}") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR -D${DEVICE_FLAG}") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_SIMULATOR ${DEVICE_FLAG}") -set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${DEVICE_FLAG} -DFPGA_HARDWARE") -set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_SIMULATOR -D${DEVICE_FLAG}") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} -D${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -D${DEVICE_FLAG} -DFPGA_HARDWARE") +set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} -D${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation ############################################################################### diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/memory_attributes/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/memory_attributes/src/CMakeLists.txt index 647989136f..fca2b87415 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/memory_attributes/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/memory_attributes/src/CMakeLists.txt @@ -27,8 +27,8 @@ set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") -set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE -Xsuse-2xclock") +set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} -Xsuse-2xclock") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation ############################################################################### diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/printf/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/printf/README.md index 021fa2d20c..4222e7f1d8 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/printf/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/printf/README.md @@ -19,6 +19,8 @@ This FPGA tutorial explains how to use the `sycl::ext::oneapi::experimental::pri > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> :warning: this sample only supports emulation, unless the target is an FPGA platform (using the `-DFPGA_DEVICE=:` shown below). + ## Prerequisites This sample is part of the FPGA code samples. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/printf/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/printf/src/CMakeLists.txt index bba5f32ab2..e6e4bbeb04 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/printf/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/printf/src/CMakeLists.txt @@ -14,6 +14,18 @@ else() message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() +# Check if the target is a BSP +if(FPGA_DEVICE MATCHES ".*:.*") + set(IS_BSP "1") + message(STATUS "Targetting a BSP.") +else() + set(IS_BSP "0") +endif() + +if(IS_BSP STREQUAL "0") + message(STATUS "Only emulation is supported if no FPGA/BSP is provided as a target") +endif() + # This is a Windows-specific flag that enables exception handling in host code if(WIN32) set(WIN_FLAG "/EHsc") @@ -45,6 +57,8 @@ set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_CO set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS}") add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET}) +# The HW related targets are only supported if an FPGA/BSP is targeted +if(IS_BSP STREQUAL "1") ############################################################################### ### FPGA Simulator ############################################################################### @@ -88,3 +102,4 @@ set_target_properties(${FPGA_TARGET} PROPERTIES COMPILE_FLAGS "${HARDWARE_COMPIL set_target_properties(${FPGA_TARGET} PROPERTIES LINK_FLAGS "${HARDWARE_LINK_FLAGS} -reuse-exe=${CMAKE_BINARY_DIR}/${FPGA_TARGET}") # The -reuse-exe flag enables rapid recompilation of host-only code changes. # See C++SYCL_FPGA/GettingStarted/fast_recompile for details. +endif() diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/speculated_iterations/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/speculated_iterations/src/CMakeLists.txt index bb4641a808..9e809ef913 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/speculated_iterations/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/speculated_iterations/src/CMakeLists.txt @@ -8,7 +8,7 @@ set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) # FPGA board selection if(NOT DEFINED FPGA_DEVICE) set(FPGA_DEVICE "Agilex") - set(DEVICE_FLAG "-DAgilex") + set(DEVICE_FLAG "Agilex") message(STATUS "FPGA_DEVICE was not specified.\ \nConfiguring the design to the default FPGA family: ${FPGA_DEVICE}\ \nPlease refer to the README for information on target selection.") @@ -39,12 +39,12 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR ${DEVICE_FLAG}") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR -D${DEVICE_FLAG}") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_SIMULATOR ${DEVICE_FLAG}") -set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${DEVICE_FLAG} -DFPGA_HARDWARE") -set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_SIMULATOR -D${DEVICE_FLAG}") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} -D${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -D${DEVICE_FLAG} -DFPGA_HARDWARE") +set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} -D${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation ############################################################################### From 7083d7c275baa477f8c4d7e436b0365d8398c1c2 Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Fri, 13 Jan 2023 08:31:32 -0800 Subject: [PATCH 03/22] supporting more samples in IPA Signed-off-by: Yohann Uguen --- .../ReferenceDesigns/anr/src/CMakeLists.txt | 2 +- .../ReferenceDesigns/anr/src/anr.hpp | 8 ------- .../ReferenceDesigns/anr/src/dma_kernels.hpp | 16 +++++++++++++ .../anr/src/intensity_sigma_lut.hpp | 17 +++++++++++-- .../ReferenceDesigns/anr/src/main.cpp | 18 ++++++++++++-- .../decompress/src/CMakeLists.txt | 24 +++++++++++++------ .../decompress/src/common/common.hpp | 9 +++++++ .../src/gzip/gzip_metadata_reader.hpp | 7 ++++++ .../decompress/src/snappy/snappy_reader.hpp | 4 ++++ .../merge_sort/src/CMakeLists.txt | 23 ++++++++++++------ .../merge_sort/src/consume.hpp | 6 +++++ .../merge_sort/src/produce.hpp | 6 +++++ .../merge_sort/src/sorting_networks.hpp | 10 ++++++++ .../mvdr_beamforming/src/CMakeLists.txt | 12 +++++++++- .../explicit_data_movement/src/CMakeLists.txt | 21 +++++++++++----- .../src/explicit_data_movement.cpp | 23 ++++++++++++++++++ .../src/CMakeLists.txt | 14 ++++++----- .../src/buffer_kernel.hpp | 17 +++++++++++++ 18 files changed, 197 insertions(+), 40 deletions(-) diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/CMakeLists.txt index 6b38376d16..1350d25376 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/CMakeLists.txt @@ -149,7 +149,7 @@ set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FL set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} ${BSP_FLAG}") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} -Xssimulation -DFPGA_SIMULATOR ${BSP_FLAG}") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} ${BSP_FLAG}") -set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -Xshardware ${PROFILE_FLAG} ${FLAT_COMPILE_FLAG} -Xsparallel=2 ${SEED_FLAG} -Xstarget=${FPGA_DEVICE} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} ${IP_MODE_FLAG} ${USER_HARDWARE_FLAGS} ${BSP_FLAG}") +set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -Xshardware ${PROFILE_FLAG} ${FLAT_COMPILE_FLAG} -Xsparallel=2 ${SEED_FLAG} -Xstarget=${FPGA_DEVICE} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} ${USER_HARDWARE_FLAGS} ${BSP_FLAG}") set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} -DFPGA_HARDWARE ${BSP_FLAG}") set(HARDWARE_LINK_FLAGS "${REPORT_LINK_FLAGS} ${AC_TYPES_FLAG} ${BSP_FLAG}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/anr.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/anr.hpp index 7ed3d2fe1d..5c0de80dcf 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/anr.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/anr.hpp @@ -347,15 +347,7 @@ std::vector SubmitANRKernels(queue& q, int cols, int rows, // submit the vertical kernel using a column stencil auto vertical_kernel = q.single_task([=] { // copy host side intensity sigma LUT to the device - // For testing the kernel system as an IP and checking the area and Fmax, - // we allow the user to turn off connections to device memory. In this case - // (the DISABLE_DEVICE_MEM macro IS defined), the results will be incorrect - // since there is no way to get the data to/from the device. -#if defined(IP_MODE) - IntensitySigmaLUT sig_i_lut; -#else IntensitySigmaLUT sig_i_lut(sig_i_lut_data_ptr); -#endif // build the constexpr exp() and inverse LUT ROMs constexpr ExpLUT exp_lut; diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/dma_kernels.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/dma_kernels.hpp index 905f13f2af..127980e148 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/dma_kernels.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/dma_kernels.hpp @@ -22,11 +22,13 @@ template event SubmitInputDMA(queue &q, T *in_ptr, int rows, int cols, int frames) { using PipeType = DataBundle; +#if defined (IS_BSP) // LSU attribute to turn off caching using NonCachingLSU = ext::intel::lsu, ext::intel::cache<0>, ext::intel::statically_coalesce, ext::intel::prefetch>; +#endif // validate the number of columns if ((cols % pixels_per_cycle) != 0) { @@ -41,7 +43,12 @@ event SubmitInputDMA(queue &q, T *in_ptr, int rows, int cols, int frames) { // Using device memory return q.single_task([=]() [[intel::kernel_args_restrict]] { + +#if defined (IS_BSP) device_ptr in(in_ptr); +#else + T* in(in_ptr); +#endif // coalesce the following two loops into a single for-loop using the // loop_coalesce attribute @@ -51,7 +58,11 @@ event SubmitInputDMA(queue &q, T *in_ptr, int rows, int cols, int frames) { PipeType pipe_data; #pragma unroll for (int k = 0; k < pixels_per_cycle; k++) { +#if defined (IS_BSP) pipe_data[k] = NonCachingLSU::load(in + i * pixels_per_cycle + k); +#else + pipe_data[k] = in[i * pixels_per_cycle + k]; +#endif } Pipe::write(pipe_data); } @@ -77,7 +88,12 @@ event SubmitOutputDMA(queue &q, T *out_ptr, int rows, int cols, int frames) { // Using device memory return q.single_task([=]() [[intel::kernel_args_restrict]] { + +#if defined (IS_BSP) device_ptr out(out_ptr); +#else + T* out(out_ptr); +#endif // coalesce the following two loops into a single for-loop using the // loop_coalesce attribute diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/intensity_sigma_lut.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/intensity_sigma_lut.hpp index d35acf52d9..4367fcf5c5 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/intensity_sigma_lut.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/intensity_sigma_lut.hpp @@ -16,6 +16,7 @@ class IntensitySigmaLUT { // default constructor IntensitySigmaLUT() {} +#if defined (IS_BSP) // construct from a device_ptr (for constructing from device memory) IntensitySigmaLUT(device_ptr ptr) { // use a pipelined LSU to load from device memory since we don't @@ -25,6 +26,14 @@ class IntensitySigmaLUT { data_[i] = PipelinedLSU::load(ptr + i); } } +#else + // construct from a regular pointer + IntensitySigmaLUT(float* ptr) { + for (int i = 0; i < lut_depth; i++) { + data_[i] = ptr[i]; + } + } +#endif // construct from the ANR parameters (actually builds the LUT) IntensitySigmaLUT(ANRParams params) { @@ -39,8 +48,12 @@ class IntensitySigmaLUT { } // helper static method to allocate enough memory to hold the LUT - static float* AllocateDevice(sycl::queue& q) { + static float* Allocate(sycl::queue& q) { +#if defined (IS_BSP) float* ptr = sycl::malloc_device(lut_depth, q); +#else + float* ptr = sycl::malloc_shared(lut_depth, q); +#endif if (ptr == nullptr) { std::cerr << "ERROR: could not allocate space for 'ptr'\n"; std::terminate(); @@ -49,7 +62,7 @@ class IntensitySigmaLUT { } // helper method to copy the data to the device - sycl::event CopyDataToDevice(sycl::queue& q, float* ptr) { + sycl::event CopyData(sycl::queue& q, float* ptr) { return q.memcpy(ptr, data_, lut_depth * sizeof(float)); } diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/main.cpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/main.cpp index ad9d8ae466..649744dd88 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/main.cpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/main.cpp @@ -117,6 +117,7 @@ int main(int argc, char* argv[]) { // create the output pixels (initialize to all 0s) std::vector out_pixels(in_pixels.size(), 0); +#if defined (IS_BSP) // allocate memory on the device for the input and output PixelT *in, *out; if ((in = malloc_device(pixel_count, q)) == nullptr) { @@ -127,18 +128,31 @@ int main(int argc, char* argv[]) { std::cerr << "ERROR: could not allocate space for 'out'\n"; std::terminate(); } +#else + // allocate memory on the host for the input and output + PixelT *in, *out; + if ((in = malloc_shared(pixel_count, q)) == nullptr) { + std::cerr << "ERROR: could not allocate space for 'in'\n"; + std::terminate(); + } + if ((out = malloc_shared(pixel_count, q)) == nullptr) { + std::cerr << "ERROR: could not allocate space for 'out'\n"; + std::terminate(); + } +#endif + // copy the input data to the device memory and wait for the copy to finish q.memcpy(in, in_pixels.data(), pixel_count * sizeof(PixelT)).wait(); // allocate space for the intensity sigma LUT - float* sig_i_lut_data_ptr = IntensitySigmaLUT::AllocateDevice(q); + float* sig_i_lut_data_ptr = IntensitySigmaLUT::Allocate(q); // create the intensity sigma LUT data locally on the host IntensitySigmaLUT sig_i_lut_host(params); // copy the intensity sigma LUT to the device - sig_i_lut_host.CopyDataToDevice(q, sig_i_lut_data_ptr).wait(); + sig_i_lut_host.CopyData(q, sig_i_lut_data_ptr).wait(); ////////////////////////////////////////////////////////////////////////////// // track timing information in ms diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/CMakeLists.txt index d85aae4282..e9d83c74d9 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/CMakeLists.txt @@ -29,6 +29,16 @@ if(NOT DEFINED DEVICE_FLAG) -DDEVICE_FLAG=Agilex.") endif() +# Check if the target is a BSP +if(FPGA_DEVICE MATCHES ".*:.*") + set(IS_BSP "1") + message(STATUS "Targetting a BSP.") + set(BSP_FLAG "-DIS_BSP") +else() + set(IS_BSP "0") + set(BSP_FLAG "") +endif() + # Select between SNAPPY and GZIP decompression if(DEFINED SNAPPY AND DEFINED GZIP) message(FATAL_ERROR "Cannot compile for both SNAPPY and GZIP compression. You must define exactly one of -DSNAPPY=1 and -DGZIP=1") @@ -109,13 +119,13 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${LITERALS_PER_CYCLE_FLAG} ${DECOMPRESS_FORMAT_FLAG} -DFPGA_EMULATOR") -set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG}") -set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${LITERALS_PER_CYCLE_FLAG} ${DECOMPRESS_FORMAT_FLAG} -DFPGA_SIMULATOR") -set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${LITERALS_PER_CYCLE_FLAG} ${DECOMPRESS_FORMAT_FLAG} -DFPGA_HARDWARE") -set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -Xshardware ${PROFILE_FLAG} ${FLAT_COMPILE_FLAG} -Xsparallel=2 ${SEED_FLAG} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_LINK_FLAGS "${REPORT_LINK_FLAGS} ${AC_TYPES_FLAG}") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${LITERALS_PER_CYCLE_FLAG} ${DECOMPRESS_FORMAT_FLAG} -DFPGA_EMULATOR ${BSP_FLAG}") +set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} ${BSP_FLAG}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${LITERALS_PER_CYCLE_FLAG} ${DECOMPRESS_FORMAT_FLAG} -DFPGA_SIMULATOR ${BSP_FLAG}") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} ${BSP_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${LITERALS_PER_CYCLE_FLAG} ${DECOMPRESS_FORMAT_FLAG} -DFPGA_HARDWARE ${BSP_FLAG}") +set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -Xshardware ${PROFILE_FLAG} ${FLAT_COMPILE_FLAG} -Xsparallel=2 ${SEED_FLAG} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} ${BSP_FLAG}") +set(HARDWARE_LINK_FLAGS "${REPORT_LINK_FLAGS} ${AC_TYPES_FLAG} ${BSP_FLAG}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation ############################################################################### diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/common/common.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/common/common.hpp index 93b1e9daeb..0c0bd02e48 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/common/common.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/common/common.hpp @@ -321,7 +321,11 @@ sycl::event SubmitProducer(sycl::queue& q, unsigned in_count_padded, // GZIP and SNAPPY designs, we guarantee this in the DecompressBytes // functions in ../gzip/gzip_decompressor.hpp and // ../snappy/snappy_decompressor.hpp respectively. +#if defined (IS_BSP) sycl::device_ptr in(in_ptr); +#else + unsigned char* in(in_ptr); +#endif fpga_tools::MemoryToPipe( in, iteration_count); }); @@ -355,7 +359,12 @@ sycl::event SubmitConsumer(sycl::queue& q, unsigned out_count_padded, // elements at once from 'OutPipe' and write them to 'out_ptr'. // For details about the 'false' template parameter, see the SubmitProducer // function above. +#if defined (IS_BSP) sycl::device_ptr out(out_ptr); +#else + unsigned char* out(out_ptr); +#endif + fpga_tools::PipeToMemory( out, iteration_count); diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/gzip/gzip_metadata_reader.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/gzip/gzip_metadata_reader.hpp index 80b15d04c4..ffc108d35a 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/gzip/gzip_metadata_reader.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/gzip/gzip_metadata_reader.hpp @@ -284,9 +284,16 @@ sycl::event SubmitGzipMetadataReader(sycl::queue& q, int in_count, GzipHeaderData* hdr_data_ptr, int* crc_ptr, int* out_count_ptr) { return q.single_task([=]() [[intel::kernel_args_restrict]] { + +#if defined (IS_BSP) sycl::device_ptr hdr_data(hdr_data_ptr); sycl::device_ptr crc(crc_ptr); sycl::device_ptr out_count(out_count_ptr); +#else + GzipHeaderData* hdr_data(hdr_data_ptr); + int* crc(crc_ptr); + int* out_count(out_count_ptr); +#endif // local copies of the output data GzipHeaderData hdr_data_loc; diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/snappy/snappy_reader.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/snappy/snappy_reader.hpp index ed93d66b80..abe0b0fb56 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/snappy/snappy_reader.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/snappy/snappy_reader.hpp @@ -385,7 +385,11 @@ template ([=] { +#if defined (IS_BSP) sycl::device_ptr preamble_count(preamble_count_ptr); +#else + unsigned* preamble_count(preamble_count_ptr); +#endif *preamble_count = SnappyReader(in_count); }); diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/CMakeLists.txt index db90e5c60e..8ddfcc2f17 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/CMakeLists.txt @@ -14,6 +14,15 @@ else() message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() +# Check if the target is a BSP +if(FPGA_DEVICE MATCHES ".*:.*") + set(IS_BSP "1") + message(STATUS "Targetting a BSP.") + set(BSP_FLAG "-DIS_BSP") +else() + set(IS_BSP "0") + set(BSP_FLAG "") +endif() # This is a Windows-specific flag that enables error handling in host code if(WIN32) @@ -22,7 +31,7 @@ endif() # check if the BSP has USM host allocations or manually enable using host allocations # e.g. cmake .. -DUSE_USM_HOST_ALLOCATIONS=1 -if(FPGA_DEVICE MATCHES ".*usm.*" OR DEFINED USE_USM_HOST_ALLOCATIONS) +if((IS_BSP STREQUAL "0") OR FPGA_DEVICE MATCHES ".*usm.*" OR DEFINED USE_USM_HOST_ALLOCATIONS) set(ENABLE_USM "-DUSM_HOST_ALLOCATIONS") message(STATUS "USM host allocations are enabled") endif() @@ -67,12 +76,12 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG} -DFPGA_EMULATOR") -set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG}") -set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG}") -set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG} -DFPGA_HARDWARE") -set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware ${PROFILE_FLAG} -Xsparallel=2 ${SEED_FLAG} -Xstarget=${FPGA_DEVICE} ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG} ${USER_HARDWARE_FLAGS}") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG} -DFPGA_EMULATOR ${BSP_FLAG}") +set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG} ${BSP_FLAG}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG} ${BSP_FLAG}") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG} ${USER_HARDWARE_FLAGS} ${BSP_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG} -DFPGA_HARDWARE ${BSP_FLAG}") +set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware ${PROFILE_FLAG} -Xsparallel=2 ${SEED_FLAG} -Xstarget=${FPGA_DEVICE} ${ENABLE_USM} ${MERGE_UNITS_FLAG} ${SORT_WIDTH_FLAG} ${USER_HARDWARE_FLAGS} ${BSP_FLAG}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation ############################################################################### diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/consume.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/consume.hpp index ccaaf788b6..7d74bae1b5 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/consume.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/consume.hpp @@ -22,7 +22,13 @@ event Consume(queue& q, ValueT* out_ptr, IndexT total_count, IndexT offset, // Creating a device_ptr tells the compiler that this pointer is in // device memory, not host memory, and avoids creating extra connections // to host memory + // This is only done in the case where we target a BSP as device + // pointers are not supported when targeting an FPGA family/part +#if defined(IS_BSP) device_ptr out(out_ptr); +#else + ValueT* out(out_ptr); +#endif for (IndexT i = 0; i < iterations; i++) { // get the data from the pipe diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/produce.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/produce.hpp index 68b945fa98..c5cc08b4fa 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/produce.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/produce.hpp @@ -24,7 +24,13 @@ event Produce(queue& q, ValueT *in_ptr, IndexT count, IndexT in_block_count, // Creating a device_ptr tells the compiler that this pointer is in // device memory, not host memory, and avoids creating extra connections // to host memory + // This is only done in the case where we target a BSP as device + // pointers are not supported when targeting an FPGA family/part +#if defined(IS_BSP) device_ptr in(in_ptr); +#else + ValueT* in(in_ptr); +#endif for (IndexT i = 0; i < iterations; i++) { // read 'k_width' elements from device memory diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/sorting_networks.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/sorting_networks.hpp index 46a7a3d4b8..487bac5a9f 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/sorting_networks.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/sorting_networks.hpp @@ -104,7 +104,17 @@ event SortNetworkKernel(queue& q, ValueT* out_ptr, IndexT total_count, const IndexT iterations = total_count / k_width; return q.single_task([=]() [[intel::kernel_args_restrict]] { + // Creating a device_ptr tells the compiler that this pointer is in + // device memory, not host memory, and avoids creating extra connections + // to host memory + // This is only done in the case where we target a BSP as device + // pointers are not supported when targeting an FPGA family/part +#if defined(IS_BSP) device_ptr out(out_ptr); +#else + ValueT* out(out_ptr); +#endif + for (IndexT i = 0; i < iterations; i++) { // read the input data from the pipe sycl::vec data = InPipe::read(); diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/CMakeLists.txt index 8e7846aff2..28040d779f 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/CMakeLists.txt @@ -14,8 +14,18 @@ else() message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() +# Check if the target is a BSP +if(FPGA_DEVICE MATCHES ".*:.*") + set(IS_BSP "1") + message(STATUS "Targetting a BSP.") + set(BSP_FLAG "-DIS_BSP") +else() + set(IS_BSP "0") + set(BSP_FLAG "") +endif() + # check if the BSP has USM host allocations -if(FPGA_DEVICE MATCHES ".usm.*") +if((IS_BSP STREQUAL "0") OR FPGA_DEVICE MATCHES ".usm.*") set(ENABLE_USM "-DUSM_HOST_ALLOCATIONS") message(STATUS "USM host allocations are enabled") endif() diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/CMakeLists.txt index 001a1ce04a..68c56924ea 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/CMakeLists.txt @@ -14,6 +14,15 @@ else() message(STATUS "Configuring the design with the following target: ${FPGA_DEVICE}") endif() +# Check if the target is a BSP +if(FPGA_DEVICE MATCHES ".*:.*") + set(IS_BSP "1") + message(STATUS "Targetting a BSP.") + set(BSP_FLAG "-DIS_BSP") +else() + set(IS_BSP "0") + set(BSP_FLAG "") +endif() # This is a Windows-specific flag that enables exception handling in host code if(WIN32) @@ -24,12 +33,12 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR") -set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR") -set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE") -set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_EMULATOR ${BSP_FLAG}") +set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${BSP_FLAG}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -DFPGA_SIMULATOR ${BSP_FLAG}") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} ${BSP_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -DFPGA_HARDWARE ${BSP_FLAG}") +set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} ${BSP_FLAG}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation ############################################################################### diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/explicit_data_movement.cpp b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/explicit_data_movement.cpp index a3b834433c..084a3f5bee 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/explicit_data_movement.cpp +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/explicit_data_movement.cpp @@ -36,8 +36,24 @@ double SubmitImplicitKernel(queue& q, std::vector& in, std::vector& out, // launch the computation kernel auto kernel_event = q.submit([&](handler& h) { + +#if defined (IS_BSP) accessor in_a(in_buf, h, read_only); accessor out_a(out_buf, h, write_only, no_init); +#else + // When targeting an FPGA family/part, the compiler does not know + // if the two kernels accesses the same memory location + // With this property, we tell the compiler that these buffers + // are in a location "1" whereas the pointers from ExplicitKernel + // are in the default location "0" + sycl::ext::oneapi::accessor_property_list location_of_buffer{ + ext::intel::buffer_location<1>}; + accessor in_a(in_buf, h, read_only, location_of_buffer); + + sycl::ext::oneapi::accessor_property_list location_of_buffer_no_init{ + no_init, ext::intel::buffer_location<1>}; + accessor out_a(out_buf, h, write_only, location_of_buffer_no_init); +#endif h.single_task([=]() [[intel::kernel_args_restrict]] { for (size_t i = 0; i < size; i ++) { @@ -68,9 +84,16 @@ double SubmitImplicitKernel(queue& q, std::vector& in, std::vector& out, template double SubmitExplicitKernel(queue& q, std::vector& in, std::vector& out, size_t size) { +#if defined (IS_BSP) // allocate the device memory T* in_ptr = malloc_device(size, q); T* out_ptr = malloc_device(size, q); +#else + // allocate the shared memory as device memory allocation is not supported + // when targeting an FPGA family/part + T* in_ptr = malloc_shared(size, q); + T* out_ptr = malloc_shared(size, q); +#endif // ensure we successfully allocated the device memory if(in_ptr == nullptr) { diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/src/CMakeLists.txt index be28c1e347..8292a60b16 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/src/CMakeLists.txt @@ -19,8 +19,10 @@ endif() if(FPGA_DEVICE MATCHES ".*:.*") set(IS_BSP "1") message(STATUS "Targetting a BSP.") + set(BSP_FLAG "-DIS_BSP") else() set(IS_BSP "0") + set(BSP_FLAG "") endif() # this tutorial requires USM host allocations. Check the BSP name (which should contain the text 'usm') @@ -43,12 +45,12 @@ endif() # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Wall -DFPGA_EMULATOR ${DEVICE_FLAG}") -set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -Wall -DFPGA_SIMULATOR ${DEVICE_FLAG}") -set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xshyper-optimized-handshaking=off -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_SIMULATOR_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Wall ${DEVICE_FLAG} -DFPGA_HARDWARE") -set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xshyper-optimized-handshaking=off -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_HARDWARE_FLAGS}") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Wall -DFPGA_EMULATOR ${DEVICE_FLAG} ${BSP_FLAG}") +set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${BSP_FLAG}") +set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Xssimulation -Wall -DFPGA_SIMULATOR ${DEVICE_FLAG} ${BSP_FLAG}") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xshyper-optimized-handshaking=off -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_SIMULATOR_FLAGS} ${BSP_FLAG}") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -Wall ${DEVICE_FLAG} -DFPGA_HARDWARE ${BSP_FLAG}") +set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xshyper-optimized-handshaking=off -Xstarget=${FPGA_DEVICE} ${DEVICE_FLAG} ${USER_HARDWARE_FLAGS} ${BSP_FLAG}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation ############################################################################### diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/src/buffer_kernel.hpp b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/src/buffer_kernel.hpp index 9b86facc61..b06c2b0886 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/src/buffer_kernel.hpp +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/src/buffer_kernel.hpp @@ -28,8 +28,25 @@ double SubmitBufferKernel(queue& q, std::vector& in, std::vector& out, // launch the computation kernel auto kernel_event = q.submit([&](handler& h) { + +#if defined (IS_BSP) accessor in_a(in_buf, h, read_only); accessor out_a(out_buf, h, write_only, no_init); +#else + // When targeting an FPGA family/part, the compiler does not know + // if the two kernels accesses the same memory location + // With this property, we tell the compiler that these buffers + // are in a location "1" whereas the pointers from ExplicitKernel + // are in the default location "0" + sycl::ext::oneapi::accessor_property_list location_of_buffer{ + ext::intel::buffer_location<1>}; + accessor in_a(in_buf, h, read_only, location_of_buffer); + + sycl::ext::oneapi::accessor_property_list location_of_buffer_no_init{ + no_init, ext::intel::buffer_location<1>}; + accessor out_a(out_buf, h, write_only, location_of_buffer_no_init); +#endif + h.single_task([=]() [[intel::kernel_args_restrict]] { for (size_t i = 0; i < size; i++) { From 1b13aa7900e71bc52df1f6420ec1e39cc3db04d6 Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Fri, 13 Jan 2023 09:02:51 -0800 Subject: [PATCH 04/22] improve comments when using IS_BSP Signed-off-by: Yohann Uguen --- .../cholesky/src/cholesky.hpp | 16 +++++++-- .../cholesky/src/memory_transfers.hpp | 16 +++++++-- .../src/memory_transfers.hpp | 32 +++++++++++++++--- .../decompress/src/common/common.hpp | 13 ++++++++ .../src/gzip/gzip_metadata_reader.hpp | 12 +++++-- .../decompress/src/snappy/snappy_reader.hpp | 6 ++++ .../qrd/src/memory_transfers.hpp | 33 ++++++++++++++++--- .../ReferenceDesigns/qrd/src/qrd.hpp | 15 ++++++++- .../qri/src/memory_transfers.hpp | 32 +++++++++++++++--- .../src/explicit_data_movement.cpp | 9 ++++- .../Features/printf/src/CMakeLists.txt | 2 +- 11 files changed, 164 insertions(+), 22 deletions(-) diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/cholesky.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/cholesky.hpp index edb8881528..80bc2df92d 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/cholesky.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/cholesky.hpp @@ -109,6 +109,18 @@ void CholeskyDecompositionImpl( for (int li = 0; li < kLoopIter; li++) { TT bank[kNumElementsPerDDRBurst]; +#if defined (IS_BSP) + // When targeting a BSP, we instruct the compiler that this pointer + // lives on the device. + // Knowing this, the compiler won't generate hardware to + // potentially get data from the host. + sycl::device_ptr vector_ptr(l_device); +#else + // Device pointers are not supported when targeting an FPGA + // family/part + TT* vector_ptr(l_device); +#endif + for (int k = 0; k < kNumElementsPerDDRBurst; k++) { if (((li * kNumElementsPerDDRBurst) + k) < kLMatrixSize) { bank[k] = LMatrixPipe::read(); @@ -121,7 +133,7 @@ void CholeskyDecompositionImpl( #pragma unroll for (int k = 0; k < kNumElementsPerDDRBurst; k++) { if (((li * kNumElementsPerDDRBurst) + k) < kLMatrixSize) { - l_device[(matrix_idx * kLMatrixSize) + + vector_ptr[(matrix_idx * kLMatrixSize) + (li * kNumElementsPerDDRBurst) + k] = bank[k]; } } @@ -129,7 +141,7 @@ void CholeskyDecompositionImpl( // Write a burst of kNumElementsPerDDRBurst elements to DDR #pragma unroll for (int k = 0; k < kNumElementsPerDDRBurst; k++) { - l_device[(matrix_idx * kLMatrixSize) + + vector_ptr[(matrix_idx * kLMatrixSize) + (li * kNumElementsPerDDRBurst) + k] = bank[k]; } } diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/memory_transfers.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/memory_transfers.hpp index 44bb9d8a8d..f587925870 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/memory_transfers.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/memory_transfers.hpp @@ -45,6 +45,18 @@ void MatrixReadFromDDRToPipe( // Only useful in the case of kIncompleteBurst int load_index = 0; +#if defined (IS_BSP) + // When targeting a BSP, we instruct the compiler that this pointer + // lives on the device. + // Knowing this, the compiler won't generate hardware to + // potentially get data from the host. + sycl::device_ptr matrix_ptr_located(matrix_ptr); +#else + // Device pointers are not supported when targeting an FPGA + // family/part + TT* matrix_ptr_located(matrix_ptr); +#endif + [[intel::initiation_interval(1)]] // NO-FORMAT: Attribute for (ac_int li = 0; li < kLoopIter; li++) { bool last_burst_of_col; @@ -69,12 +81,12 @@ void MatrixReadFromDDRToPipe( // memory address that may be beyond the matrix last address) if (!out_of_bounds) { ddr_read.template get() = - matrix_ptr[matrix_index * kMatrixSize + load_index + + matrix_ptr_located[matrix_index * kMatrixSize + load_index + k]; } } else { ddr_read.template get() = - matrix_ptr[matrix_index * kMatrixSize + + matrix_ptr_located[matrix_index * kMatrixSize + (int)(li)*num_elem_per_bank + k]; } }); diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/memory_transfers.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/memory_transfers.hpp index 1c44f3e38f..4644e6c954 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/memory_transfers.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/memory_transfers.hpp @@ -38,6 +38,18 @@ void MatrixReadFromDDRToPipe( // Size of a full matrix constexpr int kMatrixSize = rows * columns; +#if defined (IS_BSP) + // When targeting a BSP, we instruct the compiler that this pointer + // lives on the device. + // Knowing this, the compiler won't generate hardware to + // potentially get data from the host. + sycl::device_ptr matrix_ptr_located(matrix_ptr); +#else + // Device pointers are not supported when targeting an FPGA + // family/part + TT* matrix_ptr_located(matrix_ptr); +#endif + // Repeatedly read matrix_count matrices from the DDR and send them to the // pipe for (int repetition = 0; repetition < repetitions; repetition++) { @@ -70,12 +82,12 @@ void MatrixReadFromDDRToPipe( // memory address that may be beyond the matrix last address) if (!out_of_bounds) { ddr_read.template get() = - matrix_ptr[matrix_index * kMatrixSize + load_index + + matrix_ptr_located[matrix_index * kMatrixSize + load_index + k]; } } else { ddr_read.template get() = - matrix_ptr[matrix_index * kMatrixSize + + matrix_ptr_located[matrix_index * kMatrixSize + (int)(li)*num_elem_per_bank + k]; } }); @@ -116,6 +128,18 @@ void VectorReadFromPipeToDDR( constexpr int kExtraIteration = kIncompleteBurst ? 1 : 0; constexpr int kLoopIter = (vector_size / num_elem_per_bank) + kExtraIteration; +#if defined (IS_BSP) + // When targeting a BSP, we instruct the compiler that this pointer + // lives on the device. + // Knowing this, the compiler won't generate hardware to + // potentially get data from the host. + sycl::device_ptr vector_ptr_located(vector_ptr); +#else + // Device pointers are not supported when targeting an FPGA + // family/part + TT* vector_ptr_located(vector_ptr); +#endif + // Repeat vector_count complete I vector pipe reads // for as many repetitions as needed for (int rep_idx = 0; rep_idx < repetitions; rep_idx++) { @@ -135,7 +159,7 @@ void VectorReadFromPipeToDDR( #pragma unroll for (int k = 0; k < num_elem_per_bank; k++) { if (((li * num_elem_per_bank) + k) < vector_size) { - vector_ptr[(vector_idx * vector_size) + + vector_ptr_located[(vector_idx * vector_size) + (li * num_elem_per_bank) + k] = bank[k]; } } @@ -143,7 +167,7 @@ void VectorReadFromPipeToDDR( // Write a burst of num_elem_per_bank elements to DDR #pragma unroll for (int k = 0; k < num_elem_per_bank; k++) { - vector_ptr[(vector_idx * vector_size) + + vector_ptr_located[(vector_idx * vector_size) + (li * num_elem_per_bank) + k] = bank[k]; } } diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/common/common.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/common/common.hpp index 0c0bd02e48..e379258e89 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/common/common.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/common/common.hpp @@ -322,8 +322,14 @@ sycl::event SubmitProducer(sycl::queue& q, unsigned in_count_padded, // functions in ../gzip/gzip_decompressor.hpp and // ../snappy/snappy_decompressor.hpp respectively. #if defined (IS_BSP) + // When targeting a BSP, we instruct the compiler that this pointer + // lives on the device. + // Knowing this, the compiler won't generate hardware to + // potentially get data from the host. sycl::device_ptr in(in_ptr); #else + // Device pointers are not supported when targeting an FPGA + // family/part unsigned char* in(in_ptr); #endif fpga_tools::MemoryToPipe( @@ -359,9 +365,16 @@ sycl::event SubmitConsumer(sycl::queue& q, unsigned out_count_padded, // elements at once from 'OutPipe' and write them to 'out_ptr'. // For details about the 'false' template parameter, see the SubmitProducer // function above. + #if defined (IS_BSP) + // When targeting a BSP, we instruct the compiler that this pointer + // lives on the device. + // Knowing this, the compiler won't generate hardware to + // potentially get data from the host. sycl::device_ptr out(out_ptr); #else + // Device pointers are not supported when targeting an FPGA + // family/part unsigned char* out(out_ptr); #endif diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/gzip/gzip_metadata_reader.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/gzip/gzip_metadata_reader.hpp index ffc108d35a..d042458173 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/gzip/gzip_metadata_reader.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/gzip/gzip_metadata_reader.hpp @@ -286,13 +286,19 @@ sycl::event SubmitGzipMetadataReader(sycl::queue& q, int in_count, return q.single_task([=]() [[intel::kernel_args_restrict]] { #if defined (IS_BSP) + // When targeting a BSP, we instruct the compiler that this pointer + // lives on the device. + // Knowing this, the compiler won't generate hardware to + // potentially get data from the host. sycl::device_ptr hdr_data(hdr_data_ptr); sycl::device_ptr crc(crc_ptr); sycl::device_ptr out_count(out_count_ptr); #else - GzipHeaderData* hdr_data(hdr_data_ptr); - int* crc(crc_ptr); - int* out_count(out_count_ptr); + // Device pointers are not supported when targeting an FPGA + // family/part + GzipHeaderData* hdr_data(hdr_data_ptr); + int* crc(crc_ptr); + int* out_count(out_count_ptr); #endif // local copies of the output data diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/snappy/snappy_reader.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/snappy/snappy_reader.hpp index abe0b0fb56..e41a9af598 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/snappy/snappy_reader.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/snappy/snappy_reader.hpp @@ -386,8 +386,14 @@ sycl::event SubmitSnappyReader(sycl::queue& q, unsigned in_count, unsigned* preamble_count_ptr) { return q.single_task([=] { #if defined (IS_BSP) + // When targeting a BSP, we instruct the compiler that this pointer + // lives on the device. + // Knowing this, the compiler won't generate hardware to + // potentially get data from the host. sycl::device_ptr preamble_count(preamble_count_ptr); #else + // Device pointers are not supported when targeting an FPGA + // family/part unsigned* preamble_count(preamble_count_ptr); #endif *preamble_count = diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/memory_transfers.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/memory_transfers.hpp index 35a568ac62..62f575b87f 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/memory_transfers.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/memory_transfers.hpp @@ -37,6 +37,18 @@ void MatrixReadFromDDRToPipe( // Size of a full matrix constexpr int kMatrixSize = rows * columns; +#if defined (IS_BSP) + // When targeting a BSP, we instruct the compiler that this pointer + // lives on the device. + // Knowing this, the compiler won't generate hardware to + // potentially get data from the host. + sycl::device_ptr matrix_ptr_located(matrix_ptr); +#else + // Device pointers are not supported when targeting an FPGA + // family/part + TT* matrix_ptr_located(matrix_ptr); +#endif + // Repeatedly read matrix_count matrices from DDR and sends them to the pipe for (int repetition = 0; repetition < repetitions; repetition++){ @@ -70,12 +82,12 @@ void MatrixReadFromDDRToPipe( // Only perform the DDR reads that are relevant (and don't access a // memory address that may be beyond the matrix last address) if (!out_of_bounds) { - ddr_read.template get() = matrix_ptr + ddr_read.template get() = matrix_ptr_located [matrix_index * kMatrixSize + load_index + k]; } } else{ - ddr_read.template get() = matrix_ptr + ddr_read.template get() = matrix_ptr_located [matrix_index * kMatrixSize + (int)(li)*num_elem_per_bank + k]; } @@ -126,6 +138,19 @@ void MatrixReadPipeToDDR( // Size of a full matrix constexpr int kMatrixSize = rows * columns; +#if defined (IS_BSP) + // When targeting a BSP, we instruct the compiler that this pointer + // lives on the device. + // Knowing this, the compiler won't generate hardware to + // potentially get data from the host. + sycl::device_ptr matrix_ptr_located(matrix_ptr); +#else + // Device pointers are not supported when targeting an FPGA + // family/part + TT* matrix_ptr_located(matrix_ptr); +#endif + + // Repeatedly read matrix_count matrices from the pipe and write them to DDR for (int repetition = 0; repetition < repetitions; repetition++){ @@ -157,12 +182,12 @@ void MatrixReadPipeToDDR( // Only perform the DDR writes that are relevant (and don't access a // memory address that may be beyond the buffer last address) if (!out_of_bounds) { - matrix_ptr[matrix_index * kMatrixSize + write_idx + k] = + matrix_ptr_located[matrix_index * kMatrixSize + write_idx + k] = pipe_read.template get(); } } else{ - matrix_ptr[matrix_index * kMatrixSize + matrix_ptr_located[matrix_index * kMatrixSize + int(li) * num_elem_per_bank + k] = pipe_read.template get(); } diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/qrd.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/qrd.hpp index 0adb1f3d54..79dceffa08 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/qrd.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/qrd.hpp @@ -103,6 +103,19 @@ void QRDecompositionImpl( ]() [[intel::kernel_args_restrict]] { // Read the R matrix from the RMatrixPipe pipe and copy it to the // FPGA DDR + +#if defined (IS_BSP) + // When targeting a BSP, we instruct the compiler that this pointer + // lives on the device. + // Knowing this, the compiler won't generate hardware to + // potentially get data from the host. + sycl::device_ptr vector_ptr_located(r_device); +#else + // Device pointers are not supported when targeting an FPGA + // family/part + TT* vector_ptr_located(r_device); +#endif + // Repeat matrix_count complete R matrix pipe reads // for as many repetitions as needed for (int repetition_index = 0; repetition_index < repetitions; @@ -111,7 +124,7 @@ void QRDecompositionImpl( [[intel::loop_coalesce(2)]] // NO-FORMAT: Attribute for (int matrix_index = 0; matrix_index < matrix_count; matrix_index++) { for (int r_idx = 0; r_idx < kRMatrixSize; r_idx++) { - r_device[matrix_index * kRMatrixSize + r_idx] = + vector_ptr_located[matrix_index * kRMatrixSize + r_idx] = RMatrixPipe::read(); } // end of r_idx } // end of repetition_index diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/memory_transfers.hpp b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/memory_transfers.hpp index 35a568ac62..7a57aca79a 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/memory_transfers.hpp +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/memory_transfers.hpp @@ -37,6 +37,18 @@ void MatrixReadFromDDRToPipe( // Size of a full matrix constexpr int kMatrixSize = rows * columns; +#if defined (IS_BSP) + // When targeting a BSP, we instruct the compiler that this pointer + // lives on the device. + // Knowing this, the compiler won't generate hardware to + // potentially get data from the host. + sycl::device_ptr matrix_ptr_located(matrix_ptr); +#else + // Device pointers are not supported when targeting an FPGA + // family/part + TT* matrix_ptr_located(matrix_ptr); +#endif + // Repeatedly read matrix_count matrices from DDR and sends them to the pipe for (int repetition = 0; repetition < repetitions; repetition++){ @@ -70,12 +82,12 @@ void MatrixReadFromDDRToPipe( // Only perform the DDR reads that are relevant (and don't access a // memory address that may be beyond the matrix last address) if (!out_of_bounds) { - ddr_read.template get() = matrix_ptr + ddr_read.template get() = matrix_ptr_located [matrix_index * kMatrixSize + load_index + k]; } } else{ - ddr_read.template get() = matrix_ptr + ddr_read.template get() = matrix_ptr_located [matrix_index * kMatrixSize + (int)(li)*num_elem_per_bank + k]; } @@ -126,6 +138,18 @@ void MatrixReadPipeToDDR( // Size of a full matrix constexpr int kMatrixSize = rows * columns; +#if defined (IS_BSP) + // When targeting a BSP, we instruct the compiler that this pointer + // lives on the device. + // Knowing this, the compiler won't generate hardware to + // potentially get data from the host. + sycl::device_ptr matrix_ptr_located(matrix_ptr); +#else + // Device pointers are not supported when targeting an FPGA + // family/part + TT* matrix_ptr_located(matrix_ptr); +#endif + // Repeatedly read matrix_count matrices from the pipe and write them to DDR for (int repetition = 0; repetition < repetitions; repetition++){ @@ -157,12 +181,12 @@ void MatrixReadPipeToDDR( // Only perform the DDR writes that are relevant (and don't access a // memory address that may be beyond the buffer last address) if (!out_of_bounds) { - matrix_ptr[matrix_index * kMatrixSize + write_idx + k] = + matrix_ptr_located[matrix_index * kMatrixSize + write_idx + k] = pipe_read.template get(); } } else{ - matrix_ptr[matrix_index * kMatrixSize + matrix_ptr_located[matrix_index * kMatrixSize + int(li) * num_elem_per_bank + k] = pipe_read.template get(); } diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/explicit_data_movement.cpp b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/explicit_data_movement.cpp index 084a3f5bee..2e6fa9085a 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/explicit_data_movement.cpp +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/src/explicit_data_movement.cpp @@ -120,9 +120,16 @@ double SubmitExplicitKernel(queue& q, std::vector& in, h.single_task([=]() [[intel::kernel_args_restrict]] { // create device pointers to explicitly inform the compiler these // pointer reside in the device's address space +#if defined (IS_BSP) + device_ptr in_ptr_d(in_ptr); + device_ptr out_ptr_d(out_ptr); +#else + // device pointers are not supported + // when targeting an FPGA family/part T* in_ptr_d(in_ptr); T* out_ptr_d(out_ptr); - +#endif + for (size_t i = 0; i < size; i ++) { out_ptr_d[i] = in_ptr_d[i] * i; } diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/printf/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/printf/src/CMakeLists.txt index e6e4bbeb04..e20cd412b6 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/printf/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/printf/src/CMakeLists.txt @@ -57,7 +57,7 @@ set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_CO set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS}") add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET}) -# The HW related targets are only supported if an FPGA/BSP is targeted +# The HW related targets are only supported if an BSP is being targeted if(IS_BSP STREQUAL "1") ############################################################################### ### FPGA Simulator From 6e6e9dc5bb48fbcf4a70172d6bd821af5d91c330 Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Mon, 16 Jan 2023 02:55:26 -0800 Subject: [PATCH 05/22] fix cmakes Signed-off-by: Yohann Uguen --- .../C++SYCL_FPGA/ReferenceDesigns/anr/src/CMakeLists.txt | 2 +- .../C++SYCL_FPGA/ReferenceDesigns/decompress/src/CMakeLists.txt | 2 +- .../ReferenceDesigns/mvdr_beamforming/src/CMakeLists.txt | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/CMakeLists.txt index 1350d25376..ea80bbc464 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/CMakeLists.txt @@ -148,7 +148,7 @@ endif() set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} -DFPGA_EMULATOR ${BSP_FLAG}") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} ${BSP_FLAG}") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} -Xssimulation -DFPGA_SIMULATOR ${BSP_FLAG}") -set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} ${BSP_FLAG}") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} ${AC_TYPES_FLAG} ${BSP_FLAG}") set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -Xshardware ${PROFILE_FLAG} ${FLAT_COMPILE_FLAG} -Xsparallel=2 ${SEED_FLAG} -Xstarget=${FPGA_DEVICE} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} ${USER_HARDWARE_FLAGS} ${BSP_FLAG}") set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} -DFPGA_HARDWARE ${BSP_FLAG}") set(HARDWARE_LINK_FLAGS "${REPORT_LINK_FLAGS} ${AC_TYPES_FLAG} ${BSP_FLAG}") diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/CMakeLists.txt index e9d83c74d9..8840cd163b 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/src/CMakeLists.txt @@ -122,7 +122,7 @@ endif() set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${LITERALS_PER_CYCLE_FLAG} ${DECOMPRESS_FORMAT_FLAG} -DFPGA_EMULATOR ${BSP_FLAG}") set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} ${BSP_FLAG}") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${LITERALS_PER_CYCLE_FLAG} ${DECOMPRESS_FORMAT_FLAG} -DFPGA_SIMULATOR ${BSP_FLAG}") -set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} ${BSP_FLAG}") +set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} ${AC_TYPES_FLAG} ${BSP_FLAG}") set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} ${AC_TYPES_FLAG} ${LITERALS_PER_CYCLE_FLAG} ${DECOMPRESS_FORMAT_FLAG} -DFPGA_HARDWARE ${BSP_FLAG}") set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -Xshardware ${PROFILE_FLAG} ${FLAT_COMPILE_FLAG} -Xsparallel=2 ${SEED_FLAG} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} ${BSP_FLAG}") set(HARDWARE_LINK_FLAGS "${REPORT_LINK_FLAGS} ${AC_TYPES_FLAG} ${BSP_FLAG}") diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/CMakeLists.txt index 28040d779f..31570ed067 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/CMakeLists.txt @@ -100,7 +100,7 @@ set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -fbracket-depth set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} ${ENABLE_USM}") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} -fbracket-depth=512 ${AC_TYPES_FLAG} ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${STREAMING_PIPE_WIDTH_FLAG} -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Wall -fbracket-depth=512 ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${REAL_IO_PIPES_FLAG} ${STREAMING_PIPE_WIDTH_FLAG} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} ${UDP_LINK_FLAGS} ${AC_TYPES_FLAG} -Xssimulation -Xsghdl") -set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga ${WIN_FLAG} -fbracket-depth=512 ${AC_TYPES_FLAG} ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${REAL_IO_PIPES_FLAG} ${STREAMING_PIPE_WIDTH_FLAG} -FPGA_HARDWARE") +set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga ${WIN_FLAG} -fbracket-depth=512 ${AC_TYPES_FLAG} ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${REAL_IO_PIPES_FLAG} ${STREAMING_PIPE_WIDTH_FLAG} -DFPGA_HARDWARE") set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -Wall -Xshardware -fbracket-depth=512 ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${REAL_IO_PIPES_FLAG} ${STREAMING_PIPE_WIDTH_FLAG} ${PROFILE_FLAG} -Xsparallel=2 -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} ${UDP_LINK_FLAGS}") set(HARDWARE_LINK_FLAGS "${REPORT_LINK_FLAGS} ${AC_TYPES_FLAG}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation From a2961c1c06654e7a3b38b9a0c2e0cddcba9671bc Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Tue, 17 Jan 2023 02:52:14 -0800 Subject: [PATCH 06/22] updating fpga_compile readme Signed-off-by: Yohann Uguen --- .../GettingStarted/fpga_compile/README.md | 68 +++++++++++-------- 1 file changed, 40 insertions(+), 28 deletions(-) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/README.md index e6209ff515..a52d8ad4e0 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/README.md @@ -2,9 +2,9 @@ This FPGA tutorial introduces how to compile SYCL*-compliant code for FPGA through a simple vector addition example. If you are new to SYCL* for FPGA, start with this sample. | Optimized for | Description -|:--- |:--- +|:--- |:--- | OS | Linux* Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA
Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX)
Intel® FPGA 3rd party / custom platforms with oneAPI support
*__Note__: Intel® FPGA PAC hardware is only compatible with Ubuntu 18.04* +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler | What you will learn | How and why compiling SYCL* code for FPGA differs from CPU or GPU
FPGA device image types and when to use them
The compile options used to target FPGA | Time to complete | 15 minutes @@ -17,6 +17,10 @@ This FPGA tutorial introduces how to compile SYCL*-compliant code for FPGA throu > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ## Prerequisites @@ -61,12 +65,11 @@ The three types of FPGA compilation are summarized in the table below. --- |--- |--- | FPGA Emulator | seconds | The FPGA device code is compiled to the CPU.
This is used to verify the code's functional correctness. | Optimization Report | minutes | The FPGA device code is partially compiled for hardware.
The compiler generates an optimization report that describes the structures generated on the FPGA, identifies performance bottlenecks, and estimates resource utilization. -| FPGA Hardware | hours | Generates the real FPGA bitstream to execute on the target FPGA platform +| FPGA Hardware | hours | Runs Intel® Quartus® to get accurate resource usage and fmax estimates. If a BSP is targeted, generates the real FPGA bitstream to execute on the target FPGA platform The typical FPGA development workflow is to iterate in each of these stages, refining the code using the feedback provided by that stage. Intel® recommends relying on emulation and the optimization report whenever possible. -- Compiling for FPGA emulation or generating the FPGA optimization report requires only the Intel® oneAPI DPC++/C++ Compiler (part of the Intel® oneAPI Base Toolkit). -- An FPGA hardware compile requires the Intel® FPGA Add-On for oneAPI Base Toolkit. +Compiling for FPGA emulation or generating the FPGA optimization report requires only the Intel® oneAPI DPC++/C++ Compiler (part of the Intel® oneAPI Base Toolkit). #### FPGA Emulator @@ -90,7 +93,9 @@ Optimization reports are generated after both stages. The optimization report ge The [FPGA Optimization Guide for Intel® oneAPI Toolkits Developer Guide](https://software.intel.com/content/www/us/en/develop/documentation/oneapi-fpga-optimization-guide/top/analyze-your-design.html) contains a chapter on how to analyze the reports generated after the FPGA early image and FPGA image. #### FPGA Hardware -This is a full compile through to the FPGA hardware image. You can target the Intel® PAC with Intel Arria® 10 GX FPGA, the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), or a custom device. +This is a full compile through to the FPGA hardware image. +You can target an FPGA family/part number to get accurate resource usage and fmax estimates. +You can also target a device with a BSP (e.g. the Intel® PAC with Intel Arria® 10 GX FPGA) to get an executable that can be directly executed. ### Device Selectors The following code snippet demonstrates how you can specify the target device in your source code. The selector is used to specify the target device at runtime. @@ -153,11 +158,13 @@ The compiler options used are explained in the table. | `-fsycl` | Instructs the compiler that the code is written in the SYCL language | `-fintelfpga` | Perform ahead-of-time compilation for FPGA. | `-DFPGA_EMULATOR` | Adds a preprocessor define that invokes the emulator device selector in this sample (see code snippet above). +| `-DFPGA_SIMULATOR` | Adds a preprocessor define that invokes the simulator device selector in this sample (see code snippet above). +| `-DFPGA_HARDWARE` | Adds a preprocessor define that invokes the FPGA hardware device selector in this sample (see code snippet above). | `-Xshardware` | `-Xs` is used to pass arguments to the FPGA backend.
Since the emulator is the default FPGA target, you must pass `Xshardware` to instruct the compiler to target FPGA hardware. -| `-Xstarget` | Optional argument to specify the FPGA target.
If omitted, a default FPGA board is chosen. +| `-Xstarget` | Optional argument to specify the FPGA target.
If omitted, a default FPGA board is chosen. | `-fsycl-link=early`| Instructs the compiler to stop after creating the FPGA early image (and associated optimization report). -Notice that whether you target the FPGA emulator or FPGA hardware must be specified twice: through compiler options for the ahead-of-time compilation and through the runtime device selector. +Notice that whether you target the FPGA emulator, FPGA simulator or FPGA hardware must be specified twice: through compiler options for the ahead-of-time compilation and through the runtime device selector. ## Key Concepts * How and why compiling SYCL*-compliant code to FPGA differs from CPU or GPU @@ -188,19 +195,22 @@ Notice that whether you target the FPGA emulator or FPGA hardware must be specif mkdir build cd build ``` - To compile for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: + To compile for the default target (the Agilex device family), run `cmake` using the command: ``` cmake .. ``` - Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - ``` - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - ``` - cmake .. -DFPGA_DEVICE=: - ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: @@ -229,19 +239,21 @@ Notice that whether you target the FPGA emulator or FPGA hardware must be specif mkdir build cd build ``` - To compile for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: + To compile for the default target (the Agilex device family), run `cmake` using the command: ``` cmake -G "NMake Makefiles" .. ``` - Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: - ``` +> **Note**: You can change the default target by using the command: +> ``` +> cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= +> ``` +> +> Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: +> ``` +> cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: +> ``` +> +> You will only be able to run an executable on the FPGA if you specified a BSP. 2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: @@ -289,7 +301,7 @@ Browse the reports that were generated for the `VectorAdd` kernel's FPGA early i fpga_compile.fpga_sim.exe set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run the sample on the FPGA device: +3. Run the sample on the FPGA device (only if you ran cmake with `-DFPGA_DEVICE=:`): ``` ./fpga_compile.fpga (Linux) fpga_compile.fpga.exe (Windows) From 2a79ffc1db14e0f6baaf154974a27211806bbeac Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Thu, 19 Jan 2023 00:50:08 -0800 Subject: [PATCH 07/22] Initial update of all the READMEs Signed-off-by: Yohann Uguen --- DirectProgramming/C++SYCL_FPGA/README.md | 2 - .../ReferenceDesigns/anr/README.md | 53 +++++--- .../ReferenceDesigns/board_test/README.md | 84 ++++++++----- .../ReferenceDesigns/cholesky/README.md | 51 +++++--- .../cholesky_inversion/README.md | 50 +++++--- .../ReferenceDesigns/crr/README.md | 50 +++++--- .../ReferenceDesigns/db/README.md | 48 +++++-- .../ReferenceDesigns/decompress/README.md | 55 +++++--- .../ReferenceDesigns/gzip/README.md | 78 +++++++----- .../ReferenceDesigns/merge_sort/README.md | 55 +++++--- .../mvdr_beamforming/README.md | 55 +++++--- .../ReferenceDesigns/qrd/README.md | 47 +++++-- .../ReferenceDesigns/qri/README.md | 48 ++++--- .../DesignPatterns/autorun/README.md | 57 +++++---- .../buffered_host_streaming/README.md | 53 +++++--- .../DesignPatterns/compute_units/README.md | 61 +++++---- .../DesignPatterns/double_buffering/README.md | 66 +++++----- .../explicit_data_movement/README.md | 62 +++++----- .../DesignPatterns/io_streaming/README.md | 61 +++++---- .../loop_carried_dependency/README.md | 62 +++++----- .../DesignPatterns/n_way_buffering/README.md | 56 +++++---- .../onchip_memory_cache/README.md | 83 +++++++------ .../optimize_inner_loop/README.md | 84 +++++++------ .../DesignPatterns/pipe_array/README.md | 82 ++++++------ .../DesignPatterns/shannonization/README.md | 85 +++++++------ .../simple_host_streaming/README.md | 75 ++++++----- .../DesignPatterns/triangular_loop/README.md | 92 +++++++------- .../zero_copy_data_transfer/README.md | 80 +++++++----- .../Tutorials/Features/ac_fixed/README.md | 95 +++++++------- .../Tutorials/Features/ac_int/README.md | 98 +++++++-------- .../Tutorials/Features/dsp_control/README.md | 98 +++++++-------- .../Features/experimental/hostpipes/README.md | 77 +++++++----- .../experimental/latency_control/README.md | 99 +++++++-------- .../Tutorials/Features/fpga_reg/README.md | 58 +++++---- .../Features/kernel_args_restrict/README.md | 94 +++++++------- .../Features/loop_coalesce/README.md | 84 +++++++------ .../Tutorials/Features/loop_fusion/README.md | 87 +++++++------ .../loop_initiation_interval/README.md | 89 ++++++------- .../Tutorials/Features/loop_ivdep/README.md | 83 +++++++------ .../Tutorials/Features/loop_unroll/README.md | 115 +++++++++-------- .../Tutorials/Features/lsu_control/README.md | 75 ++++++----- .../Features/max_interleaving/README.md | 87 +++++++------ .../Tutorials/Features/mem_channel/README.md | 94 +++++++------- .../Features/memory_attributes/README.md | 83 +++++++------ .../Tutorials/Features/pipes/README.md | 84 +++++++------ .../Tutorials/Features/printf/README.md | 77 ++++++------ .../Features/private_copies/README.md | 85 +++++++------ .../Features/read_only_cache/README.md | 98 +++++++-------- .../Features/scheduler_target_fmax/README.md | 103 ++++++++------- .../Features/speculated_iterations/README.md | 117 ++++++++++-------- .../Tutorials/Features/stall_enable/README.md | 99 ++++++++------- .../GettingStarted/fast_recompile/README.md | 75 ++++++----- .../GettingStarted/fpga_compile/README.md | 28 ++--- .../Tools/dynamic_profiler/README.md | 44 ++++--- .../Tools/system_profiling/README.md | 41 +++--- .../Tutorials/Tools/use_library/README.md | 89 ++++++------- 56 files changed, 2275 insertions(+), 1816 deletions(-) diff --git a/DirectProgramming/C++SYCL_FPGA/README.md b/DirectProgramming/C++SYCL_FPGA/README.md index 1a1a94554a..98670d92a9 100644 --- a/DirectProgramming/C++SYCL_FPGA/README.md +++ b/DirectProgramming/C++SYCL_FPGA/README.md @@ -269,8 +269,6 @@ qsub -I -l nodes=1:fpga_runtime:ppn=2 -d . Only `fpga_compile` nodes support compiling to FPGA. When compiling for FPGA hardware, increase the job timeout to 24 hours. -Executing programs on FPGA hardware is only supported on `fpga_runtime` nodes of the appropriate type, such as `fpga_runtime:arria10` or `fpga_runtime:stratix10`. - Neither compiling nor executing programs on FPGA hardware are supported on the login nodes. For more information, see the [Intel® oneAPI Base Toolkit Get Started Guide](https://devcloud.intel.com/oneapi/documentation/base-toolkit/). >**Note**: Since Intel® DevCloud for oneAPI includes the appropriate development environment already configured for you, you do not need to set environment variables. diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/README.md b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/README.md index 4ab42594ac..111beac477 100755 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/README.md +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/README.md @@ -37,7 +37,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA
FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX)
Intel Xeon® CPU E5-1650 v2 @ 3.50GHz (host machine) +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. @@ -48,6 +48,10 @@ You can also find more information about [troubleshooting build errors](/DirectP > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ## Key Implementation Details @@ -149,17 +153,26 @@ The design uses the following generic header files. ### On Linux* 1. Change to the sample directory. -2. Configure the build system for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Configure the build system for the Agilex device family, which is the default. ``` mkdir build cd build cmake .. ``` - For **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. + 3. Compile the design. (The provided targets match the recommended development flow.) 1. Compile for emulation (fast compile time, targets emulated FPGA device). @@ -185,19 +198,25 @@ The design uses the following generic header files. ### On Windows* ->**Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not yet support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - 1. Change to the sample directory. -2. Configure the build system for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Configure the build system for the Agilex device family, which is the default. ``` mkdir build cd build cmake -G "NMake Makefiles" .. ``` - To compile for the **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 3. Compile the design. (The provided targets match the recommended development flow.) @@ -229,11 +248,11 @@ The design uses the following generic header files. ``` ./anr.fpga_emu ``` -2. Run the sample on the FPGA simulator device: +2. Run the sample on the FPGA simulator device. ``` CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./anr.fpga_sim ``` -3. Alternatively, run the sample on the FPGA device. +3. Alternatively, run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` ./anr.fpga ``` @@ -244,13 +263,13 @@ The design uses the following generic header files. ``` anr.fpga_emu.exe ``` -2. Run the sample on the FPGA simulator device: +2. Run the sample on the FPGA simulator device. ``` set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 anr.fpga_sim.exe set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Alternatively, run the sample on the FPGA device. +3. Alternatively, run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` anr.fpga.exe ``` diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/board_test/README.md b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/board_test/README.md index f74484a9f7..65c5022066 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/board_test/README.md +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/board_test/README.md @@ -40,18 +40,24 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA (Intel® PAC with Intel® Arria® 10 GX FPGA)
Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX FPGA)
Intel® FPGA 3rd party / custom platforms with oneAPI support
**Note**: Intel® FPGA PAC hardware is only compatible with Ubuntu 18.04* +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler -> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. -> -> For using the simulator flow, Intel® Quartus® Prime Pro Edition and one of the following simulators must be installed and accessible through your PATH: -> - Questa*-Intel® FPGA Edition -> - Questa*-Intel® FPGA Starter Edition -> - ModelSim® SE -> -> When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. - +> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. +> +> For using the simulator flow, Intel® Quartus® Prime Pro Edition and one of the following simulators must be installed and accessible through your PATH: +> - Questa*-Intel® FPGA Edition +> - Questa*-Intel® FPGA Starter Edition +> - ModelSim® SE +> +> When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. + +> :warning: This sample is benchmarking an FPGA board, therefore it should really be used when targeting an FPGA board/BSP. + ## Key Implementation Details A oneAPI Board Support Package (BSP) consists of software layers and an FPGA hardware scaffold design, making it possible to target an FPGA through the Intel® oneAPI DPC++/C++ Compiler. @@ -118,21 +124,26 @@ Performance results are based on testing as of Jan 31, 2022. ### On Linux* 1. Change to the sample directory. -2. Configure the build system for **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, which is the default. +2. Configure the build system for the Agilex device family, which is the default. ``` mkdir build cd build cmake .. ``` - For **Intel® PAC with Intel Arria® 10 GX FPGA**, enter the following: - ``` - cmake -DFPGA_DEVICE=intel_a10gx_pac:pac_a10 .. - ``` - You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system, and enter a command similar to the following example: - ``` - cmake -DFPGA_DEVICE=: .. - ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. + 3. Compile the design. (The provided targets match the recommended development flow.) 1. Compile for emulation (fast compile time, targets emulated FPGA device). @@ -154,23 +165,26 @@ Performance results are based on testing as of Jan 31, 2022. ### On Windows* ->**Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not yet support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - 1. Change to the sample directory. -2. Configure the build system for **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, which is the default. +2. Configure the build system for the Agilex device family, which is the default. ``` mkdir build cd build cmake -G "NMake Makefiles" .. ``` - To compile for the **Intel® PAC with Intel Arria® 10 GX FPGA**, enter the following: - ``` - cmake -G "NMake Makefiles" -DFPGA_DEVICE=intel_a10gx_pac:pac_a10 .. - ``` - You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system, and enter a command similar to the following example: - ``` - cmake -G "NMake Makefiles" -DFPGA_DEVICE=: .. - ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. + 3. Compile the design. (The provided targets match the recommended development flow.) 1. Compile for emulation (fast compile time, targets emulated FPGA device). @@ -229,7 +243,7 @@ To view test details and usage information using the binary, use the `-help` opt ``` ./board_test.fpga_emu ``` - 2. Run the sample on the FPGA device. + 2. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` ./board_test.fpga ``` @@ -247,6 +261,14 @@ To view test details and usage information using the binary, use the `-help` opt ``` board_test.exe -test= ``` + 2. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). + ``` + ./board_test.fpga.exe + ``` + By default the program runs all tests. To run a specific test, enter the test number as an argument to the `-test` option: + ``` + ./board_test.fpga.exe -test= + ``` ## Example Output diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/README.md b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/README.md index f38d47df95..5545bc1f74 100755 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/README.md +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/README.md @@ -44,7 +44,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware |Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA (Intel® PAC with Intel® Arria® 10 GX FPGA)
Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX)
Intel Xeon® CPU E5-1650 v2 @ 3.50GHz (host machine) +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. @@ -55,6 +55,10 @@ You can also find more information about [troubleshooting build errors](/DirectP > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ### Performance @@ -145,16 +149,26 @@ For `constexpr_math.hpp`, `memory_utils.hpp`, `metaprogramming_utils.hpp`, and ` ### On Linux* 1. Change to the sample directory. -2. Configure the build system for **Intel® PAC with Intel Arria® 10 GX** FPGA, which is the default. +2. Configure the build system for the Agilex device family, which is the default. + ``` mkdir build cd build cmake .. ``` - For the **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following command instead: - ``` - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. + 3. Compile the design. (The provided targets match the recommended development flow.) 1. Compile for emulation (fast compile time, targets emulated FPGA device). @@ -180,19 +194,26 @@ For `constexpr_math.hpp`, `memory_utils.hpp`, `metaprogramming_utils.hpp`, and ` ### On Windows* ->**Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not yet support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - 1. Change to the sample directory. -2. Configure the build system for the Intel® PAC with Intel Arria® 10 GX FPGA, which is the default. +2. Configure the build system for the Agilex device family, which is the default. ``` mkdir build cd build cmake -G "NMake Makefiles" .. ``` - For the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), enter the following command instead: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. + 3. Compile the design. (The provided targets match the recommended development flow.) 1. Compile for emulation (fast compile time, targets emulated FPGA device): ``` @@ -236,7 +257,7 @@ You can apply the Cholesky decomposition to a number of matrices, as shown below ``` CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./cholesky.fpga_sim ``` -3. Run the sample on the FPGA device. +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` ./cholesky.fpga ``` @@ -253,7 +274,7 @@ You can apply the Cholesky decomposition to a number of matrices, as shown below cholesky.fpga_sim.exe set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run the sample on the FPGA device. +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` cholesky.fpga.exe ``` diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/README.md b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/README.md index 88dcfbb230..17043f9fed 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/README.md +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/README.md @@ -57,7 +57,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA (Intel® PAC with Intel® Arria® 10 GX FPGA)
Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX) +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. @@ -68,6 +68,10 @@ You can also find more information about [troubleshooting build errors](/DirectP > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ### Performance @@ -167,16 +171,26 @@ Additionaly, the cmake build system can be configured using the following parame ### On Linux* 1. Change to the sample directory. -2. Configure the build system for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Configure the build system for the Agilex device family, which is the default. + ``` mkdir build cd build cmake .. ``` - For the **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. + 3. Compile the design. (The provided targets match the recommended development flow.) 1. Compile for emulation (fast compile time, targets emulated FPGA device). @@ -202,19 +216,25 @@ Additionaly, the cmake build system can be configured using the following parame ### On Windows* -> **Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not yet support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - 1. Change to the sample directory. -2. Configure the build system for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default +2. Configure the build system for the Agilex device family, which is the default. ``` mkdir build cd build cmake -G "NMake Makefiles" .. ``` - For the **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 3. Compile the design. (The provided targets match the recommended development flow.) @@ -263,7 +283,7 @@ You can apply the Cholesky-based inversion to 8 matrices repeated a number of ti ``` CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./cholesky_inversion.fpga_sim ``` -3. Run on the FPGA device. +3. Run on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` ./cholesky_inversion.fpga ``` @@ -280,7 +300,7 @@ You can apply the Cholesky-based inversion to 8 matrices repeated a number of ti cholesky_inversion.fpga_sim.exe set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run on the FPGA device. +3. Run on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` cholesky_inversion.fpga.exe ``` diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/crr/README.md b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/crr/README.md index 4c1e0e1a76..195adf4424 100755 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/crr/README.md +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/crr/README.md @@ -39,7 +39,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA (Intel® PAC with Intel® Arria® 10 GX FPGA)
Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX) +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. @@ -50,6 +50,10 @@ You can also find more information about [troubleshooting build errors](/DirectP > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ### Performance @@ -151,16 +155,26 @@ This design measures the FPGA performance to determine how many assets can be pr ### On Linux* 1. Change to the sample directory. -2. Configure the build system for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Configure the build system for the Agilex device family, which is the default. + ``` mkdir build cd build cmake .. ``` - For the **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. + 3. Compile the design. (The provided targets match the recommended development flow.) 1. Compile for emulation (fast compile time, targets emulated FPGA device). @@ -182,19 +196,25 @@ This design measures the FPGA performance to determine how many assets can be pr ### On Windows* -> **Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not yet support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - 1. Change to the sample directory. -2. Configure the build system for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default +2. Configure the build system for the Agilex device family, which is the default. ``` mkdir build cd build cmake -G "NMake Makefiles" .. ``` - For the **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 3. Compile the design. (The provided targets match the recommended development flow.) @@ -229,7 +249,7 @@ This design measures the FPGA performance to determine how many assets can be pr ``` CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./crr.fpga_sim [-o=] ``` -3. Run the sample on the FPGA device. +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` ./crr.fpga [-o=] ``` @@ -250,7 +270,7 @@ This design measures the FPGA performance to determine how many assets can be pr set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run the sample on the FPGA device. +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` crr.fpga.exe [-o=] ``` diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/README.md b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/README.md index 31c532ef45..84e1eb3beb 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/README.md +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/README.md @@ -38,7 +38,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description --- |--- | OS | Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX) +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. @@ -49,8 +49,10 @@ You can also find more information about [troubleshooting build errors](/DirectP > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. - -> **Note**: This example design is only officially supported for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX). +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ### Performance @@ -144,7 +146,7 @@ Query 12 showcases the `MergeJoin` database operator. The block diagram of the d ### On Linux* 1. Change to the sample directory. -2. Configure the build system for query number 1. +2. Configure the build system for the default target (the Agilex device family). ``` mkdir build cd build @@ -152,6 +154,18 @@ Query 12 showcases the `MergeJoin` database operator. The block diagram of the d ``` `-DQUERY=` can be any of the following query numbers: `1`, `9`, `11` or `12`. + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DQUERY= -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DQUERY= -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. + 3. Compile the design. (The provided targets match the recommended development flow.) 1. Compile for emulation (fast compile time, targets emulated FPGA device). @@ -182,17 +196,27 @@ Query 12 showcases the `MergeJoin` database operator. The block diagram of the d ### On Windows* ->**Note**: The FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX) does not yet support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - 1. Change to the sample directory. -2. Configure the build system for query number 1. +2. Configure the build system for the default target (the Agilex device family). ``` mkdir build cd build - cmake -G "NMake Makefiles" -DQUERY=1 + cmake -G "NMake Makefiles" .. -DQUERY=1 ``` `-DQUERY=` can be any of the following query numbers: `1`, `9`, `11` or `12`. + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DQUERY= -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DQUERY= -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. + 3. Compile the design. (The provided targets match the recommended development flow.) 1. Compile for emulation (fast compile time, targets emulated FPGA device). @@ -238,11 +262,11 @@ Query 12 showcases the `MergeJoin` database operator. The block diagram of the d ./db.fpga_emu --dbroot=../data/sf0.01 --test ``` (Optional) Run the design for queries `9`, `11` and `12`. -2. Run the sample on the FPGA simulator device: +2. Run the sample on the FPGA simulator device. ``` CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./db.fpga_sim --dbroot=../data/sf0.01 --test ``` -3. Run the design on an FPGA device. +3. Run the design on an FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` ./db.fpga --dbroot=../data/sf1 --test ``` @@ -254,13 +278,13 @@ Query 12 showcases the `MergeJoin` database operator. The block diagram of the d db.fpga_emu.exe --dbroot=../data/sf0.01 --test ``` (Optional) Run the design for queries `9`, `11` and `12`. -2. Run the sample on the FPGA simulator device: +2. Run the sample on the FPGA simulator device. ``` set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 db.fpga_sim.exe --dbroot=../data/sf0.01 --test set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run the sample on an FPGA device. +3. Run the sample on an FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` db.fpga.exe --dbroot=../data/sf1 --test ``` diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/README.md b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/README.md index fcb5b7b8d9..54391b20d4 100755 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/README.md +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/README.md @@ -36,7 +36,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA (Intel® PAC with Intel® Arria® 10 GX FPGA)
Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX) +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. @@ -47,6 +47,10 @@ You can also find more information about [troubleshooting build errors](/DirectP > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ## Key Implementation Details @@ -302,21 +306,31 @@ For `constexpr_math.hpp`, `memory_utils.hpp`, `metaprogramming_utils.hpp`, `tupl ### On Linux* 1. Change to the sample directory. -2. Configure the build system for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Configure the build system for the Agilex device family, which is the default. + ``` mkdir build cd build cmake .. ``` + To select between GZIP and Snappy decompression, use `-DGZIP=1` or `-DSNAPPY=1`. If you do not specify the decompression, the code defaults to **Snappy**. ``` cmake .. -DGZIP=1 cmake .. -DSNAPPY=1 ``` - For the **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 3. Compile the design. (The provided targets match the recommended development flow.) @@ -343,10 +357,8 @@ For `constexpr_math.hpp`, `memory_utils.hpp`, `metaprogramming_utils.hpp`, `tupl ### On Windows* -> **Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not yet support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - 1. Change to the sample directory. -2. Configure the build system for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default +2. Configure the build system for the Agilex device family, which is the default. ``` mkdir build cd build @@ -357,10 +369,19 @@ For `constexpr_math.hpp`, `memory_utils.hpp`, `metaprogramming_utils.hpp`, `tupl cmake -G "NMake Makefiles" .. -DGZIP=1 cmake -G "NMake Makefiles" .. -DSNAPPY=1 ``` - For the **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. + 3. Compile the design. (The provided targets match the recommended development flow.) 1. Compile for emulation (fast compile time, targets emulated FPGA device). @@ -391,11 +412,11 @@ For `constexpr_math.hpp`, `memory_utils.hpp`, `metaprogramming_utils.hpp`, `tupl ``` ./decompress.fpga_emu ``` -2. Run the sample on the FPGA simulator device: +2. Run the sample on the FPGA simulator device. ``` CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./decompress.fpga_sim ``` -3. Run the sample on the FPGA device. +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` ./decompress.fpga ``` @@ -406,13 +427,13 @@ For `constexpr_math.hpp`, `memory_utils.hpp`, `metaprogramming_utils.hpp`, `tupl ``` decompress.fpga_emu.exe ``` -2. Run the sample on the FPGA simulator device: +2. Run the sample on the FPGA simulator device. ``` set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 decompress.fpga_sim.exe set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run the sample on the FPGA device. +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` decompress.fpga.exe ``` diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/README.md b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/README.md index ae930552aa..45d3c2ba41 100644 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/README.md +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/README.md @@ -39,7 +39,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA (Intel® PAC with Intel® Arria® 10 GX FPGA)
Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX) +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. @@ -50,18 +50,22 @@ You can also find more information about [troubleshooting build errors](/DirectP > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ## Key Implementation Details The GZIP DEFLATE algorithm uses a GZIP-compatible Limpel-Ziv 77 (LZ77) algorithm for data de-duplication and a GZIP-compatible Static Huffman algorithm for bit reduction. The implementation includes three FPGA accelerated tasks (LZ77, Static Huffman, and CRC). -The FPGA implementation of the algorithm enables either one or two independent GZIP compute engines to operate in parallel on the FPGA. The available FPGA resources constrain the number of engines. By default, the design is parameterized to create a single engine when the design is compiled to target Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA (Intel® PAC with Intel® Arria® 10 GX FPGA). Two engines are created when compiling for Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX), which is a larger device. +The FPGA implementation of the algorithm enables either one or two independent GZIP compute engines to operate in parallel on the FPGA. The available FPGA resources constrain the number of engines. By default, the design is parameterized to create a single engine when the design is compiled to target an Intel® Arria10 FPGA. Two engines are created when compiling for an Intel® Stratix10 FPGA, which is a larger device. This reference design contains two variants: "High Bandwidth" and "Low-Latency." - The High Bandwidth variant maximizes system throughput without regard for latency. It transfers input/output SYCL Buffers to FPGA-attached DDR. The kernel then operates on these buffers. - The Low-Latency variant takes advantage of Universal Shared Memory (USM) to avoid these copy operations, allowing the GZIP engine to access input/output buffers in host-memory directly. This reduces latency, but throughput is also reduced. "Latency" in this context is defined as the duration of time between when the input buffer is available in host memory to when the output buffer (i.e., the compressed result) is available in host memory. -The Low-Latency variant is only supported on Intel Stratix® 10 SX. +The Low-Latency variant is only supported on USM capable BSPs, or when targeting an FPGA family/part number. | Kernel | Description |:--- |:--- @@ -99,14 +103,14 @@ To optimize performance, GZIP leverages techniques discussed in the following FP | `-Xshardware` | Targets FPGA hardware (instead of FPGA emulator). | `-Xsparallel=2` | Uses two cores when compiling the bitstream through Intel® Quartus®. | `-Xsseed=` | Uses a particular seed while running Intel® Quartus®, selected to yield the best Fmax for this design. -| `-Xsnum-reorder=6` | On Intel Stratix® 10 SX only, specify a wider data path for read data from global memory. +| `-Xsnum-reorder=6` | On FPGA boards that have a large memory bandwidth, specify a wider data path for read data from global memory. | `-Xsopt-arg="-nocaching"` | Specifies that cached LSUs should not be used. Additionaly, the cmake build system can be configured using the following parameter: | cmake option | Description |:--- |:--- -| `-DNUM_ENGINES=<1\|2>` | Specifies that 1 GZIP engine should be compiled when targeting Intel Arria® 10 GX and two engines when targeting Intel Stratix® 10 SX. +| `-DNUM_ENGINES=<1\|2>` | Specifies that the number of GZIP engine that should be compiled. ### Performance @@ -114,9 +118,9 @@ Performance results are based on testing as of October 27, 2020. > **Note**: Refer to the [Performance Disclaimers](/DirectProgramming/C++SYCL_FPGA/README.md#performance-disclaimers) section for important performance information. -| Device | Throughput -|:--- |:--- -| Intel® PAC with Intel® Arria® 10 GX FPGA | 1 engine @ 3.4 GB/s +| Device | Throughput +|:--- |:--- +| Intel® PAC with Intel® Arria® 10 GX FPGA | 1 engine @ 3.4 GB/s | Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX) | 2 engines @ 4.5 GB/s each = 9.0 GB/s total (High Bandwidth variant) using 120MB+ input
2 engines @ 3.5 GB/s = 7.0 GB/s (Low Latency variant) using 80 KB input ## Build the `GZIP` Design @@ -140,20 +144,28 @@ Performance results are based on testing as of October 27, 2020. ### On Linux* 1. Change to the sample directory. -2. Configure the build system for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Configure the build system for the Agilex device family, which is the default. + ``` mkdir build cd build cmake .. ``` - For the **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - For the **low latency** version of the design, add `-DLOW_LATENCY=1`. - ``` - cmake .. -DLOW_LATENCY=1 -DFPGA_DEVICE=intel_s10sx_pac:pac_s10_usm - ``` + + For the **low latency** version of the design, add `-DLOW_LATENCY=1` to your `cmake` command. + + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. + 3. Compile the design. (The provided targets match the recommended development flow.) 1. Compile for emulation (fast compile time, targets emulated FPGA device). @@ -179,23 +191,27 @@ Performance results are based on testing as of October 27, 2020. ### On Windows* -> **Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not yet support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - 1. Change to the sample directory. -2. Configure the build system for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default +2. Configure the build system for the Agilex device family, which is the default. ``` mkdir build cd build cmake -G "NMake Makefiles" .. ``` - For the **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - For the **low latency** version of the design, add `-DLOW_LATENCY=1`. - ``` - cmake -G "Nmake Makefiles" .. -DLOW_LATENCY=1 -DFPGA_DEVICE=intel_s10sx_pac:pac_s10_usm - ``` + + For the **low latency** version of the design, add `-DLOW_LATENCY=1` to your `cmake` command. + + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 3. Compile the design. (The provided targets match the recommended development flow.) @@ -227,7 +243,7 @@ Performance results are based on testing as of October 27, 2020. | Argument | Description |:--- |:--- | `` | Specifies the file to be compressed.
Use an 120+ MB file to achieve peak performance.
Use an 80 KB file for Low Latency variant. -| `-o=` | Specifies the name of the output file. The default name of the output file is `.gz`.
When targeting Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), the single `` is fed to both engines, yielding two identical output files, using `` as the basis for the filenames. +| `-o=` | Specifies the name of the output file. The default name of the output file is `.gz`.
When using two engines, the single `` is fed to both engines, yielding two identical output files, using `` as the basis for the filenames. ### On Linux @@ -241,7 +257,7 @@ Performance results are based on testing as of October 27, 2020. CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./gzip.fpga_sim -o= ``` - 3. Run the sample on the FPGA device. + 3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` aocl initialize acl0 pac_s10_usm ./gzip.fpga -o= @@ -258,7 +274,7 @@ Performance results are based on testing as of October 27, 2020. gzip.fpga_sim.exe -o= set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` - 3. Run the sample on the FPGA device. + 3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` aocl initialize acl0 pac_s10_usm gzip.fpga.exe -o= diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/README.md b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/README.md index 952891b52e..eedcabc33a 100755 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/README.md +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/README.md @@ -41,7 +41,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA (Intel® PAC with Intel® Arria® 10 GX FPGA)
Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX) +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. @@ -52,6 +52,10 @@ You can also find more information about [troubleshooting build errors](/DirectP > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ## Key Implementation Details @@ -120,16 +124,26 @@ For `constexpr_math.hpp`, `pipe_utils.hpp`, and `unrolled_loop.hpp` see the READ ### On Linux* 1. Change to the sample directory. -2. Configure the build system for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Configure the build system for the Agilex device family, which is the default. + ``` mkdir build cd build cmake .. ``` - For the **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. + 3. Compile the design. (The provided targets match the recommended development flow.) 1. Compile for emulation (fast compile time, targets emulated FPGA device). @@ -155,19 +169,26 @@ For `constexpr_math.hpp`, `pipe_utils.hpp`, and `unrolled_loop.hpp` see the READ ### On Windows* -> **Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not yet support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - 1. Change to the sample directory. -2. Configure the build system for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default +2. Configure the build system for the Agilex device family, which is the default. ``` mkdir build cd build cmake -G "NMake Makefiles" .. ``` - For the **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. + 3. Compile the design. (The provided targets match the recommended development flow.) 1. Compile for emulation (fast compile time, targets emulated FPGA device). @@ -198,11 +219,11 @@ For `constexpr_math.hpp`, `pipe_utils.hpp`, and `unrolled_loop.hpp` see the READ ``` ./merge_sort.fpga_emu ``` -2. Run the sample on the FPGA simulator device: +2. Run the sample on the FPGA simulator device. ``` CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./merge_sort.fpga_sim ``` -3. Run the sample on the FPGA device. +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` ./merge_sort.fpga ``` @@ -212,13 +233,13 @@ For `constexpr_math.hpp`, `pipe_utils.hpp`, and `unrolled_loop.hpp` see the READ ``` merge_sort.fpga_emu.exe ``` -2. Run the sample on the FPGA simulator device: +2. Run the sample on the FPGA simulator device. ``` set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 merge_sort.fpga_sim.exe set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run the sample on the FPGA device. +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` merge_sort.fpga.exe ``` diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/README.md b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/README.md index fabb9cf5c3..0a5b4e2a18 100755 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/README.md +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/README.md @@ -49,7 +49,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA (Intel® PAC with Intel® Arria® 10 GX FPGA)
Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX) +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. @@ -60,6 +60,10 @@ You can also find more information about [troubleshooting build errors](/DirectP > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ## Key Implementation Details @@ -119,16 +123,26 @@ The `DataProducer` kernel replaces the input IO pipe in the first image. The spl ### On Linux* 1. Change to the sample directory. -2. Configure the build system for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Configure the build system for the Agilex device family, which is the default. + ``` mkdir build cd build cmake .. ``` - For the **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. + 3. Compile the design. (The provided targets match the recommended development flow.) 1. Compile for emulation (fast compile time, targets emulated FPGA device). @@ -154,19 +168,26 @@ The `DataProducer` kernel replaces the input IO pipe in the first image. The spl ### On Windows* -> **Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not yet support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - 1. Change to the sample directory. -2. Configure the build system for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default +2. Configure the build system for the Agilex device family, which is the default. ``` mkdir build cd build cmake -G "NMake Makefiles" .. ``` - For the **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. + 3. Compile the design. (The provided targets match the recommended development flow.) 1. Compile for emulation (fast compile time, targets emulated FPGA device). @@ -208,11 +229,11 @@ The general syntax for running the program is shown below and the table describe ``` ./mvdr_beamforming.fpga_emu 1024 ../data . ``` -2. Run the sample on the FPGA simulator device: +2. Run the sample on the FPGA simulator device. ``` CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./mvdr_beamforming.fpga_sim 1024 ../data . ``` -3. Run the sample on the FPGA device. +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` ./mvdr_beamforming.fpga 1024 ../data . ``` @@ -223,13 +244,13 @@ The general syntax for running the program is shown below and the table describe ``` mvdr_beamforming.fpga_emu.exe 1024 ../data . ``` -2. Run the sample on the FPGA simulator device: +2. Run the sample on the FPGA simulator device. ``` set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 mvdr_beamforming.fpga_sim.exe ../data . set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run the sample on the FPGA device. +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` mvdr_beamforming.fpga.exe 1024 ../data . ``` diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/README.md b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/README.md index 28b11d95b4..3ab62a9713 100755 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/README.md +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/README.md @@ -44,7 +44,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA (Intel® PAC with Intel® Arria® 10 GX FPGA)
Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX) +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. @@ -55,6 +55,10 @@ You can also find more information about [troubleshooting build errors](/DirectP > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ### Performance @@ -135,17 +139,26 @@ Additionaly, the cmake build system can be configured using the following parame ### On Linux* 1. Change to the sample directory. -2. Configure the build system for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Configure the build system for the Agilex device family, which is the default. ``` mkdir build cd build cmake .. ``` - For **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake .. -DFPGA_BOARD=intel_s10sx_pac:pac_s10 - ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. + 3. Compile the design. (The provided targets match the recommended development flow.) 1. Compile for emulation (fast compile time, targets emulated FPGA device). @@ -174,16 +187,24 @@ Additionaly, the cmake build system can be configured using the following parame >**Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not yet support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. 1. Change to the sample directory. -2. Configure the build system for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Configure the build system for the Agilex device family, which is the default. ``` mkdir build cd build cmake -G "NMake Makefiles" .. ``` - To compile for the **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_BOARD=intel_s10sx_pac:pac_s10 - ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 3. Compile the design. (The provided targets match the recommended development flow.) @@ -240,7 +261,7 @@ You can perform the QR decomposition of the set of matrices repeatedly. This ste #### Run on FPGA -1. Run the sample on the FPGA device. +1. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` ./qrd.fpga ``` @@ -267,7 +288,7 @@ You can perform the QR decomposition of the set of matrices repeatedly. This ste #### Run on FPGA -1. Run the sample on the FPGA device. +1. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` qrd.fpga.exe ``` diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/README.md b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/README.md index 9b6576f876..920d7f5c42 100755 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/README.md +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/README.md @@ -44,7 +44,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA (Intel® PAC with Intel® Arria® 10 GX FPGA)
Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX) +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. @@ -55,6 +55,10 @@ You can also find more information about [troubleshooting build errors](/DirectP > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ## Key Implementation Details @@ -127,17 +131,25 @@ Additionaly, the cmake build system can be configured using the following parame ### On Linux* 1. Change to the sample directory. -2. Configure the build system for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Configure the build system for the Agilex device family, which is the default. ``` mkdir build cd build cmake .. ``` - For **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake .. -DFPGA_BOARD=intel_s10sx_pac:pac_s10 - ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. + 3. Compile the design. (The provided targets match the recommended development flow.) 1. Compile for emulation (fast compile time, targets emulated FPGA device). @@ -163,19 +175,25 @@ Additionaly, the cmake build system can be configured using the following parame ### On Windows* ->**Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not yet support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - 1. Change to the sample directory. -2. Configure the build system for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Configure the build system for the Agilex device family, which is the default. ``` mkdir build cd build cmake -G "NMake Makefiles" .. ``` - To compile for the **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_BOARD=intel_s10sx_pac:pac_s10 - ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 3. Compile the design. (The provided targets match the recommended development flow.) @@ -233,7 +251,7 @@ You can perform the QR-based inversion of the set of matrices repeatedly, as sho #### Run on FPGA -1. Run the sample on the FPGA device. +1. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` ./qri.fpga ``` @@ -260,7 +278,7 @@ You can perform the QR-based inversion of the set of matrices repeatedly, as sho #### Run on FPGA -1. Run the sample on the FPGA device. +1. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` qri.fpga.exe ``` diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/autorun/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/autorun/README.md index 10848c6f24..462f8a7c6a 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/autorun/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/autorun/README.md @@ -38,7 +38,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA
FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX) +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. @@ -49,8 +49,10 @@ You can also find more information about [troubleshooting build errors](/DirectP > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. - ->**Note**: Intel® FPGA PAC hardware is only compatible with Ubuntu 18.04*. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ## Key Implementation Details @@ -85,22 +87,25 @@ Typically, these kernels are meant to run forever, and data is streamed to and f ### On Linux* 1. Change to the sample directory. -2. Build the program for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Build the program for the Agilex device family, which is the default. ``` mkdir build cd build cmake .. ``` - For **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - For a custom FPGA platform, ensure that the board support package is installed on your system then enter a command similar to the following: - ``` - cmake .. -DFPGA_DEVICE=: - ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 3. Compile the design. (The provided targets match the recommended development flow.) @@ -125,23 +130,25 @@ Typically, these kernels are meant to run forever, and data is streamed to and f ### On Windows* ->**Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not yet support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - 1. Change to the sample directory. -2. Build the program for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Build the program for the Agilex device family, which is the default. ``` mkdir build cd build cmake -G "NMake Makefiles" .. ``` - To compile for the **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - For a custom FPGA platform, ensure that the board support package is installed on your system then enter a command similar to the following: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: - ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 3. Compile the design. (The provided targets match the recommended development flow.) @@ -177,7 +184,7 @@ Typically, these kernels are meant to run forever, and data is streamed to and f ``` CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./autorun.fpga_sim ``` -3. Run on an FPGA device. +3. Run on an FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` ./autorun.fpga ``` @@ -198,7 +205,7 @@ Typically, these kernels are meant to run forever, and data is streamed to and f autorun.fpga_sim.exe set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run on an FPGA device. +3. Run on an FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` autorun.fpga.exe ``` diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/buffered_host_streaming/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/buffered_host_streaming/README.md index 3b3d7277fa..2fba64dce8 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/buffered_host_streaming/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/buffered_host_streaming/README.md @@ -47,7 +47,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX) +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. @@ -58,10 +58,12 @@ You can also find more information about [troubleshooting build errors](/DirectP > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ->**Note**: Intel® FPGA PAC hardware is only compatible with Ubuntu 18.04*. - ->**Note**: SYCL* USM host allocations (and the code in this sample) are only supported for the **FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX)** with USM support (for example, intel_s10sx_pac:pac_s10_usm). +*Notice: SYCL USM host allocations, and therefore this tutorial, are only supported on FPGA boards that have a USM capable BSP (e.g. the Intel® FPGA PAC D5005 with Intel Stratix® 10 SX with USM support: intel_s10sx_pac:pac_s10_usm). USM host allocations are supported for all non FPGA board targets (e.g. Agilex).* ## Key Implementation Details @@ -92,16 +94,25 @@ This sample demonstrates the following concepts: ### On Linux* 1. Change to the sample directory. -2. Build the program for **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**. +2. Build the program for the Agilex device family, which is the default. + ``` mkdir build cd build cmake .. ``` - For a custom FPGA platform, ensure that the board support package is installed on your system then enter a command similar to the following: - ``` - cmake .. -DFPGA_DEVICE=: -DUSM_HOST_ALLOCATIONS_ENABLED=1 - ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 3. Compile the design. (The provided targets match the recommended development flow.) @@ -128,19 +139,25 @@ This sample demonstrates the following concepts: ### On Windows* ->**Note**: The Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) does not yet support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - 1. Change to the sample directory. -2. Build the program for **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**. +2. Build the program for the Agilex device family, which is the default. ``` mkdir build cd build cmake -G "NMake Makefiles" .. ``` - For a custom FPGA platform, ensure that the board support package is installed on your system then enter a command similar to the following: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: -DUSM_HOST_ALLOCATIONS_ENABLED=1 - ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 3. Compile the design. (The provided targets match the recommended development flow.) @@ -177,7 +194,7 @@ This sample demonstrates the following concepts: ``` CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./buffered_host_streaming.fpga_sim ``` -3. Run the sample on the FPGA device: +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`): ``` ./buffered_host_streaming.fpga ``` @@ -194,7 +211,7 @@ This sample demonstrates the following concepts: buffered_host_streaming.fpga_sim.exe set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run the sample on the FPGA device: +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`): ``` buffered_host_streaming.fpga.exe ``` diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/compute_units/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/compute_units/README.md index 1eca0d48ca..82574de948 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/compute_units/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/compute_units/README.md @@ -41,7 +41,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA
FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX)
FPGA third-party/custom platforms with oneAPI support +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. @@ -52,8 +52,10 @@ You can also find more information about [troubleshooting build errors](/DirectP > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. - ->**Note**: Intel® FPGA PAC hardware is only compatible with Ubuntu 18.04*. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ## Key Implementation Details @@ -134,22 +136,26 @@ Each compute unit in the chain from `Source` to `Sink` must read from a unique p ### On Linux* 1. Change to the sample directory. -2. Build the program for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Build the program for the Agilex device family, which is the default. ``` mkdir build cd build cmake .. ``` - For **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - For a custom FPGA platform, ensure that the board support package is installed on your system then enter a command similar to the following: - ``` - cmake .. -DFPGA_DEVICE=: - ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. + 3. Compile the design. (The provided targets match the recommended development flow.) 1. Compile for emulation (fast compile time, targets emulated FPGA device). @@ -175,24 +181,25 @@ Each compute unit in the chain from `Source` to `Sink` must read from a unique p ### On Windows* ->**Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not yet support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - 1. Change to the sample directory. -2. Build the program for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Build the program for the Agilex device family, which is the default. ``` mkdir build cd build cmake -G "NMake Makefiles" .. ``` - To compile for the **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - For a custom FPGA platform, ensure that the board support package is installed on your system then enter a command similar to the following: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: - ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 3. Compile the design. (The provided targets match the recommended development flow.) @@ -225,11 +232,11 @@ Each compute unit in the chain from `Source` to `Sink` must read from a unique p ``` ./compute_units.fpga_emu ``` -2. Run the sample on the FPGA simulator device: +2. Run the sample on the FPGA simulator device. ``` CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./compute_units.fpga_sim ``` -3. Run the sample on the FPGA device. +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` ./compute_units.fpga ``` @@ -239,13 +246,13 @@ Each compute unit in the chain from `Source` to `Sink` must read from a unique p ``` compute_units.fpga_emu.exe ``` -2. Run the sample on the FPGA simulator device: +2. Run the sample on the FPGA simulator device. ``` set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 compute_units.fpga_sim.exe set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run the sample on the FPGA device. +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` compute_units.fpga.exe ``` diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/double_buffering/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/double_buffering/README.md index 8d992f4108..87b9e21f6d 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/double_buffering/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/double_buffering/README.md @@ -42,7 +42,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA
FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX)
FPGA third-party/custom platforms with oneAPI support +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. @@ -53,8 +53,10 @@ You can also find more information about [troubleshooting build errors](/DirectP > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. - ->**Note**: Intel® FPGA PAC hardware is only compatible with Ubuntu 18.04*. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ## Key Implementation Details @@ -84,22 +86,25 @@ The key concepts discussed in this sample are as followed: ### On Linux* 1. Change to the sample directory. -2. Build the program for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Build the program for the Agilex device family, which is the default. ``` mkdir build cd build cmake .. ``` - For **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - For a custom FPGA platform, ensure that the board support package is installed on your system then enter a command similar to the following: - ``` - cmake .. -DFPGA_DEVICE=: - ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 3. Compile the design. (The provided targets match the recommended development flow.) @@ -126,24 +131,25 @@ The key concepts discussed in this sample are as followed: ### On Windows* ->**Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not yet support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - 1. Change to the sample directory. -2. Build the program for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Build the program for the Agilex device family, which is the default. ``` mkdir build cd build cmake -G "NMake Makefiles" .. ``` - To compile for the **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - For a custom FPGA platform, ensure that the board support package is installed on your system then enter a command similar to the following: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: - ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 3. Compile the design. (The provided targets match the recommended development flow.) @@ -168,16 +174,6 @@ The key concepts discussed in this sample are as followed: >**Note**: If you encounter any issues with long paths when compiling under Windows*, you may have to create your `build` directory in a shorter path, for example `C:\samples\build`. You can then build the sample in the new location, but you must specify the full path to the build files. -#### Troubleshooting - -If an error occurs, you can get more details by running `make` with -the `VERBOSE=1` argument: -``` -make VERBOSE=1 -``` -If you receive an error message, troubleshoot the problem using the **Diagnostics Utility for Intel® oneAPI Toolkits**. The diagnostic utility provides configuration and system checks to help find missing dependencies, permissions errors, and other issues. See the *[Diagnostics Utility for Intel® oneAPI Toolkits User Guide](https://www.intel.com/content/www/us/en/develop/documentation/diagnostic-utility-user-guide/top.html)* for more information on using the utility. - - ## Run the `Double Buffering` Sample ### On Linux @@ -190,7 +186,7 @@ If you receive an error message, troubleshoot the problem using the **Diagnostic ``` CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./double_buffering.fpga_sim ``` -3. Run the sample on the FPGA device. +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` ./double_buffering.fpga ``` @@ -207,7 +203,7 @@ If you receive an error message, troubleshoot the problem using the **Diagnostic double_buffering.fpga_sim.exe set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run the sample on the FPGA device. +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` double_buffering.fpga.exe ``` diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/README.md index 0d6ddbf035..3c029dfd7d 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/README.md @@ -38,8 +38,8 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA
FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX)
FPGA third-party/custom platforms with oneAPI support -| Software | Intel® oneAPI DPC++/C++ Compiler
Intel® FPGA Add-On for oneAPI Base Toolkit +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs +| Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. > @@ -49,8 +49,10 @@ You can also find more information about [troubleshooting build errors](/DirectP > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. - ->**Note**: Intel® FPGA PAC hardware is only compatible with Ubuntu 18.04*. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ## Key Implementation Details @@ -107,22 +109,25 @@ Alternatively, there is a hybrid approach that uses some implicit data movement ### On Linux* 1. Change to the sample directory. -2. Build the program for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Build the program for the Agilex device family, which is the default. ``` mkdir build cd build cmake .. ``` - For **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - For a custom FPGA platform, ensure that the board support package is installed on your system then enter a command similar to the following: - ``` - cmake .. -DFPGA_DEVICE=: - ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 3. Compile the design. (The provided targets match the recommended development flow.) @@ -149,24 +154,25 @@ Alternatively, there is a hybrid approach that uses some implicit data movement ### On Windows* ->**Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not yet support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - 1. Change to the sample directory. -2. Build the program for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Build the program for the Agilex device family, which is the default. ``` mkdir build cd build cmake -G "NMake Makefiles" .. ``` - To compile for the **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - For a custom FPGA platform, ensure that the board support package is installed on your system then enter a command similar to the following: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: - ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 3. Compile the design. (The provided targets match the recommended development flow.) @@ -199,11 +205,11 @@ Alternatively, there is a hybrid approach that uses some implicit data movement ``` ./explicit_data_movement.fpga_emu ``` -2. Run the sample on the FPGA simulator device: +2. Run the sample on the FPGA simulator device. ``` CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./explicit_data_movement.fpga_sim ``` -3. Run the sample on the FPGA device. +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` ./explicit_data_movement.fpga ``` @@ -214,13 +220,13 @@ Alternatively, there is a hybrid approach that uses some implicit data movement ``` explicit_data_movement.fpga_emu.exe ``` -2. Run the sample on the FPGA simulator device: +2. Run the sample on the FPGA simulator device. ``` set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 explicit_data_movement.fpga_sim.exe set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run the sample on the FPGA device. +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` explicit_data_movement.fpga.exe ``` diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/io_streaming/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/io_streaming/README.md index b74d5d1994..faaff59155 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/io_streaming/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/io_streaming/README.md @@ -38,7 +38,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA
FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX)
FPGA third-party/custom platforms with oneAPI support +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. @@ -49,8 +49,10 @@ You can also find more information about [troubleshooting build errors](/DirectP > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. - ->**Note**: Intel® FPGA PAC hardware is only compatible with Ubuntu 18.04*. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ## Key Implementation Details @@ -136,22 +138,26 @@ Notice that the main kernel in the `SubmitSideChannelKernels` function in *src/S ### On Linux* 1. Change to the sample directory. -2. Build the program for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Build the program for the Agilex device family, which is the default. ``` mkdir build cd build cmake .. ``` - For **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - For a custom FPGA platform, ensure that the board support package is installed on your system then enter a command similar to the following: - ``` - cmake .. -DFPGA_DEVICE=: - ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. + 3. Compile the design. (The provided targets match the recommended development flow.) 1. Compile for emulation (fast compile time, targets emulated FPGA device). @@ -176,24 +182,25 @@ Notice that the main kernel in the `SubmitSideChannelKernels` function in *src/S ### On Windows* ->**Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not yet support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - 1. Change to the sample directory. -2. Build the program for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Build the program for the Agilex device family, which is the default. ``` mkdir build cd build cmake -G "NMake Makefiles" .. ``` - To compile for the **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - For a custom FPGA platform, ensure that the board support package is installed on your system then enter a command similar to the following: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: - ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 3. Compile the design. (The provided targets match the recommended development flow.) @@ -226,11 +233,11 @@ Notice that the main kernel in the `SubmitSideChannelKernels` function in *src/S ``` ./io_streaming.fpga_emu ``` -2. Run the sample on the FPGA simulator device: +2. Run the sample on the FPGA simulator device. ``` CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./io_streaming.fpga_sim ``` -3. Run the sample on the FPGA device. +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` ./io_streaming.fpga ``` @@ -241,13 +248,13 @@ Notice that the main kernel in the `SubmitSideChannelKernels` function in *src/S ``` io_streaming.fpga_emu.exe ``` -2. Run the sample on the FPGA simulator device: +2. Run the sample on the FPGA simulator device. ``` set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 io_streaming.fpga_sim.exe set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run the sample on the FPGA device. +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` io_streaming.fpga.exe ``` diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/loop_carried_dependency/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/loop_carried_dependency/README.md index 049ddc4b9a..f1d2ccdd35 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/loop_carried_dependency/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/loop_carried_dependency/README.md @@ -41,10 +41,10 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA
FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX) +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler -> **Note**: Even though the Intel® DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. +> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. > > For using the simulator flow, Intel® Quartus® Prime Pro Edition and one of the following simulators must be installed and accessible through your PATH: > - Questa*-Intel® FPGA Edition @@ -52,6 +52,10 @@ You can also find more information about [troubleshooting build errors](/DirectP > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ## Key Implementation Details @@ -122,22 +126,25 @@ Look at the _Compiler Report > Throughput Analysis > Loop Analysis_ section in t > For more information on configuring environment variables, see [Use the setvars Script with Linux* or macOS*](https://www.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/oneapi-development-environment-setup/use-the-setvars-script-with-linux-or-macos.html) or [Use the setvars Script with Windows*](https://www.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/oneapi-development-environment-setup/use-the-setvars-script-with-windows.html). 1. Change to the sample directory. -2. Build the program for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Build the program for the Agilex device family, which is the default. ``` mkdir build cd build cmake .. ``` - For **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - For a custom FPGA platform, ensure that the board support package is installed on your system then enter a command similar to the following: - ``` - cmake .. -DFPGA_DEVICE=: - ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 3. Compile the design. (The provided targets match the recommended development flow.) @@ -167,19 +174,25 @@ Look at the _Compiler Report > Throughput Analysis > Loop Analysis_ section in t ### On Windows* ->**Note**: The Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) does not yet support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - 1. Change to the sample directory. -2. Build the program for **Intel® PAC with Intel Arria® 10 GX FPGA**. +2. Build the program for the Agilex device family, which is the default. ``` mkdir build cd build cmake -G "NMake Makefiles" .. ``` - For a custom FPGA platform, ensure that the board support package is installed on your system then enter a command similar to the following: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: -DUSM_HOST_ALLOCATIONS_ENABLED=1 - ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 3. Compile the design. (The provided targets match the recommended development flow.) @@ -202,15 +215,6 @@ Look at the _Compiler Report > Throughput Analysis > Loop Analysis_ section in t >**Note**: If you encounter any issues with long paths when compiling under Windows*, you may have to create your `build` directory in a shorter path, for example `C:\samples\build`. You can then build the sample in the new location, but you must specify the full path to the build files. -#### Troubleshooting - -If an error occurs, you can get more details by running `make` with -the `VERBOSE=1` argument: -``` -make VERBOSE=1 -``` -If you receive an error message, troubleshoot the problem using the **Diagnostics Utility for Intel® oneAPI Toolkits**. The diagnostic utility provides configuration and system checks to help find missing dependencies, permissions errors, and other issues. See the *[Diagnostics Utility for Intel® oneAPI Toolkits User Guide](https://www.intel.com/content/www/us/en/develop/documentation/diagnostic-utility-user-guide/top.html)* for more information on using the utility. - ## Run the `Remove Loop Carried Dependency` Sample ### On Linux @@ -223,7 +227,7 @@ If you receive an error message, troubleshoot the problem using the **Diagnostic ``` CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./loop_carried_dependency.fpga_sim ``` -3. Run the sample on the FPGA device. +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` ./loop_carried_dependency.fpga ``` @@ -240,7 +244,7 @@ If you receive an error message, troubleshoot the problem using the **Diagnostic loop_carried_dependency.fpga_sim.exe set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run the sample on the FPGA device. +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` loop_carried_dependency.fpga.exe ``` diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/n_way_buffering/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/n_way_buffering/README.md index 7cf4383846..ce7cc10fc9 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/n_way_buffering/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/n_way_buffering/README.md @@ -39,7 +39,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA
FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX) +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. @@ -50,6 +50,10 @@ You can also find more information about [troubleshooting build errors](/DirectP > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ## Key Implementation Details @@ -162,22 +166,26 @@ After each kernel is launched, the host-side operations (that occur *after* the ### On Linux* 1. Change to the sample directory. -2. Build the program for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Build the program for the Agilex device family, which is the default. ``` mkdir build cd build cmake .. ``` - For **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - For a custom FPGA platform, ensure that the board support package is installed on your system then enter a command similar to the following: - ``` - cmake .. -DFPGA_DEVICE=: - ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. + 3. Compile the design. (The provided targets match the recommended development flow.) 1. Compile for emulation (fast compile time, targets emulated FPGA device). @@ -206,25 +214,25 @@ After each kernel is launched, the host-side operations (that occur *after* the ### On Windows* ->**Note**: The Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) does not yet support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - 1. Change to the sample directory. -2. Build the program for **Intel® PAC with Intel Arria® 10 GX FPGA**, which is the default. +2. Build the program for the Agilex device family, which is the default. ``` mkdir build cd build cmake -G "NMake Makefiles" .. ``` - For **Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX)**, enter the following: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - - For a custom FPGA platform, ensure that the board support package is installed on your system then enter a command similar to the following: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: - ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 3. Compile the design. (The provided targets match the recommended development flow.) @@ -261,7 +269,7 @@ After each kernel is launched, the host-side operations (that occur *after* the ``` CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./n_way_buffering.fpga_sim ``` -3. Run the sample on the FPGA device. +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` ./n_way_buffering.fpga ``` @@ -278,7 +286,7 @@ After each kernel is launched, the host-side operations (that occur *after* the n_way_buffering.fpga_sim.exe set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run the sample on the FPGA device. +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`). ``` n_way_buffering.fpga.exe ``` diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/onchip_memory_cache/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/onchip_memory_cache/README.md index 36e5700fe4..f2b293e007 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/onchip_memory_cache/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/onchip_memory_cache/README.md @@ -4,7 +4,7 @@ This FPGA tutorial demonstrates how to build a simple cache (implemented in FPGA | Optimized for | Description --- |--- | OS | Linux* Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA
Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX)
Intel® FPGA 3rd party / custom platforms with oneAPI support
**Note**: Intel® FPGA PAC hardware is only compatible with Ubuntu 18.04* +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler | What you will learn | How and when to implement the on-chip memory cache optimization | Time to complete | 30 minutes @@ -17,6 +17,10 @@ This FPGA tutorial demonstrates how to build a simple cache (implemented in FPGA > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ## Prerequisites @@ -101,23 +105,26 @@ This tutorial creates multiple kernels sweeping across different cache depths wi ### On a Linux* System 1. Generate the `Makefile` by running `cmake`. - ``` - mkdir build - cd build - ``` - To compile for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: - ``` - cmake .. - ``` - Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - - ``` - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - ``` - cmake .. -DFPGA_DEVICE=: - ``` + ``` + mkdir build + cd build + ``` + To compile for the default target (the Agilex device family), run `cmake` using the command: + ``` + cmake .. + ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: @@ -142,23 +149,25 @@ This tutorial creates multiple kernels sweeping across different cache depths wi ### On a Windows* System 1. Generate the `Makefile` by running `cmake`. - ``` - mkdir build - cd build - ``` - To compile for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: - ``` - cmake -G "NMake Makefiles" .. - ``` - Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: - ``` + ``` + mkdir build + cd build + ``` + To compile for the default target (the Agilex device family), run `cmake` using the command: + ``` + cmake -G "NMake Makefiles" .. + ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: @@ -179,8 +188,6 @@ This tutorial creates multiple kernels sweeping across different cache depths wi nmake fpga ``` -> **Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - > **Note**: If you encounter any issues with long paths when compiling under Windows*, you may have to create your ‘build’ directory in a shorter path, for example c:\samples\build. You can then run cmake from that directory, and provide cmake with the full path to your sample directory. ## Examining the Reports @@ -208,7 +215,7 @@ Open the Kernel Memory viewer and compare the Load Latency on the loads from ker onchip_memory_cache.fpga_sim.exe set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run the sample on the FPGA device: +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`): ``` ./onchip_memory_cache.fpga (Linux) onchip_memory_cache.fpga.exe (Windows) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/optimize_inner_loop/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/optimize_inner_loop/README.md index fc594bceeb..9d727d8ae2 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/optimize_inner_loop/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/optimize_inner_loop/README.md @@ -4,7 +4,7 @@ This FPGA tutorial discusses optimizing the throughput of an inner loop with a l | Optimized for | Description --- |--- | OS | Linux* Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA
Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX)
Intel® FPGA 3rd party / custom platforms with oneAPI support
*__Note__: Intel® FPGA PAC hardware is only compatible with Ubuntu 18.04* +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler | What you will learn | How to optimize the throughput of an inner loop with a low trip. | Time to complete | 45 minutes @@ -17,6 +17,10 @@ This FPGA tutorial discusses optimizing the throughput of an inner loop with a l > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ## Prerequisites @@ -140,23 +144,26 @@ while (Pipe::read()) { ### On a Linux* System 1. Generate the `Makefile` by running `cmake`. - ``` - mkdir build - cd build - ``` - To compile for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: - ``` - cmake .. - ``` - Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - - ``` - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - ``` - cmake .. -DFPGA_DEVICE=: - ``` + ``` + mkdir build + cd build + ``` + To compile for the default target (the Agilex device family), run `cmake` using the command: + ``` + cmake .. + ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: @@ -181,23 +188,25 @@ while (Pipe::read()) { ### On a Windows* System 1. Generate the `Makefile` by running `cmake`. - ``` - mkdir build - cd build - ``` - To compile for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: - ``` - cmake -G "NMake Makefiles" .. - ``` - Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: - ``` + ``` + mkdir build + cd build + ``` + To compile for the default target (the Agilex device family), run `cmake` using the command: + ``` + cmake -G "NMake Makefiles" .. + ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: @@ -218,7 +227,6 @@ while (Pipe::read()) { nmake fpga ``` -*Note:* The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support.
*Note:* If you encounter any issues with long paths when compiling under Windows*, you may have to create your ‘build’ directory in a shorter path, for example c:\samples\build. You can then run cmake from that directory, and provide cmake with the full path to your sample directory. ## Examining the Reports @@ -253,7 +261,7 @@ Version 2 of the kernel (`Producer<2>`) explicitly bounds the inner loop trip co loop_carried_dependency.fpga_sim.exe set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run the sample on the FPGA device: +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`): ``` ./optimize_inner_loop.fpga (Linux) optimize_inner_loop.fpga.exe (Windows) @@ -282,7 +290,7 @@ You should see the following output in the console: Kernel 2 throughput: 636.29 MB/s PASSED ``` - NOTE: These throughput numbers were collected using the Intel® PAC with Intel Arria® 10 GX FPGA. + NOTE: These throughput numbers were collected using the Intel® PAC with Intel Arria® 10 GX FPGA. ## License diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/pipe_array/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/pipe_array/README.md index 0f9046d6f1..011faad4fd 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/pipe_array/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/pipe_array/README.md @@ -5,7 +5,7 @@ This FPGA tutorial showcases a design pattern that makes it possible to create a | Optimized for | Description --- |--- | OS | Linux* Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA
Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX)
Intel® FPGA 3rd party / custom platforms with oneAPI support
*__Note__: Intel® FPGA PAC hardware is only compatible with Ubuntu 18.04* +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler | What you will learn | A design pattern to generate an array of pipes using SYCL*
Static loop unrolling through template metaprogramming | Time to complete | 15 minutes @@ -18,6 +18,10 @@ This FPGA tutorial showcases a design pattern that makes it possible to create a > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ## Prerequisites @@ -182,24 +186,26 @@ The host must thus enqueue the producer kernel and `kNumRows * kNumCols` separat ### On a Linux* System 1. Generate the `Makefile` by running `cmake`. - ``` - mkdir build - cd build - ``` - To compile for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: - ``` - cmake .. - ``` - Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - - ``` - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - ``` - cmake .. -DFPGA_DEVICE=: - ``` - + ``` + mkdir build + cd build + ``` + To compile for the default target (the Agilex device family), run `cmake` using the command: + ``` + cmake .. + ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: * Compile for emulation (fast compile time, targets emulated FPGA device): @@ -223,23 +229,25 @@ The host must thus enqueue the producer kernel and `kNumRows * kNumCols` separat ### On a Windows* System 1. Generate the `Makefile` by running `cmake`. - ``` - mkdir build - cd build - ``` - To compile for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: - ``` - cmake -G "NMake Makefiles" .. - ``` - Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: - ``` + ``` + mkdir build + cd build + ``` + To compile for the default target (the Agilex device family), run `cmake` using the command: + ``` + cmake -G "NMake Makefiles" .. + ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: @@ -287,7 +295,7 @@ You can visualize the kernels and pipes generated by looking at the "System View pipe_array.fpga_sim.exe set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run the sample on the FPGA device: +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`): ``` ./pipe_array.fpga (Linux) pipe_array.fpga.exe (Windows) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/shannonization/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/shannonization/README.md index b698f45e2b..539020ff27 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/shannonization/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/shannonization/README.md @@ -4,7 +4,7 @@ This tutorial describes the process of _Shannonization_ (named after [Claude Sha | Optimized for | Description |:--- |:--- | OS | Linux* Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA
Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX)
Intel® FPGA 3rd party / custom platforms with oneAPI support
*__Note__: Intel® FPGA PAC hardware is only compatible with Ubuntu 18.04* +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler | What you will learn | How to make FPGA-specific optimizations to remove computation from the critical path and improve fMAX/II | Time to complete | 45 minutes @@ -17,6 +17,10 @@ This tutorial describes the process of _Shannonization_ (named after [Claude Sha > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ## Prerequisites @@ -162,23 +166,26 @@ To achieve an II of 1 for the main `while` loop in the FPGA code shown above, th ### On a Linux* System 1. Generate the `Makefile` by running `cmake`. - ``` - mkdir build - cd build - ``` - To compile for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: - ``` - cmake .. - ``` - Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - - ``` - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - ``` - cmake .. -DFPGA_DEVICE=: - ``` + ``` + mkdir build + cd build + ``` + To compile for the default target (the Agilex device family), run `cmake` using the command: + ``` + cmake .. + ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: @@ -203,23 +210,25 @@ To achieve an II of 1 for the main `while` loop in the FPGA code shown above, th ### On a Windows* System 1. Generate the `Makefile` by running `cmake`. - ``` - mkdir build - cd build - ``` - To compile for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: - ``` - cmake -G "NMake Makefiles" .. - ``` - Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: - ``` + ``` + mkdir build + cd build + ``` + To compile for the default target (the Agilex device family), run `cmake` using the command: + ``` + cmake -G "NMake Makefiles" .. + ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: @@ -240,8 +249,6 @@ To achieve an II of 1 for the main `while` loop in the FPGA code shown above, th nmake fpga ``` -*Note:* The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - ## Examining the Reports This section will walk through how the HTML reports show the result of the optimizations we made in each version of the kernel, the definition of which can be found in `src/IntersectionKernel.hpp`. Start by locating `report.html` in the `shannonization_report.prj/reports/` directory. Open the report in Chrome*, Firefox*, Edge*, or Internet Explorer*. The fMAX numbers mentioned in these sections assume that the Arria® 10 GX FPGA is the target. However, the discussion is similar for the Stratix® 10 SX FPGA. @@ -339,7 +346,7 @@ As a consequence of the fabric architecture of the Intel Stratix® 10 SX FPGA shannonization.fpga_sim.exe set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run the sample on the FPGA device: +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`): ``` ./shannonization.fpga (Linux) shannonization.fpga.exe (Windows) @@ -381,7 +388,7 @@ You should see the following output in the console: Kernel 2 average throughput: 742.257 MB/s PASSED ``` -> **Note**: These throughput numbers were collected using the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX). +> **Note**: These throughput numbers were collected using the Intel® FPGA PAC D5005 with Intel Stratix® 10 SX. ## License diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/simple_host_streaming/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/simple_host_streaming/README.md index 8decb023de..9258ddd007 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/simple_host_streaming/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/simple_host_streaming/README.md @@ -5,7 +5,7 @@ This tutorial demonstrates how to use SYCL* Universal Shared Memory (USM) to str | Optimized for | Description --- |--- | OS | Linux* Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX)
Intel® FPGA 3rd party / custom platforms with oneAPI support (and SYCL USM support)
**Note**: Intel® FPGA PAC hardware is only compatible with Ubuntu 18.04* +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler | What you will learn | How to achieve low-latency host-device streaming while maintaining throughput | Time to complete | 45 minutes @@ -18,8 +18,12 @@ This tutorial demonstrates how to use SYCL* Universal Shared Memory (USM) to str > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. -> **Notice**: SYCL USM host allocations (and therefore this tutorial) are only supported for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) with USM support (i.e., intel_s10sx_pac:pac_s10_usm)* +*Notice: SYCL USM host allocations, and therefore this tutorial, are only supported on FPGA boards that have a USM capable BSP (e.g. the Intel® FPGA PAC D5005 with Intel Stratix® 10 SX with USM support: intel_s10sx_pac:pac_s10_usm). USM host allocations are supported for all non FPGA board targets (e.g. Agilex).* > **Notice**: This tutorial demonstrates an implementation of host streaming that will be supplanted by better techniques in a future release. See the [Drawbacks and Future Work](#drawbacks-and-future-work)* @@ -134,18 +138,26 @@ We are currently working on an API and tutorial to address both of these drawbac ### On a Linux* System 1. Generate the `Makefile` by running `cmake`. - ``` - mkdir build - cd build - ``` - To compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - ``` - cmake .. - ``` - You can also compile for a custom FPGA platform with SYCL USM support. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - ``` - cmake .. -DFPGA_DEVICE=: -DUSM_HOST_ALLOCATIONS_ENABLED=1 - ``` + ``` + mkdir build + cd build + ``` + To compile for the default target (the Agilex device family), run `cmake` using the command: + ``` + cmake .. + ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: @@ -169,18 +181,25 @@ We are currently working on an API and tutorial to address both of these drawbac ### On a Windows* System 1. Generate the `Makefile` by running `cmake`. - ``` - mkdir build - cd build - ``` - To compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - ``` - cmake -G "NMake Makefiles" .. - ``` - You can also compile for a custom FPGA platform with SYCL USM support. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: -DUSM_HOST_ALLOCATIONS_ENABLED=1 - ``` + ``` + mkdir build + cd build + ``` + To compile for the default target (the Agilex device family), run `cmake` using the command: + ``` + cmake -G "NMake Makefiles" .. + ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: @@ -226,7 +245,7 @@ Locate `report.html` in the `simple_host_streaming_report.prj/reports/` director simple_host_streaming.fpga_sim.exe set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run the sample on the FPGA device: +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`): ``` ./simple_host_streaming.fpga (Linux) simple_host_streaming.fpga.exe (Windows) @@ -258,7 +277,7 @@ You should see the following output in the console: ``` > **Note**: The FPGA emulator does not accurately represent the performance (throughput or latency) of the kernels. -2. When running on the FPGA device +2. When running on the Intel® FPGA PAC D5005 with Intel Stratix® 10 SX with USM support: ``` # Chunks: 512 Chunk count: 32768 diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/triangular_loop/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/triangular_loop/README.md index 68c7652085..8aa16d0a43 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/triangular_loop/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/triangular_loop/README.md @@ -6,7 +6,7 @@ This FPGA tutorial demonstrates an advanced technique to improve the performance | Optimized for | Description |:--- |:--- | OS | Linux* Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA
Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX)
Intel® FPGA 3rd party / custom platforms with oneAPI support
**Note**: Intel® FPGA PAC hardware is only compatible with Ubuntu 18.04* +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler | What you will learn | How and when to apply the triangular loop optimization technique | Time to complete | 30 minutes @@ -19,6 +19,10 @@ This FPGA tutorial demonstrates an advanced technique to improve the performance > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ## Prerequisites @@ -209,24 +213,26 @@ Summing the number of real and dummy iterations gives the total iterations of th ### On a Linux* System 1. Generate the `Makefile` by running `cmake`. - ``` - mkdir build - cd build - ``` - To compile for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: - ``` - cmake .. - ``` - Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - - ``` - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - ``` - cmake .. -DFPGA_DEVICE=: - ``` + ``` + mkdir build + cd build + ``` + To compile for the default target (the Agilex device family), run `cmake` using the command: + ``` + cmake .. + ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: * Compile for emulation (fast compile time, targets emulated FPGA device): @@ -250,23 +256,25 @@ Summing the number of real and dummy iterations gives the total iterations of th ### On a Windows* System 1. Generate the `Makefile` by running `cmake`. - ``` - mkdir build - cd build - ``` - To compile for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: - ``` - cmake -G "NMake Makefiles" .. - ``` - Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: - ``` + ``` + mkdir build + cd build + ``` + To compile for the default target (the Agilex device family), run `cmake` using the command: + ``` + cmake -G "NMake Makefiles" .. + ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: @@ -287,8 +295,6 @@ Summing the number of real and dummy iterations gives the total iterations of th nmake fpga ``` -> **Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - > **Note**: If you encounter any issues with long paths when compiling under Windows*, you may have to create your ‘build’ directory in a shorter path, for example c:\samples\build. You can then run cmake from that directory, and provide cmake with the full path to your sample directory. ## Examining the Reports @@ -314,7 +320,7 @@ Consult the "Loop Analysis" report to compare the optimized and unoptimized vers triangular_loop.fpga_sim.exe set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run the sample on the FPGA device: +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`): ``` ./triangular_loop.fpga (Linux) triangular_loop.fpga.exe (Windows) @@ -346,12 +352,12 @@ Throughput with optimization: 904.489876 MB/s ``` ### Discussion of Results -A test compile of this tutorial design achieved an fMAX of approximately 210 MHz on the Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA. The results with and without the optimization are shown in the following table: +A test compile of this tutorial design achieved an fMAX of approximately 210 MHz on the Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA. The results with and without the optimization are shown in the following table: -Configuration | Overall Execution Time (ms) | Throughput (MB/s) -|:---|:---|:--- -|Without optimization | 4972 | 25.7 -|With optimization | 161 | 796.6 +Configuration | Overall Execution Time (ms) | Throughput (MB/s) +|:--- |:--- |:--- +|Without optimization | 4972 | 25.7 +|With optimization | 161 | 796.6 Without optimization, the compiler achieved an II of 30 on the inner-loop. With the optimization, the compiler achieves an II of 1, and the throughput increased by approximately 30x. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/README.md index 630cdcb4e4..1ca35885c4 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/README.md @@ -4,7 +4,7 @@ This tutorial demonstrates how to use zero-copy host memory via the SYCL Unified | Optimized for | Description |:--- |:--- | OS | Linux* Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX)
Intel® FPGA 3rd party / custom platforms with oneAPI support (and SYCL USM support)
*__Note__: Intel® FPGA PAC hardware is only compatible with Ubuntu 18.04* +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler | What you will learn | How to use SYCL USM host allocations for the FPGA | Time to complete | 15 minutes @@ -17,8 +17,12 @@ This tutorial demonstrates how to use zero-copy host memory via the SYCL Unified > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. -*Notice: SYCL USM host allocations (and therefore this tutorial) are only supported for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) with USM support (i.e., intel_s10sx_pac:pac_s10_usm)* +*Notice: SYCL USM host allocations, and therefore this tutorial, are only supported on FPGA boards that have a USM capable BSP (e.g. the Intel® FPGA PAC D5005 with Intel Stratix® 10 SX with USM support: intel_s10sx_pac:pac_s10_usm). USM host allocations are supported for all non FPGA board targets (e.g. Agilex).* ## Prerequisites @@ -83,19 +87,26 @@ This approach is not considered host streaming since the CPU and FPGA cannot (re ### On a Linux* System 1. Generate the `Makefile` by running `cmake`. - ``` - mkdir build - cd build - ``` - - To compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - ``` - cmake .. - ``` - You can also compile for a custom FPGA platform with SYCL USM support. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - ``` - cmake .. -DFPGA_DEVICE=: -DUSM_HOST_ALLOCATIONS_ENABLED=1 - ``` + ``` + mkdir build + cd build + ``` + To compile for the default target (the Agilex device family), run `cmake` using the command: + ``` + cmake .. + ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: @@ -116,23 +127,30 @@ This approach is not considered host streaming since the CPU and FPGA cannot (re make fpga ``` -3. (Optional) As the above hardware compile may take several hours to complete, an Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) precompiled binary (compatible with Linux* Ubuntu* 18.04) can be downloaded here. +3. (Optional) As the above hardware compile may take several hours to complete, an Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) precompiled binary (compatible with Linux* Ubuntu* 18.04) can be downloaded here. ### On a Windows* System 1. Generate the `Makefile` by running `cmake`. - ``` - mkdir build - cd build - ``` - To compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - ``` - cmake -G "NMake Makefiles" .. - ``` - You can also compile for a custom FPGA platform with SYCL USM support. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: -DUSM_HOST_ALLOCATIONS_ENABLED=1 - ``` + ``` + mkdir build + cd build + ``` + To compile for the default target (the Agilex device family), run `cmake` using the command: + ``` + cmake -G "NMake Makefiles" .. + ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: @@ -153,8 +171,6 @@ This approach is not considered host streaming since the CPU and FPGA cannot (re nmake fpga ``` -> **Note**: The Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) does not support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - > **Note**: If you encounter any issues with long paths when compiling under Windows*, you may have to create your `build` directory in a shorter path, for example `c:\samples\build`. You can then run cmake from that directory, and provide cmake with the full path to your sample directory. ## Examining the Reports @@ -167,7 +183,7 @@ Locate `report.html` in the `zero_copy_data_transfer_report.prj/reports/` direct ./zero_copy_data_transfer.fpga_emu (Linux) zero_copy_data_transfer.fpga_emu.exe (Windows) ``` -2. Run the sample on the FPGA simulator: +2. Run the sample on the FPGA simulator (the kernel executes on the CPU): * On Linux ``` CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./zero_copy_data_transfer.fpga_sim @@ -178,7 +194,7 @@ Locate `report.html` in the `zero_copy_data_transfer_report.prj/reports/` direct zero_copy_data_transfer.fpga_sim.exe set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run the sample on the FPGA device: +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`): ``` ./zero_copy_data_transfer.fpga (Linux) zero_copy_data_transfer.fpga.exe (Windows) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/README.md index 6be533e935..fae9f3d46c 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/README.md @@ -5,7 +5,7 @@ This FPGA tutorial demonstrates how to use the Algorithmic C (AC) data type `ac_ | Optimized for | Description |:--- |:--- | OS | CentOS*Linux 8
Red Hat* Enterprise Linux*8
SUSE* Linux Enterprise Server 15
Ubuntu*18.04 LTS
Ubuntu 20.04
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA
Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX)
Intel® FPGA 3rd party / custom platforms with oneAPI support
**Note**: Intel® FPGA PAC hardware is only compatible with Ubuntu 18.04* +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler | What you will learn | How different methods of `ac_fixed` number construction affect hardware resource utilization
Recommended method for constructing `ac_fixed` numbers in your kernel
Accessing and using the `ac_fixed` math library functions
Trading off accuracy of results for reduced resource usage on the FPGA | Time to complete | 30 minutes @@ -18,6 +18,10 @@ This FPGA tutorial demonstrates how to use the Algorithmic C (AC) data type `ac_ > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ## Prerequisites @@ -162,28 +166,26 @@ When you use the `ac_fixed` library, keep the following points in mind: 1. Install the design in `build` directory from the design directory by running `cmake`: - ```bash - mkdir build - cd build - ``` - - If you are compiling for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: - - ```bash - cmake .. - ``` - - Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - - ```bash - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - - You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - - ```bash - cmake .. -DFPGA_DEVICE=: - ``` + ``` + mkdir build + cd build + ``` + To compile for the default target (the Agilex device family), run `cmake` using the command: + ``` + cmake .. + ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 2. Compile the design using the generated `Makefile`. The following four build targets are provided that match the recommended development flow: @@ -217,28 +219,25 @@ When you use the `ac_fixed` library, keep the following points in mind: 1. Generate the `Makefile` by running `cmake`. - ``` - mkdir build - cd build - ``` - - To compile for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: - - ``` - cmake -G "NMake Makefiles" .. - ``` - - Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - - You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: - ``` + ``` + mkdir build + cd build + ``` + To compile for the default target (the Agilex device family), run `cmake` using the command: + ``` + cmake -G "NMake Makefiles" .. + ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: @@ -266,8 +265,6 @@ When you use the `ac_fixed` library, keep the following points in mind: nmake fpga ``` -> **Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not yet support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. - > **Note**: If you encounter any issues with long paths when compiling under Windows*, you might have to create your `build` directory in a shorter path, for example `c:\samples\build`. You can then run `cmake` from that directory, and provide `cmake` with the full path to your sample directory. ## Examining the Reports @@ -288,7 +285,7 @@ Scroll down on the Summary page of the report and expand the section titled **Co ac_fixed.fpga_emu.exe (Windows) ``` -2. Run the sample of the FPGA simulator device +2. Run the sample of the FPGA simulator device (the kernel executes on the CPU): * On Linux ```bash @@ -301,7 +298,7 @@ Scroll down on the Summary page of the report and expand the section titled **Co set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run the sample on the FPGA device +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`): ```bash ./ac_fixed.fpga (Linux) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_int/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_int/README.md index e2d4fff73f..2c4e2220f2 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_int/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_int/README.md @@ -5,7 +5,7 @@ This FPGA tutorial demonstrates how to use the Algorithmic C (AC) data type `ac_ | Optimized for | Description |:--- |:--- | OS | Linux* Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA
Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX)
Intel® FPGA 3rd party / custom platforms with oneAPI support
**Note**: Intel® FPGA PAC hardware is only compatible with Ubuntu 18.04* +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler | What you will learn | Using the `ac_int` data type for basic operations
Efficiently using the left shift operation
Setting and reading certain bits of an `ac_int` number | Time to complete | 20 minutes @@ -18,6 +18,10 @@ This FPGA tutorial demonstrates how to use the Algorithmic C (AC) data type `ac_ > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ## Prerequisites @@ -142,28 +146,26 @@ Kernel `BitOps` demonstrates bit operations with bit select operator `[]` and bi 1. Install the design in `build` directory from the design directory by running `cmake`: - ```bash - mkdir build - cd build - ``` - - If you are compiling for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: - - ```bash - cmake .. - ``` - - Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - - ```bash - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - - You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - - ```bash - cmake .. -DFPGA_DEVICE=: - ``` + ``` + mkdir build + cd build + ``` + To compile for the default target (the Agilex device family), run `cmake` using the command: + ``` + cmake .. + ``` + + > **Note**: You can change the default target by using the command: + > ``` + > cmake .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 2. Compile the design using the generated `Makefile`. The following four build targets are provided that match the recommended development flow: @@ -197,28 +199,25 @@ Kernel `BitOps` demonstrates bit operations with bit select operator `[]` and bi 1. Generate the `Makefile` by running `cmake`. - ``` - mkdir build - cd build - ``` - - To compile for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: - - ``` - cmake -G "NMake Makefiles" .. - ``` - - Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - - You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: - ``` + ``` + mkdir build + cd build + ``` + To compile for the default target (the Agilex device family), run `cmake` using the command: + ``` + cmake -G "NMake Makefiles" .. + ``` + > **Note**: You can change the default target by using the command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE= + > ``` + > + > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command: + > ``` + > cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: + > ``` + > + > You will only be able to run an executable on the FPGA if you specified a BSP. 2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: @@ -246,11 +245,6 @@ Kernel `BitOps` demonstrates bit operations with bit select operator `[]` and bi nmake fpga ``` -> **Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 -(with Intel Stratix® 10 SX) do not yet support Windows*. Compiling to FPGA -hardware on Windows* requires a third-party or custom Board Support Package -(BSP) with Windows* support. - > **Note**: If you encounter any issues with long paths when compiling under Windows*, you may have to create your ‘build’ directory in a shorter path, for example c:\samples\build. You can then run @@ -274,7 +268,7 @@ Navigate to *System Viewer* (*Views* > *System Viewer*) and find the cluster in ac_int.fpga_emu.exe (Windows) ``` -2. Run the sample of the FPGA simulator device +2. Run the sample of the FPGA simulator device (the kernel executes on the CPU): * On Linux ```bash @@ -287,7 +281,7 @@ Navigate to *System Viewer* (*Views* > *System Viewer*) and find the cluster in set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA= ``` -3. Run the sample on the FPGA device +3. Run the sample on the FPGA device (only if you ran `cmake` with `-DFPGA_DEVICE=:`): ```bash ./ac_int.fpga (Linux) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/dsp_control/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/dsp_control/README.md index fa3aa09284..4d9d9cb901 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/dsp_control/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/dsp_control/README.md @@ -3,9 +3,9 @@ This FPGA tutorial demonstrates how to set the implementation preference for certain math operations (addition, subtraction, and multiplication) between hardened DSP blocks and soft logic. | Optimized for | Description -|:--- |:--- +|:--- |:--- | OS | Linux* Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 -| Hardware | Intel® Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA
Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX)
Intel® FPGA 3rd party / custom platforms with oneAPI support
**Note**: Intel® FPGA PAC hardware is only compatible with Ubuntu 18.04* +| Hardware | Intel® CycloneV, Cyclone10GX, Agilex, Arria10, and Stratix10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler | What you will learn | How to apply global DSP control in command-line interface.
How to apply local DSP control in source code.
Scope of datatypes and math operations that support DSP control. | Time to complete | 15 minutes @@ -18,6 +18,10 @@ This FPGA tutorial demonstrates how to set the implementation preference for cer > - ModelSim® SE > > When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. +> +> When targeting the CycloneV FPGA family, Intel® Quartus® Standard Edition must be used instead of Intel® Quartus® Prime Pro Edition. +> +> :warning: The appropriate device files must be installed during the Intel® Quartus® installation. ## Prerequisites @@ -114,28 +118,26 @@ The second template argument `Propagate::