diff --git a/DirectProgramming/C++SYCL_FPGA/README.md b/DirectProgramming/C++SYCL_FPGA/README.md index da8698ad39..a6743bcb84 100644 --- a/DirectProgramming/C++SYCL_FPGA/README.md +++ b/DirectProgramming/C++SYCL_FPGA/README.md @@ -131,6 +131,7 @@ flowchart LR | [n_way_buffering](Tutorials/DesignPatterns/n_way_buffering) | [Tutorials/DesignPatterns](Tutorials/DesignPatterns) | How and when to apply the N-way buffering optimization technique | [onchip_memory_cache](Tutorials/DesignPatterns/onchip_memory_cache) | [Tutorials/DesignPatterns](Tutorials/DesignPatterns) | How and when to implement the on-chip memory cache optimization | [optimize_inner_loop](Tutorials/DesignPatterns/optimize_inner_loop) | [Tutorials/DesignPatterns](Tutorials/DesignPatterns) | How to optimize the throughput of an inner loop with a low trip +| [platform_designer](Tutorials/Tools/experimental/platform_designer) | [Tutorials/Tools](Tutorials/Tools) | How to use an IP Component with Intel® Quartus® Prime Pro Edition software suite and Platform Designer | [pipe_array](Tutorials/DesignPatterns/pipe_array) | [Tutorials/DesignPatterns](Tutorials/DesignPatterns) | A design pattern to generate an array of pipes using SYCL*
Static loop unrolling through template metaprogramming | [private_copies](Tutorials/Features/private_copies) | [Tutorials/Features](Tutorials/Features) | The basic usage of the `private_copies` attribute
How the `private_copies` attribute affects the throughput and resource use of your FPGA program
How to apply the `private_copies` attribute to variables or arrays in your program
How to identify the correct `private_copies` factor for your program | [read_only_cache](Tutorials/Features/read_only_cache) | [Tutorials/Features](Tutorials/Features) | How and when to use the read-only cache feature diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/README.md new file mode 100644 index 0000000000..b5e1aa38da --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/README.md @@ -0,0 +1,318 @@ +# `Platform Designer` Sample + +This example design shows how to use an FPGA IP produced with the Intel® oneAPI DPC++/C++ Compiler with the Intel® Quartus® Prime Pro Edition software suite. + +| Optimized for | Description +|:--- |:--- +| OS | Linux* Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 +| Hardware | This process applies to any Intel® FPGA that is supported by the DPC++/C++ compiler, but the sample Intel® Quartus® Prime Pro Edition project targets the [Intel® Arria® 10 SX SoC Development Kit](https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/arria/10-sx.html) +| Software | Intel® oneAPI DPC++/C++ Compiler
Intel® Quartus® Prime Pro Edition Version 22.3 or later +| What you will learn | How to integrate an RTL IP generated from a SYCL kernel with an Intel® Quartus® Prime Pro Edition project +| Time to complete | 1 hour + +> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. +> +> To use the simulator flow, Intel® Quartus® Prime Pro Edition and one of the following simulators must be installed and accessible through your PATH: +> - Questa*-Intel® FPGA Edition +> - Questa*-Intel® FPGA Starter Edition +> - Questa* Advanced Simulator +> - ModelSim® SE +> +> To use the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. + +> **Note**: In oneAPI full systems, kernels that use SYCL Unified Shared Memory (USM) host allocations or USM shared allocations (and therefore the code in this tutorial) are supported only by Board Support Packages (BSPs) with USM support (for example the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) `intel_s10sx_pac:pac_s10_usm`). Kernels that use these types of allocations can always be used to generate standalone IPs. + +## Prerequisites + +This sample is part of the FPGA code samples. +It is categorized as a Tier 1 sample that helps you getting started. + +```mermaid +flowchart LR + tier1("Tier 1: Get Started") + tier2("Tier 2: Explore the Fundamentals") + tier3("Tier 3: Explore the Advanced Techniques") + tier4("Tier 4: Explore the Reference Designs") + + tier1 --> tier2 --> tier3 --> tier4 + + style tier1 fill:#f96,stroke:#333,stroke-width:1px,color:#fff + style tier2 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff + style tier3 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff + style tier4 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff +``` + +Find more information about how to navigate this part of the code samples in the [FPGA top-level README.md](/DirectProgramming/C++SYCL_FPGA/README.md). +You can also find more information about [troubleshooting build errors](/DirectProgramming/C++SYCL_FPGA/README.md#troubleshooting), [running the sample on the Intel® DevCloud](/DirectProgramming/C++SYCL_FPGA/README.md#build-and-run-the-samples-on-intel-devcloud-optional), [using Visual Studio Code with the code samples](/DirectProgramming/C++SYCL_FPGA/README.md#use-visual-studio-code-vs-code-optional), [links to selected documentation](/DirectProgramming/C++SYCL_FPGA/README.md#documentation), etc. + +## Purpose + +This sample demonstrates how to compile a SYCL kernel into an IP component and add that component to an Intel® Platform Designer system, and how to run the resulting system on a hardware board. The sample uses the JTAG to Avalon® Master Bridge Intel FPGA IP to expose your IP component to the JTAG control interface. You can use the System Console application to control and observe the behavior of your IP component. + +![](assets/csr-output-example-simple.svg) + +This example is intended for users interested in creating standalone modules that can be included in Intel® Quartus® Prime projects. It serves as a minimal example, and while it targets a specific board, a user familiar with the Intel® Quartus® Prime Software Suite should be able to easily port this design to other hardware. + +### Board-specific Considerations + +This design is intended to work with the Intel® Arria® 10 SX SoC Development Kit. The board-specific configurations that you should specify in Intel® Quartus® Prime are as follows: +1. Choose `10AS066N3F40E2SG` device to match the devkit +2. Choose pin `PIN_AM10` to drive the `i_clk` signal +3. Choose pin `PIN_AR23` to drive the `fpga_led` signal +4. Choose pin `PIN_AV21` to drive the `reset_button_n` signal +5. Use `jtag.sdc` from the Intel® Arria® 10 SoC Golden Hardware Reference Design (GHRD) [source code](https://github.com/altera-opensource/ghrd-socfpga). + +## Building the `platform_designer` Tutorial + +> **Note**: When working with the command-line interface (CLI), you should configure the oneAPI toolkits using environment variables. +> Set up your CLI environment by sourcing the `setvars` script located in the root of your oneAPI installation every time you open a new terminal window. +> This practice ensures that your compiler, libraries, and tools are ready for development. +> +> Linux*: +> - For system-wide installations: `. /opt/intel/oneapi/setvars.sh` +> - For private installations: ` . ~/intel/oneapi/setvars.sh` +> - For non-POSIX shells, like csh, use the following command: `bash -c 'source /setvars.sh ; exec csh'` +> +> Windows*: +> - `C:\Program Files(x86)\Intel\oneAPI\setvars.bat` +> - Windows PowerShell*, use the following command: `cmd.exe "/K" '"C:\Program Files (x86)\Intel\oneAPI\setvars.bat" && powershell'` +> +> For more information on configuring environment variables, see [Use the setvars Script with Linux* or macOS*](https://www.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/oneapi-development-environment-setup/use-the-setvars-script-with-linux-or-macos.html) or [Use the setvars Script with Windows*](https://www.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/oneapi-development-environment-setup/use-the-setvars-script-with-windows.html). + +Follow these steps to compile and test the design: +1. Compile the SYCL code to RTL. Although this design supports emulation and simulation like other FPGA code samples, they are not the focus of this tutorial. The emulation and simulation commands have been omitted. + + Linux: + + ```bash + $> cd add-oneapi + $> mkdir build + $> cd build + $> cmake .. + $> make fpga_ip_export + ``` + + Windows: + + ```bash + > cd add-oneapi + > mkdir build + > cd build + > cmake -G "NMake Makefiles" .. + > nmake fpga_ip_export + ``` + +2. **From the same terminal**, launch the Intel® Quartus® Prime Pro Edition GUI, and create a new Intel® Quartus® Prime project using the 'New Project' wizard. + +> **Note**: You may confirm your Intel® Quartus® Prime project settings by comparing with the sample Intel® Quartus® Prime project included in the `add-quartus-sln` directory. + + Linux: + + ``` + $> cd ../../ + $> mkdir add-quartus + $> cd add-quartus + $> quartus + ``` + + Windows: + + ``` + > cd ..\..\ + > mkdir add-quartus + > cd add-quartus + > quartus.exe + ``` + + 1. Set the project directory to be the `add-quartus` directory of this code sample. + + 2. Set the top-level entity to be `add` to make project management easier. + + ![](assets/quartus_new_project.png) + + 3. Choose **Empty Project** when prompted to select a project type. + + 4. Add the source file `add.sv` and `jtag.sdc` to the design when the wizard prompts you. These may be copied from `add-quartus-sln`. + + ![](assets/add-files.png) + + 5. Make sure you choose an appropriate device. See **Board-specific Considerations** above. + +3. Copy the generated IP to the Intel Quartus® Prime project. This design uses host pipes, which generates additional internal SYCL kernels. The `fpga_ip_export` build target uses the `-fsycl-device-code-split=per_kernel` flag to separate these additional kernels from your kernel, but these kernels have their own reports and associated RTL. You must locate the the `.prj_X` directory that contains the IP you want to use in your design. + + You can identify the correct `.prj_X` folder by looking for the folder that contains `*_di_inst.v` file where the interfaces match your kernel. For example, in this project, `add_xample.fpga_ip.prj_1` is the correct `.prj_x` directory, because `add_example_fpga_ip_1_di_inst.v` contains only a CSR Agent interface in addition to the clock/reset signals: + + ```verilog + add_fpga_ip_export_1_di add_fpga_ip_export_1_di_inst ( + // Interface: clock (clock end) + .clock ( ), // 1-bit clk input + // Interface: resetn (reset end) + .resetn ( ), // 1-bit reset_n input + // Interface: device_exception_bus (conduit end) + .device_exception_bus ( ), // 64-bit data output + // Interface: kernel_irqs (interrupt end) + .kernel_irqs ( ), // 1-bit irq output + // Interface: csr_ring_root_avs (avalon end) + .csr_ring_root_avs_read ( ), // 1-bit read input + .csr_ring_root_avs_readdata ( ), // 64-bit readdata output + .csr_ring_root_avs_readdatavalid( ), // 1-bit readdatavalid output + .csr_ring_root_avs_write ( ), // 1-bit write input + .csr_ring_root_avs_writedata ( ), // 64-bit writedata input + .csr_ring_root_avs_address ( ), // 5-bit address input + .csr_ring_root_avs_byteenable ( ), // 8-bit byteenable input + .csr_ring_root_avs_waitrequest ( ) // 1-bit waitrequest output + ); + ``` + + Linux: + + ``` + $> cd .. # navigate to project root if not there already + $> cp -r add-oneapi/build/add.fpga_ip_export.prj_1/ add-quartus/ + ``` + + Windows: + + ``` + > cd .. # navigate to project root if not there already + > xcopy add-oneapi\build\add.fpga_ip_export.prj_1\ add-quartus\add.fpga_ip_export.prj_1 /e /s /i + ``` + +4. Create the Platform Designer system. + + 1. Open Platform Designer from the Intel® Quartus® Prime GUI: + + ![](assets/open-platform-designer-button.png) + + Create a new system by clicking the 'New Platform Designer System' button (![](assets/new-platform-designer-system-button.png)) and name it `add_kernel_wrapper.qsys`. + + Configure the `Reset Bridge` IP as shown: + + ![](assets/reset-bridge.png) + + 2. Add the following IP to your system: + + * Basic Functions > Bridges and Adaptors > Memory Mapped > **JTAG to Avalon Master Bridge Intel® FPGA IP** + + * oneAPI > **add_fpga_ip_export_1_di** + + ![](assets/add-ip-platform-designer.png) + + 3. Connect the modules as shown: + + ![](assets/complete-system_platform-designer.png) + + Don't forget to export the `irq_add` and `exception_add` signals. The provided top-level RTL file (`add.sv`) uses the generated IP. Following these naming conventions allows the IP to connect to this handwritten RTL. + + > **Important**: If you are using the oneAPI Base Toolkit 2023.1, the DCP++/C++ compiler causes the generated IP to be incorrectly documented in its hardware TCL script. You can override this in Platform Designer by changing the signal type of the `resetn` signal to `reset_n`: + > + > ![](assets/fix-reset_n-platform-designer.png) + + 4. Save the system by clicking `File` > `Save` + + 5. Generate the system so that it can be included in the Intel® Quartus® Prime project by clicking `Generate HDL...` + + ![](assets/generate-hdl.png) + + 6. Close Platform Designer. + +6. In the Intel® Quartus® Prime window, run Analysis and Elaboration by clicking 'Start Analysis and Elaboration'. + + ![](assets/start-analysis.png) + +7. Select pins for the `i_clk` and `reset_button_n` inputs and `fpga_led` output. The JTAG to Avalon® Master Bridge Intel FPGA IP handles the connection between your design and the JTAG pins on your board automatically. + + 1. Open the pin planner using `Assignments` > `Pin Planner` in the main Intel® Quartus® Prime GUI. Consult the data sheet for your board to choose an appropriate clock input. In this project, the `PIN_AM10` was chosen because it supplies a 100MHz clock signal in the the GHRD source code (see link in **Board-specifc Considerations**). + + 2. Assign pins for the `fpga_led` and `reset_button_n` signals using the same method: + + *Pin planner from GHRD:* + + ![](assets/pins-from-ghrd.png) + + *Final pin planner configuration:* + + ![](assets/pins-from-design.png) + +8. Add the timing constraints. + + 1. If you are using the Intel® Arria® 10 SX SoC Dev Kit, you can find a timing constraints file for the JTAG interface (jtag.sdc) in the GHRD. This file was added during project creation. + + 2. Create a new Synopsis Design Constraints (SDC) file named `add.sdc` and insert a new clock called `i_clk` to match the clock you defined in `add.sv`. Set the period to be 10ns: + + ``` + set_time_format -unit ns -decimal_places 3 + create_clock -name i_clk -period 10 [get_ports {i_clk}] + ``` + + 3. Cut the clock paths for asynchronous I/O: + + ``` + set_false_path -from [get_ports {reset_button_n}] -to * + set_false_path -from [get_ports {fpga_led}] -to * + set_false_path -from * -to [get_ports {fpga_led}] + ``` + +9. Compile the full design by clicking the 'Start Compilation' button in the Intel® Quartus® Prime GUI. + + ![](assets/start-compilation-quartus.png) + +10. Copy the generated `add.sof` file to the `system_console` directory. + +### Additional Documentation +- [Intel® Arria® 10 SoC Golden System Reference Design](https://rocketboards.org/foswiki/Documentation/Arria10SoCGSRD) describes a reference design you can use with your Intel® Arria® 10 SX SoC Developer kit. +- [Intel® Arria® 10 SX SoC Development Kit](https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/arria/10-sx.html) describes the Intel® Arria® 10 SX SoC Development kit in greater detail. +- [Intel® FPGA Software Installation and Licensing](https://www.intel.com/content/www/us/en/docs/programmable/683472/current/) describes how to license Intel® Quartus® Prime Pro Edition software. +- [Intel® Quartus® Prime Pro Edition User Guide: Getting Started](https://www.intel.com/content/www/us/en/docs/programmable/683463/current/) introduces you to the Intel® Quartus® Prime Pro Edition software. +- [Intel® Quartus® Prime Pro Edition User Guide: Platform Designer](https://www.intel.com/content/www/us/en/docs/programmable/683609/current/) describes the Intel® Platform Designer software. +- [Intel® Quartus® Prime Pro Edition User Guide: Programmer](https://www.intel.com/content/www/us/en/docs/programmable/683039/current/) describes the Intel® Quartus® Prime Pro Programmer software. + +## Running the Sample + +Use the `test.bat` script in the `system_console` directory to flash the design to your development board, and launch the system console. The included `.tcl` scripts in the `system_console` directory demonstrate how to use the System Console to interact with your IP through the JTAG to Avalon® Master Bridge Intel FPGA IP on the FPGA. + +To move the design to a different computer, copy the `system_console` and directories from the `add-quartus` directory. + +See output: + +``` +> test.bat +Info: ******************************************************************* +Info: Running Quartus Prime Programmer + +Info: Quartus Prime Programmer was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 1309 megabytes + Info: Processing ended: Wed Feb 8 15:26:54 2023 + Info: Elapsed time: 00:00:20 + Info: System process ID: 16980 +Press any key to continue . . . + +--------------------------------------- +--------------------------------------- + Welcome to Intel's FPGA System Console + + +--------------------------------------- +% source jtag_avmm.tcl +% source read_outputs.tcl +Outputs: + Data (0x80): 0x00000000 0x00000000 + Status (0x00): 0x00050000 0x00000000 + finish (0x30): 0x00000000 0x00000000 +% source load_inputs.tcl +Store 6 to address 0x94 +Store 3 to address 0x90 +Set 'Start' bit to 1 +% source read_outputs.tcl +Outputs: + Data (0x80): 0x00000009 0x00000000 + Status (0x00): 0x00050002 0x00000000 + finish (0x30): 0x00000001 0x00000000 +% +``` + +## License +Code samples are licensed under the MIT license. See +[License.txt](https://github.com/oneapi-src/oneAPI-samples/blob/master/License.txt) for details. + +Third party program Licenses can be found here: [third-party-programs.txt](https://github.com/oneapi-src/oneAPI-samples/blob/master/third-party-programs.txt). \ No newline at end of file diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/README_2023-0.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/README_2023-0.md new file mode 100644 index 0000000000..6eba2b5ab4 --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/README_2023-0.md @@ -0,0 +1,327 @@ +# `Platform Designer` Sample + +This example design shows how to use an FPGA IP produced with the Intel® oneAPI DPC++/C++ Compiler with the Intel® Quartus® Prime Pro Edition software suite. + +| Optimized for | Description +|:--- |:--- +| OS | Linux* Ubuntu* 18.04/20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10 +| Hardware | This process applies to any Intel® FPGA that is supported by the DPC++/C++ compiler, but the sample Intel® Quartus® Prime Pro Edition project targets the [Intel® Arria® 10 SX SoC Development Kit](https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/arria/10-sx.html) +| Software | Intel® oneAPI DPC++/C++ Compiler
Intel® Quartus® Prime Pro Edition Version 22.3 or later +| What you will learn | How to integrate an RTL IP generated from a SYCL kernel with an Intel® Quartus® Prime Pro Edition project +| Time to complete | 1 hour + +> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. +> +> To use the simulator flow, Intel® Quartus® Prime Pro Edition and one of the following simulators must be installed and accessible through your PATH: +> - Questa*-Intel® FPGA Edition +> - Questa*-Intel® FPGA Starter Edition +> - ModelSim® SE +> +> To use the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH. + +> **Note**: In oneAPI full systems, kernels that use SYCL Unified Shared Memory (USM) host allocations or USM shared allocations (and therefore the code in this tutorial) are supported only by Board Support Packages (BSPs) with USM support (for example the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) `intel_s10sx_pac:pac_s10_usm`). Kernels that use these types of allocations can always be used to generate standalone IPs. + +## Prerequisites + +This sample is part of the FPGA code samples. +It is categorized as a Tier 1 sample that helps you getting started. + +```mermaid +flowchart LR + tier1("Tier 1: Get Started") + tier2("Tier 2: Explore the Fundamentals") + tier3("Tier 3: Explore the Advanced Techniques") + tier4("Tier 4: Explore the Reference Designs") + + tier1 --> tier2 --> tier3 --> tier4 + + style tier1 fill:#f96,stroke:#333,stroke-width:1px,color:#fff + style tier2 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff + style tier3 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff + style tier4 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff +``` + +Find more information about how to navigate this part of the code samples in the [FPGA top-level README.md](/DirectProgramming/C++SYCL_FPGA/README.md). +You can also find more information about [troubleshooting build errors](/DirectProgramming/C++SYCL_FPGA/README.md#troubleshooting), [running the sample on the Intel® DevCloud](/DirectProgramming/C++SYCL_FPGA/README.md#build-and-run-the-samples-on-intel-devcloud-optional), [using Visual Studio Code with the code samples](/DirectProgramming/C++SYCL_FPGA/README.md#use-visual-studio-code-vs-code-optional), [links to selected documentation](/DirectProgramming/C++SYCL_FPGA/README.md#documentation), etc. + +## Purpose + +This sample demonstrates how to compile a SYCL kernel into an IP component and add that component to an Intel® Platform Designer system, and how to run the resulting system on a hardware board. The sample uses the JTAG to Avalon® Master Bridge Intel FPGA IP to expose your IP component to the JTAG control interface. You can use the System Console application to control and observe the behavior of your IP component. + +![](assets/csr-output-example-simple.svg) + +This example is intended for users interested in creating standalone modules that can be included in Intel® Quartus® Prime projects. It serves as a minimal example, and while it targets a specific board, a user familiar with the Intel® Quartus® Prime Software Suite should be able to easily port this design to other hardware. + +### Board-specific Considerations + +This design is intended to work with the Intel® Arria® 10 SX SoC Development Kit. The board-specific configurations that you should specify in Intel® Quartus® Prime are as follows: +1. Choose `10AS066N3F40E2SG` device to match the devkit +2. Choose pin `PIN_AM10` to drive the `i_clk` signal +3. Choose pin `PIN_AR23` to drive the `fpga_led` signal +4. Choose pin `PIN_AV21` to drive the `reset_button_n` signal +5. Use `jtag.sdc` from the Intel® Arria® 10 SoC Golden Hardware Reference Design (GHRD) [source code](https://github.com/altera-opensource/ghrd-socfpga). + +## Building the `platform_designer` Tutorial + +> **Note**: When working with the command-line interface (CLI), you should configure the oneAPI toolkits using environment variables. +> Set up your CLI environment by sourcing the `setvars` script located in the root of your oneAPI installation every time you open a new terminal window. +> This practice ensures that your compiler, libraries, and tools are ready for development. +> +> Linux*: +> - For system-wide installations: `. /opt/intel/oneapi/setvars.sh` +> - For private installations: ` . ~/intel/oneapi/setvars.sh` +> - For non-POSIX shells, like csh, use the following command: `bash -c 'source /setvars.sh ; exec csh'` +> +> Windows*: +> - `C:\Program Files(x86)\Intel\oneAPI\setvars.bat` +> - Windows PowerShell*, use the following command: `cmd.exe "/K" '"C:\Program Files (x86)\Intel\oneAPI\setvars.bat" && powershell'` +> +> For more information on configuring environment variables, see [Use the setvars Script with Linux* or macOS*](https://www.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/oneapi-development-environment-setup/use-the-setvars-script-with-linux-or-macos.html) or [Use the setvars Script with Windows*](https://www.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/oneapi-development-environment-setup/use-the-setvars-script-with-windows.html). + +Follow these steps to compile and test the design: +1. Compile the SYCL code to RTL. Although this design supports emulation and simulation like other FPGA code samples, they are not the focus of this tutorial. The emulation and simulation commands have been omitted. + + Linux: + + ```bash + $> cd add-oneapi + $> mkdir build + $> cd build + $> cmake .. + $> make fpga_ip_export + ``` + + Windows: + + ```bash + > cd add-oneapi + > mkdir build + > cd build + > cmake -G "NMake Makefiles" .. + > nmake fpga_ip_export + ``` + +2. **From the same terminal**, launch the Intel® Quartus® Prime Pro Edition GUI, and create a new Intel® Quartus® Prime project using the 'New Project' wizard. + +> **Note**: You may confirm your Intel® Quartus® Prime project settings by comparing with the sample Intel® Quartus® Prime project included in the `add-quartus-sln` directory. + + Linux: + + ``` + $> cd ../../ + $> mkdir add-quartus + $> cd add-quartus + $> quartus + ``` + + Windows: + + ``` + > cd ..\..\ + > mkdir add-quartus + > cd add-quartus + > quartus.exe + ``` + + 1. Set the project directory to be the `add-quartus` directory of this code sample. + + 2. Set the top-level entity to be `add` to make project management easier. + + ![](assets/quartus_new_project.png) + + 3. Choose **Empty Project** when prompted to select a project type. + + 4. Add the source file `add.sv` and `jtag.sdc` to the design when the wizard prompts you. These may be copied from `add-quartus-sln`. + + ![](assets/add-files.png) + + 5. Make sure you choose an appropriate device. See **Board-specific Considerations** above. + +3. Copy the generated IP to the Intel Quartus® Prime project. This design uses host pipes, which generates additional internal SYCL kernels. The `fpga_ip_export` build target uses the `-fsycl-device-code-split=per_kernel` flag to separate these additional kernels from your kernel, but these kernels have their own reports and associated RTL. You must locate the the `.prj_X` directory that contains the IP you want to use in your design. + + You can identify the correct `.prj_X` folder by looking for the folder that contains `*_di_inst.v` file where the interfaces match your kernel. For example, in this project, `add_xample.fpga_ip.prj_1` is the correct `.prj_x` directory, because `add_example_fpga_ip_1_di_inst.v` contains only a CSR Agent interface in addition to the clock/reset signals: + + ```verilog + add_fpga_ip_export_1_di add_fpga_ip_export_1_di_inst ( + // Interface: clock (clock end) + .clock ( ), // 1-bit clk input + // Interface: clock2x (clock end) + .clock2x ( ), // 1-bit clk input + // Interface: resetn (conduit end) + .resetn ( ), // 1-bit data input + // Interface: device_exception_bus (conduit end) + .device_exception_bus ( ), // 64-bit data output + // Interface: kernel_irqs (interrupt end) + .kernel_irqs ( ), // 1-bit irq output + // Interface: csr_ring_root_avs (avalon end) + .csr_ring_root_avs_read ( ), // 1-bit read input + .csr_ring_root_avs_readdata ( ), // 64-bit readdata output + .csr_ring_root_avs_readdatavalid( ), // 1-bit readdatavalid output + .csr_ring_root_avs_write ( ), // 1-bit write input + .csr_ring_root_avs_writedata ( ), // 64-bit writedata input + .csr_ring_root_avs_address ( ), // 5-bit address input + .csr_ring_root_avs_byteenable ( ), // 8-bit byteenable input + .csr_ring_root_avs_waitrequest ( ) // 1-bit waitrequest output + ); + ``` + + Linux: + + ``` + $> cd .. # navigate to project root if not there already + $> cp -r add-oneapi/build/add.fpga_ip_export.prj_1/ add-quartus/ + ``` + + Windows: + + ``` + > cd .. # navigate to project root if not there already + > xcopy add-oneapi\build\add.fpga_ip_export.prj_1\ add-quartus\add.fpga_ip_export.prj_1 /e /s /i + ``` + +4. [oneAPI 2023.0 only] Correct the generated `_hw.tcl` file by running the `*_di_hw_tcl_adjustment_script.py` script in the .prj directory. + + Linux/Windows: + + ``` + $> cd add.fpga_ip_export.prj_1 + $> python add_fpga_ip_export_1_di_hw_tcl_adjustment_script.py + Success! Adjusted add_fpga_ip_export_1_di_hw.tcl file! + The adjustment log is in: adjustments_di_hw_tcl.log + The original file is in: add_fpga_ip_export_1_di_hw.tcl_original + ``` + +5. Create the Platform Designer system. + + 1. Open Platform Designer from the Intel® Quartus® Prime GUI: + + ![](assets/open-platform-designer-button.png) + + Create a new system by clicking the 'New Platform Designer System' button (![](assets/new-platform-designer-system-button.png)) and name it `add_kernel_wrapper.qsys`. + + Configure the `Reset Bridge` IP as shown: + + ![](assets/reset-bridge.png) + + 2. Add the following IP to your system: + + * Basic Functions > Bridges and Adaptors > Memory Mapped > **JTAG to Avalon Master Bridge Intel® FPGA IP** + + * oneAPI > **add_fpga_ip_export_1_di** + + ![](assets/add-ip-platform-designer.png) + + 3. Connect the modules as shown: + + ![](assets/complete-system_platform-designer.png) + + Don't forget to export the `irq_add` and `exception_add` signals. The provided top-level RTL file (`add.sv`) uses the generated IP. Following these naming conventions allows the IP to connect to this handwritten RTL. + + 4. Save the system by clicking `File` > `Save` + + 5. Generate the system so that it can be included in the Intel® Quartus® Prime project by clicking `Generate HDL...` + + ![](assets/generate-hdl.png) + + 6. Close Platform Designer. + +6. In the Intel® Quartus® Prime window, run Analysis and Elaboration by clicking 'Start Analysis and Elaboration'. + + ![](assets/start-analysis.png) + +7. Select pins for the `i_clk` and `reset_button_n` inputs and `fpga_led` output. The JTAG to Avalon® Master Bridge Intel FPGA IP handles the connection between your design and the JTAG pins on your board automatically. + + 1. Open the pin planner using `Assignments` > `Pin Planner` in the main Intel® Quartus® Prime GUI. Consult the data sheet for your board to choose an appropriate clock input. In this project, the `PIN_AM10` was chosen because it supplies a 100MHz clock signal in the the GHRD source code (see link in **Board-specifc Considerations**). + + 2. Assign pins for the `fpga_led` and `reset_button_n` signals using the same method: + + *Pin planner from GHRD:* + + ![](assets/pins-from-ghrd.png) + + *Final pin planner configuration:* + + ![](assets/pins-from-design.png) + +8. Add the timing constraints. + + 1. If you are using the Intel® Arria® 10 SX SoC Dev Kit, you can find a timing constraints file for the JTAG interface (jtag.sdc) in the GHRD. This file was added during project creation. + + 2. Create a new Synopsis Design Constraints (SDC) file named `add.sdc` and insert a new clock called `i_clk` to match the clock you defined in `add.sv`. Set the period to be 10ns: + + ``` + set_time_format -unit ns -decimal_places 3 + create_clock -name i_clk -period 10 [get_ports {i_clk}] + ``` + + 3. Cut the clock paths for asynchronous I/O: + + ``` + set_false_path -from [get_ports {reset_button_n}] -to * + set_false_path -from [get_ports {fpga_led}] -to * + set_false_path -from * -to [get_ports {fpga_led}] + ``` + +9. Compile the full design by clicking the 'Start Compilation' button in the Intel® Quartus® Prime GUI. + + ![](assets/start-compilation-quartus.png) + +10. Copy the generated `add.sof` file to the `system_console` directory. + +### Additional Documentation +- [Intel® Arria® 10 SoC Golden System Reference Design](https://rocketboards.org/foswiki/Documentation/Arria10SoCGSRD) describes a reference design you can use with your Intel® Arria® 10 SX SoC Developer kit. +- [Intel® Arria® 10 SX SoC Development Kit](https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/arria/10-sx.html) describes the Intel® Arria® 10 SX SoC Development kit in greater detail. +- [Intel® FPGA Software Installation and Licensing](https://www.intel.com/content/www/us/en/docs/programmable/683472/current/) describes how to license Intel® Quartus® Prime Pro Edition software. +- [Intel® Quartus® Prime Pro Edition User Guide: Getting Started](https://www.intel.com/content/www/us/en/docs/programmable/683463/current/) introduces you to the Intel® Quartus® Prime Pro Edition software. +- [Intel® Quartus® Prime Pro Edition User Guide: Platform Designer](https://www.intel.com/content/www/us/en/docs/programmable/683609/current/) describes the Intel® Platform Designer software. +- [Intel® Quartus® Prime Pro Edition User Guide: Programmer](https://www.intel.com/content/www/us/en/docs/programmable/683039/current/) describes the Intel® Quartus® Prime Pro Programmer software. + +## Running the Sample + +Use the `test.bat` script in the `system_console` directory to flash the design to your development board, and launch the system console. The included `.tcl` scripts in the `system_console` directory demonstrate how to use the System Console to interact with your IP through the JTAG to Avalon® Master Bridge Intel FPGA IP on the FPGA. + +To move the design to a different computer, copy the `system_console` and directories from the `add-quartus` directory. + +See output: + +``` +> test.bat +Info: ******************************************************************* +Info: Running Quartus Prime Programmer + +Info: Quartus Prime Programmer was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 1309 megabytes + Info: Processing ended: Wed Feb 8 15:26:54 2023 + Info: Elapsed time: 00:00:20 + Info: System process ID: 16980 +Press any key to continue . . . + +--------------------------------------- +--------------------------------------- + Welcome to Intel's FPGA System Console + + +--------------------------------------- +% source jtag_avmm.tcl +% source read_outputs.tcl +Outputs: + Data (0x78): 0x00000000 0x00000000 + Status (0x00): 0x00040000 + finish (0x28): 0x00000000 0x00000000 +% source load_inputs.tcl +Store 6 to address 0x88 +Store 3 to address 0x8c +Set 'Start' bit to 1 +% source read_outputs.tcl +Outputs: + Data (0x78): 0x00000009 0x00000000 + Status (0x00): 0x00040002 + finish (0x28): 0x00000001 0x00000000 +% +``` + +## License +Code samples are licensed under the MIT license. See +[License.txt](https://github.com/oneapi-src/oneAPI-samples/blob/master/License.txt) for details. + +Third party program Licenses can be found here: [third-party-programs.txt](https://github.com/oneapi-src/oneAPI-samples/blob/master/third-party-programs.txt). \ No newline at end of file diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-oneapi/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-oneapi/CMakeLists.txt new file mode 100644 index 0000000000..46558396f4 --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-oneapi/CMakeLists.txt @@ -0,0 +1,320 @@ +# Direct CMake to use icpx rather than the default C++ compiler/linker on Linux +# and icx-cl on Windows +if(UNIX) + set(CMAKE_CXX_COMPILER icpx) +else() # Windows + include (CMakeForceCompiler) + CMAKE_FORCE_CXX_COMPILER (icx-cl IntelDPCPP) + include (Platform/Windows-Clang) +endif() + +cmake_minimum_required (VERSION 3.7.2) + +project(Add_oneAPI CXX) + +set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) +set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) +set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) + +############################################################################### +### Customize these build variables +############################################################################### +set(SOURCE_FILES src/add.cpp) +set(TARGET_NAME add) + +# Use cmake -DFPGA_DEVICE=: to choose a +# different device. Here are a few device examples (this list is not +# exhaustive): +# intel_s10sx_pac:pac_s10 +# intel_s10sx_pac:pac_s10_usm +# intel_a10gx_pac:pac_a10 +# Note that depending on your installation, you may need to specify the full +# path to the board support package (BSP), this usually is in your install +# folder. +# +# You can also specify a device family (E.g. "Arria10" or "Stratix10") or a +# specific part number (E.g. "10AS066N3F40E2SG") to generate a standalone IP. +if(NOT DEFINED FPGA_DEVICE) + set(FPGA_DEVICE "10AS066N3F40E2SG") +endif() + +# Use cmake -DUSER_FPGA_FLAGS= to set extra flags for FPGA backend +# compilation. +set(USER_FPGA_FLAGS ${USER_FPGA_FLAGS}) + +# Use cmake -DUSER_FLAGS= to set extra flags for general compilation. +set(USER_FLAGS ${USER_FLAGS}) + +# Use cmake -DUSER_INCLUDE_PATHS= to set extra paths for general +# compilation. +set(USER_INCLUDE_PATHS ../../../../../include;${USER_INCLUDE_PATHS}) + +############################################################################### +### no changes after here +############################################################################### + +# Print the device being used for the compiles +message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + +# Set the names of the makefile targets to be generated by cmake +set(EMULATOR_TARGET fpga_emu) +set(SIMULATOR_TARGET fpga_sim) +set(REPORT_TARGET report) +set(FPGA_TARGET fpga) +set(IP_EXPORT_TARGET fpga_ip_export) + +# Set the names of the generated files per makefile target +set(EMULATOR_OUTPUT_NAME ${TARGET_NAME}.${EMULATOR_TARGET}) +set(SIMULATOR_OUTPUT_NAME ${TARGET_NAME}.${SIMULATOR_TARGET}) +set(REPORT_OUTPUT_NAME ${TARGET_NAME}.${REPORT_TARGET}) +set(FPGA_OUTPUT_NAME ${TARGET_NAME}.${FPGA_TARGET}) +set(IP_EXPORT_OUTPUT_NAME ${TARGET_NAME}.${IP_EXPORT_TARGET}) + +message(STATUS "Additional USER_FPGA_FLAGS=${USER_FPGA_FLAGS}") +message(STATUS "Additional USER_FLAGS=${USER_FLAGS}") + +include_directories(${USER_INCLUDE_PATHS}) +message(STATUS "Additional USER_INCLUDE_PATHS=${USER_INCLUDE_PATHS}") + +link_directories(${USER_LIB_PATHS}) +message(STATUS "Additional USER_LIB_PATHS=${USER_LIB_PATHS}") + +link_libraries(${USER_LIBS}) +message(STATUS "Additional USER_LIBS=${USER_LIBS}") + +if(WIN32) + # add qactypes for Windows + set(QACTYPES "-Qactypes") + # This is a Windows-specific flag that enables exception handling in host code + set(WIN_FLAG "/EHsc") +else() + # add qactypes for Linux + set(QACTYPES "-qactypes") +endif() + +set(COMMON_COMPILE_FLAGS -fsycl -fintelfpga -Wall ${WIN_FLAG} ${QACTYPES} ${USER_FLAGS}) +set(COMMON_LINK_FLAGS -fsycl -fintelfpga ${QACTYPES} ${USER_FLAGS}) + +# A SYCL ahead-of-time (AoT) compile processes the device code in two stages. +# 1. The "compile" stage compiles the device code to an intermediate +# representation (SPIR-V). +# 2. The "link" stage invokes the compiler's FPGA backend before linking. For +# this reason, FPGA backend flags must be passed as link flags in CMake. +set(EMULATOR_COMPILE_FLAGS -DFPGA_EMULATOR) +set(EMULATOR_LINK_FLAGS ) +set(REPORT_COMPILE_FLAGS -DFPGA_HARDWARE) +set(REPORT_LINK_FLAGS -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_FPGA_FLAGS} -fsycl-link=early) +set(SIMULATOR_COMPILE_FLAGS -Xssimulation -DFPGA_SIMULATOR) +set(SIMULATOR_LINK_FLAGS -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_FPGA_FLAGS} -reuse-exe=${CMAKE_BINARY_DIR}/${SIMULATOR_OUTPUT_NAME}) +set(FPGA_COMPILE_FLAGS -DFPGA_HARDWARE) +set(FPGA_LINK_FLAGS -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_FPGA_FLAGS} -reuse-exe=${CMAKE_BINARY_DIR}/${FPGA_OUTPUT_NAME}) +# get rid of this once host pipes work properly +set(IP_EXPORT_COMPILE_FLAGS -DFPGA_HARDWARE) +set(IP_EXPORT_LINK_FLAGS -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_FPGA_FLAGS} -fsycl-link=early -fsycl-device-code-split=per_kernel) + +############################################################################### +### FPGA Emulator +############################################################################### +add_executable(${EMULATOR_TARGET} ${SOURCE_FILES}) +target_compile_options(${EMULATOR_TARGET} PRIVATE ${COMMON_COMPILE_FLAGS}) +target_compile_options(${EMULATOR_TARGET} PRIVATE ${EMULATOR_COMPILE_FLAGS}) +target_link_libraries(${EMULATOR_TARGET} ${COMMON_LINK_FLAGS}) +target_link_libraries(${EMULATOR_TARGET} ${EMULATOR_LINK_FLAGS}) +set_target_properties(${EMULATOR_TARGET} PROPERTIES OUTPUT_NAME ${EMULATOR_OUTPUT_NAME}) + +############################################################################### +### FPGA Simulator +############################################################################### +add_executable(${SIMULATOR_TARGET} ${SOURCE_FILES}) +target_compile_options(${SIMULATOR_TARGET} PRIVATE ${COMMON_COMPILE_FLAGS}) +target_compile_options(${SIMULATOR_TARGET} PRIVATE ${SIMULATOR_COMPILE_FLAGS}) +target_link_libraries(${SIMULATOR_TARGET} ${COMMON_LINK_FLAGS}) +target_link_libraries(${SIMULATOR_TARGET} ${SIMULATOR_LINK_FLAGS}) +set_target_properties(${SIMULATOR_TARGET} PROPERTIES OUTPUT_NAME ${SIMULATOR_OUTPUT_NAME}) + +############################################################################### +### Generate Report +############################################################################### +add_executable(${REPORT_TARGET} ${SOURCE_FILES}) +target_compile_options(${REPORT_TARGET} PRIVATE ${COMMON_COMPILE_FLAGS}) +target_compile_options(${REPORT_TARGET} PRIVATE ${REPORT_COMPILE_FLAGS}) + +# The report target does not need the QACTYPES flag at link stage +set(MODIFIED_COMMON_LINK_FLAGS_REPORT ${COMMON_LINK_FLAGS}) +list(REMOVE_ITEM MODIFIED_COMMON_LINK_FLAGS_REPORT ${QACTYPES}) + +target_link_libraries(${REPORT_TARGET} ${MODIFIED_COMMON_LINK_FLAGS_REPORT}) +target_link_libraries(${REPORT_TARGET} ${REPORT_LINK_FLAGS}) +set_target_properties(${REPORT_TARGET} PROPERTIES OUTPUT_NAME ${REPORT_OUTPUT_NAME}) + +############################################################################### +### FPGA Hardware +############################################################################### +add_executable(${FPGA_TARGET} EXCLUDE_FROM_ALL ${SOURCE_FILES}) +target_compile_options(${FPGA_TARGET} PRIVATE ${COMMON_COMPILE_FLAGS}) +target_compile_options(${FPGA_TARGET} PRIVATE ${FPGA_COMPILE_FLAGS}) +target_link_libraries(${FPGA_TARGET} ${COMMON_LINK_FLAGS}) +target_link_libraries(${FPGA_TARGET} ${FPGA_LINK_FLAGS}) +set_target_properties(${FPGA_TARGET} PROPERTIES OUTPUT_NAME ${FPGA_OUTPUT_NAME}) + +############################################################################### +### FPGA IP Export (only necessary until native host pipes) +############################################################################### +add_executable(${IP_EXPORT_TARGET} ${SOURCE_FILES}) +target_compile_options(${IP_EXPORT_TARGET} PRIVATE ${COMMON_COMPILE_FLAGS}) +target_compile_options(${IP_EXPORT_TARGET} PRIVATE ${IP_EXPORT_COMPILE_FLAGS}) + +# The ip export target does not need the QACTYPES flag at link stage +set(MODIFIED_COMMON_LINK_FLAGS_EXPORT ${COMMON_LINK_FLAGS}) +list(REMOVE_ITEM MODIFIED_COMMON_LINK_FLAGS_EXPORT ${QACTYPES}) + +target_link_libraries(${IP_EXPORT_TARGET} ${MODIFIED_COMMON_LINK_FLAGS_EXPORT}) +target_link_libraries(${IP_EXPORT_TARGET} ${IP_EXPORT_LINK_FLAGS}) +set_target_properties(${IP_EXPORT_TARGET} PROPERTIES OUTPUT_NAME ${IP_EXPORT_OUTPUT_NAME}) + +############################################################################### +### This part only manipulates cmake variables to print the commands to the user +############################################################################### + +# set the correct object file extension depending on the target platform +if(WIN32) + set(OBJ_EXTENSION "obj") +else() + set(OBJ_EXTENSION "o") +endif() + +# Set the source file names in a string +set(SOURCE_FILE_NAME "${SOURCE_FILES}") + +function(getCompileCommands common_compile_flags special_compile_flags common_link_flags special_link_flags target output_name) + + set(file_names ${SOURCE_FILE_NAME}) + set(COMPILE_COMMAND ) + set(LINK_COMMAND ) + + foreach(source ${file_names}) + # Get the relative path to the source and object files + file(RELATIVE_PATH CURRENT_SOURCE_FILE ${CMAKE_CURRENT_BINARY_DIR} ${CMAKE_CURRENT_LIST_DIR}/${source}) + file(RELATIVE_PATH OBJ_FILE ${CMAKE_CURRENT_BINARY_DIR} ${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/${target}.dir/${source}.${OBJ_EXTENSION}) + + # Creating a string that contains the compile command + # Start by the compiler invocation + set(COMPILE_COMMAND "${COMPILE_COMMAND}${CMAKE_CXX_COMPILER}") + + # Add all the potential includes + foreach(INCLUDE ${USER_INCLUDE_PATHS}) + if(NOT IS_ABSOLUTE ${INCLUDE}) + file(RELATIVE_PATH INCLUDE ${CMAKE_CURRENT_BINARY_DIR} ${CMAKE_CURRENT_LIST_DIR}/${INCLUDE}) + endif() + set(COMPILE_COMMAND "${COMPILE_COMMAND} -I${INCLUDE}") + endforeach() + + # Add all the common compile flags + foreach(FLAG ${common_compile_flags}) + set(COMPILE_COMMAND "${COMPILE_COMMAND} ${FLAG}") + endforeach() + + # Add all the specific compile flags + foreach(FLAG ${special_compile_flags}) + set(COMPILE_COMMAND "${COMPILE_COMMAND} ${FLAG}") + endforeach() + + # Get the location of the object file + file(RELATIVE_PATH OBJ_FILE ${CMAKE_CURRENT_BINARY_DIR} ${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/${target}.dir/${source}.${OBJ_EXTENSION}) + + # Add the source file and the output file + set(COMPILE_COMMAND "${COMPILE_COMMAND} -c ${CURRENT_SOURCE_FILE} -o ${OBJ_FILE}\n") + endforeach() + + set(COMPILE_COMMAND "${COMPILE_COMMAND}" PARENT_SCOPE) + + # Creating a string that contains the link command + # Start by the compiler invocation + set(LINK_COMMAND "${LINK_COMMAND}${CMAKE_CXX_COMPILER}") + + # Add all the common link flags + foreach(FLAG ${common_link_flags}) + set(LINK_COMMAND "${LINK_COMMAND} ${FLAG}") + endforeach() + + # Add all the specific link flags + foreach(FLAG ${special_link_flags}) + set(LINK_COMMAND "${LINK_COMMAND} ${FLAG}") + endforeach() + + # Add the output file + set(LINK_COMMAND "${LINK_COMMAND} -o ${output_name}") + + foreach(source ${file_names}) + # Get the relative path to the source and object files + file(RELATIVE_PATH OBJ_FILE ${CMAKE_CURRENT_BINARY_DIR} ${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/${target}.dir/${source}.${OBJ_EXTENSION}) + + # Add the source file and the output file + set(LINK_COMMAND "${LINK_COMMAND} ${OBJ_FILE}") + endforeach() + + # Add all the potential library paths + foreach(LIB_PATH ${USER_LIB_PATHS}) + if(NOT IS_ABSOLUTE ${LIB_PATH}) + file(RELATIVE_PATH LIB_PATH ${CMAKE_CURRENT_BINARY_DIR} ${CMAKE_CURRENT_LIST_DIR}/${LIB_PATH}) + endif() + if(NOT WIN32) + set(LINK_COMMAND "${LINK_COMMAND} -L${LIB_PATH}") + else() + set(LINK_COMMAND "${LINK_COMMAND} -L${LIB_PATH} -Wl,-rpath,${LIB_PATH}") + endif() + endforeach() + + # Add all the potential includes + foreach(LIB ${USER_LIBS}) + set(LINK_COMMAND "${LINK_COMMAND} -l${LIB}") + endforeach() + + set(LINK_COMMAND "${LINK_COMMAND}" PARENT_SCOPE) + +endfunction() + +# Windows executable is going to have the .exe extension +if(WIN32) + set(EXECUTABLE_EXTENSION ".exe") +endif() + +# Display the compile instructions in the emulation flow +getCompileCommands("${COMMON_COMPILE_FLAGS}" "${EMULATOR_COMPILE_FLAGS}" "${COMMON_LINK_FLAGS}" "${EMULATOR_LINK_FLAGS}" "${EMULATOR_TARGET}" "${EMULATOR_OUTPUT_NAME}${EXECUTABLE_EXTENSION}") + +add_custom_target( displayEmulationCompileCommands ALL + ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" + COMMENT "To compile manually:\n${COMPILE_COMMAND}\nTo link manually:\n${LINK_COMMAND}") +add_dependencies(${EMULATOR_TARGET} displayEmulationCompileCommands) + +# Display the compile instructions in the simulation flow +getCompileCommands("${COMMON_COMPILE_FLAGS}" "${SIMULATOR_COMPILE_FLAGS}" "${COMMON_LINK_FLAGS}" "${SIMULATOR_LINK_FLAGS}" "${SIMULATOR_TARGET}" "${SIMULATOR_OUTPUT_NAME}${EXECUTABLE_EXTENSION}") + +add_custom_target( displaySimulationCompileCommands ALL + ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" + COMMENT "To compile manually:\n${COMPILE_COMMAND}\nTo link manually:\n${LINK_COMMAND}") +add_dependencies(${SIMULATOR_TARGET} displaySimulationCompileCommands) + +# Display the compile instructions in the report flow +getCompileCommands("${COMMON_COMPILE_FLAGS}" "${REPORT_COMPILE_FLAGS}" "${MODIFIED_COMMON_LINK_FLAGS_REPORT}" "${REPORT_LINK_FLAGS}" "${REPORT_TARGET}" "${REPORT_OUTPUT_NAME}${EXECUTABLE_EXTENSION}") + +add_custom_target( displayReportCompileCommands ALL + ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" + COMMENT "To compile manually:\n${COMPILE_COMMAND}\nTo link manually:\n${LINK_COMMAND}") +add_dependencies(${REPORT_TARGET} displayReportCompileCommands) + +# Display the compile instructions in the IP export flow (Remove after native host pipes work properly) +getCompileCommands("${COMMON_COMPILE_FLAGS}" "${IP_EXPORT_COMPILE_FLAGS}" "${MODIFIED_COMMON_LINK_FLAGS_EXPORT}" "${IP_EXPORT_LINK_FLAGS}" "${IP_EXPORT_TARGET}" "${IP_EXPORT_OUTPUT_NAME}${EXECUTABLE_EXTENSION}") + +add_custom_target( displayExportCompileCommands ALL + ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" + COMMENT "To compile manually:\n${COMPILE_COMMAND}\nTo link manually:\n${LINK_COMMAND}") +add_dependencies(${IP_EXPORT_TARGET} displayExportCompileCommands) + +# Display the compile instructions in the fpga flow +getCompileCommands("${COMMON_COMPILE_FLAGS}" "${FPGA_COMPILE_FLAGS}" "${COMMON_LINK_FLAGS}" "${FPGA_LINK_FLAGS}" "${FPGA_TARGET}" "${FPGA_OUTPUT_NAME}${EXECUTABLE_EXTENSION}") + +add_custom_target( displayFPGACompileCommands ALL + ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" + COMMENT "To compile manually:\n${COMPILE_COMMAND}\nTo link manually:\n${LINK_COMMAND}") +add_dependencies(${FPGA_TARGET} displayFPGACompileCommands) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-oneapi/src/add.cpp b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-oneapi/src/add.cpp new file mode 100644 index 0000000000..bed2279b41 --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-oneapi/src/add.cpp @@ -0,0 +1,115 @@ +// Copyright (c) 2023 Intel Corporation +// SPDX-License-Identifier: MIT + +#include + +#include + +// oneAPI headers +#include +#include +#include + +#include "exception_handler.hpp" + +// use host pipes to write into addresses in the CSR +class OutputPipeID; +using OutputPipe = sycl::ext::intel::prototype::pipe< + OutputPipeID, int, 1, + // choose defaults for these 4: + 0, 1, true, false, + // store the most recently processed index to the CSR + sycl::ext::intel::prototype::internal::protocol_name::AVALON_MM>; + +// Forward declare the kernel name in the global scope. This is an FPGA best +// practice that reduces name mangling in the optimization reports. +class AdderID; + +struct Adder { + int a; + int b; + + void operator()() const { + int sum = a + b; + + OutputPipe::write(sum); + } +}; + +int main() { + bool passed = false; + + try { +// This design is tested with 2023.0, but also accounts for a syntax change in +// 2023.1 +#if __INTEL_CLANG_COMPILER >= 20230100 +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; +#endif +#elif __INTEL_CLANG_COMPILER >= 20230000 +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector{}; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector{}; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector{}; +#endif +#else + assert(false) && "this design requires oneAPI 2023.0 or 2023.1!" +#endif + + sycl::queue q(selector, fpga_tools::exception_handler, + sycl::property::queue::enable_profiling{}); + + auto device = q.get_device(); + std::cout << "Running on device: " + << device.get_info().c_str() + << std::endl; + + int a = 3; + int b = 76; + + int expected_sum = a + b; + + std::cout << "add two integers using CSR for input." << std::endl; + + // no need to wait() since the pipe read will block until `Adder` has some + // output. + q.single_task(Adder{a, b}); + + // verify that outputs are correct + passed = true; + + std::cout << "collect results." << std::endl; + int calc_add = OutputPipe::read(q); + + std::cout << a << " + " << b << " = " << calc_add << ", expected " + << expected_sum << ". " << std::endl; + + if (calc_add != expected_sum) { + passed = false; + } + + } catch (sycl::exception const &e) { + // Catches exceptions in the host code. + std::cerr << "Caught a SYCL host exception:\n" << e.what() << "\n"; + + // Most likely the runtime couldn't find FPGA hardware! + if (e.code().value() == CL_DEVICE_NOT_FOUND) { + std::cerr << "If you are targeting an FPGA, please ensure that your " + "system has a correctly configured FPGA board.\n"; + std::cerr << "Run sys_check in the oneAPI root directory to verify.\n"; + std::cerr << "If you are targeting the FPGA emulator, compile with " + "-DFPGA_EMULATOR.\n"; + } + std::terminate(); + } + + std::cout << (passed ? "PASSED" : "FAILED") << std::endl; + + return passed ? EXIT_SUCCESS : EXIT_FAILURE; +} diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/.gitignore b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/.gitignore new file mode 100644 index 0000000000..1d89b3d608 --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/.gitignore @@ -0,0 +1,18 @@ +# ignore temp files and caches created by quartus +DNI +output_files +qdb +tmp-clearbox +add.qws + +# ignore files generated by platform designer +.qsys_edit/ +add_kernel_wrapper + +# ignore oneAPI generated IP +add.fpga_ip_export.prj_1 + +# save .ip files, but not generated RTL +ip/**/* +!ip/**/ +!ip/**/*.ip \ No newline at end of file diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/add.qpf b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/add.qpf new file mode 100644 index 0000000000..65eb611e9a --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/add.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2022 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 22.3.0 Build 104 09/14/2022 SC Pro Edition +# Date created = 08:31:30 February 03, 2023 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "22.3" +DATE = "08:31:30 February 03, 2023" + +# Revisions + +PROJECT_REVISION = "add" diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/add.qsf b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/add.qsf new file mode 100644 index 0000000000..5b4125c620 --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/add.qsf @@ -0,0 +1,28 @@ +set_global_assignment -name TOP_LEVEL_ENTITY add +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 22.3.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:31:30 FEBRUARY 03, 2023" +set_global_assignment -name LAST_QUARTUS_VERSION "22.3.0 Pro Edition" +set_global_assignment -name SDC_FILE jtag.sdc +set_global_assignment -name SYSTEMVERILOG_FILE add.sv +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name DEVICE 10AS066N3F40E2SG +set_global_assignment -name FAMILY "Arria 10" +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2 +set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name IP_FILE ip/add_kernel_wrapper/add_kernel_wrapper_clock_in.ip +set_global_assignment -name IP_FILE ip/add_kernel_wrapper/add_kernel_wrapper_reset_in.ip +set_global_assignment -name QSYS_FILE add_kernel_wrapper.qsys +set_global_assignment -name IP_FILE ip/add_kernel_wrapper/add_kernel_wrapper_master_0.ip +set_location_assignment PIN_AM10 -to i_clk +set_location_assignment PIN_AR23 -to fpga_led +set_location_assignment PIN_AV21 -to reset_button_n +set_global_assignment -name SDC_FILE add.sdc +set_global_assignment -name IP_FILE ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0.ip +set_instance_assignment -name IO_STANDARD LVDS -to i_clk -entity add +set_instance_assignment -name IO_STANDARD "1.8 V" -to fpga_led -entity add +set_instance_assignment -name IO_STANDARD "1.8 V" -to reset_button_n -entity add +set_location_assignment PIN_AL10 -to "i_clk(n)" diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/add.sdc b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/add.sdc new file mode 100644 index 0000000000..f5989dbcf9 --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/add.sdc @@ -0,0 +1,6 @@ +set_time_format -unit ns -decimal_places 3 +create_clock -name i_clk -period 10 [get_ports {i_clk}] + +set_false_path -from [get_ports {reset_button_n}] -to * +set_false_path -from [get_ports {fpga_led}] -to * +set_false_path -from * -to [get_ports {fpga_led}] \ No newline at end of file diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/add.sv b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/add.sv new file mode 100644 index 0000000000..1ba745435d --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/add.sv @@ -0,0 +1,38 @@ +// Copyright (c) 2023 Intel Corporation +// SPDX-License-Identifier: MIT + +module add ( + input wire i_clk, + input wire reset_button_n, + output logic fpga_led + ); + + // invert reset_button_n and pipeline it a bit + logic reset_button_d1; + logic reset_button_d2; + logic reset_button_d3; + + always @ (posedge i_clk) + begin + reset_button_d1 <= ~reset_button_n; + reset_button_d2 <= reset_button_d1; + reset_button_d3 <= reset_button_d2; + end + + + // register the signal used by the LED + wire sort_done; + always @(posedge i_clk) + begin + // led is inverted + fpga_led <= ~sort_done; + end + + add_kernel_wrapper u0 ( + .exception_add_data (), // output, width = 64, exception_add_1.data + .irq_add_irq (sort_done), // output, width = 1, irq_add_1.irq + .clk_clk (i_clk), // input, width = 1, clk.clk + .reset_reset (reset_button_d3) // input, width = 1, reset.reset + ); + +endmodule diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/add_kernel_wrapper.qsys b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/add_kernel_wrapper.qsys new file mode 100644 index 0000000000..8cad3ddf75 --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/add_kernel_wrapper.qsys @@ -0,0 +1,2594 @@ + + + + Altera Corporation + add_kernel_wrapper + add_kernel_wrapper + 1.0 + + + + $${FILENAME} + $${FILENAME} + 1.0 + + + System + QsysPro + + + + + board + Board + default + + + bonusData + bonusData + bonusData +{ + element add_fpga_ip_export_1_di_0 + { + datum _sortIndex + { + value = "3"; + type = "int"; + } + } + element clock_in + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } + element master_0 + { + datum _sortIndex + { + value = "2"; + type = "int"; + } + } + element reset_in + { + datum _sortIndex + { + value = "1"; + type = "int"; + } + } +} + + + + designId + designId + + + + device + Device + 10AS066N3F40E2SG + + + deviceFamily + Device family + Arria 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + fabricMode + fabricMode + QSYS + + + generateLegacySim + generateLegacySim + false + + + generationId + Generation Id + 0 + + + globalResetBus + Global reset + false + + + hdlLanguage + hdlLanguage + VERILOG + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + + + + pinAssignmentListDefinition + pinAssignmentListDefinition + + + + sopcBorderPoints + Use SOPC Builder port naming + false + + + systemHash + systemHash + 0 + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + systemScripts + systemScripts + + + + testBenchDutName + Use Test Bench Naming Pattern + + + + timeStamp + timeStamp + 0 + + + useTestBenchNamingPattern + Use Test Bench Naming Pattern + false + + + + + + + + + Altera Corporation + add_fpga_ip_export_1_di_0 + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clock</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>resetn</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>resetn</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>BOTH</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>device_exception_bus</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>device_exception_bus</name> + <role>data</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>resetn</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>kernel_irqs</name> + <type>interrupt</type> + <isStart>false</isStart> + <ports> + <port> + <name>kernel_irqs</name> + <role>irq</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedAddressablePoint</key> + </entry> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>resetn</value> + </entry> + <entry> + <key>bridgedReceiverOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToReceiver</key> + </entry> + <entry> + <key>irqScheme</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>csr_ring_root_avs</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>csr_ring_root_avs_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>csr_ring_root_avs_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>csr_ring_root_avs_readdatavalid</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>csr_ring_root_avs_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>csr_ring_root_avs_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>csr_ring_root_avs_address</name> + <role>address</role> + <direction>Input</direction> + <width>5</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>csr_ring_root_avs_byteenable</name> + <role>byteenable</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>csr_ring_root_avs_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + <entry> + <key>hls.cosim.name</key> + <value></value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>256</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>resetn</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>1</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>add_fpga_ip_export_1_di</className> + <version>1.0</version> + <displayName>add_fpga_ip_export_1_di</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>csr_ring_root_avs</key> + <value> + <connectionPointName>csr_ring_root_avs</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='csr_ring_root_avs' start='0x0' end='0x100' datawidth='64' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>8</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>64</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clock</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>resetn</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>resetn</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>BOTH</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>device_exception_bus</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>device_exception_bus</name> + <role>data</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>resetn</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>kernel_irqs</name> + <type>interrupt</type> + <isStart>false</isStart> + <ports> + <port> + <name>kernel_irqs</name> + <role>irq</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedAddressablePoint</key> + </entry> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>resetn</value> + </entry> + <entry> + <key>bridgedReceiverOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToReceiver</key> + </entry> + <entry> + <key>irqScheme</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>csr_ring_root_avs</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>csr_ring_root_avs_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>csr_ring_root_avs_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>csr_ring_root_avs_readdatavalid</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>csr_ring_root_avs_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>csr_ring_root_avs_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>csr_ring_root_avs_address</name> + <role>address</role> + <direction>Input</direction> + <width>5</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>csr_ring_root_avs_byteenable</name> + <role>byteenable</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>csr_ring_root_avs_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + <entry> + <key>hls.cosim.name</key> + <value></value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>256</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>resetn</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>1</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>add_kernel_wrapper_add_fpga_ip_export_1_di_0</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>add_kernel_wrapper_add_fpga_ip_export_1_di_0</fileSetName> + <fileSetFixedName>add_kernel_wrapper_add_fpga_ip_export_1_di_0</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>add_kernel_wrapper_add_fpga_ip_export_1_di_0</fileSetName> + <fileSetFixedName>add_kernel_wrapper_add_fpga_ip_export_1_di_0</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>add_kernel_wrapper_add_fpga_ip_export_1_di_0</fileSetName> + <fileSetFixedName>add_kernel_wrapper_add_fpga_ip_export_1_di_0</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>add_kernel_wrapper_add_fpga_ip_export_1_di_0</fileSetName> + <fileSetFixedName>add_kernel_wrapper_add_fpga_ip_export_1_di_0</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>add_kernel_wrapper_add_fpga_ip_export_1_di_0</fileSetName> + <fileSetFixedName>add_kernel_wrapper_add_fpga_ip_export_1_di_0</fileSetFixedName> + <fileSetKind>CDC_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> + <pinAssignments/> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + clock_in + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>in_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>in_clk</value> + </entry> + <entry> + <key>clockRate</key> + <value>50000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_clock_bridge</className> + <version>19.2.0</version> + <displayName>Clock Bridge Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>DERIVED_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>in_clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>in_clk</key> + <value> + <connectionPointName>in_clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>out_clk</key> + <value> + <connectionPointName>out_clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>50000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>in_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>in_clk</value> + </entry> + <entry> + <key>clockRate</key> + <value>50000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>add_kernel_wrapper_clock_in</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>add_kernel_wrapper_clock_in</fileSetName> + <fileSetFixedName>add_kernel_wrapper_clock_in</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>add_kernel_wrapper_clock_in</fileSetName> + <fileSetFixedName>add_kernel_wrapper_clock_in</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>add_kernel_wrapper_clock_in</fileSetName> + <fileSetFixedName>add_kernel_wrapper_clock_in</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>add_kernel_wrapper_clock_in</fileSetName> + <fileSetFixedName>add_kernel_wrapper_clock_in</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>add_kernel_wrapper_clock_in</fileSetName> + <fileSetFixedName>add_kernel_wrapper_clock_in</fileSetFixedName> + <fileSetKind>CDC_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> + <pinAssignments/> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/add_kernel_wrapper/add_kernel_wrapper_clock_in.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + master_0 + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk_reset_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>master_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>master_reset_reset</name> + <role>reset</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>none</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>master</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>master_address</name> + <role>address</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_readdatavalid</name> + <role>readdatavalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_byteenable</name> + <role>byteenable</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>debug.controlledBy</key> + <value>in_stream</value> + </entry> + <entry> + <key>debug.providesServices</key> + <value>master</value> + </entry> + <entry> + <key>debug.typeName</key> + <value>altera_jtag_avalon_master.master</value> + </entry> + <entry> + <key>debug.visible</key> + <value>true</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>clk_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_jtag_avalon_master</className> + <version>19.1</version> + <displayName>JTAG to Avalon Master Bridge Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>AUTO_DEVICE</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>DEVICE</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>AUTO_DEVICE_FAMILY</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>DEVICE_FAMILY</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>AUTO_DEVICE_SPEEDGRADE</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>DEVICE_SPEEDGRADE</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>COMPONENT_CLOCK</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>clock</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk_reset_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>master_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>master_reset_reset</name> + <role>reset</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>none</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>master</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>master_address</name> + <role>address</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_readdatavalid</name> + <role>readdatavalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_byteenable</name> + <role>byteenable</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>debug.controlledBy</key> + <value>in_stream</value> + </entry> + <entry> + <key>debug.providesServices</key> + <value>master</value> + </entry> + <entry> + <key>debug.typeName</key> + <value>altera_jtag_avalon_master.master</value> + </entry> + <entry> + <key>debug.visible</key> + <value>true</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>clk_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>add_kernel_wrapper_master_0</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>add_kernel_wrapper_master_0</fileSetName> + <fileSetFixedName>add_kernel_wrapper_master_0</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>add_kernel_wrapper_master_0</fileSetName> + <fileSetFixedName>add_kernel_wrapper_master_0</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>add_kernel_wrapper_master_0</fileSetName> + <fileSetFixedName>add_kernel_wrapper_master_0</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>add_kernel_wrapper_master_0</fileSetName> + <fileSetFixedName>add_kernel_wrapper_master_0</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>add_kernel_wrapper_master_0</fileSetName> + <fileSetFixedName>add_kernel_wrapper_master_0</fileSetFixedName> + <fileSetKind>CDC_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> + <pinAssignments/> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/add_kernel_wrapper/add_kernel_wrapper_master_0.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap> + <entry> + <key>debug.hostConnection</key> + <value>type jtag id 110:132</value> + </entry> + </assignmentValueMap> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + reset_in + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_reset</name> + <role>reset</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_reset_bridge</className> + <version>19.2.0</version> + <displayName>Reset Bridge Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_CLK_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_reset</name> + <role>reset</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>add_kernel_wrapper_reset_in</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>add_kernel_wrapper_reset_in</fileSetName> + <fileSetFixedName>add_kernel_wrapper_reset_in</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>add_kernel_wrapper_reset_in</fileSetName> + <fileSetFixedName>add_kernel_wrapper_reset_in</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>add_kernel_wrapper_reset_in</fileSetName> + <fileSetFixedName>add_kernel_wrapper_reset_in</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>add_kernel_wrapper_reset_in</fileSetName> + <fileSetFixedName>add_kernel_wrapper_reset_in</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>add_kernel_wrapper_reset_in</fileSetName> + <fileSetFixedName>add_kernel_wrapper_reset_in</fileSetFixedName> + <fileSetKind>CDC_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> + <pinAssignments/> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/add_kernel_wrapper/add_kernel_wrapper_reset_in.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Intel Corporation + addressMap + addressMap + 1.0 + + + add_fpga_ip_export_1_di_0.csr_ring_root_avs + + + + master_0.master + + + + 0x0000_0000 + + + + + + + master_0.master + + + add_fpga_ip_export_1_di_0.csr_ring_root_avs + 0x0000_0000 + 0x0000_0100 + + + + + + + + false + false + + \ No newline at end of file diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/add_kernel_wrapper.qsys.legacy b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/add_kernel_wrapper.qsys.legacy new file mode 100644 index 0000000000..c40d0bc8fe --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/add_kernel_wrapper.qsys.legacy @@ -0,0 +1,2324 @@ + + + + + + + + + + + + + + + + + + + + + + + + clk + + clk + + + CLOCK_RATE + + + + + + +]]> + + + + + + + + + + + + + + + clock + clock + false + + + clock + clk + Input + 1 + 0 + STD_LOGIC + 0 + + + + + + + + + clockRate + 0 + + + externallyDriven + false + + + ptfSchematicName + + + + + + resetn + reset + false + + + resetn + reset_n + Input + 1 + 0 + STD_LOGIC + 0 + + + + + + + + + associatedClock + clock + + + synchronousEdges + BOTH + + + + + + device_exception_bus + conduit + false + + + device_exception_bus + data + Output + 64 + 0 + STD_LOGIC_VECTOR + 0 + + + + + + + + + associatedClock + clock + + + associatedReset + resetn + + + prSafe + false + + + + + + kernel_irqs + interrupt + false + + + kernel_irqs + irq + Output + 1 + 0 + STD_LOGIC + 0 + + + + + + + + + associatedAddressablePoint + + + associatedClock + clock + + + associatedReset + resetn + + + bridgedReceiverOffset + 0 + + + bridgesToReceiver + + + irqScheme + NONE + + + + + + csr_ring_root_avs + avalon + false + + + csr_ring_root_avs_read + read + Input + 1 + 0 + STD_LOGIC + 0 + + + csr_ring_root_avs_readdata + readdata + Output + 64 + 0 + STD_LOGIC_VECTOR + 0 + + + csr_ring_root_avs_readdatavalid + readdatavalid + Output + 1 + 0 + STD_LOGIC + 0 + + + csr_ring_root_avs_write + write + Input + 1 + 0 + STD_LOGIC + 0 + + + csr_ring_root_avs_writedata + writedata + Input + 64 + 0 + STD_LOGIC_VECTOR + 0 + + + csr_ring_root_avs_address + address + Input + 5 + 0 + STD_LOGIC_VECTOR + 0 + + + csr_ring_root_avs_byteenable + byteenable + Input + 8 + 0 + STD_LOGIC_VECTOR + 0 + + + csr_ring_root_avs_waitrequest + waitrequest + Output + 1 + 0 + STD_LOGIC + 0 + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + hls.cosim.name + + + + + + + + addressAlignment + DYNAMIC + + + addressGroup + 0 + + + addressSpan + 256 + + + addressUnits + WORDS + + + alwaysBurstMaxBurst + false + + + associatedClock + clock + + + associatedReset + resetn + + + bitsPerSymbol + 8 + + + bridgedAddressOffset + 0 + + + bridgesToMaster + + + burstOnBurstBoundariesOnly + false + + + burstcountUnits + WORDS + + + constantBurstBehavior + false + + + explicitAddressSpan + 0 + + + holdTime + 0 + + + interleaveBursts + false + + + isBigEndian + false + + + isFlash + false + + + isMemoryDevice + false + + + isNonVolatileStorage + false + + + linewrapBursts + false + + + maximumPendingReadTransactions + 1 + + + maximumPendingWriteTransactions + 0 + + + minimumReadLatency + 1 + + + minimumResponseLatency + 1 + + + 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add_kernel_wrapper_add_fpga_ip_export_1_di_0 + SIM_VERILOG + + + + add_kernel_wrapper_add_fpga_ip_export_1_di_0 + add_kernel_wrapper_add_fpga_ip_export_1_di_0 + SIM_VHDL + + + + add_kernel_wrapper_add_fpga_ip_export_1_di_0 + add_kernel_wrapper_add_fpga_ip_export_1_di_0 + CDC + + + + add_kernel_wrapper_add_fpga_ip_export_1_di_0 + add_kernel_wrapper_add_fpga_ip_export_1_di_0 + CDC_VHDL + + + + +]]> + ]]> + + ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0.ip + + +]]> + + + + + + + + in_clk + clock + false + + + in_clk + clk + Input + 1 + 0 + STD_LOGIC + 0 + + + + + + + + + clockRate + 0 + + + externallyDriven + false + + + ptfSchematicName + + + + + + out_clk + clock + true + + + out_clk + clk + Output + 1 + 0 + STD_LOGIC + 0 + + + + + + + + + associatedDirectClock + in_clk + + + clockRate + 50000000 + + + clockRateKnown + true + + + externallyDriven + false + + + ptfSchematicName + + + + + + + + altera_clock_bridge + 19.2.0 + Clock Bridge Intel FPGA IP + + + + + 0 + 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add_kernel_wrapper_clock_in + CDC_VHDL + + + + +]]> + ]]> + + ip/add_kernel_wrapper/add_kernel_wrapper_clock_in.ip + + +]]> + + + + + + + + clk + clock + false + + + clk_clk + clk + Input + 1 + 0 + STD_LOGIC + 0 + + + + + + + + + clockRate + 0 + + + externallyDriven + false + + + ptfSchematicName + + + + + + clk_reset + reset + false + + + clk_reset_reset + reset + Input + 1 + 0 + STD_LOGIC + 0 + + + + + + + + + associatedClock + + + synchronousEdges + NONE + + + + + + master_reset + reset + true + + + master_reset_reset + reset + Output + 1 + 0 + STD_LOGIC + 0 + + + + + + + + + associatedClock + + + associatedDirectReset + + + associatedResetSinks + none + + + synchronousEdges + NONE + + + + + + master + avalon + true + + + master_address + address + Output + 32 + 0 + STD_LOGIC_VECTOR + 0 + + + master_readdata + readdata + Input + 32 + 0 + STD_LOGIC_VECTOR + 0 + + + master_read + read + Output + 1 + 0 + STD_LOGIC + 0 + + + master_write + write + Output + 1 + 0 + STD_LOGIC + 0 + + + master_writedata + writedata + Output + 32 + 0 + STD_LOGIC_VECTOR + 0 + + + master_waitrequest + waitrequest + Input + 1 + 0 + STD_LOGIC + 0 + + + master_readdatavalid + readdatavalid + Input + 1 + 0 + STD_LOGIC + 0 + + + master_byteenable + byteenable + Output + 4 + 0 + STD_LOGIC_VECTOR + 0 + + + + + + debug.controlledBy + in_stream + + + debug.providesServices + master + + + debug.typeName + altera_jtag_avalon_master.master + + + debug.visible + true + + + + + + + adaptsTo + + + addressGroup + 0 + + + addressUnits + SYMBOLS + + + alwaysBurstMaxBurst + false + + + associatedClock + clk + + + associatedReset + clk_reset + + + bitsPerSymbol + 8 + + + burstOnBurstBoundariesOnly + false + + + burstcountUnits + WORDS + + + constantBurstBehavior + false + + + dBSBigEndian + false + + + doStreamReads + false + + + doStreamWrites + false + + + holdTime + 0 + + + interleaveBursts + false + + + isAsynchronous + false + + + isBigEndian + false + + + isReadable + false + + + isWriteable + false + + + linewrapBursts + false + + + maxAddressWidth + 32 + + + maximumPendingReadTransactions + 0 + + + maximumPendingWriteTransactions + 0 + + + minimumReadLatency + 1 + + + minimumResponseLatency + 1 + + + prSafe + false + + + readLatency + 0 + + + readWaitTime + 1 + + + registerIncomingSignals + false + + + registerOutgoingSignals + false + + + setupTime + 0 + + + timingUnits + Cycles + + + waitrequestAllowance + 0 + + + writeWaitTime + 0 + + + + + + + + altera_jtag_avalon_master + 19.1 + JTAG to Avalon Master Bridge Intel FPGA IP + + + + + + AUTO_DEVICE + java.lang.String + DEVICE + + + + AUTO_DEVICE_FAMILY + java.lang.String + DEVICE_FAMILY + + + + AUTO_DEVICE_SPEEDGRADE + java.lang.String + DEVICE_SPEEDGRADE + + + 0 + COMPONENT_CLOCK + java.lang.Integer + clock + CLOCK_RATE + + + + + + +]]> + + + + clk + clock + false + + + clk_clk + clk + Input + 1 + 0 + STD_LOGIC + 0 + + + + + + + + + clockRate + 0 + + + externallyDriven + false + + + ptfSchematicName + + + + + + clk_reset + reset + false + + + clk_reset_reset + reset + Input + 1 + 0 + STD_LOGIC + 0 + + + + + + + + + associatedClock + + + synchronousEdges + NONE + + + + + + master_reset + reset + true + + + master_reset_reset + reset + Output + 1 + 0 + STD_LOGIC + 0 + + + + + + + + + associatedClock + + + associatedDirectReset + + + associatedResetSinks + none + + + synchronousEdges + NONE + + + + + + master + avalon + true + + + master_address + address + Output + 32 + 0 + STD_LOGIC_VECTOR + 0 + + + master_readdata + readdata + Input + 32 + 0 + STD_LOGIC_VECTOR + 0 + + + master_read + read + Output + 1 + 0 + STD_LOGIC + 0 + + + master_write + write + Output + 1 + 0 + STD_LOGIC + 0 + + + master_writedata + writedata + Output + 32 + 0 + STD_LOGIC_VECTOR + 0 + + + master_waitrequest + waitrequest + Input + 1 + 0 + STD_LOGIC + 0 + + + master_readdatavalid + readdatavalid + Input + 1 + 0 + STD_LOGIC + 0 + + + master_byteenable + byteenable + Output + 4 + 0 + STD_LOGIC_VECTOR + 0 + + + + + + debug.controlledBy + in_stream + + + debug.providesServices + master + + + debug.typeName + altera_jtag_avalon_master.master + + + debug.visible + true + + + + + + + adaptsTo + + + addressGroup + 0 + + + addressUnits + SYMBOLS + + + alwaysBurstMaxBurst + false + + + associatedClock + clk + + + associatedReset + clk_reset + + + bitsPerSymbol + 8 + + + burstOnBurstBoundariesOnly + false + + + burstcountUnits + WORDS + + + constantBurstBehavior + false + + + dBSBigEndian + false + + + doStreamReads + false + + + doStreamWrites + false + + + holdTime + 0 + + + interleaveBursts + false + + + isAsynchronous + false + + + isBigEndian + false + + + isReadable + false + + + isWriteable + false + + + linewrapBursts + false + + + maxAddressWidth + 32 + + + maximumPendingReadTransactions + 0 + + + maximumPendingWriteTransactions + 0 + + + minimumReadLatency + 1 + + + minimumResponseLatency + 1 + + + prSafe + false + + + readLatency + 0 + + + readWaitTime + 1 + + + registerIncomingSignals + false + + + registerOutgoingSignals + false + + + setupTime + 0 + + + timingUnits + Cycles + + + waitrequestAllowance + 0 + + + writeWaitTime + 0 + + + + + +]]> + + add_kernel_wrapper_master_0 + + + add_kernel_wrapper_master_0 + add_kernel_wrapper_master_0 + QUARTUS_SYNTH + + + + add_kernel_wrapper_master_0 + add_kernel_wrapper_master_0 + SIM_VERILOG + + + + add_kernel_wrapper_master_0 + add_kernel_wrapper_master_0 + SIM_VHDL + + + + add_kernel_wrapper_master_0 + add_kernel_wrapper_master_0 + CDC + + + + add_kernel_wrapper_master_0 + add_kernel_wrapper_master_0 + CDC_VHDL + + + + +]]> + ]]> + + ip/add_kernel_wrapper/add_kernel_wrapper_master_0.ip + + + + debug.hostConnection + type jtag id 110:132 + + +]]> + + + + + + + + in_reset + reset + false + + + in_reset + reset + Input + 1 + 0 + STD_LOGIC + 0 + + + + + + + + + associatedClock + + + synchronousEdges + NONE + + + + + + out_reset + reset + true + + + out_reset + reset + Output + 1 + 0 + STD_LOGIC + 0 + + + + + + + + + associatedClock + + + associatedDirectReset + in_reset + + + associatedResetSinks + in_reset + + + synchronousEdges + NONE + + + + + + + + altera_reset_bridge + 19.2.0 + Reset Bridge Intel FPGA IP + + + + + -1 + AUTO_CLK_CLOCK_RATE + java.lang.Long + clk + CLOCK_RATE + + + + + + +]]> + + + + in_reset + reset + false + + + in_reset + reset + Input + 1 + 0 + STD_LOGIC + 0 + + + + + + + + + associatedClock + + + synchronousEdges + NONE + + + + + + out_reset + reset + true + + + out_reset + reset + Output + 1 + 0 + STD_LOGIC + 0 + + + + + + + + + associatedClock + + + associatedDirectReset + in_reset + + + associatedResetSinks + in_reset + + + synchronousEdges + NONE + + + + + +]]> + + add_kernel_wrapper_reset_in + + + add_kernel_wrapper_reset_in + add_kernel_wrapper_reset_in + QUARTUS_SYNTH + + + + add_kernel_wrapper_reset_in + add_kernel_wrapper_reset_in + SIM_VERILOG + + + + add_kernel_wrapper_reset_in + add_kernel_wrapper_reset_in + SIM_VHDL + + + + add_kernel_wrapper_reset_in + add_kernel_wrapper_reset_in + CDC + + + + add_kernel_wrapper_reset_in + add_kernel_wrapper_reset_in + CDC_VHDL + + + + +]]> + ]]> + + ip/add_kernel_wrapper/add_kernel_wrapper_reset_in.ip + + +]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0.ip b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0.ip new file mode 100644 index 0000000000..06a9f51d18 --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0.ip @@ -0,0 +1,1238 @@ + + + + Altera Corporation + add_kernel_wrapper_add_fpga_ip_export_1_di_0 + add_fpga_ip_export_1_di_0 + 1.0 + + + clock + + + + + + + + clk + + + clock + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + resetn + + + + + + + + reset + + + resetn + + + + + + + + + associatedClock + Associated clock + clock + + + synchronousEdges + Synchronous edges + BOTH + + + + + device_exception_bus + + + + + + + + data + + + device_exception_bus + + + + + + + + + associatedClock + associatedClock + clock + + + associatedReset + associatedReset + resetn + + + prSafe + Partial Reconfiguration Safe + false + + + + + kernel_irqs + + + + + + + + irq + + + kernel_irqs + + + + + + + + + associatedAddressablePoint + Associated addressable interface + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + resetn + + + bridgedReceiverOffset + Bridged receiver offset + 0 + + + bridgesToReceiver + Bridges to receiver + + + + irqScheme + Interrupt scheme + NONE + + + + + csr_ring_root_avs + + + + + + + + read + + + csr_ring_root_avs_read + + + + + readdata + + + csr_ring_root_avs_readdata + + + + + readdatavalid + + + csr_ring_root_avs_readdatavalid + + + + + write + + + csr_ring_root_avs_write + + + + + writedata + + + csr_ring_root_avs_writedata + + + + + address + + + csr_ring_root_avs_address + + + + + byteenable + + + csr_ring_root_avs_byteenable + + + + + waitrequest + + + csr_ring_root_avs_waitrequest + + + + + + + + + addressAlignment + Agent addressing + DYNAMIC + + + addressGroup + Address group + 0 + + + addressSpan + Address span + 256 + + + addressUnits + Address units + WORDS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + resetn + + + bitsPerSymbol + Bits per symbol + 8 + + + bridgedAddressOffset + Bridged Address Offset + 0 + + + bridgesToMaster + Bridges to host + + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + explicitAddressSpan + Explicit address span + 0 + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isBigEndian + Big endian + false + + + isFlash + Flash memory + false + + + isMemoryDevice + Memory device + false + + + isNonVolatileStorage + Non-volatile storage + false + + + linewrapBursts + Linewrap bursts + false + + + maximumPendingReadTransactions + Maximum pending read transactions + 1 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + minimumUninterruptedRunLength + Minimum uninterrupted run length + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + printableDevice + Can receive stdout/stderr + false + + + readLatency + Read latency + 0 + + + readWaitStates + Read wait states + 0 + + + readWaitTime + Read wait + 0 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + transparentBridge + Transparent bridge + false + + + waitrequestAllowance + Waitrequest allowance + 0 + + + wellBehavedWaitrequest + Well-behaved waitrequest + false + + + writeLatency + Write latency + 0 + + + writeWaitStates + Write wait states + 0 + + + writeWaitTime + Write wait + 0 + + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + hls.cosim.name + + + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + add_fpga_ip_export_1_di + + QUARTUS_SYNTH + + + + + + + clock + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + resetn + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + device_exception_bus + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + kernel_irqs + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + csr_ring_root_avs_read + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + csr_ring_root_avs_readdata + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + csr_ring_root_avs_readdatavalid + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + csr_ring_root_avs_write + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + csr_ring_root_avs_writedata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + csr_ring_root_avs_address + + in + + + 0 + 4 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + csr_ring_root_avs_byteenable + + in + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + csr_ring_root_avs_waitrequest + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Altera Corporation + add_kernel_wrapper_add_fpga_ip_export_1_di_0 + add_fpga_ip_export_1_di + 1.0 + + + + + + + + board + Board + default + + + device + Device + 10AS066N3F40E2SG + + + deviceFamily + Device family + Arria 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element $system + { + datum _originalDeviceFamily + { + value = "Arria 10"; + type = "String"; + } + } + element add_fpga_ip_export_1_di_0 + { + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clock</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>resetn</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>resetn</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>BOTH</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>device_exception_bus</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>device_exception_bus</name> + <role>data</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>resetn</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>kernel_irqs</name> + <type>interrupt</type> + <isStart>false</isStart> + <ports> + <port> + <name>kernel_irqs</name> + <role>irq</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedAddressablePoint</key> + </entry> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>resetn</value> + </entry> + <entry> + <key>bridgedReceiverOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToReceiver</key> + </entry> + <entry> + <key>irqScheme</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>csr_ring_root_avs</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>csr_ring_root_avs_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>csr_ring_root_avs_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>csr_ring_root_avs_readdatavalid</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>csr_ring_root_avs_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>csr_ring_root_avs_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>csr_ring_root_avs_address</name> + <role>address</role> + <direction>Input</direction> + <width>5</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>csr_ring_root_avs_byteenable</name> + <role>byteenable</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>csr_ring_root_avs_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + <entry> + <key>hls.cosim.name</key> + <value></value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>256</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>resetn</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>1</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>csr_ring_root_avs</key> + <value> + <connectionPointName>csr_ring_root_avs</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='csr_ring_root_avs' start='0x0' end='0x100' datawidth='64' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>8</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>64</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + pinAssignmentListDefinition + pinAssignmentListDefinition + <pinAssignmentListDefinition/> + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/ip/add_kernel_wrapper/add_kernel_wrapper_clock_in.ip b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/ip/add_kernel_wrapper/add_kernel_wrapper_clock_in.ip new file mode 100644 index 0000000000..65a1c0ecc3 --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/ip/add_kernel_wrapper/add_kernel_wrapper_clock_in.ip @@ -0,0 +1,371 @@ + + + + Intel Corporation + add_kernel_wrapper_clock_in + clock_in + 19.2.0 + + + in_clk + + + + + + + + clk + + + in_clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + out_clk + + + + + + + + clk + + + out_clk + + + + + + + + + associatedDirectClock + Associated direct clock + in_clk + + + clockRate + Clock rate + 50000000 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_clock_bridge + + QUARTUS_SYNTH + + + + + + + in_clk + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + out_clk + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + add_kernel_wrapper_clock_in + altera_clock_bridge + 19.2.0 + + + + + DERIVED_CLOCK_RATE + Derived clock rate + 0 + + + EXPLICIT_CLOCK_RATE + Explicit clock rate + 50000000 + + + NUM_CLOCK_OUTPUTS + Number of Clock Outputs + 1 + + + + + + + board + Board + default + + + device + Device + 10AS066N3F40E2SG + + + deviceFamily + Device family + Arria 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element $system + { + datum _originalDeviceFamily + { + value = "Arria 10"; + type = "String"; + } + } + element clock_in + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>in_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>in_clk</value> + </entry> + <entry> + <key>clockRate</key> + <value>50000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>in_clk</key> + <value> + <connectionPointName>in_clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>out_clk</key> + <value> + <connectionPointName>out_clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>50000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + pinAssignmentListDefinition + pinAssignmentListDefinition + <pinAssignmentListDefinition/> + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/ip/add_kernel_wrapper/add_kernel_wrapper_master_0.ip b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/ip/add_kernel_wrapper/add_kernel_wrapper_master_0.ip new file mode 100644 index 0000000000..56bd44aab5 --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/ip/add_kernel_wrapper/add_kernel_wrapper_master_0.ip @@ -0,0 +1,1087 @@ + + + + Intel Corporation + add_kernel_wrapper_master_0 + master_0 + 19.1 + + + clk + + + + + + + + clk + + + clk_clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + clk_reset + + + + + + + + reset + + + clk_reset_reset + + + + + + + + + associatedClock + Associated clock + + + + synchronousEdges + Synchronous edges + NONE + + + + + master_reset + + + + + + + + reset + + + master_reset_reset + + + + + + + + + associatedClock + Associated clock + + + + associatedDirectReset + Associated direct reset + + + + associatedResetSinks + Associated reset sinks + none + + + synchronousEdges + Synchronous edges + NONE + + + + + master + + + + + + + + address + + + master_address + + + + + readdata + + + master_readdata + + + + + read + + + master_read + + + + + write + + + master_write + + + + + writedata + + + master_writedata + + + + + waitrequest + + + master_waitrequest + + + + + readdatavalid + + + master_readdatavalid + + + + + byteenable + + + master_byteenable + + + + + + + + + adaptsTo + Adapts to + + + + addressGroup + Address group + 0 + + + addressUnits + Address units + SYMBOLS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + clk + + + associatedReset + Associated reset + clk_reset + + + bitsPerSymbol + Bits per symbol + 8 + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + dBSBigEndian + dBS big endian + false + + + doStreamReads + Use flow control for read transfers + false + + + doStreamWrites + Use flow control for write transfers + false + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isAsynchronous + Is asynchronous + false + + + isBigEndian + Is big endian + false + + + isReadable + Is readable + false + + + isWriteable + Is writeable + false + + + linewrapBursts + Linewrap bursts + false + + + maxAddressWidth + Maximum address width + 32 + + + maximumPendingReadTransactions + Maximum pending read transactions + 0 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + readLatency + Read latency + 0 + + + readWaitTime + Read wait + 1 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + waitrequestAllowance + Waitrequest allowance + 0 + + + writeWaitTime + Write wait + 0 + + + + + + + debug.controlledBy + in_stream + + + debug.providesServices + master + + + debug.typeName + altera_jtag_avalon_master.master + + + debug.visible + true + + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_jtag_avalon_master + + QUARTUS_SYNTH + + + + + + + clk_clk + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + clk_reset_reset + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + master_reset_reset + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + master_address + + out + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + master_readdata + + in + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + master_read + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + master_write + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + master_writedata + + out + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + master_waitrequest + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + master_readdatavalid + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + master_byteenable + + out + + + 0 + 3 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + add_kernel_wrapper_master_0 + altera_jtag_avalon_master + 19.1 + + + + + USE_PLI + Use Simulation Link Mode + 1 + + + PLI_PORT + Simulation Link Server Port + 50000 + + + COMPONENT_CLOCK + COMPONENT_CLOCK + 0 + + + FAST_VER + Enhanced transaction master + 0 + + + FIFO_DEPTHS + FIFO depth + 2 + + + AUTO_DEVICE_FAMILY + Auto DEVICE_FAMILY + Arria 10 + + + AUTO_DEVICE + Auto DEVICE + 10AS066N3F40E2SG + + + AUTO_DEVICE_SPEEDGRADE + Auto DEVICE_SPEEDGRADE + 2 + + + + + + + debug.hostConnection + type jtag id 110:132 + + + + + + + board + Board + default + + + device + Device + 10AS066N3F40E2SG + + + deviceFamily + Device family + Arria 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element $system + { + datum _originalDeviceFamily + { + value = "Arria 10"; + type = "String"; + } + } + element master_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk_reset_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>master_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>master_reset_reset</name> + <role>reset</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>none</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>master</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>master_address</name> + <role>address</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_readdatavalid</name> + <role>readdatavalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_byteenable</name> + <role>byteenable</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>debug.controlledBy</key> + <value>in_stream</value> + </entry> + <entry> + <key>debug.providesServices</key> + <value>master</value> + </entry> + <entry> + <key>debug.typeName</key> + <value>altera_jtag_avalon_master.master</value> + </entry> + <entry> + <key>debug.visible</key> + <value>true</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>clk_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + pinAssignmentListDefinition + pinAssignmentListDefinition + <pinAssignmentListDefinition/> + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/ip/add_kernel_wrapper/add_kernel_wrapper_reset_in.ip b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/ip/add_kernel_wrapper/add_kernel_wrapper_reset_in.ip new file mode 100644 index 0000000000..73cfcff501 --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/ip/add_kernel_wrapper/add_kernel_wrapper_reset_in.ip @@ -0,0 +1,342 @@ + + + + Intel Corporation + add_kernel_wrapper_reset_in + reset_in + 19.2.0 + + + in_reset + + + + + + + + reset + + + in_reset + + + + + + + + + associatedClock + Associated clock + + + + synchronousEdges + Synchronous edges + NONE + + + + + out_reset + + + + + + + + reset + + + out_reset + + + + + + + + + associatedClock + Associated clock + + + + associatedDirectReset + Associated direct reset + in_reset + + + associatedResetSinks + Associated reset sinks + in_reset + + + synchronousEdges + Synchronous edges + NONE + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_reset_bridge + + QUARTUS_SYNTH + + + + + + + in_reset + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + out_reset + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + add_kernel_wrapper_reset_in + altera_reset_bridge + 19.2.0 + + + + + ACTIVE_LOW_RESET + Active low reset + 0 + + + SYNCHRONOUS_EDGES + Synchronous edges + none + + + NUM_RESET_OUTPUTS + Number of reset outputs + 1 + + + USE_RESET_REQUEST + Use reset request signal + 0 + + + SYNC_RESET + Use synchronous resets + 0 + + + AUTO_CLK_CLOCK_RATE + Auto CLOCK_RATE + -1 + + + + + + + board + Board + default + + + device + Device + 10AS066N3F40E2SG + + + deviceFamily + Device family + Arria 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element $system + { + datum _originalDeviceFamily + { + value = "Arria 10"; + type = "String"; + } + } + element reset_in + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_reset</name> + <role>reset</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + pinAssignmentListDefinition + pinAssignmentListDefinition + <pinAssignmentListDefinition/> + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/jtag.sdc b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/jtag.sdc new file mode 100644 index 0000000000..abbaefac73 --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/jtag.sdc @@ -0,0 +1,84 @@ +#**************************************************************************** +# +# SPDX-License-Identifier: MIT-0 +# Copyright(c) 2015-2023 Intel Corporation. +# +#**************************************************************************** +# +# Sample SDC for A10 GHRD. Targeting JTAG. +# +#**************************************************************************** +# For USB BlasterII running at 24MHz or 41.666 ns period +set t_period 41.666 +create_clock -name {altera_reserved_tck} -period $t_period [get_ports {altera_reserved_tck}] +set_clock_groups -asynchronous -group {altera_reserved_tck} + +#Datasheet parameters from UBII IP on EPM570F100C5 +#TCO/TSU/TH are measured w.r.t usb_clk inside UBII IP which is used to generate TCK signal +set tck_blaster_tco_max 14.603 +set tck_blaster_tco_min 14.603 +set tdi_blaster_tco_max 8.551 +set tdi_blaster_tco_min 8.551 +set tms_blaster_tco_max 9.468 +set tms_blaster_tco_min 9.468 + +#In bitbang mode, TDO is sampled through MAX at FX2 +set tdo_blaster_tpd_max 10.718 +set tdo_blaster_tpd_min 10.718 +set fx2_pb0_trace_max 0.152 +set fx2_pb0_trace_min 0.152 + +#Cable delays are from USB Blaster II +#TCK +set tck_cable_max 11.627 +set tck_cable_min 10.00 +#*USER MODIFY* This depends on the trace length from JTAG 10-pin header to FPGA on board +set tck_header_trace_max 0.5 +set tck_header_trace_min 0.1 + +#TMS +set tms_cable_max 11.627 +set tms_cable_min 10.0 +#*USER MODIFY* This depends on the trace length from JTAG 10-pin header to FPGA on board +set tms_header_trace_max 0.5 +set tms_header_trace_min 0.1 + +#TDI +set tdi_cable_max 11.627 +set tdi_cable_min 10.0 +#*USER MODIFY* This depends on the trace length from JTAG 10-pin header to FPGA on board +set tdi_header_trace_max 0.5 +set tdi_header_trace_min 0.1 + +#TDO +set tdo_cable_max 11.627 +set tdo_cable_min 10.0 +#*USER MODIFY* This depends on the trace length from JTAG 10-pin header to FPGA on board +set tdo_header_trace_max 0.5 +set tdo_header_trace_min 0.1 + +derive_clock_uncertainty + +#TMS +set tms_in_max [expr {$tms_cable_max + $tms_header_trace_max + $tms_blaster_tco_max - $tck_blaster_tco_min - $tck_cable_min - $tck_header_trace_min }] +set tms_in_min [expr {$tms_cable_min + $tms_header_trace_min + $tms_blaster_tco_min - $tck_blaster_tco_max - $tck_cable_max - $tck_header_trace_max }] +set_input_delay -add_delay -clock_fall -clock altera_reserved_tck -max $tms_in_max [get_ports {altera_reserved_tms}] +set_input_delay -add_delay -clock_fall -clock altera_reserved_tck -min $tms_in_min [get_ports {altera_reserved_tms}] + +#TDI +set tdi_in_max [expr {$tdi_cable_max + $tdi_header_trace_max + $tdi_blaster_tco_max - $tck_blaster_tco_min - $tck_cable_min - $tck_header_trace_min }] +set tdi_in_min [expr {$tdi_cable_min + $tdi_header_trace_min + $tdi_blaster_tco_min - $tck_blaster_tco_max - $tck_cable_max - $tck_header_trace_max }] +set_input_delay -add_delay -clock_fall -clock altera_reserved_tck -max $tdi_in_max [get_ports {altera_reserved_tdi}] +set_input_delay -add_delay -clock_fall -clock altera_reserved_tck -min $tdi_in_min [get_ports {altera_reserved_tdi}] + +#TDO Timing in Bitbang Mode +#TDO timing delays must take into account the TCK delay from the Blaster to the FPGA TCK input pin +set tdo_out_max [expr {$tdo_cable_max + $tdo_header_trace_max + $tdo_blaster_tpd_max + $fx2_pb0_trace_max + $tck_blaster_tco_max + $tck_cable_max + $tck_header_trace_max }] +set tdo_out_min [expr {$tdo_cable_min + $tdo_header_trace_min + $tdo_blaster_tpd_min + $fx2_pb0_trace_min + $tck_blaster_tco_min + $tck_cable_min + $tck_header_trace_min }] + +#TDO does not latch inside the USB Blaster II at the rising edge of TCK, it actually is passed through to the Cypress FX2 and is latched 3 FX2 cycles later (equivalent to 1.5 JTAG cycles) +set_output_delay -add_delay -clock altera_reserved_tck -max $tdo_out_max [get_ports {altera_reserved_tdo}] +set_output_delay -add_delay -clock altera_reserved_tck -min $tdo_out_min [get_ports {altera_reserved_tdo}] + +set_multicycle_path -setup -end 2 -from * -to [get_ports {altera_reserved_tdo}] + diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/quartus_sh.log b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/quartus_sh.log new file mode 100644 index 0000000000..c34927b1ba --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus-sln/quartus_sh.log @@ -0,0 +1,653 @@ +Info: ******************************************************************* +Info: Running Quartus Prime Shell + Info: Version 22.3.0 Build 104 09/14/2022 SC Pro Edition + Info: Copyright (C) 2022 Intel Corporation. All rights reserved. + Info: Your use of Intel Corporation's design tools, logic functions + Info: and other software and tools, and any partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Intel Program License + Info: Subscription Agreement, the Intel Quartus Prime License Agreement, + Info: the Intel FPGA IP License Agreement, or other applicable license + Info: agreement, including, without limitation, that your use is for + Info: the sole purpose of programming logic devices manufactured by + Info: Intel and sold by Intel or its authorized distributors. Please + Info: refer to the applicable agreement for further details, at + Info: https://fpgasoftware.intel.com/eula. + Info: Processing started: Wed Feb 8 04:58:07 2023 + Info: System process ID: 6049 +Info: Command: quartus_sh --flow compile add.qpf -c add +Info: Quartus(args): compile add.qpf -c add +Info: Project Name = /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/add +Info: Revision Name = add +Info: Run task: IP Generation +Info: ******************************************************************* +Info: Running Quartus Prime IP Generation Tool + Info: Version 22.3.0 Build 104 09/14/2022 SC Pro Edition + Info: Processing started: Wed Feb 8 04:58:09 2023 + Info: System process ID: 6085 +Info: Command: quartus_ipgenerate add -c add --run_default_mode_op +Info: Found 5 IP file(s) in the project. + Info: IP file /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/add_kernel_wrapper.qsys was found in the project. + Info: IP file /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_clock_in.ip was found in the project. + Info: IP file /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_reset_in.ip was found in the project. + Info: IP file /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_master_0.ip was found in the project. + Info: IP file /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0.ip was found in the project. +Info: Started running qsys-validate on Platform Designer system add_kernel_wrapper.qsys +Info: Performing Platform Designer system validation using the command line: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/../qsys/bin/qsys-validate add_kernel_wrapper.qsys +Warning: add_kernel_wrapper: add_fpga_ip_export_1_di_0 has port resetn declared with role reset_n which is declared as reset in file add_kernel_wrapper_add_fpga_ip_export_1_di_0.ip +Info: Finished running qsys-validate on Platform Designer system add_kernel_wrapper.qsys +Info: Only synthesis files will be generated. +Info: Performing IP Generation using the command line: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/sopc_builder/bin/qsys-generate {--family=Arria 10} --part=10AS066N3F40E2SG --block-symbol-file --quartus-project=/nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/add --rev=add --top-level-generation=true {--bypass-quartus-project } --synthesis=verilog --parallel --batch=ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0.ip --batch=ip/add_kernel_wrapper/add_kernel_wrapper_master_0.ip --batch=ip/add_kernel_wrapper/add_kernel_wrapper_reset_in.ip --batch=ip/add_kernel_wrapper/add_kernel_wrapper_clock_in.ip add_kernel_wrapper.qsys +Info: Batch generation will generate the listed files in this order: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/add_kernel_wrapper.qsys, ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0.ip, ip/add_kernel_wrapper/add_kernel_wrapper_master_0.ip, ip/add_kernel_wrapper/add_kernel_wrapper_reset_in.ip, ip/add_kernel_wrapper/add_kernel_wrapper_clock_in.ip +Info: Parallel IP Generation is enabled. +Info: Platform Designer will attempt to use 5 processors for parallel IP generation based on available number of processors and the total number of IP to be generated. +Info: Starting: Platform Designer system generation +Info: Saving generation log to /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_clock_in/add_kernel_wrapper_clock_in_generation.rpt +Info: Generated by version: 22.3 build 104 +Info: Starting: Create block symbol file (.bsf) +Info: qsys-generate /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_clock_in.ip --block-symbol-file --output-directory=/nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_clock_in --family="Arria 10" --part=10AS066N3F40E2SG +Info: Finished: Create block symbol file (.bsf) +Info: Starting: Create HDL design files for synthesis +Info: qsys-generate /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_clock_in.ip --synthesis=VERILOG --output-directory=/nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_clock_in --family="Arria 10" --part=10AS066N3F40E2SG +Info: add_kernel_wrapper_clock_in: "Transforming system: add_kernel_wrapper_clock_in" +Info: add_kernel_wrapper_clock_in: "Naming system components in system: add_kernel_wrapper_clock_in" +Info: add_kernel_wrapper_clock_in: "Processing generation queue" +Info: add_kernel_wrapper_clock_in: "Generating: add_kernel_wrapper_clock_in" +Info: add_kernel_wrapper_clock_in: Done "add_kernel_wrapper_clock_in" with 1 modules, 1 files +Info: Finished: Create HDL design files for synthesis +Info: Generation of /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_clock_in.ip (add_kernel_wrapper_clock_in) took 1465 ms +Info: Saving generation log to /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_kernel_wrapper_add_fpga_ip_export_1_di_0_generation.rpt +Info: Generated by version: 22.3 build 104 +Info: Starting: Create block symbol file (.bsf) +Info: qsys-generate /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0.ip --block-symbol-file --output-directory=/nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0 --family="Arria 10" --part=10AS066N3F40E2SG +Info: Finished: Create block symbol file (.bsf) +Info: Starting: Create HDL design files for synthesis +Info: qsys-generate /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0.ip --synthesis=VERILOG --output-directory=/nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0 --family="Arria 10" --part=10AS066N3F40E2SG +Info: add_kernel_wrapper_add_fpga_ip_export_1_di_0: "Transforming system: add_kernel_wrapper_add_fpga_ip_export_1_di_0" +Info: add_kernel_wrapper_add_fpga_ip_export_1_di_0: "Naming system components in system: add_kernel_wrapper_add_fpga_ip_export_1_di_0" +Info: add_kernel_wrapper_add_fpga_ip_export_1_di_0: "Processing generation queue" +Info: add_kernel_wrapper_add_fpga_ip_export_1_di_0: "Generating: add_kernel_wrapper_add_fpga_ip_export_1_di_0" +Info: add_kernel_wrapper_add_fpga_ip_export_1_di_0: "Generating: add_fpga_ip_export_1_di" +Info: add_kernel_wrapper_add_fpga_ip_export_1_di_0: Done "add_kernel_wrapper_add_fpga_ip_export_1_di_0" with 2 modules, 71 files +Info: Finished: Create HDL design files for synthesis +Info: Generation of /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0.ip (add_kernel_wrapper_add_fpga_ip_export_1_di_0) took 2181 ms +Info: Saving generation log to /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_reset_in/add_kernel_wrapper_reset_in_generation.rpt +Info: Generated by version: 22.3 build 104 +Info: Starting: Create block symbol file (.bsf) +Info: qsys-generate /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_reset_in.ip --block-symbol-file --output-directory=/nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_reset_in --family="Arria 10" --part=10AS066N3F40E2SG +Info: Finished: Create block symbol file (.bsf) +Info: Starting: Create HDL design files for synthesis +Info: qsys-generate /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_reset_in.ip --synthesis=VERILOG --output-directory=/nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_reset_in --family="Arria 10" --part=10AS066N3F40E2SG +Info: add_kernel_wrapper_reset_in: "Transforming system: add_kernel_wrapper_reset_in" +Info: add_kernel_wrapper_reset_in: "Naming system components in system: add_kernel_wrapper_reset_in" +Info: add_kernel_wrapper_reset_in: "Processing generation queue" +Info: add_kernel_wrapper_reset_in: "Generating: add_kernel_wrapper_reset_in" +Info: add_kernel_wrapper_reset_in: Done "add_kernel_wrapper_reset_in" with 1 modules, 1 files +Info: Finished: Create HDL design files for synthesis +Info: Generation of /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_reset_in.ip (add_kernel_wrapper_reset_in) took 1414 ms +Info: Saving generation log to /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_master_0/add_kernel_wrapper_master_0_generation.rpt +Info: Generated by version: 22.3 build 104 +Info: Starting: Create block symbol file (.bsf) +Info: qsys-generate /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_master_0.ip --block-symbol-file --output-directory=/nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_master_0 --family="Arria 10" --part=10AS066N3F40E2SG +Info: Finished: Create block symbol file (.bsf) +Info: Starting: Create HDL design files for synthesis +Info: qsys-generate /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_master_0.ip --synthesis=VERILOG --output-directory=/nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_master_0 --family="Arria 10" --part=10AS066N3F40E2SG +Info: add_kernel_wrapper_master_0: "Transforming system: add_kernel_wrapper_master_0" +Info: add_kernel_wrapper_master_0: "Naming system components in system: add_kernel_wrapper_master_0" +Info: add_kernel_wrapper_master_0: "Processing generation queue" +Info: add_kernel_wrapper_master_0: "Generating: add_kernel_wrapper_master_0" +Info: add_kernel_wrapper_master_0: "Generating: add_kernel_wrapper_master_0_altera_jtag_avalon_master_191_xta54la" +Info: add_kernel_wrapper_master_0: "Generating: altera_avalon_st_jtag_interface" +Info: add_kernel_wrapper_master_0: "Generating: add_kernel_wrapper_master_0_timing_adapter_1930_iogftka" +Info: add_kernel_wrapper_master_0: "Generating: add_kernel_wrapper_master_0_altera_avalon_sc_fifo_1931_fzgstwy" +Info: add_kernel_wrapper_master_0: "Generating: altera_avalon_st_bytes_to_packets" +Info: add_kernel_wrapper_master_0: "Generating: altera_avalon_st_packets_to_bytes" +Info: add_kernel_wrapper_master_0: "Generating: altera_avalon_packets_to_master" +Info: add_kernel_wrapper_master_0: "Generating: add_kernel_wrapper_master_0_channel_adapter_1921_5wnzrci" +Info: add_kernel_wrapper_master_0: "Generating: add_kernel_wrapper_master_0_channel_adapter_1921_fkajlia" +Info: add_kernel_wrapper_master_0: "Generating: altera_reset_controller" +Info: add_kernel_wrapper_master_0: Done "add_kernel_wrapper_master_0" with 11 modules, 23 files +Info: Finished: Create HDL design files for synthesis +Info: Generation of /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_master_0.ip (add_kernel_wrapper_master_0) took 1612 ms +Warning: add_kernel_wrapper: add_fpga_ip_export_1_di_0 has port resetn declared with role reset_n which is declared as reset in file add_kernel_wrapper_add_fpga_ip_export_1_di_0.ip +Info: Saving generation log to /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/add_kernel_wrapper/add_kernel_wrapper_generation.rpt +Info: Generated by version: 22.3 build 104 +Info: Starting: Create block symbol file (.bsf) +Info: qsys-generate /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/add_kernel_wrapper.qsys --block-symbol-file --output-directory=/nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/add_kernel_wrapper --family="Arria 10" --part=10AS066N3F40E2SG +Info: Loading add-quartus/add_kernel_wrapper.qsys +Info: Reading input file +Info: Parameterizing module add_fpga_ip_export_1_di_0 +Info: Parameterizing module clock_in +Info: Parameterizing module master_0 +Info: Parameterizing module reset_in +Info: Building connections +Info: Parameterizing connections +Info: Validating +Info: Done reading input file +Info: Finished: Create block symbol file (.bsf) +Info: Starting: Create HDL design files for synthesis +Info: qsys-generate /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/add_kernel_wrapper.qsys --synthesis=VERILOG --output-directory=/nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/add_kernel_wrapper --family="Arria 10" --part=10AS066N3F40E2SG +Info: Loading add-quartus/add_kernel_wrapper.qsys +Info: Reading input file +Info: Parameterizing module add_fpga_ip_export_1_di_0 +Info: Parameterizing module clock_in +Info: Parameterizing module master_0 +Info: Parameterizing module reset_in +Info: Building connections +Info: Parameterizing connections +Info: Validating +Info: Done reading input file +Info: add_kernel_wrapper: "Transforming system: add_kernel_wrapper" +Info: Interconnect is inserted between master master_0.master and slave add_fpga_ip_export_1_di_0.csr_ring_root_avs because the master has address signal 32 bit wide, but the slave is 5 bit wide. +Info: Interconnect is inserted between master master_0.master and slave add_fpga_ip_export_1_di_0.csr_ring_root_avs because the master has readdata signal 32 bit wide, but the slave is 64 bit wide. +Info: Interconnect is inserted between master master_0.master and slave add_fpga_ip_export_1_di_0.csr_ring_root_avs because the master has writedata signal 32 bit wide, but the slave is 64 bit wide. +Info: Interconnect is inserted between master master_0.master and slave add_fpga_ip_export_1_di_0.csr_ring_root_avs because the master has byteenable signal 4 bit wide, but the slave is 8 bit wide. +Info: add_kernel_wrapper: "Naming system components in system: add_kernel_wrapper" +Info: add_kernel_wrapper: "Processing generation queue" +Info: add_kernel_wrapper: "Generating: add_kernel_wrapper" +Info: add_kernel_wrapper: "Generating: add_kernel_wrapper_add_fpga_ip_export_1_di_0" +Info: add_kernel_wrapper: "Generating: add_kernel_wrapper_clock_in" +Info: add_kernel_wrapper: "Generating: add_kernel_wrapper_master_0" +Info: add_kernel_wrapper: "Generating: add_kernel_wrapper_reset_in" +Info: add_kernel_wrapper: "Generating: add_kernel_wrapper_altera_mm_interconnect_1920_r7ss2sq" +Info: add_kernel_wrapper: "Generating: altera_reset_controller" +Info: add_kernel_wrapper: "Generating: add_kernel_wrapper_altera_merlin_master_translator_191_g7h47bq" +Info: add_kernel_wrapper: "Generating: add_kernel_wrapper_altera_merlin_slave_translator_191_x56fcki" +Info: add_kernel_wrapper: "Generating: add_kernel_wrapper_altera_merlin_master_agent_191_mpbm6tq" +Info: add_kernel_wrapper: "Generating: add_kernel_wrapper_altera_merlin_slave_agent_191_ncfkfri" +Info: add_kernel_wrapper: "Generating: add_kernel_wrapper_altera_avalon_sc_fifo_1931_fzgstwy" +Info: add_kernel_wrapper: "Generating: add_kernel_wrapper_altera_merlin_router_1921_lzreodq" +Info: add_kernel_wrapper: "Generating: add_kernel_wrapper_altera_merlin_router_1921_4dfykji" +Info: add_kernel_wrapper: "Generating: add_kernel_wrapper_altera_merlin_demultiplexer_1921_cxey4iy" +Info: add_kernel_wrapper: "Generating: add_kernel_wrapper_altera_merlin_multiplexer_1921_yont6ya" +Info: add_kernel_wrapper: "Generating: add_kernel_wrapper_altera_merlin_multiplexer_1921_deglkyq" +Info: add_kernel_wrapper: "Generating: add_kernel_wrapper_altera_merlin_width_adapter_1920_qo37njq" +Info: add_kernel_wrapper: "Generating: add_kernel_wrapper_altera_merlin_width_adapter_1920_xqv2fwa" +Info: add_kernel_wrapper: Done "add_kernel_wrapper" with 19 modules, 24 files +Info: Finished: Create HDL design files for synthesis +Info: Generation of /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/add_kernel_wrapper.qsys (add_kernel_wrapper) took 2652 ms +Info: Finished: Platform Designer system generation +Info: Finished generating IP file(s) in the project. +Info: Quartus Prime IP Generation Tool was successful. 0 errors, 2 warnings + Info: Peak virtual memory: 982 megabytes + Info: Processing ended: Wed Feb 8 04:58:37 2023 + Info: Elapsed time: 00:00:28 + Info: System process ID: 6085 +Info: Run task: Analysis & Synthesis +Info: ******************************************************************* +Info: Running Quartus Prime Synthesis + Info: Version 22.3.0 Build 104 09/14/2022 SC Pro Edition + Info: Processing started: Wed Feb 8 04:58:39 2023 + Info: System process ID: 6685 +Info: Command: quartus_syn --read_settings_files=on --write_settings_files=off add -c add +Info: qis_default_flow_script.tcl version: #2 +Info: Initializing Synthesis... +Info: Project = "add" +Info: Revision = "add" +Info: Analyzing source files +Info (18237): File "/nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_master_0/altera_reset_controller_1921/synth/altera_reset_controller.v" is a duplicate of already analyzed file "/nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/add_kernel_wrapper/altera_reset_controller_1921/synth/altera_reset_controller.v" (same filename, same library name and same md5 digest). Skipping analysis of this file. +Info (18237): File "/nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_master_0/altera_reset_controller_1921/synth/altera_reset_synchronizer.v" is a duplicate of already analyzed file "/nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/add_kernel_wrapper/altera_reset_controller_1921/synth/altera_reset_synchronizer.v" (same filename, same library name and same md5 digest). Skipping analysis of this file. +Warning (17326): Verilog HDL warning at acl_altera_syncram_wrapped.sv(246): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_altera_syncram_wrapped.sv Line: 246 +Warning (17326): Verilog HDL warning at acl_altera_syncram_wrapped.sv(249): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_altera_syncram_wrapped.sv Line: 249 +Info (16884): Verilog HDL info at hld_fifo.sv(146): analyzing included file ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_parameter_assert.svh File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/hld_fifo.sv Line: 146 +Info (19624): Verilog HDL info at hld_fifo.sv(146): back to file 'ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/hld_fifo.sv' File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/hld_fifo.sv Line: 146 +Info (16884): Verilog HDL info at acl_mid_speed_fifo.sv(85): analyzing included file ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_parameter_assert.svh File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_mid_speed_fifo.sv Line: 85 +Info (19624): Verilog HDL info at acl_mid_speed_fifo.sv(85): back to file 'ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_mid_speed_fifo.sv' File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_mid_speed_fifo.sv Line: 85 +Warning (17326): Verilog HDL warning at acl_latency_one_ram_fifo.sv(196): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_latency_one_ram_fifo.sv Line: 196 +Warning (17326): Verilog HDL warning at acl_latency_one_ram_fifo.sv(199): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_latency_one_ram_fifo.sv Line: 199 +Warning (17326): Verilog HDL warning at acl_latency_one_ram_fifo.sv(202): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_latency_one_ram_fifo.sv Line: 202 +Warning (17326): Verilog HDL warning at acl_latency_one_ram_fifo.sv(205): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_latency_one_ram_fifo.sv Line: 205 +Warning (17326): Verilog HDL warning at acl_latency_one_ram_fifo.sv(208): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_latency_one_ram_fifo.sv Line: 208 +Warning (17326): Verilog HDL warning at acl_latency_one_ram_fifo.sv(211): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_latency_one_ram_fifo.sv Line: 211 +Warning (17326): Verilog HDL warning at acl_latency_one_ram_fifo.sv(214): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_latency_one_ram_fifo.sv Line: 214 +Warning (17326): Verilog HDL warning at acl_latency_one_ram_fifo.sv(217): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_latency_one_ram_fifo.sv Line: 217 +Warning (17326): Verilog HDL warning at acl_latency_one_ram_fifo.sv(220): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_latency_one_ram_fifo.sv Line: 220 +Warning (17326): Verilog HDL warning at acl_latency_zero_ram_fifo.sv(126): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_latency_zero_ram_fifo.sv Line: 126 +Warning (17326): Verilog HDL warning at acl_latency_zero_ram_fifo.sv(129): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_latency_zero_ram_fifo.sv Line: 129 +Warning (17326): Verilog HDL warning at acl_latency_zero_ram_fifo.sv(132): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_latency_zero_ram_fifo.sv Line: 132 +Warning (17326): Verilog HDL warning at acl_latency_zero_ram_fifo.sv(135): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_latency_zero_ram_fifo.sv Line: 135 +Warning (17326): Verilog HDL warning at acl_latency_zero_ram_fifo.sv(138): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_latency_zero_ram_fifo.sv Line: 138 +Warning (17326): Verilog HDL warning at acl_latency_zero_ram_fifo.sv(141): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_latency_zero_ram_fifo.sv Line: 141 +Warning (17326): Verilog HDL warning at acl_latency_zero_ram_fifo.sv(144): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_latency_zero_ram_fifo.sv Line: 144 +Warning (17326): Verilog HDL warning at acl_latency_zero_ram_fifo.sv(147): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_latency_zero_ram_fifo.sv Line: 147 +Warning (17326): Verilog HDL warning at acl_latency_zero_ram_fifo.sv(150): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_latency_zero_ram_fifo.sv Line: 150 +Warning (17326): Verilog HDL warning at acl_high_speed_fifo.sv(218): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_high_speed_fifo.sv Line: 218 +Warning (17326): Verilog HDL warning at acl_high_speed_fifo.sv(221): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_high_speed_fifo.sv Line: 221 +Warning (17326): Verilog HDL warning at acl_high_speed_fifo.sv(224): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_high_speed_fifo.sv Line: 224 +Warning (17326): Verilog HDL warning at acl_high_speed_fifo.sv(227): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_high_speed_fifo.sv Line: 227 +Warning (17326): Verilog HDL warning at acl_high_speed_fifo.sv(230): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_high_speed_fifo.sv Line: 230 +Warning (17326): Verilog HDL warning at acl_high_speed_fifo.sv(233): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_high_speed_fifo.sv Line: 233 +Warning (17326): Verilog HDL warning at acl_high_speed_fifo.sv(236): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_high_speed_fifo.sv Line: 236 +Warning (17326): Verilog HDL warning at acl_high_speed_fifo.sv(239): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_high_speed_fifo.sv Line: 239 +Warning (17326): Verilog HDL warning at acl_high_speed_fifo.sv(242): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_high_speed_fifo.sv Line: 242 +Warning (17326): Verilog HDL warning at acl_low_latency_fifo.sv(157): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_low_latency_fifo.sv Line: 157 +Warning (17326): Verilog HDL warning at acl_low_latency_fifo.sv(160): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_low_latency_fifo.sv Line: 160 +Warning (17326): Verilog HDL warning at acl_low_latency_fifo.sv(163): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_low_latency_fifo.sv Line: 163 +Warning (17326): Verilog HDL warning at acl_low_latency_fifo.sv(166): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_low_latency_fifo.sv Line: 166 +Warning (17326): Verilog HDL warning at acl_low_latency_fifo.sv(169): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_low_latency_fifo.sv Line: 169 +Warning (17326): Verilog HDL warning at acl_low_latency_fifo.sv(172): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_low_latency_fifo.sv Line: 172 +Warning (17326): Verilog HDL warning at acl_low_latency_fifo.sv(175): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_low_latency_fifo.sv Line: 175 +Warning (17326): Verilog HDL warning at acl_low_latency_fifo.sv(178): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_low_latency_fifo.sv Line: 178 +Warning (17326): Verilog HDL warning at acl_low_latency_fifo.sv(181): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_low_latency_fifo.sv Line: 181 +Warning (17326): Verilog HDL warning at acl_zero_latency_fifo.sv(161): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_zero_latency_fifo.sv Line: 161 +Warning (17326): Verilog HDL warning at acl_zero_latency_fifo.sv(164): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_zero_latency_fifo.sv Line: 164 +Warning (17326): Verilog HDL warning at acl_zero_latency_fifo.sv(167): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_zero_latency_fifo.sv Line: 167 +Warning (17326): Verilog HDL warning at acl_zero_latency_fifo.sv(170): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_zero_latency_fifo.sv Line: 170 +Warning (17326): Verilog HDL warning at acl_zero_latency_fifo.sv(173): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_zero_latency_fifo.sv Line: 173 +Warning (17326): Verilog HDL warning at acl_zero_latency_fifo.sv(176): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_zero_latency_fifo.sv Line: 176 +Warning (17326): Verilog HDL warning at acl_zero_latency_fifo.sv(179): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_zero_latency_fifo.sv Line: 179 +Warning (17326): Verilog HDL warning at acl_zero_latency_fifo.sv(182): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_zero_latency_fifo.sv Line: 182 +Warning (17326): Verilog HDL warning at acl_zero_latency_fifo.sv(185): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_zero_latency_fifo.sv Line: 185 +Info (16884): Verilog HDL info at acl_mlab_fifo.sv(32): analyzing included file ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_parameter_assert.svh File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_mlab_fifo.sv Line: 32 +Info (19624): Verilog HDL info at acl_mlab_fifo.sv(32): back to file 'ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_mlab_fifo.sv' File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_mlab_fifo.sv Line: 32 +Info (16884): Verilog HDL info at hld_iowr.sv(34): analyzing included file ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_parameter_assert.svh File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/hld_iowr.sv Line: 34 +Info (19624): Verilog HDL info at hld_iowr.sv(34): back to file 'ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/hld_iowr.sv' File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/hld_iowr.sv Line: 34 +Warning (17326): Verilog HDL warning at acl_push.v(100): elaboration system task fatal violates IEEE 1800 (2005) syntax File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_push.v Line: 100 +Info: Elaborating from top-level entity "add" +Info (18235): Library search order is as follows: "add_kernel_wrapper_clock_in; add_kernel_wrapper_reset_in; altera_merlin_master_translator_191; altera_merlin_slave_translator_191; altera_merlin_master_agent_191; altera_merlin_slave_agent_191; altera_avalon_sc_fifo_1931; altera_merlin_router_1921; altera_merlin_demultiplexer_1921; altera_merlin_multiplexer_1921; altera_merlin_width_adapter_1920; altera_mm_interconnect_1920; altera_reset_controller_1921; add_kernel_wrapper; altera_jtag_dc_streaming_191; timing_adapter_1930; altera_avalon_st_bytes_to_packets_1920; altera_avalon_st_packets_to_bytes_1920; altera_avalon_packets_to_master_1920; channel_adapter_1921; altera_jtag_avalon_master_191; add_kernel_wrapper_master_0; add_fpga_ip_export_1_di_10; add_kernel_wrapper_add_fpga_ip_export_1_di_0". Quartus will look for undefined design units in your libraries in that order. To modify the ordering, please specify a semi-colon separated library list using the assignment LIBRARY_SEARCH_ORDER. +Warning (13469): Verilog HDL assignment warning at acl_multistage_accumulator.v(201): truncated value with size 115 to match size of target (96) File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_multistage_accumulator.v Line: 201 +Warning (13469): Verilog HDL assignment warning at acl_multistage_accumulator.v(201): truncated value with size 115 to match size of target (96) File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_multistage_accumulator.v Line: 201 +Warning (13469): Verilog HDL assignment warning at acl_multistage_adder.v(168): truncated value with size 19 to match size of target (14) File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_multistage_adder.v Line: 168 +Warning (13469): Verilog HDL assignment warning at acl_token_fifo_counter.v(131): truncated value with size 2 to match size of target (1) File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_token_fifo_counter.v Line: 131 +Warning (13469): Verilog HDL assignment warning at acl_token_fifo_counter.v(147): truncated value with size 2 to match size of target (1) File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_token_fifo_counter.v Line: 147 +Warning (13469): Verilog HDL assignment warning at acl_token_fifo_counter.v(156): truncated value with size 3 to match size of target (2) File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_token_fifo_counter.v Line: 156 +Warning (16735): Verilog HDL warning at hld_iowr.sv(419): actual bit length 35 differs from formal bit length 34 for port "i_data" File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/hld_iowr.sv Line: 419 +Warning (16735): Verilog HDL warning at hld_iowr.sv(429): actual bit length 35 differs from formal bit length 34 for port "o_fifodata" File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/hld_iowr.sv Line: 429 +Info (19337): VHDL info at sld_jtag_endpoint_adapter.vhd(96): executing entity "sld_jtag_endpoint_adapter(sld_ir_width=3,sld_auto_instance_index="YES",sld_node_info_internal=203451904)(1,1)(1,3)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd Line: 96 +Info (19337): VHDL info at altera_sld_agent_endpoint.vhd(120): executing entity "altera_sld_agent_endpoint(mfr_code=110,type_code=132,version=1,ir_width=3)(1,1)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/altera_sld_agent_endpoint.vhd Line: 120 +Info (19337): VHDL info at altera_fabric_endpoint.vhd(126): executing entity "altera_fabric_endpoint(send_width=5,receive_width=26,settings="{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance -1 ir_width 3 bridge_agent 0 prefer_host { } psig 9b67919e}")(1,127)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd Line: 126 +Info (22567): Verilog HDL info at add_kernel_wrapper_master_0_altera_avalon_sc_fifo_1931_fzgstwy.v(125): extracting RAM for identifier 'mem' File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_master_0/altera_avalon_sc_fifo_1931/synth/add_kernel_wrapper_master_0_altera_avalon_sc_fifo_1931_fzgstwy.v Line: 125 +Info (22567): Verilog HDL info at add_kernel_wrapper_master_0_altera_avalon_sc_fifo_1931_fzgstwy.v(126): extracting RAM for identifier 'infer_mem' File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_master_0/altera_avalon_sc_fifo_1931/synth/add_kernel_wrapper_master_0_altera_avalon_sc_fifo_1931_fzgstwy.v Line: 126 +Info (22567): Verilog HDL info at add_kernel_wrapper_altera_avalon_sc_fifo_1931_fzgstwy.v(126): extracting RAM for identifier 'infer_mem' File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/add_kernel_wrapper/altera_avalon_sc_fifo_1931/synth/add_kernel_wrapper_altera_avalon_sc_fifo_1931_fzgstwy.v Line: 126 +Info (22567): Verilog HDL info at add_kernel_wrapper_altera_merlin_width_adapter_1920_qo37njq.sv(317): extracting RAM for identifier 'data_array' File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/add_kernel_wrapper/altera_merlin_width_adapter_1920/synth/add_kernel_wrapper_altera_merlin_width_adapter_1920_qo37njq.sv Line: 317 +Info (22567): Verilog HDL info at add_kernel_wrapper_altera_merlin_width_adapter_1920_qo37njq.sv(318): extracting RAM for identifier 'byteen_array' File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/add_kernel_wrapper/altera_merlin_width_adapter_1920/synth/add_kernel_wrapper_altera_merlin_width_adapter_1920_qo37njq.sv Line: 318 +Info (22567): Verilog HDL info at add_kernel_wrapper_altera_merlin_width_adapter_1920_xqv2fwa.sv(317): extracting RAM for identifier 'data_array' File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/add_kernel_wrapper/altera_merlin_width_adapter_1920/synth/add_kernel_wrapper_altera_merlin_width_adapter_1920_xqv2fwa.sv Line: 317 +Info (22567): Verilog HDL info at add_kernel_wrapper_altera_merlin_width_adapter_1920_xqv2fwa.sv(318): extracting RAM for identifier 'byteen_array' File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/add_kernel_wrapper/altera_merlin_width_adapter_1920/synth/add_kernel_wrapper_altera_merlin_width_adapter_1920_xqv2fwa.sv Line: 318 +Warning (16753): Verilog HDL warning at add_kernel_wrapper_altera_merlin_width_adapter_1920_xqv2fwa.sv(477): right shift count is greater than or equal to the width of the value File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/add_kernel_wrapper/altera_merlin_width_adapter_1920/synth/add_kernel_wrapper_altera_merlin_width_adapter_1920_xqv2fwa.sv Line: 477 +Warning (21610): Output port "device_exception_bus[0..63]" in instance "u0|add_fpga_ip_export_1_di_0|add_fpga_ip_export_1_di_0" of entity "add_fpga_ip_export_1_di" does not have a driver. Connecting to the default value "gnd". File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/add_fpga_ip_export_1_di.sv Line: 26 +Warning (21610): Output port "stall_out_lookahead" in instance "u0|add_fpga_ip_export_1_di_0|add_fpga_ip_export_1_di_0|ZTS7AdderID_std_ic_inst|ZTS7AdderID_id_iter_inst_0" of entity "acl_id_iterator" does not have a driver. Connecting to the default value "gnd". File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_id_iterator.v Line: 70 +Warning (21610): Output port "avm_burstcount" in instance "u0|add_fpga_ip_export_1_di_0|add_fpga_ip_export_1_di_0|cra_ring_wrapper_inst|csr_ring_node_avm_wire_0_cra_ring_inst_0" of entity "cra_ring_node" does not have a driver. Connecting to the default value "gnd". File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/cra_ring_node.sv Line: 47 +Warning (21610): Output port "avm_enable" in instance "u0|add_fpga_ip_export_1_di_0|add_fpga_ip_export_1_di_0|cra_ring_wrapper_inst|csr_ring_node_avm_wire_0_cra_ring_inst_0" of entity "cra_ring_node" does not have a driver. Connecting to the default value "gnd". File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/cra_ring_node.sv Line: 45 +Info: Found 147 design entities +Info: There are 195 partitions after elaboration. +Info: Creating instance-specific data models and dissolving soft partitions +Info (18299): Expanding entity and wildcard assignments. +Info (18300): Expanded entity and wildcard assignments. Elapsed time: 00:00:00 +Info (11170): Starting IP generation for the debug fabric: alt_sld_fab_0. +Info (11172): *************************************************************** +Info (11172): Quartus is a registered trademark of Intel Corporation in the +Info (11172): US and other countries. Portions of the Quartus Prime software +Info (11172): Code, and other portions of the code included in this download +Info (11172): Or on this DVD, are licensed to Intel Corporation and are the +Info (11172): Copyrighted property of third parties. For license details, +Info (11172): Refer to the End User License Agreement at +Info (11172): Http://fpgasoftware.intel.com/eula. +Info (11172): *************************************************************** +Info (11172): Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0: SLD fabric agents which did not specify prefer_host were connected to JTAG +Info (11172): Deploying alt_sld_fab_0 to /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/qdb/_compiler/add/_flat/22.3.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0.ip +Info (11172): *************************************************************** +Info (11172): Quartus is a registered trademark of Intel Corporation in the +Info (11172): US and other countries. Portions of the Quartus Prime software +Info (11172): Code, and other portions of the code included in this download +Info (11172): Or on this DVD, are licensed to Intel Corporation and are the +Info (11172): Copyrighted property of third parties. For license details, +Info (11172): Refer to the End User License Agreement at +Info (11172): Http://fpgasoftware.intel.com/eula. +Info (11172): *************************************************************** +Info (11172): Saving generation log to /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/qdb/_compiler/add/_flat/22.3.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0/alt_sld_fab_0_generation.rpt +Info (11172): Generated by version: 22.3 build 104 +Info (11172): Starting: Create HDL design files for synthesis +Info (11172): Qsys-generate /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/qdb/_compiler/add/_flat/22.3.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0.ip --synthesis=VERILOG --output-directory=/nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/qdb/_compiler/add/_flat/22.3.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0 --family="Arria 10" --part=10AS066N3F40E2SG +Info (11172): Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0: SLD fabric agents which did not specify prefer_host were connected to JTAG +Info (11172): Alt_sld_fab_0: "Transforming system: alt_sld_fab_0" +Info (11172): Alt_sld_fab_0: "Naming system components in system: alt_sld_fab_0" +Info (11172): Alt_sld_fab_0: "Processing generation queue" +Info (11172): Alt_sld_fab_0: "Generating: alt_sld_fab_0" +Info (11172): Alt_sld_fab_0: "Generating: alt_sld_fab_0_alt_sld_fab_0_10_mgvf7lq" +Info (11172): Alt_sld_fab_0: "Generating: alt_sld_fab_0_alt_sld_fab_1920_fnonq3i" +Info (11172): Alt_sld_fab_0: "Generating: altera_signaltap_agent_wrapper" +Info (11172): Alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_sld_splitter_1920_yq5fuqa" +Info (11172): Alt_sld_fab_0: "Generating: altera_jtag_wys_atom" +Info (11172): Alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_sld_jtag_hub_1920_ashi6lq" +Info (11172): Alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_connection_identification_hub_1920_cpxib3y" +Info (11172): Alt_sld_fab_0: "Generating: alt_sld_fab_0_intel_configuration_debug_reset_release_hub_203_vuwprxq" +Info (11172): Conf_reset_src: "Generating: conf_reset_src" +Info (11172): Grounded_conf_reset_src: "Generating: grounded_conf_reset_src" +Info (11172): Alt_sld_fab_0: "Generating: conf_reset_src" +Info (11172): Alt_sld_fab_0: "Generating: grounded_conf_reset_src" +Info (11172): Alt_sld_fab_0: "Generating: intel_configuration_reset_release_for_debug" +Info (11172): Alt_sld_fab_0: "Generating: intel_configuration_reset_release_to_debug_logic" +Info (11172): Alt_sld_fab_0: Done "alt_sld_fab_0" with 13 modules, 14 files +Info (11172): Finished: Create HDL design files for synthesis +Info (11172): Generation of /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/qdb/_compiler/add/_flat/22.3.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0.ip (alt_sld_fab_0) took 577 ms +Info (11171): Finished IP generation for the debug fabric: alt_sld_fab_0. +Info (19337): VHDL info at sld_signaltap.vhd(39): executing entity "sld_signaltap(sld_node_info=805334528,sld_section_id="auto_signaltap_0",sld_data_bits=215,sld_trigger_bits=215,sld_node_crc_hiword=12345,sld_node_crc_loword=19899,sld_incremental_routing=1,sld_sample_depth=131072,sld_segment_size=131072,sld_trigger_level=2,sld_advanced_trigger_entity="basic,1,sld_reserved_add_auto_signaltap_0_2_3f40,",sld_enable_advanced_trigger=1,sld_inversion_mask_length=676,sld_inversion_mask="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",sld_current_resource_width=1,sld_create_monitor_interface=1,sld_use_jtag_signal_adapter=0)(1,13)(1,16)(1,4)(1,49)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(0,675)(1,25)(1,3)(1,3)(1,5)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_signaltap.vhd Line: 39 +Info (19337): VHDL info at sld_signaltap_impl.vhd(167): executing entity "sld_signaltap_impl(sld_data_bits=215,sld_trigger_bits=215,sld_node_crc_hiword=12345,sld_node_crc_loword=19899,sld_incremental_routing=1,sld_sample_depth=131072,sld_segment_size=131072,sld_state_bits=11,sld_trigger_level=2,sld_advanced_trigger_entity="basic,1,sld_reserved_add_auto_signaltap_0_2_3f40,",sld_enable_advanced_trigger=1,sld_inversion_mask_length=676,sld_inversion_mask="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",sld_current_resource_width=1,sld_trigger_pipeline=0,sld_ram_pipeline=0,sld_counter_pipeline=0)(1,13)(1,4)(1,49)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(0,675)(1,25)(1,3)(1,3)(1,5)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_signaltap_impl.vhd Line: 167 +Info (19337): VHDL info at sld_signaltap_impl.vhd(522): executing entity "sld_signaltap_jtag(sld_data_bits=215,sld_trigger_bits=215,sld_node_crc_hiword=12345,sld_node_crc_loword=19899,sld_incremental_routing=1,sld_sample_depth=131072,sld_segment_size=131072,sld_state_bits=11,sld_buffer_full_stop=1,sld_trigger_level=2,sld_trigger_in_enabled=0,sld_advanced_trigger_entity="basic,1,sld_reserved_add_auto_signaltap_0_2_3f40,",sld_enable_advanced_trigger=1,sld_inversion_mask_length=676,sld_inversion_mask="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",sld_state_flow_mgr_entity="state_flow_mgr_entity.vhd",sld_current_resource_width=1)(1,4)(1,49)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(0,675)(1,25)(1,3)(1,3)(1,5)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_signaltap_impl.vhd Line: 522 +Info (19337): VHDL info at sld_stp_acq_core.vhd(16): executing entity "sld_stp_acq_core(sld_data_bits=215,sld_trigger_bits=215,sld_node_crc_hiword=12345,sld_node_crc_loword=19899,sld_incremental_routing=1,sld_sample_depth=131072,sld_segment_size=131072,sld_state_bits=11,sld_buffer_full_stop=1,sld_trigger_level=2,sld_trigger_in_enabled=0,sld_advanced_trigger_entity="basic,1,sld_reserved_add_auto_signaltap_0_2_3f40,",sld_enable_advanced_trigger=1,sld_inversion_mask_length=676,sld_inversion_mask="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",sld_state_flow_mgr_entity="state_flow_mgr_entity.vhd",sld_current_resource_width=1)(16,0)(16,0)(16,0)(34,0)(0,0)(16,0)(1,4)(1,49)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(0,675)(1,25)(1,3)(1,3)(1,5)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_stp_acq_core.vhd Line: 16 +Info (19337): VHDL info at sld_ela_control.vhd(72): executing entity "sld_ela_control(ip_major_version=6,trigger_input_width=215,trigger_level=2,advanced_trigger_entity="basic,1,sld_reserved_add_auto_signaltap_0_2_3f40,",enable_advanced_trigger=1,mem_address_bits=17,sample_depth=131072,state_bits=11,segment_size_bits=17,state_flow_mgr_entity="state_flow_mgr_entity.vhd",storage_qualifier_inversion_mask_length=0,storage_qualifier_advanced_condition_entity="basic")(1,49)(675,675)(1,25)(1,3)(1,5)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_ela_control.vhd Line: 72 +Info (19337): VHDL info at sld_ela_trigger_flow_mgr.vhd(10): executing entity "sld_ela_trigger_flow_mgr(ip_major_version=6,segment_size_bits=17)(0,0)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd Line: 10 +Info (19337): VHDL info at sld_buffer_manager.vhd(47): executing entity "sld_buffer_manager(ip_major_version=6,address_bits=17,segment_size_bits=17,num_segments_bits=1)(1,3)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_buffer_manager.vhd Line: 47 +Info (19337): VHDL info at sld_stp_comm_acq_domain_xing.vhd(21): executing entity "sld_stp_comm_acq_domain_xing(sld_data_bits=215,sld_trigger_bits=215,sld_node_crc_hiword=12345,sld_node_crc_loword=19899,sld_incremental_routing=1,sld_sample_depth=131072,sld_segment_size=131072,sld_state_bits=11,sld_buffer_full_stop=1,sld_trigger_level=2,sld_trigger_in_enabled=0,sld_advanced_trigger_entity="basic,1,sld_reserved_add_auto_signaltap_0_2_3f40,",sld_enable_advanced_trigger=1,sld_inversion_mask_length=676,sld_inversion_mask="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",sld_state_flow_mgr_entity="state_flow_mgr_entity.vhd",sld_current_resource_width=1)(16,0)(34,0)(0,0)(16,0)(16,0)(16,0)(16,0)(16,0)(16,0)(34,0)(0,0)(16,0)(1,4)(1,49)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(0,675)(1,25)(1,3)(1,3)(1,5)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_stp_comm_acq_domain_xing.vhd Line: 21 +Info (19337): VHDL info at intel_stp_status_bits_cdc.vhd(26): executing entity "intel_stp_status_bits_cdc(stp_status_bits_width=17)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/intel_stp_status_bits_cdc.vhd Line: 26 +Info (19337): VHDL info at sld_stp_comm_jtag.vhd(16): executing entity "sld_stp_comm_jtag(sld_data_bits=215,sld_trigger_bits=215,sld_node_crc_hiword=12345,sld_node_crc_loword=19899,sld_incremental_routing=1,sld_sample_depth=131072,sld_segment_size=131072,sld_state_bits=11,sld_buffer_full_stop=1,sld_trigger_level=2,sld_trigger_in_enabled=0,sld_advanced_trigger_entity="basic,1,sld_reserved_add_auto_signaltap_0_2_3f40,",sld_enable_advanced_trigger=1,sld_inversion_mask_length=676,sld_inversion_mask="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",sld_state_flow_mgr_entity="state_flow_mgr_entity.vhd",sld_current_resource_width=1)(16,0)(16,0)(16,0)(34,0)(0,0)(16,0)(1,4)(1,49)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(1,4)(0,675)(1,25)(1,3)(1,3)(1,5)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_stp_comm_jtag.vhd Line: 16 +Info (19337): VHDL info at sld_buffer_manager.vhd(563): executing entity "sld_offload_buffer_mgr(ip_major_version=6,buffer_depth=131072,segment_count=1,mem_address_bits=17,data_bits=215,status_bits=35,data_bit_cntr_bits=8,status_bit_cntr_bits=6,ela_status_bits=4)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_buffer_manager.vhd Line: 563 +Info (19337): VHDL info at sld_rom_sr.vhd(5): executing entity "sld_rom_sr" with architecture "INFO_REG" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_rom_sr.vhd Line: 5 +Info (19337): VHDL info at sld_stp_comm_jtag.vhd(849): executing entity "serial_crc_16" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_stp_comm_jtag.vhd Line: 849 +Info (19337): VHDL info at alt_sld_fab_0_altera_sld_jtag_hub_1920_ashi6lq.vhd(13): executing entity "alt_sld_fab_0_altera_sld_jtag_hub_1920_ashi6lq(device_family="Arria 10",count=2,n_node_ir_bits=10,node_info="0000110000100000011011100000000000110000000000000110111000000000",compilation_mode=0,force_pre_1_4_feature=0,negedge_tdo_latch=0,bridge_start_index=3)(1,8)(1,0)(1,64)" with architecture "rtl" File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/qdb/_compiler/add/_flat/22.3.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0/altera_sld_jtag_hub_1920/synth/alt_sld_fab_0_altera_sld_jtag_hub_1920_ashi6lq.vhd Line: 13 +Info (19337): VHDL info at sld_jtag_hub.vhd(89): executing entity "sld_jtag_hub(device_family="Arria 10",n_nodes=2,n_node_ir_bits=10,node_info="0000110000100000011011100000000000110000000000000110111000000000",force_pre_1_4_feature=0,negedge_tdo_latch=0,bridge_start_index=3)(1,8)(63,0)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_jtag_hub.vhd Line: 89 +Info (19337): VHDL info at sld_hub.vhd(1554): executing entity "sld_shadow_jsm(ip_major_version=1,ip_minor_version=5)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_hub.vhd Line: 1554 +Info (19337): VHDL info at sld_rom_sr.vhd(5): executing entity "sld_rom_sr(n_bits=96)" with architecture "INFO_REG" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_rom_sr.vhd Line: 5 +Info (19337): VHDL info at sld_ela_control.vhd(1174): executing entity "sld_ela_basic_multi_level_trigger(ip_major_version=6,data_bits=215)(0,0)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_ela_control.vhd Line: 1174 +Info (19337): VHDL info at sld_mbpmg.vhd(37): executing entity "sld_mbpmg(ip_major_version=6,data_bits=215)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_mbpmg.vhd Line: 37 +Info (19337): VHDL info at sld_mbpmg.vhd(257): executing entity "sld_sbpmg(ip_major_version=6)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_mbpmg.vhd Line: 257 +Info (19337): VHDL info at sld_alt_reduction.vhd(143): executing entity "sld_alt_reduction(ip_major_version=6,data_bits=15)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_alt_reduction.vhd Line: 143 +Info (19337): VHDL info at sld_alt_reduction.vhd(143): executing entity "sld_alt_reduction(ip_major_version=6,data_bits=64)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_alt_reduction.vhd Line: 143 +Info (19337): VHDL info at sld_alt_reduction.vhd(143): executing entity "sld_alt_reduction(ip_major_version=6,data_bits=8)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_alt_reduction.vhd Line: 143 +Info (19337): VHDL info at sld_alt_reduction.vhd(143): executing entity "sld_alt_reduction(ip_major_version=6,data_bits=5)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_alt_reduction.vhd Line: 143 +Info (19337): VHDL info at sld_mbpmg.vhd(37): executing entity "sld_mbpmg(ip_major_version=6,pipeline=0)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_mbpmg.vhd Line: 37 +Info (19337): VHDL info at sld_mbpmg.vhd(257): executing entity "sld_sbpmg(ip_major_version=6,pipeline=0)" with architecture "rtl" File: /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/libraries/megafunctions/sld_mbpmg.vhd Line: 257 +Info: found pre-synthesis snapshots for 2 partition(s) +Info: Synthesizing partition "root_partition" +Info (286031): Timing-Driven Synthesis is running on partition "root_partition" +Info (19000): Inferred 4 megafunctions from design logic + Info (276034): Inferred altshift_taps megafunction from the following design logic: "u0|add_fpga_ip_export_1_di_0|add_fpga_ip_export_1_di_0|ZTS7AdderID_std_ic_inst|ZTS7AdderID_finish_detector|ndrange_sum|pipelined_data_rtl_0" File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_multistage_accumulator.v Line: 113 + Info (286033): Parameter NUMBER_OF_TAPS set to 1 + Info (286033): Parameter TAP_DISTANCE set to 4 + Info (286033): Parameter WIDTH set to 19 + Info (286033): Parameter POWER_UP_STATE set to DONT_CARE + Info (276034): Inferred altshift_taps megafunction from the following design logic: "u0|add_fpga_ip_export_1_di_0|add_fpga_ip_export_1_di_0|ZTS7AdderID_std_ic_inst|ZTS7AdderID_finish_detector|ndrange_completed|pipelined_data_rtl_0" File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_multistage_accumulator.v Line: 113 + Info (286033): Parameter NUMBER_OF_TAPS set to 1 + Info (286033): Parameter TAP_DISTANCE set to 4 + Info (286033): Parameter WIDTH set to 19 + Info (286033): Parameter POWER_UP_STATE set to DONT_CARE + Info (276034): Inferred altshift_taps megafunction from the following design logic: "u0|add_fpga_ip_export_1_di_0|add_fpga_ip_export_1_di_0|ZTS7AdderID_std_ic_inst|ZTS7AdderID_finish_detector|ndrange_sum|pipelined_data_rtl_1" File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_multistage_accumulator.v Line: 113 + Info (286033): Parameter NUMBER_OF_TAPS set to 1 + Info (286033): Parameter TAP_DISTANCE set to 3 + Info (286033): Parameter WIDTH set to 19 + Info (286033): Parameter POWER_UP_STATE set to DONT_CARE + Info (276034): Inferred altshift_taps megafunction from the following design logic: "u0|add_fpga_ip_export_1_di_0|add_fpga_ip_export_1_di_0|ZTS7AdderID_std_ic_inst|ZTS7AdderID_finish_detector|ndrange_completed|pipelined_data_rtl_1" File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_multistage_accumulator.v Line: 113 + Info (286033): Parameter NUMBER_OF_TAPS set to 1 + Info (286033): Parameter TAP_DISTANCE set to 3 + Info (286033): Parameter WIDTH set to 19 + Info (286033): Parameter POWER_UP_STATE set to DONT_CARE +Info (18062): Inserted logic cells for Maximum Fan-Out assignment + Info (18058): Inserted 5 logic cells for Maximum Fan-Out assignment on "u0|add_fpga_ip_export_1_di_0|add_fpga_ip_export_1_di_0|ZTS7AdderID_std_ic_inst|ZTS7AdderID_inst_0|kernel|theZTS7AdderID_function|thebb_ZTS7AdderID_B0|thebb_ZTS7AdderID_B0_stall_region|thei_llvm_fpga_push_token_i1_throttle_push_zts7adderid_26_6gr|thei_llvm_fpga_push_token_i1_throttle_push_zts7adderid_94_1gr|fifo|valid_counter[0]" File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/ip/add_kernel_wrapper/add_kernel_wrapper_add_fpga_ip_export_1_di_0/add_fpga_ip_export_1_di_10/synth/acl_token_fifo_counter.v Line: 97 +Info (17049): 3264 registers lost all their fanouts during netlist optimizations. +Info (21057): Implemented 3474 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 5 input pins + Info (21059): Implemented 2 output pins + Info (21061): Implemented 3382 logic cells + Info (21064): Implemented 84 RAM segments + Info (21071): Implemented 1 partitions +Info: Successfully synthesized partition +Info: Synthesizing partition "auto_fab_0" +Info (286031): Timing-Driven Synthesis is running on partition "auto_fab_0" +Info (17049): 21 registers lost all their fanouts during netlist optimizations. +Info (17016): Found the following redundant logic cells in design + Info (17048): Logic cell "auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|configresetfabric|conf_reset_src|universal.lc" File: /nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/qdb/_compiler/add/_flat/22.3.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0/intel_configuration_reset_release_for_debug_203/synth/intel_configuration_reset_release_for_debug.v Line: 45 +Info (21057): Implemented 7600 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 475 input pins + Info (21059): Implemented 30 output pins + Info (21061): Implemented 5374 logic cells + Info (21064): Implemented 1720 RAM segments +Info: Successfully synthesized partition +Info: Saving post-synthesis snapshots for 2 partition(s) +Info: Quartus Prime Synthesis was successful. 0 errors, 61 warnings + Info: Peak virtual memory: 1798 megabytes + Info: Processing ended: Wed Feb 8 04:59:25 2023 + Info: Elapsed time: 00:00:46 + Info: System process ID: 6685 +Info (19538): Reading SDC files took 00:00:01 cumulatively in this process. +Info: Run task: Fitter +Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected +Info: ******************************************************************* +Info: Running Quartus Prime Fitter + Info: Version 22.3.0 Build 104 09/14/2022 SC Pro Edition + Info: Processing started: Wed Feb 8 04:59:27 2023 + Info: System process ID: 7230 +Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off add -c add +Info: qfit2_default_script.tcl version: #1 +Info: Project = add +Info: Revision = add +Info (16677): Loading synthesized database. +Info (16734): Loading "synthesized" snapshot for partition "root_partition". +Info (16734): Loading "synthesized" snapshot for partition "auto_fab_0". +Info (16678): Successfully loaded synthesized database: elapsed time is 00:00:02. +Info (119006): Selected device 10AS066N3F40E2SG for design "add" +Info (21076): Core supply voltage operating condition is not set. Assuming a default value of '0.9V'. +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 100 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Info (18824): Fitter is performing the Signal Tap Post-Fit tapping flow. +Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. +Info (12262): Starting Fitter periphery placement operations +Info (12290): Loading the periphery placement data. +Info (12291): Periphery placement data loaded: elapsed time is 00:00:24 +Critical Warning (16643): Found CONNECT_TO_SLD_NODE_ENTITY_PORT assignments found for "fpga_led" pin with multiple values. Using value: "acq_data_in[0]" + Info (16644): Assignment value for "fpga_led": "acq_data_in[0]" + Info (16644): Assignment value for "fpga_led": "acq_trigger_in[0]" +Critical Warning (16643): Found CONNECT_TO_SLD_NODE_ENTITY_PORT assignments found for "reset_button_n" pin with multiple values. Using value: "acq_data_in[1]" + Info (16644): Assignment value for "reset_button_n": "acq_data_in[1]" + Info (16644): Assignment value for "reset_button_n": "acq_trigger_in[1]" +Info (12627): Pin ~ALTERA_DATA0~ is reserved at location AH18 +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. +Info (16210): Plan updated with currently enabled project assignments. +Info (12295): Periphery placement of all unplaced cells complete: elapsed time is 00:00:00 +Critical Warning (17951): There are 48 unused RX channels in the design. + Info (19540): Add the QSF assignment 'set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to ' for each unused channel that will be used in future. + Info (19541): The above QSF assignment will preserve the performance of specified channels over time, and works only if the design uses at least 1 transceiver channel. +Critical Warning (18655): There are 48 unused TX channels in the design. + Info (19540): Add the QSF assignment 'set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to ' for each unused channel that will be used in future. + Info (19541): The above QSF assignment will preserve the performance of specified channels over time, and works only if the design uses at least 1 transceiver channel. +Info (11191): Automatically promoted 2 clocks (2 global) + Info (13173): auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|atom_inst|core_tck~CLKENA0 (4062 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_3A_G_I28 + Info (13173): i_clk~inputCLKENA0 (6510 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_3A_G_I21 +Info (332164): Evaluating HDL-embedded SDC commands + Info (332165): Entity altera_std_synchronizer + Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] + Info (332165): Entity sld_synchronizer_no_reset + Info (332166): set_false_path -to [get_keepers {*sld_synchronizer_no_reset:*|din_s1}] +Info (19539): Reading the HDL-embedded SDC files elapsed 00:00:00. +Info (332104): Reading SDC File: 'jtag.sdc' +Info (332151): Clock uncertainty is not calculated until you update the timing netlist. +Info (332104): Reading SDC File: 'add_kernel_wrapper/altera_reset_controller_1921/synth/altera_reset_controller.sdc' +Info (332104): Reading SDC File: 'ip/add_kernel_wrapper/add_kernel_wrapper_master_0/altera_jtag_dc_streaming_191/synth/altera_avalon_st_jtag_interface.sdc' +Info (332104): Reading SDC File: 'ip/add_kernel_wrapper/add_kernel_wrapper_master_0/altera_reset_controller_1921/synth/altera_reset_controller.sdc' +Info (332104): Reading SDC File: 'add.sdc' +Info (18794): Reading SDC File: '/nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/qdb/_compiler/add/_flat/22.3.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0/altera_signaltap_agent_1920/synth/intel_signal_tap.sdc' for instance: 'auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_auto_signaltap_0' +Info: Constraints on the CDC paths between acquisition clock and communication clock are created in the Signal Tap instance, auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_auto_signaltap_0 +Info (332104): Reading SDC File: '/p/psg/swip/releases5/acds/22.3/104/linux64/ip/altera/sld/jtag/altera_jtag_wys_atom/default_jtag.sdc' +Info (19449): Reading SDC files elapsed 00:00:00. +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements +Info (332111): Found 2 clocks + Info (332111): Period Clock Name + Info (332111): ======== ============ + Info (332111): 41.666 altera_reserved_tck + Info (332111): 10.000 i_clk +Info (176233): Starting register packing +Info: Constraints on the CDC paths between acquisition clock and communication clock are created in the Signal Tap instance, auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_auto_signaltap_0 +Info (176235): Finished register packing + Extra Info (176218): Packed 8 registers into blocks of type Block RAM +Info (20273): Intermediate fitter snapshots will not be committed because ENABLE_INTERMEDIATE_SNAPSHOTS QSF assignment is disabled during compilation. +Info (12517): Periphery placement operations ending: elapsed time is 00:00:43 +Info (11165): Fitter preparation operations ending: elapsed time is 00:00:40 +Info (22300): Design uses Placement Effort Multiplier = 1.0. +Info (170189): Fitter placement preparation operations beginning +Info: Constraints on the CDC paths between acquisition clock and communication clock are created in the Signal Tap instance, auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_auto_signaltap_0 +Info (14951): The Fitter is using Advanced Physical Optimization. +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:19 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:01:06 +Info: Constraints on the CDC paths between acquisition clock and communication clock are created in the Signal Tap instance, auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_auto_signaltap_0 +Info (11888): Total time spent on timing analysis during Placement is 1.87 seconds. +Info (170193): Fitter routing operations beginning +Info: Constraints on the CDC paths between acquisition clock and communication clock are created in the Signal Tap instance, auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_auto_signaltap_0 +Info (11888): Total time spent on timing analysis during Routing is 4.85 seconds. +Info (16607): Fitter routing operations ending: elapsed time is 00:02:06 +Info (22300): Design uses Placement Effort Multiplier = 1.0. +Info (11888): Total time spent on timing analysis during Post-Routing is 0.00 seconds. +Info (16557): Fitter post-fit operations ending: elapsed time is 00:01:59 +Info (20274): Successfully committed final database. +Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 6123 megabytes + Info: Processing ended: Wed Feb 8 05:06:18 2023 + Info: Elapsed time: 00:06:51 + Info: System process ID: 7230 +Info: Run task: Timing Analysis (Signoff) +Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected +Info: ******************************************************************* +Info: Running Quartus Prime Timing Analyzer + Info: Version 22.3.0 Build 104 09/14/2022 SC Pro Edition + Info: Processing started: Wed Feb 8 05:06:20 2023 + Info: System process ID: 10997 +Info: Command: quartus_sta add -c add --mode=finalize +Info: qsta_default_script.tcl version: #1 +Info (16677): Loading final database. +Info (16734): Loading "final" snapshot for partition "root_partition". +Info (16734): Loading "final" snapshot for partition "auto_fab_0". +Info (16678): Successfully loaded final database: elapsed time is 00:00:03. +Info (21076): Core supply voltage operating condition is not set. Assuming a default value of '0.9V'. +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 100 degrees C +Info (332164): Evaluating HDL-embedded SDC commands + Info (332165): Entity altera_std_synchronizer + Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] + Info (332165): Entity sld_synchronizer_no_reset + Info (332166): set_false_path -to [get_keepers {*sld_synchronizer_no_reset:*|din_s1}] +Info (19539): Reading the HDL-embedded SDC files elapsed 00:00:00. +Info (332104): Reading SDC File: 'jtag.sdc' +Info (332151): Clock uncertainty is not calculated until you update the timing netlist. +Info (332104): Reading SDC File: 'add_kernel_wrapper/altera_reset_controller_1921/synth/altera_reset_controller.sdc' +Info (332104): Reading SDC File: 'ip/add_kernel_wrapper/add_kernel_wrapper_master_0/altera_jtag_dc_streaming_191/synth/altera_avalon_st_jtag_interface.sdc' +Info (332104): Reading SDC File: 'ip/add_kernel_wrapper/add_kernel_wrapper_master_0/altera_reset_controller_1921/synth/altera_reset_controller.sdc' +Info (332104): Reading SDC File: 'add.sdc' +Info (18794): Reading SDC File: '/nfs/site/disks/swuser_work_whitepau/oneAPI_Examples/oneAPI-samples.platform-designer-ipa/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/add-quartus/qdb/_compiler/add/_flat/22.3.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0/altera_signaltap_agent_1920/synth/intel_signal_tap.sdc' for instance: 'auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_auto_signaltap_0' +Info: Constraints on the CDC paths between acquisition clock and communication clock are created in the Signal Tap instance, auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_auto_signaltap_0 +Info (332104): Reading SDC File: '/p/psg/swip/releases5/acds/22.3/104/linux64/ip/altera/sld/jtag/altera_jtag_wys_atom/default_jtag.sdc' +Info (19449): Reading SDC files elapsed 00:00:00. +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332146): Worst-case setup slack is 0.554 + Info (332119): Slack End Point TNS Failing End Points Clock Worst-Case Operating Conditions + Info (332119): ========= =================== ========= ========== ===================== + Info (332119): 0.554 0.000 0 i_clk Slow 900mV 100C Model + Info (332119): 1.464 0.000 0 altera_reserved_tck Slow 900mV 0C Model +Info (332146): Worst-case hold slack is 0.018 + Info (332119): Slack End Point TNS Failing End Points Clock Worst-Case Operating Conditions + Info (332119): ========= =================== ========= ========== ===================== + Info (332119): 0.018 0.000 0 altera_reserved_tck Fast 900mV 0C Model + Info (332119): 0.019 0.000 0 i_clk Fast 900mV 0C Model +Info (332146): Worst-case recovery slack is 6.330 + Info (332119): Slack End Point TNS Failing End Points Clock Worst-Case Operating Conditions + Info (332119): ========= =================== ========= ========== ===================== + Info (332119): 6.330 0.000 0 i_clk Slow 900mV 100C Model + Info (332119): 35.471 0.000 0 altera_reserved_tck Slow 900mV 100C Model +Info (332146): Worst-case removal slack is 0.160 + Info (332119): Slack End Point TNS Failing End Points Clock Worst-Case Operating Conditions + Info (332119): ========= =================== ========= ========== ===================== + Info (332119): 0.160 0.000 0 i_clk Fast 900mV 0C Model + Info (332119): 0.202 0.000 0 altera_reserved_tck Fast 900mV 0C Model +Info (332140): No Setup paths to report +Info (332140): No Recovery paths to report +Info (332146): Worst-case minimum pulse width slack is 4.402 + Info (332119): Slack End Point TNS Failing End Points Clock Worst-Case Operating Conditions + Info (332119): ========= =================== ========= ========== ===================== + Info (332119): 4.402 0.000 0 i_clk Slow 900mV 0C Model + Info (332119): 20.328 0.000 0 altera_reserved_tck Slow 900mV 0C Model +Info (332114): Report Metastability (Slow 900mV 100C Model): Found 71 synchronizer chains. + Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 71 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Number of Chains For Which MTBFs Could Not be Calculated Due to Timing Violations: 0, or 0.0%. + Info (332114): Number of Chains Excluded from MTBF Analysis: 56, or 78.9% + Info (332114): +Worst Case Available Settling Time: 12.460 ns + + Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 288.8 + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 4590.3 +Info (332114): Report Metastability (Slow 900mV 0C Model): Found 71 synchronizer chains. + Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 71 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Number of Chains For Which MTBFs Could Not be Calculated Due to Timing Violations: 0, or 0.0%. + Info (332114): Number of Chains Excluded from MTBF Analysis: 56, or 78.9% + Info (332114): +Worst Case Available Settling Time: 12.860 ns + + Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 78.2 + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 4590.3 +Info (332114): Report Metastability (Fast 900mV 100C Model): Found 71 synchronizer chains. + Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 71 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Number of Chains For Which MTBFs Could Not be Calculated Due to Timing Violations: 0, or 0.0%. + Info (332114): Number of Chains Excluded from MTBF Analysis: 56, or 78.9% + Info (332114): +Worst Case Available Settling Time: 14.458 ns + + Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 288.8 + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 4590.3 +Info (332114): Report Metastability (Fast 900mV 0C Model): Found 71 synchronizer chains. + Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 71 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Number of Chains For Which MTBFs Could Not be Calculated Due to Timing Violations: 0, or 0.0%. + Info (332114): Number of Chains Excluded from MTBF Analysis: 56, or 78.9% + Info (332114): +Worst Case Available Settling Time: 15.301 ns + + Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 78.2 + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 4590.3 +Info (332101): Design is fully constrained for setup requirements +Info (332101): Design is fully constrained for hold requirements +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 2594 megabytes + Info: Processing ended: Wed Feb 8 05:06:28 2023 + Info: Elapsed time: 00:00:08 + Info: System process ID: 10997 +Info: Run task: Assembler (Generate programming files) +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 22.3.0 Build 104 09/14/2022 SC Pro Edition + Info: Processing started: Wed Feb 8 05:06:30 2023 + Info: System process ID: 11037 +Info: Command: quartus_asm --read_settings_files=on --write_settings_files=off add -c add +Info (16677): Loading final database. +Info (16734): Loading "final" snapshot for partition "root_partition". +Info (16734): Loading "final" snapshot for partition "auto_fab_0". +Info (16678): Successfully loaded final database: elapsed time is 00:00:03. +Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 5128 megabytes + Info: Processing ended: Wed Feb 8 05:07:05 2023 + Info: Elapsed time: 00:00:35 + Info: System process ID: 11037 +Info (21793): Quartus Prime Full Compilation was successful. 0 errors, 69 warnings +Info (23030): Evaluation of Tcl script /p/psg/swip/releases5/acds/22.3/104/linux64/quartus/common/tcl/internal/qsh_flowengine.tcl was successful +Info: Quartus Prime Shell was successful. 0 errors, 69 warnings + Info: Peak virtual memory: 1048 megabytes + Info: Processing ended: Wed Feb 8 05:07:16 2023 + Info: Elapsed time: 00:09:09 + Info: System process ID: 6049 diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/assets/add-files.png b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/assets/add-files.png new file mode 100644 index 0000000000..e4509931c3 Binary files /dev/null and b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/assets/add-files.png differ diff --git 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2-line bus.1029 + + + + + + + + + + + + + + + + + Dynamic connector.1030 + + + + 2-line bus.1082 + Avalon MM Interconnect + + + + + Avalon MM Interconnect + + Dynamic connector.1083 + + + + Sheet.1084 + + Rectangle.1026 + JTAG-Avalon MM Master + + + + + + + JTAG-Avalon MM Master + + Sheet.1071 + MM Host + + + + MM Host + + + Rectangle + Kernel + + + + + + + Kernel + + Sheet.1085 + + Sheet.1040 + Control/Status Register + + + + Control/Status Register + + Sheet.1041 + MM Agent + + + + MM Agent + + Sheet.1042 + Start + + + + Start + + Sheet.1043 + Done + + + + Done + + Sheet.1044 + FinishCounter + + + + FinishCounter + + Sheet.1045 + + + + Sheet.1046 + + + + Sheet.1047 + + + + Sheet.1048 + + + + Sheet.1049 + + + + Sheet.1050 + + + + Sheet.1051 + + + + Sheet.1052 + + + + Sheet.1053 + + + + Sheet.1054 + + + + Sheet.1055 + some_arg + + + + some_arg + + Sheet.1056 + some_other_arg + + + + some_other_arg + + Sheet.1057 + some_output + + + + some_output + + Sheet.1058 + + + + Sheet.1059 + + + + Sheet.1060 + + + + Sheet.1061 + + + + Sheet.1062 + + + + Sheet.1063 + + + + Sheet.1064 + + + + Sheet.1065 + + + + Sheet.1066 + + + + Sheet.1067 + + + + Sheet.1068 + + + + Sheet.1069 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Laptop.1086 + + Sheet.1087 + + + + Sheet.1088 + + + + + + + + Sheet.1089 + + + + + + + + + Dynamic connector.1090 + USB + + + + + USB + + diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/assets/fix-reset_n-platform-designer.png b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/assets/fix-reset_n-platform-designer.png new file mode 100755 index 0000000000..2353559d57 Binary files /dev/null and b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/assets/fix-reset_n-platform-designer.png differ diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/assets/generate-hdl.png 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diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/assets/start-analysis.png b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/assets/start-analysis.png new file mode 100644 index 0000000000..6b443a8ebf Binary files /dev/null and b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/assets/start-analysis.png differ diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/assets/start-compilation-quartus.png b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/assets/start-compilation-quartus.png new file mode 100755 index 0000000000..840491a575 Binary files /dev/null and b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/assets/start-compilation-quartus.png differ diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/sample.json b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/sample.json new file mode 100755 index 0000000000..60b5bb4069 --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/sample.json @@ -0,0 +1,71 @@ +{ + "guid": "293B78FB-40A3-4F81-A3CB-D2C3ED344AE1", + "name": "Platform Designer - Intel® Arria® 10 SX SoC Developer Kit", + "categories": ["Toolkit/oneAPI Direct Programming/C++SYCL FPGA/Tutorials/Tools/experimental"], + "description": "An Intel® FPGA tutorial demonstrating how to export a reusable IP component to Intel® Quartus® Prime Pro and Platform Designer.", + "toolchain": ["icpx"], + "os": ["linux", "windows"], + "targetDevice": ["FPGA"], + "builder": ["cmake"], + "languages": [{"cpp":{}}], + "commonFolder": { + "base": "../../../../", + "include": [ + "README.md", + "Tutorials/Tools/experimental/platform_designer", + "include" + ], + "exclude": [] + }, + "ciTests": { + "linux": [ + { + "id": "fpga_emu", + "steps": [ + "icpx --version", + "mkdir add-oneapi/build", + "cd add-oneapi/build", + "cmake ..", + "make fpga_emu", + "./add.fpga_emu" + ] + }, + { + "id": "report", + "steps": [ + "icpx --version", + "mkdir add-oneapi/build", + "cd add-oneapi/build", + "cmake ..", + "make report" + ] + } + ], + "windows": [ + { + "id": "fpga_emu", + "steps": [ + "icx-cl --version", + "cd ../../..", + "mkdir add-oneapi/build", + "cd add-oneapi/build", + "cmake -G \"NMake Makefiles\" ../Tutorials/Tools/experimental/platform_designer/add-oneapi", + "nmake fpga_emu", + "add.fpga_emu.exe" + ] + }, + { + "id": "report", + "steps": [ + "icx-cl --version", + "cd ../../..", + "mkdir add-oneapi/build", + "cd add-oneapi/build", + "cmake -G \"NMake Makefiles\" ../Tutorials/Tools/experimental/platform_designer/add-oneapi", + "nmake report" + ] + } + ] + }, + "expertise": "Getting Started" +} diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/system_console/jtag_avmm.tcl b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/system_console/jtag_avmm.tcl new file mode 100755 index 0000000000..0f4dcee9e3 --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/system_console/jtag_avmm.tcl @@ -0,0 +1,6 @@ +# Copyright (c) 2022 Intel Corporation +# SPDX-License-Identifier: MIT + +get_service_paths master +set master_service_path [ lindex [get_service_paths master] 0] +open_service master $master_service_path diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/system_console/load_inputs.tcl b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/system_console/load_inputs.tcl new file mode 100755 index 0000000000..cbc0abade9 --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/system_console/load_inputs.tcl @@ -0,0 +1,20 @@ +# Copyright (c) 2022 Intel Corporation +# SPDX-License-Identifier: MIT + +# addresses from add-oneapi/build/add.fpga_ip_export.prj_1/AdderID_register_map.hpp + +set ADDR_A 0x90 +set VAL_A 3 +set ADDR_B 0x94 +set VAL_B 6 +set ADDR_START 0x08 + +puts "Store $VAL_A to address $ADDR_A" +master_write_32 $master_service_path $ADDR_A $VAL_A + +puts "Store $VAL_B to address $ADDR_B" +master_write_32 $master_service_path $ADDR_B $VAL_B + +# start component +puts "Set 'Start' bit to 1" +master_write_32 $master_service_path $ADDR_START 0x01 diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/system_console/read_outputs.tcl b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/system_console/read_outputs.tcl new file mode 100755 index 0000000000..f907a4b10a --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/system_console/read_outputs.tcl @@ -0,0 +1,18 @@ +# Copyright (c) 2022 Intel Corporation +# SPDX-License-Identifier: MIT + +# addresses from add-oneapi/build/add.fpga_ip_export.prj_1/AdderID_register_map.hpp + +set ADDR_STATUS 0x00 +set ADDR_C 0x80 +set ADDR_FINISH_COUNT 0x30 + +puts "Outputs:" + +set readData [master_read_32 $master_service_path $ADDR_C 2]; +set statusReg [master_read_32 $master_service_path $ADDR_STATUS 2]; +set finishCounter [master_read_32 $master_service_path $ADDR_FINISH_COUNT 2]; + +puts " Data ($ADDR_C): $readData" +puts " Status ($ADDR_STATUS): $statusReg" +puts " finish ($ADDR_FINISH_COUNT): $finishCounter" \ No newline at end of file diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/system_console/test.bat b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/system_console/test.bat new file mode 100644 index 0000000000..0539e8c565 --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/system_console/test.bat @@ -0,0 +1,25 @@ +@ REM Check if quartus.exe is on the PATH +@ WHERE /q quartus.exe +@ IF ERRORLEVEL 1 ( + ECHO quartus.exe not found. Ensure it is installed and placed in your PATH. + EXIT /B +) + +@ REM Find Quartus in PATH +@ WHERE quartus.exe > .quartus-log.txt +@ SET /p QUARTUS_PATH=<.quartus-log.txt +@ DEL .quartus-log.txt +@ SET QUARTUS_PATH=%QUARTUS_PATH:\quartus.exe=% + +@ REM derive paths to system-console.exe and quartus_pgm.exe +@ SET SYSCONSOLE_PATH=%QUARTUS_PATH%\..\..\syscon\bin +@ SET QUARTUSPGM_PATH=%QUARTUS_PATH% + +%QUARTUSPGM_PATH%\quartus_pgm.exe -m jtag -c 1 -o "p;add.sof@1" + +@ IF %ERRORLEVEL% EQU 0 ( + PAUSE + "%SYSCONSOLE_PATH%\system-console.exe" -cli --rc_script=main.tcl +) ELSE ( + EXIT /B 1 +) \ No newline at end of file