From 686c95adbe1a20e1d7a44a22861337a28a87112e Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Mon, 27 Feb 2023 00:03:02 -0800 Subject: [PATCH] update seed Signed-off-by: Yohann Uguen --- .../C++SYCL_FPGA/ReferenceDesigns/gzip/src/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/CMakeLists.txt index 133c8c1de0..635c19ec5a 100755 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/CMakeLists.txt @@ -77,7 +77,7 @@ elseif(DEVICE_FLAG MATCHES "S10") set(SEED "-Xsseed=16") set(NUM_REORDER "") else() - set(SEED "-Xsseed=4") + set(SEED "-Xsseed=1") # For the High Bandwidth variant, specify 6 reordering units to improve global memory read bandwidth across 4 channels of DDR. # For Low Latency variant this is not necessary since only one channel of global memory is used (host memory). set(NUM_REORDER "-Xsnum-reorder=6")