From 71e8253852907c8f6972504aa86bf0d865ec96dc Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Mon, 27 Feb 2023 04:25:49 -0800 Subject: [PATCH] reduce problem size sim Signed-off-by: Yohann Uguen --- .../Features/memory_attributes/src/memory_attributes.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/memory_attributes/src/memory_attributes.cpp b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/memory_attributes/src/memory_attributes.cpp index da6ad25c43..70fa8c02b0 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/memory_attributes/src/memory_attributes.cpp +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/memory_attributes/src/memory_attributes.cpp @@ -12,7 +12,12 @@ using namespace sycl; // constants for this tutorial constexpr size_t kRows = 8; +#if defined(FPGA_SIMULATOR) +// Use a smaller unroll factor when running simulation +constexpr size_t kVec = 1; +#else constexpr size_t kVec = 4; +#endif constexpr size_t kMaxVal = 512; constexpr size_t kNumTests = 64; constexpr size_t kMaxIter = 8;