From a515711b1fae774c19f392fa33fd350091788db0 Mon Sep 17 00:00:00 2001 From: Yohann Uguen Date: Thu, 23 Mar 2023 07:19:43 -0700 Subject: [PATCH] document RTL library issue Signed-off-by: Yohann Uguen --- .../C++SYCL_FPGA/Tutorials/Tools/use_library/README.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/use_library/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/use_library/README.md index ed1ff249b9..3ffb929fb1 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/use_library/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/use_library/README.md @@ -21,6 +21,9 @@ This FPGA tutorial demonstrates how to build SYCL device libraries from RTL sour > > :warning: Make sure you add the device files associated with the FPGA that you are targeting to your Intel® Quartus® Prime installation. + +> :warning: When targeting an IP-only flow, the RTL library feature will not work when compiling to Quartus and will error out in the late-stage compile. RTL libraries will work in the simulation flow. This will be fixed in a future release. This is documented in the [compiler release notes](https://www.intel.com/content/www/us/en/developer/articles/release-notes/intel-oneapi-dpc-c-compiler-release-notes.html). + ## Prerequisites This sample is part of the FPGA code samples.