FPGA: Switch to default seed 2 to avoid Stratix10 timing failures in the stall_enable sample #2035
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…the stall_enable sample (oneapi-src#2034) This avoids a timing failure on Stratix10 for the default seed
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Port of #2034
Existing Sample Changes
Description
This avoids a timing failure on Stratix10 for the default seed
Type of change
How Has This Been Tested?
Generated the makefiles using cmake and looked for -Xsseed=2 argument