From cbf71e0d9bb0092ea3575fe33f67fe7f514cf2c5 Mon Sep 17 00:00:00 2001 From: Mark Mendell Date: Tue, 7 Nov 2023 12:27:01 -0500 Subject: [PATCH] FPGA: Switch to default seed 2 to avoid Stratix10 timing failures in the stall_enable sample (#2034) This avoids a timing failure on Stratix10 for the default seed --- .../Features/stall_enable/src/CMakeLists.txt | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/stall_enable/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/stall_enable/src/CMakeLists.txt index 4c8615b19b..2e51bbf705 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/stall_enable/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/stall_enable/src/CMakeLists.txt @@ -30,6 +30,21 @@ if(WIN32) set(WIN_FLAG "/EHsc") endif() +# Choose the random seed for the hardware compile +# e.g. cmake .. -DSEED=7 +if(NOT DEFINED SEED) + # Seed 1 fails for S10 on Windows + set(SEED 2) +else() + message(STATUS "Seed explicitly set to ${SEED}") +endif() + +if(IGNORE_DEFAULT_SEED) + set(SEED_FLAG "") +else() + set(SEED_FLAG "-Xsseed=${SEED}") +endif() + # A SYCL ahead-of-time (AoT) compile processes the device code in two stages. # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. @@ -39,7 +54,7 @@ set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${HYPER_FLAG} -Xssimulation -DFPGA_SIMULATOR") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} ${HYPER_FLAG} ${USER_HARDWARE_FLAGS}") set(HARDWARE_COMPILE_FLAGS "-fsycl -fintelfpga -Wall ${WIN_FLAG} ${HYPER_FLAG} -DFPGA_HARDWARE") -set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${HYPER_FLAG} ${USER_HARDWARE_FLAGS}") +set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware ${SEED_FLAG} -Xstarget=${FPGA_DEVICE} ${HYPER_FLAG} ${USER_HARDWARE_FLAGS}") # use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation ###############################################################################