diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/autorun/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/autorun/README.md index d78a021e37..ba095aa3bf 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/autorun/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/autorun/README.md @@ -38,7 +38,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/buffered_host_streaming/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/buffered_host_streaming/README.md index c6aecf4ebb..da1be8c44d 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/buffered_host_streaming/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/buffered_host_streaming/README.md @@ -47,7 +47,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/compute_units/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/compute_units/README.md index bfa3a66fa0..4213792302 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/compute_units/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/compute_units/README.md @@ -41,7 +41,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/double_buffering/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/double_buffering/README.md index 8cefea26d1..817e5351e9 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/double_buffering/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/double_buffering/README.md @@ -42,7 +42,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/README.md index a28649d864..7c0c5c55c0 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/README.md @@ -38,7 +38,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/io_streaming/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/io_streaming/README.md index cc0bead86b..605e04715b 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/io_streaming/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/io_streaming/README.md @@ -38,7 +38,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/loop_carried_dependency/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/loop_carried_dependency/README.md index 310c720f20..11252f7223 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/loop_carried_dependency/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/loop_carried_dependency/README.md @@ -41,7 +41,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/n_way_buffering/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/n_way_buffering/README.md index 066c56a7ee..21b295a830 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/n_way_buffering/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/n_way_buffering/README.md @@ -39,7 +39,7 @@ You can also find more information about [troubleshooting build errors](/DirectP | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/onchip_memory_cache/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/onchip_memory_cache/README.md index 60821fa11f..0f5e850bf5 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/onchip_memory_cache/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/onchip_memory_cache/README.md @@ -21,7 +21,7 @@ This sample demonstrates the following concepts: | Optimized for | Description --- |--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/optimize_inner_loop/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/optimize_inner_loop/README.md index 551bd02559..1d130a5abf 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/optimize_inner_loop/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/optimize_inner_loop/README.md @@ -19,7 +19,7 @@ This is an advanced sample (tutorial) that relies on understanding fMAX RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel® oneAPI DPC++/C++ Compiler is enough to compile for emulation, generating reports, generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/pipe_array/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/pipe_array/README.md index 09d7966739..a2b06782ea 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/pipe_array/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/pipe_array/README.md @@ -22,7 +22,7 @@ This tutorial provides a convenient pair of header files defining an abstraction | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel® oneAPI DPC++/C++ Compiler is enough to compile for emulation, generating reports, generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/shannonization/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/shannonization/README.md index 7534805009..5e4ffd587d 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/shannonization/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/shannonization/README.md @@ -17,7 +17,7 @@ Demonstrate a loop optimization to improve the fMAX/II of an FPGA des | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel® oneAPI DPC++/C++ Compiler is enough to compile for emulation, generating reports, generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/shannonization/src/shannonization.cpp b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/shannonization/src/shannonization.cpp index 6ebdbe5542..6928afa1fc 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/shannonization/src/shannonization.cpp +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/shannonization/src/shannonization.cpp @@ -311,6 +311,10 @@ int main(int argc, char** argv) { success &= Intersection<0,3>(q, a, b, golden_n); success &= Intersection<1,2>(q, a, b, golden_n); success &= Intersection<2,2>(q, a, b, golden_n); +#elif defined(Agilex5) + success &= Intersection<0,3>(q, a, b, golden_n); + success &= Intersection<1,2>(q, a, b, golden_n); + success &= Intersection<2,2>(q, a, b, golden_n); #else success &= Intersection<0,3>(q, a, b, golden_n); success &= Intersection<1,3>(q, a, b, golden_n); diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/simple_host_streaming/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/simple_host_streaming/README.md index 390a0f7bd5..0800c49812 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/simple_host_streaming/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/simple_host_streaming/README.md @@ -25,7 +25,7 @@ This tutorial includes three designs: | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/triangular_loop/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/triangular_loop/README.md index 784c39c1a9..2ed5bf4da8 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/triangular_loop/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/triangular_loop/README.md @@ -18,7 +18,7 @@ This FPGA sample introduces an advanced optimization technique to improve the pe | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel® oneAPI DPC++/C++ Compiler is enough to compile for emulation, generating reports, generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/README.md index 3eb4b9a300..3a2875dc85 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/README.md @@ -22,7 +22,7 @@ This sample demonstrates how to take advantage of zero-copy host memory for the | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel® oneAPI DPC++/C++ Compiler is enough to compile for emulation, generating reports, generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/README.md index 7612382d94..5e076f57b8 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/README.md @@ -21,7 +21,7 @@ This tutorial shows the recommended method for constructing an `ac_fixed` number | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_int/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_int/README.md index 81349ea14e..1a5ab4de48 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_int/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_int/README.md @@ -21,7 +21,7 @@ This data type can be used in place of native integer types to generate area eff | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/annotated_class_clean_coding/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/annotated_class_clean_coding/README.md index ab2fc08e42..617ef70a92 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/annotated_class_clean_coding/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/annotated_class_clean_coding/README.md @@ -7,7 +7,7 @@ This Intel® FPGA tutorial demonstrates how to use the included `annotated_class | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler | What you will learn | How to use the provided helper funtion to allocate host/shared memory with properties for your FPGA IP components | Time to complete | 10 minutes diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/annotated_ptr/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/annotated_ptr/README.md index 3eb44813fa..e426589558 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/annotated_ptr/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/annotated_ptr/README.md @@ -5,7 +5,7 @@ This tutorial demonstrates how to use the `annotated_ptr` class to constrain mem | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler | What you will learn | Best practices for creating and managing a oneAPI FPGA project | Time to complete | 15 minutes diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/device_global/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/device_global/README.md index c25d15804e..bd3bf230ca 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/device_global/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/device_global/README.md @@ -17,7 +17,7 @@ This tutorial demonstrates a simple example of initializing a `device_global` cl | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/hostpipes/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/hostpipes/README.md index e207c443e5..b5dac56087 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/hostpipes/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/hostpipes/README.md @@ -19,7 +19,7 @@ Pipes connecting a host and a device are called host pipes. Use host pipes to mo | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/latency_control/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/latency_control/README.md index 14d8c76392..7f5b8c25fa 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/latency_control/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/experimental/latency_control/README.md @@ -17,7 +17,7 @@ This FPGA tutorial demonstrates how to set latency constraints to pipes and LSUs | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/fpga_reg/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/fpga_reg/README.md index 794c82622c..62c833e92a 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/fpga_reg/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/fpga_reg/README.md @@ -24,7 +24,7 @@ This FPGA tutorial demonstrates an example of using the `ext::intel::fpga_reg` e | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/hls_flow_interfaces/component_interfaces_comparison/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/hls_flow_interfaces/component_interfaces_comparison/README.md index fe51956142..94a0d7ea49 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/hls_flow_interfaces/component_interfaces_comparison/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/hls_flow_interfaces/component_interfaces_comparison/README.md @@ -12,7 +12,7 @@ This sample introduces different invocation/data interfaces that can be used whe | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel® oneAPI DPC++/C++ Compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/hls_flow_interfaces/invocation_interfaces/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/hls_flow_interfaces/invocation_interfaces/README.md index c792487398..1a071aea25 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/hls_flow_interfaces/invocation_interfaces/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/hls_flow_interfaces/invocation_interfaces/README.md @@ -19,7 +19,7 @@ Use the `get` kernel properties method to specify how the IP is started, and `an | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/hls_flow_interfaces/mmhost/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/hls_flow_interfaces/mmhost/README.md index c60be72854..4977a0afbf 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/hls_flow_interfaces/mmhost/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/hls_flow_interfaces/mmhost/README.md @@ -4,7 +4,7 @@ This tutorial demonstrates how to configure Avalon memory-mapped host data inter | Optimized for | Description --- |--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler | What you will learn | How to customize Avalon memory-mapped host interfaces in your FPGA IP components | Time to complete | 45 minutes diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/hls_flow_interfaces/streaming_data_interfaces/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/hls_flow_interfaces/streaming_data_interfaces/README.md index c28602eb15..19afbd45c8 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/hls_flow_interfaces/streaming_data_interfaces/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/hls_flow_interfaces/streaming_data_interfaces/README.md @@ -19,7 +19,7 @@ The concept of a pipe is an intuitive mechanism for specifying streaming data in | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note:** Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/kernel_args_restrict/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/kernel_args_restrict/README.md index fd486b3375..bf52dbc37d 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/kernel_args_restrict/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/kernel_args_restrict/README.md @@ -17,7 +17,7 @@ Due to pointer aliasing, the compiler must be conservative about optimizations t | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_coalesce/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_coalesce/README.md index caa170978b..363bf814ad 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_coalesce/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_coalesce/README.md @@ -20,7 +20,7 @@ The `loop_coalesce` attribute enables you to direct the compiler to combine nest | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_fusion/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_fusion/README.md index d57c8bd81b..22afdca057 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_fusion/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_fusion/README.md @@ -18,7 +18,7 @@ This sample demonstrates how to apply loop fusion to loops in your design. It is | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_initiation_interval/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_initiation_interval/CMakeLists.txt index e00d4fbd89..44f8c400cf 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_initiation_interval/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_initiation_interval/CMakeLists.txt @@ -44,8 +44,10 @@ else() set(DEVICE_FLAG "A10") elseif(FPGA_DEVICE_NAME MATCHES ".*s10.*" OR FPGA_DEVICE_NAME MATCHES ".*stratix10.*") set(DEVICE_FLAG "S10") - elseif(FPGA_DEVICE_NAME MATCHES ".*agilex.*") + elseif(FPGA_DEVICE_NAME MATCHES ".*agilex7.*") set(DEVICE_FLAG "Agilex7") + elseif(FPGA_DEVICE_NAME MATCHES ".*agilex5.*") + set(DEVICE_FLAG "Agilex5") elseif(FPGA_DEVICE_NAME MATCHES ".*cyclonev.*") set(DEVICE_FLAG "CycloneV") endif() @@ -53,8 +55,8 @@ endif() if(NOT DEFINED DEVICE_FLAG) message(FATAL_ERROR "An unrecognized or custom board was passed, but DEVICE_FLAG was not specified. \ - Please make sure you have set -DDEVICE_FLAG=A10, -DDEVICE_FLAG=S10, -DDEVICE_FLAG=CycloneV or \ - -DDEVICE_FLAG=Agilex7.") + Please make sure you have set -DDEVICE_FLAG=A10, -DDEVICE_FLAG=S10, -DDEVICE_FLAG=CycloneV, \ + -DDEVICE_FLAG=Agilex5, or -DDEVICE_FLAG=Agilex7.") endif() if (NOT DEFINED PART) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_initiation_interval/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_initiation_interval/README.md index 7aab1aecf5..2751ed0015 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_initiation_interval/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_initiation_interval/README.md @@ -25,7 +25,7 @@ This FPGA tutorial demonstrates how to use the `intel::initiation_interval` attr | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_initiation_interval/src/loop_initiation_interval.cpp b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_initiation_interval/src/loop_initiation_interval.cpp index 508cca69b7..2868c47707 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_initiation_interval/src/loop_initiation_interval.cpp +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_initiation_interval/src/loop_initiation_interval.cpp @@ -122,6 +122,8 @@ void RunKernel(std::vector &in, std::vector &out) { [[intel::initiation_interval(5)]] #elif defined(CycloneV) [[intel::initiation_interval(5)]] +#elif defined(Agilex5) + [[intel::initiation_interval(5)]] #elif defined(Agilex7) [[intel::initiation_interval(5)]] #else diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_ivdep/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_ivdep/README.md index e6a5923f3f..aa66197fe6 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_ivdep/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_ivdep/README.md @@ -17,7 +17,7 @@ To understand and apply `ivdep` to loops in your design, you must understand the | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_unroll/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_unroll/README.md index 78fdee758d..0577929109 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_unroll/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/loop_unroll/README.md @@ -17,7 +17,7 @@ The loop unrolling mechanism is used to increase program parallelism by duplicat | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/max_interleaving/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/max_interleaving/README.md index 1efa5ca595..0b03916a65 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/max_interleaving/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/max_interleaving/README.md @@ -23,7 +23,7 @@ The `[[intel::max_interleaving(0 or 1)]]` attribute can instruct the compiler to | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/max_reinvocation_delay/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/max_reinvocation_delay/README.md index 3c7488242d..f3cd125694 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/max_reinvocation_delay/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/max_reinvocation_delay/README.md @@ -17,7 +17,7 @@ This tutorial demonstrates how and when to apply the `max_reinvocation_delay` at | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel® oneAPI DPC++/C++ Compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/mem_channel/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/mem_channel/README.md index 8ed94bf0d4..23ecd84435 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/mem_channel/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/mem_channel/README.md @@ -7,7 +7,7 @@ SYCL*-compliant FPGA design. | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex®, Arria® 10, and Stratix® 10 FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, and Stratix® 10 FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler | What you will learn | How and when to use the `mem_channel` buffer property and the `-Xsno-interleaving` flag | Time to complete | 30 minutes diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/memory_attributes/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/memory_attributes/README.md index ae47e47fe9..f5a214015d 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/memory_attributes/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/memory_attributes/README.md @@ -17,7 +17,7 @@ For each private or local array in your FPGA device code, the compiler creates a | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/optimization_targets/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/optimization_targets/README.md index 0ad767d17e..69266c562a 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/optimization_targets/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/optimization_targets/README.md @@ -31,7 +31,7 @@ As an example, this tutorial shows how to use the minimum latency optimization t | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/pipes/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/pipes/README.md index 550b1ec440..28f8e12f76 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/pipes/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/pipes/README.md @@ -18,7 +18,7 @@ data to or from another kernel using the pipe abstraction. | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/printf/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/printf/README.md index c29e13149f..5d3f9bbf3d 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/printf/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/printf/README.md @@ -17,7 +17,7 @@ This tutorial shows how to use some simple macros to enable easy use of the SYCL | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/private_copies/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/private_copies/README.md index f777e9a895..5c6aebc758 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/private_copies/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/private_copies/README.md @@ -18,7 +18,7 @@ This tutorial demonstrates a simple example of applying the `private_copies` att | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/read_only_cache/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/read_only_cache/README.md index 5424f063a9..432926d3d3 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/read_only_cache/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/read_only_cache/README.md @@ -43,7 +43,7 @@ by the `-Xsread-only-cache-size=` flag. | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/scheduler_target_fmax/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/scheduler_target_fmax/README.md index b578b456e9..bb1f688c78 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/scheduler_target_fmax/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/scheduler_target_fmax/README.md @@ -17,7 +17,7 @@ This tutorial demonstrates how to use the `[[intel::scheduler_target_fmax_mhz(N) | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/speculated_iterations/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/speculated_iterations/CMakeLists.txt index ee3be391b4..0553051d78 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/speculated_iterations/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/speculated_iterations/CMakeLists.txt @@ -44,8 +44,10 @@ else() set(DEVICE_FLAG "A10") elseif(FPGA_DEVICE_NAME MATCHES ".*s10.*" OR FPGA_DEVICE_NAME MATCHES ".*stratix10.*") set(DEVICE_FLAG "S10") - elseif(FPGA_DEVICE_NAME MATCHES ".*agilex.*") + elseif(FPGA_DEVICE_NAME MATCHES ".*agilex7.*") set(DEVICE_FLAG "Agilex7") + elseif(FPGA_DEVICE_NAME MATCHES ".*agilex5.*") + set(DEVICE_FLAG "Agilex5") elseif(FPGA_DEVICE_NAME MATCHES ".*cyclonev.*") set(DEVICE_FLAG "CycloneV") endif() @@ -53,8 +55,8 @@ endif() if(NOT DEFINED DEVICE_FLAG) message(FATAL_ERROR "An unrecognized or custom board was passed, but DEVICE_FLAG was not specified. \ - Please make sure you have set -DDEVICE_FLAG=A10, -DDEVICE_FLAG=S10, -DDEVICE_FLAG=CycloneV or \ - -DDEVICE_FLAG=Agilex7.") + Please make sure you have set -DDEVICE_FLAG=A10, -DDEVICE_FLAG=S10, -DDEVICE_FLAG=CycloneV, \ + -DDEVICE_FLAG=Agilex5, or -DDEVICE_FLAG=Agilex7.") endif() # Use cmake -DUSER_FPGA_FLAGS= to set extra flags for FPGA backend diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/speculated_iterations/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/speculated_iterations/README.md index e6aa6b0167..efdf218888 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/speculated_iterations/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/speculated_iterations/README.md @@ -20,7 +20,7 @@ The `speculated_iterations` attribute is a loop attribute that enables you to di | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/speculated_iterations/src/speculated_iterations.cpp b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/speculated_iterations/src/speculated_iterations.cpp index 87676352ec..53ad1aee6e 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/speculated_iterations/src/speculated_iterations.cpp +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/speculated_iterations/src/speculated_iterations.cpp @@ -140,6 +140,10 @@ int main(int argc, char *argv[]) { ComplexExit<0, true>(bound, r0); ComplexExit<10>(bound, r1); ComplexExit<54>(bound, r2); +#elif defined(Agilex5) + ComplexExit<0, true>(bound, r0); + ComplexExit<10>(bound, r1); + ComplexExit<50>(bound, r2); #elif defined(Agilex7) ComplexExit<0, true>(bound, r0); ComplexExit<10>(bound, r1); diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/stall_enable/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/stall_enable/README.md index 65881cbde7..0d01b5f868 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/stall_enable/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/stall_enable/README.md @@ -22,7 +22,7 @@ Computations in an FPGA kernel are normally grouped into *Stall Free Clusters*. | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/README.md index 7138563d5b..f5bfe65b4f 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/README.md @@ -29,7 +29,7 @@ This tutorial explains both mechanisms and the pros and cons of each. The includ | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/README.md index 8704c89d58..7f93d0cb97 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/README.md @@ -19,7 +19,7 @@ While SYCL* code can be compiled for CPU, GPU, or FPGA, compiling to FPGA is som | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/README.md index be1df4838e..d398b1c481 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/README.md @@ -5,7 +5,7 @@ This project serves as a template for Intel® oneAPI FPGA designs, and demonstra | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler | What you will learn | Best practices for creating and managing a oneAPI FPGA project | Time to complete | 10 minutes diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/dynamic_profiler/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/dynamic_profiler/README.md index 5e67d9fac7..1950cb3f9d 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/dynamic_profiler/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/dynamic_profiler/README.md @@ -7,7 +7,7 @@ This FPGA tutorial demonstrates how to use the Intel® FPGA Dynamic Profiler for | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler | What you will learn | About the Intel® FPGA Dynamic Profiler for DPC++
How to set up and use this tool
A case study of using this tool to identify performance bottlenecks in pipes. | Time to complete | 15 minutes diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/system_profiling/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/system_profiling/README.md index 65e846380a..b18e099ab7 100644 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/system_profiling/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/system_profiling/README.md @@ -8,7 +8,7 @@ The [Intercept Layer for OpenCL™ Applications](https://github.com/intel/opencl | Optimized for | Description --- |--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler | What you will learn | Summary of profiling tools available for performance optimization
About the Intercept Layer for OpenCL™ Applications
How to set up and use this tool
A case study of using this tool to identify when the double buffering system-level optimization is beneficial | Time to complete | 30 minutes diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/use_library/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/use_library/CMakeLists.txt index f75666750d..1a61ae05c6 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/use_library/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/use_library/CMakeLists.txt @@ -60,8 +60,10 @@ else() set(DEVICE_FLAG "A10") elseif(FPGA_DEVICE_NAME MATCHES ".*s10.*" OR FPGA_DEVICE_NAME MATCHES ".*stratix10.*") set(DEVICE_FLAG "S10") - elseif(FPGA_DEVICE_NAME MATCHES ".*agilex.*") + elseif(FPGA_DEVICE_NAME MATCHES ".*agilex7.*") set(DEVICE_FLAG "Agilex7") + elseif(FPGA_DEVICE_NAME MATCHES ".*agilex5.*") + set(DEVICE_FLAG "Agilex5") elseif(FPGA_DEVICE_NAME MATCHES ".*cyclonev.*") set(DEVICE_FLAG "CycloneV") endif() @@ -70,8 +72,8 @@ endif() if(NOT DEFINED DEVICE_FLAG) message(FATAL_ERROR "An unrecognized or custom board was passed, but DEVICE_FLAG was not specified. \ - Please make sure you have set -DDEVICE_FLAG=A10, -DDEVICE_FLAG=S10, -DDEVICE_FLAG=CycloneV or \ - -DDEVICE_FLAG=Agilex7.") + Please make sure you have set -DDEVICE_FLAG=A10, -DDEVICE_FLAG=S10, -DDEVICE_FLAG=CycloneV, \ + -DDEVICE_FLAG=Agilex5, or -DDEVICE_FLAG=Agilex7.") endif() # Use cmake -DUSER_FPGA_FLAGS= to set extra flags for FPGA backend @@ -170,8 +172,10 @@ elseif(DEVICE_FLAG MATCHES S10) set(FAMILY "Stratix 10") elseif(DEVICE_FLAG MATCHES CycloneV) set(FAMILY "Cyclone V") +elseif(DEVICE_FLAG MATCHES Agilex5) + set(FAMILY "Agilex 5") else() - set(FAMILY "Agilex") + set(FAMILY "Agilex7") endif() # The RTL file (specified in lib_rtl_spec.xml) must be copied to the CMake working directory for the final stage of FPGA hardware compilation diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/use_library/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/use_library/README.md index 72dc5096b5..f31f79ce93 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/use_library/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/use_library/README.md @@ -15,7 +15,7 @@ This FPGA tutorial demonstrates how to build SYCL device libraries from RTL sour | Optimized for | Description |:--- |:--- | OS | Ubuntu* 20.04
RHEL*/CentOS* 8
SUSE* 15
Windows* 10
Windows Server* 2019 -| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs +| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs | Software | Intel® oneAPI DPC++/C++ Compiler > **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.