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Intan Technologies Rhythm Verilog HDL code
Verilog Coq
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ipcore_dir
.gitignore
ADC_input.v
DAC_output.v
DAC_output_scalable.v
DAC_output_scalable_HPF.v
LED_controller.v
LED_status.v
MISO_phase_selector.v
RAM_bank.v
RAM_block.v
RHD2000InterfaceXEM6010.xise
SDRAM_FIFO.v
TFIFO64x8a_64x8b.ngc
ddr2_state_machine.v
fifo_w16_2048_r64_512.ngc
fifo_w16_2048_r64_512.v
fifo_w64_512_r16_2048.ngc
fifo_w64_512_r16_2048.v
freqdiv.v
freqdiv_tb.v
iodrp_controller.v
iodrp_mcb_controller.v
main.v
mcb_raw_wrapper.v
mcb_soft_calibration.v
mcb_soft_calibration_top.v
memc3_infrastructure.v
memc3_wrapper.v
multiplier.ngc
multiplier.v
multiplier_18x18.ngc
multiplier_18x18.v
okBTPipeIn.ngc
okBTPipeOut.ngc
okCoreHarness.ngc
okLibrary.v
okPipeIn.ngc
okPipeOut.ngc
okTriggerIn.ngc
okTriggerOut.ngc
okWireIn.ngc
okWireOut.ngc
variable_freq_clk_generator.v
xem6010.ucf
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