From abe84794dea88db06ee97da63571c2ac140d934d Mon Sep 17 00:00:00 2001 From: Prem Shanker Jha Date: Thu, 20 Dec 2018 04:06:40 -0600 Subject: [PATCH] VDM(Part 2): CME hcode support for per quad VDM. If per quad VDM is enabled by hcode image build through CME header, CME downloads local pstate parameter block and repair rings in second block copy. If per quad VDM is not enabled CME retains legacy behavior. Key_Cronus_Test=PM_REGRESS Change-Id: I97112b6816657a8201d7b8122bca01909ca20aa5 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69971 Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: Cronus HW CI Tested-by: Hostboot CI Tested-by: FSP CI Jenkins Reviewed-by: Gregory S. Still Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA Reviewed-by: Jennifer A. Stofer --- .../procedures/hwp/lib/p9_hcd_memmap_base.H | 3 ++- .../cme/pstate_cme/p9_cme_thread_db.c | 13 ++++++++++-- .../ppe_closed/cme/stop_cme/p9_cme_img_edit.c | 13 ++++++++++++ .../cme/stop_cme/p9_cme_stop_init.c | 20 ++++++++++++++----- 4 files changed, 41 insertions(+), 8 deletions(-) diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H index 2e6f5c5a4..7417d69ae 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H +++ b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H @@ -46,7 +46,7 @@ /// Image Magic Numbers -HCD_CONST64(CPMR_MAGIC_NUMBER, ULL(0x43504d525f312e30)) // CPMR_1.0 +HCD_CONST64(CPMR_MAGIC_NUMBER, ULL(0x43504d525f322e30)) // CPMR_2.0 HCD_CONST64(CME_MAGIC_NUMBER , ULL(0x434d455f5f312e30)) // CME__1.0 HCD_CONST64(QPMR_MAGIC_NUMBER, ULL(0x51504d525f312e30)) // QPMR_1.0 @@ -434,6 +434,7 @@ HCD_CONST(CME_QM_FLAG_SYS_WOF_ENABLE, 0x1000) HCD_CONST(CME_QM_FLAG_SYS_DYN_FMIN_ENABLE, 0x0800) HCD_CONST(CME_QM_FLAG_SYS_DYN_FMAX_ENABLE, 0x0400) HCD_CONST(CME_QM_FLAG_SYS_JUMP_PROTECT, 0x0200) +HCD_CONST(CME_QM_FLAG_PER_QUAD_VDM_ENABLE, 0x0100) HCD_CONST(CME_QM_FLAG_PSTATE_PHANTOM_HALT_EN, 0x0001) /// CME Hcode diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c index 72ba30ef8..0c3f8cde2 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c +++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c @@ -386,9 +386,18 @@ void p9_cme_pstate_init() uint64_t eimr_clr = 0; uint64_t eimr_or = 0; uint32_t resclk_data; + uint32_t pstate_offset = 0; + + G_cmeHeader = (cmeHeader_t*)(CME_SRAM_HEADER_ADDR); + pstate_offset = G_cmeHeader->g_cme_pstate_region_offset; + + if( G_cmeHeader->g_cme_qm_mode_flags & CME_QM_FLAG_PER_QUAD_VDM_ENABLE ) + { + pstate_offset = G_cmeHeader->g_cme_pstate_offset << 5; + } + + G_lppb = (LocalPstateParmBlock*)(pstate_offset + CME_SRAM_BASE_ADDR); - G_cmeHeader = (cmeHeader_t*)(CME_SRAM_HEADER_ADDR); - G_lppb = (LocalPstateParmBlock*)(G_cmeHeader->g_cme_pstate_region_offset + CME_SRAM_BASE_ADDR); PK_TRACE_INF("PSTATE: Hdr=0x%x, LPPB=0x%x, Nominal_Freq_Mhz=%d ", (uint32_t)G_cmeHeader, (uint32_t)G_lppb, G_lppb->operating_points[NOMINAL].frequency_mhz); diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_img_edit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_img_edit.c index a7e4ad48a..ba6336abe 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_img_edit.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_img_edit.c @@ -26,6 +26,7 @@ #include #include #include +#include #include /* offsetof */ #include @@ -116,6 +117,18 @@ int main(int narg, char* argv[]) rewind(pSelfRest); printf(" Self Restore size %s : %d (0x%X)\n", argv[3], selfRestSize, selfRestSize); + time_t buildTime = time(NULL); + struct tm* headerTime = localtime(&buildTime); + uint32_t temp = (((headerTime->tm_year + 1900) << 16) | + ((headerTime->tm_mon + 1) << 8) | + (headerTime->tm_mday)); + + printf(" Build date : %X -> %04d/%02d/%02d (YYYY/MM/DD)\n", + temp, headerTime->tm_year + 1900, headerTime->tm_mon + 1, headerTime->tm_mday); + fseek ( pImage , CPMR_BUILD_DATE_BYTE, SEEK_SET ); + temp = htonl( temp ); + fwrite(&temp, sizeof(uint32_t), 1, pImage ); + fseek ( pImage , CPMR_SELF_RESTORE_OFFSET_BYTE , SEEK_SET ); temp = htonl( SELF_RESTORE_CPMR_OFFSET ); fwrite(&temp, sizeof(uint32_t), 1, pImage ); diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_init.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_init.c index ff2be8c09..5c7d86632 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_init.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_init.c @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2016,2018 */ +/* COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -42,6 +42,7 @@ p9_cme_stop_init() uint32_t exit_first = 0; uint32_t cme_flags = 0; uint32_t core_mask = 0; + uint32_t bce_cpy_len = 0; //-------------------------------------------------------------------------- // Parse CME Flags and Initialize Core States @@ -104,11 +105,20 @@ p9_cme_stop_init() cmeHeader_t* pCmeImgHdr = (cmeHeader_t*)(CME_SRAM_HEADER_ADDR); + if( pCmeImgHdr->g_cme_qm_mode_flags & CME_QM_FLAG_PER_QUAD_VDM_ENABLE ) + { + bce_cpy_len = pCmeImgHdr->g_cme_custom_length; + } + else + { + bce_cpy_len = pCmeImgHdr->g_cme_max_spec_ring_length; + } + //right now a blocking call. Need to confirm this. - start_cme_block_copy(CME_BCEBAR_1, - (CME_IMAGE_CPMR_OFFSET + (pCmeImgHdr->g_cme_core_spec_ring_offset << 5)), - pCmeImgHdr->g_cme_core_spec_ring_offset, - pCmeImgHdr->g_cme_max_spec_ring_length); + start_cme_block_copy( CME_BCEBAR_1, + (CME_IMAGE_CPMR_OFFSET + (pCmeImgHdr->g_cme_core_spec_ring_offset << 5)), + pCmeImgHdr->g_cme_core_spec_ring_offset, + bce_cpy_len ); PK_TRACE_DBG("Setup: BCE Check for Copy Completed");