From bc04b3a019b396db616d13607954f6152fb988f9 Mon Sep 17 00:00:00 2001 From: Yue Du Date: Mon, 21 Sep 2020 06:41:24 -0500 Subject: [PATCH] PFET: detect bad pfet through cme sgpe plumbling - checks for PFET Sense enable/disable ever being the same - check at STOP power on and power off - add FIT routine to peform check upon each interval - if checks fail, mark the core in a CME scratch reg and halt - CME halt is noticed by SGPE. SGPE checks the CME scratch reg for either core to be marked. Sets OCC LFIR[61] to id PFET issue. - Use CPMMR bit5:6 instead of scratch1 reg for pfet failure bits OCC LFIR bit will be used by p9_pm_callout to log PFET related errors by core. (not in this commit). Change-Id: I86a06ad951cbe879f06ace10cd40a0a484454f23 CQ:SW508755 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/104675 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Gregory S Still Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA Reviewed-by: NAREN A DEVAIAH --- .../p9/procedures/hwp/lib/p9_pm_hcd_flags.h | 4 ++ .../ppe_closed/cme/cme_panic_codes.h | 12 +++--- .../p9/procedures/ppe_closed/cme/p9_cme.h | 3 +- .../ppe_closed/cme/p9_cme_iota_main.c | 42 ++++++++++++++++--- .../cme/pstate_cme/p9_cme_intercme.c | 6 +-- .../cme/pstate_cme/p9_cme_thread_db.c | 20 ++++----- .../cme/pstate_cme/p9_cme_thread_pmcr.c | 4 +- .../cme/stop_cme/p9_cme_copy_scan_ring.c | 6 +-- .../cme/stop_cme/p9_cme_stop_entry.c | 36 +++++++++++++++- .../cme/stop_cme/p9_cme_stop_exit.c | 8 ++-- .../cme/stop_cme/p9_cme_stop_irq_handlers.c | 4 +- .../cme/stop_cme/p9_cme_stop_threads.c | 4 +- .../cme/stop_cme/p9_hcd_core_poweron.c | 41 ++++++++++++++++-- .../pgpe/pstate_gpe/p9_pgpe_irq_handlers.c | 35 +++++++++++++++- .../sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c | 10 ++++- 15 files changed, 187 insertions(+), 48 deletions(-) diff --git a/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h b/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h index 2deab0721..1f6182c0a 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h +++ b/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h @@ -102,6 +102,8 @@ enum PM_GPE_OCC_SCRATCH2_DEFS PGPE_SAFE_MODE_ERROR = 14, PM_DEBUG_HALT_ENABLE = 15, CORE_THROTTLE_CONTINUOUS_CHANGE_ENABLE = 16, + CME_PFET_DELAY_TO_TIMEOUT = 20, + CME_PFET_TIMEOUT_INJECTION = 21, PGPE_OP_TRACE_DISABLE = 24, PGPE_OP_TRACE_MEM_MODE = 25 @@ -130,6 +132,8 @@ enum PM_CME_FLAGS_DEFS CME_FLAGS_SAFE_MODE = 16, CME_FLAGS_PSTATES_SUSPENDED = 17, CME_FLAGS_DB0_COMM_RECV_STARVATION_CNT_ENABLED = 18, + CME_FLAGS_PFET_FIT_INJECTION = 20, + CME_FLAGS_PFET_TIMEOUT_INJECTION = 21, CME_FLAGS_SPWU_CHECK_ENABLE = 22, CME_FLAGS_BLOCK_ENTRY_STOP11 = 23, CME_FLAGS_PSTATES_ENABLED = 24, diff --git a/import/chips/p9/procedures/ppe_closed/cme/cme_panic_codes.h b/import/chips/p9/procedures/ppe_closed/cme/cme_panic_codes.h index 8c664dd83..bebbd225f 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/cme_panic_codes.h +++ b/import/chips/p9/procedures/ppe_closed/cme/cme_panic_codes.h @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2016,2018 */ +/* COPYRIGHT 2016,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -57,7 +57,7 @@ CME_PVREF_FAIL_DETECTED = 0x1c0d, CME_OCC_HEARTBEAT_LOST_DETECTED = 0x1c1c, CME_CORE_CHECKSTOP_DETECTED = 0x1c1d, CME_BAD_DD_LEVEL = 0x1c1e, -//_UNUSED_1c1f = 0x1c1f, +CME_BAD_PFET = 0x1c1f, // CME_STOP_EXIT_PHANTOM_WAKEUP = 0x1d00, // Stop Error CME_STOP_EXIT_BCE_SCOM_FAILED = 0x1d01, @@ -66,14 +66,14 @@ CME_STOP_EXIT_STARTCLK_FAILED = 0x1d03, CME_STOP_EXIT_STARTCLK_XSTOP_ERROR = 0x1d04, CME_STOP_EXIT_SCOM_RES_XSTOP_ERROR = 0x1d05, CME_STOP_SPWU_PROTOCOL_ERROR = 0x1d06, -//_UNUSED_1d07 = 0x1d07, +CME_PFET_ENTRY_SENSE_TIMEOUT = 0x1d07, CME_STOP_ENTRY_STOPCLK_FAILED = 0x1d08, CME_STOP_ENTRY_XSTOP_ERROR = 0x1d09, // NDD1 CME_STOP_ENTRY_TRAP_INJECT = 0x1d0a, CME_STOP_ENTRY_HANDOFF_LESSTHAN5 = 0x1d0d, -//_UNUSED_1d1c = 0x1d1c, -//_UNUSED_1d1d = 0x1d1d, -//_UNUSED_1d1e = 0x1d1e, +CME_PFET_EXIT_SENSE_TIMEOUT = 0x1d1c, +CME_PFET_EXIT_SENSE_TIMEOUT_INJECT = 0x1d1d, +CME_PFET_EXIT_SENSE_FIT_INJECT = 0x1d1e, //_UNUSED_1d1f = 0x1d1f, CME_PSTATE_RESCLK_ENABLED_AT_BOOT = 0x1e00, // Pstate Error diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme.h b/import/chips/p9/procedures/ppe_closed/cme/p9_cme.h index 314889f72..5d95fad4c 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme.h +++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme.h @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2017,2018 */ +/* COPYRIGHT 2017,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -42,6 +42,7 @@ extern uint32_t G_CME_LCL_FLAGS; extern uint32_t G_CME_LCL_FLAGS_CLR; extern uint32_t G_CME_LCL_FLAGS_OR; extern uint32_t G_CME_LCL_SRTCH0; +extern uint32_t G_CME_LCL_SRTCH1; extern uint32_t G_CME_LCL_TSEL; extern uint32_t G_CME_LCL_TBR; extern uint32_t G_CME_LCL_DBG; diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_iota_main.c b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_iota_main.c index 1c81eacd0..15bbc63b3 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_iota_main.c +++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_iota_main.c @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2017,2019 */ +/* COPYRIGHT 2017,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -61,6 +61,7 @@ uint32_t G_CME_LCL_FLAGS = CME_LCL_FLAGS; uint32_t G_CME_LCL_FLAGS_CLR = CME_LCL_FLAGS_CLR; uint32_t G_CME_LCL_FLAGS_OR = CME_LCL_FLAGS_OR; uint32_t G_CME_LCL_SRTCH0 = CME_LCL_SRTCH0; +uint32_t G_CME_LCL_SRTCH1 = CME_LCL_SRTCH1; uint32_t G_CME_LCL_TSEL = CME_LCL_TSEL; uint32_t G_CME_LCL_TBR = CME_LCL_TBR; uint32_t G_CME_LCL_DBG = CME_LCL_DBG; @@ -88,6 +89,35 @@ void fit_handler() data64_t scom_data; scom_data.value = 0; + if( in32(G_CME_LCL_FLAGS) & BIT32(CME_FLAGS_PFET_FIT_INJECTION) ) + { + // Inject Core 0 as bad + CME_PUTSCOM_NOP(CPPM_CPMMR_OR, CME_MASK_C0, BIT64(5)); + PK_PANIC(CME_PFET_EXIT_SENSE_FIT_INJECT); + } + + CME_GETSCOM(PPM_PFSNS, CME_MASK_C0, scom_data); + + if( ( ( ( scom_data.words.upper & BIT32(0) ) == 1 ) && + ( ( scom_data.words.upper & BIT32(1) ) == 1 ) ) || + ( ( ( scom_data.words.upper & BIT32(0) ) == 0 ) && + ( ( scom_data.words.upper & BIT32(1) ) == 0 ) ) ) + { + CME_PUTSCOM_NOP(CPPM_CPMMR_OR, CME_MASK_C0, BIT64(5)); + PK_PANIC(CME_BAD_PFET); + } + + CME_GETSCOM(PPM_PFSNS, CME_MASK_C1, scom_data); + + if( ( ( ( scom_data.words.upper & BIT32(0) ) == 1 ) && + ( ( scom_data.words.upper & BIT32(1) ) == 1 ) ) || + ( ( ( scom_data.words.upper & BIT32(0) ) == 0 ) && + ( ( scom_data.words.upper & BIT32(1) ) == 0 ) ) ) + { + CME_PUTSCOM_NOP(CPPM_CPMMR_OR, CME_MASK_C1, BIT64(6)); + PK_PANIC(CME_BAD_PFET); + } + CME_GETSCOM_OR(CPPM_CSAR, CME_MASK_BC, scom_data.value); if(BIT32(CPPM_CSAR_FIT_HCODE_ERROR_INJECT) & scom_data.words.upper) @@ -98,7 +128,7 @@ void fit_handler() mtspr(SPRN_TSR, TSR_FIS); - PK_TRACE("FIT Timer Handler"); + //PK_TRACE("FIT Timer Handler"); #if !DISABLE_PERIODIC_CORE_QUIESCE && (NIMBUS_DD_LEVEL == 20 || NIMBUS_DD_LEVEL == 21 || CUMULUS_DD_LEVEL == 10) p9_cme_core_livelock_buster(); @@ -198,7 +228,7 @@ int main() pk_trace_set_freq(trace_timebase); - PK_TRACE(">CME MAIN"); + // PK_TRACE(">CME MAIN"); // Clear SPRG0 ppe42_app_ctx_set(0); @@ -212,7 +242,7 @@ int main() out32(G_CME_LCL_LMCR_OR, BITS32(8, 2)); #endif - PK_TRACE("Set Watch Dog Timer Rate to 6 and FIT Timer Rate to 8"); + // PK_TRACE("Set Watch Dog Timer Rate to 6 and FIT Timer Rate to 8"); out32(G_CME_LCL_TSEL, (BITS32(1, 2) | BIT32(4))); #if (!DISABLE_CME_FIT_TIMER || ENABLE_CME_DEC_TIMER) @@ -220,12 +250,12 @@ int main() uint32_t TCR_VAL = 0; #if !DISABLE_CME_FIT_TIMER - PK_TRACE("Enable FIT Timer"); + // PK_TRACE("Enable FIT Timer"); TCR_VAL |= TCR_FIE; #endif #if ENABLE_CME_DEC_TIMER - PK_TRACE("Enable DEC Timer"); + // PK_TRACE("Enable DEC Timer"); TCR_VAL |= TCR_DIE; #endif diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c index 9497442c9..579db457b 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c +++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2016,2019 */ +/* COPYRIGHT 2016,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -63,7 +63,7 @@ void p9_cme_pstate_intercme_msg_handler(void) void p9_cme_pstate_sibling_lock_and_intercme_protocol(INTERCME_MSG_LOCK_ACTION intercme_msg_lock_action) { - PK_TRACE_INF("SIBL: Enter"); + PK_TRACE_DBG("SIBL: Enter"); uint32_t msg; if (intercme_msg_lock_action == INTERCME_MSG_LOCK_WAIT_ON_RECV) @@ -101,7 +101,7 @@ void p9_cme_pstate_process_db0_sibling() //writes same value for both cores CME_GETSCOM(CPPM_CMEDB0, G_cme_pstate_record.firstGoodCoreMask, dbData.value); - PK_TRACE_INF("INTER0: Enter"); + PK_TRACE_DBG("INTER0: Enter"); dbQuadInfo = (dbData.value >> (in32(G_CME_LCL_SRTCH0) & (BITS32(CME_SCRATCH_LOCAL_PSTATE_IDX_START, CME_SCRATCH_LOCAL_PSTATE_IDX_LENGTH) diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c index 1d40203aa..d177495e2 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c +++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2016,2019 */ +/* COPYRIGHT 2016,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -368,7 +368,7 @@ void p9_cme_pstate_db3_handler(void) } else if (db3.fields.cme_message_numbern == MSGID_DB3_CLIP_BROADCAST) { - PK_TRACE_INF("PSTATE: DB3 Clip Enter"); + PK_TRACE_DBG("PSTATE: DB3 Clip Enter"); uint32_t dbQuadInfo, dbBit8_15; cppm_cmedb0_t dbData; @@ -732,7 +732,7 @@ void p9_cme_pstate_process_db0() //Clear out db0_pending_tick_count g_db0_pending_fit_tick_count = 0; - PK_TRACE_INF("PSTATE: Process DB0 Enter"); + PK_TRACE_DBG("PSTATE: Process DB0 Enter"); //Clear EISR and read DB0 register out32_sh(CME_LCL_EISR_CLR, BITS64SH(36, 2)); @@ -942,7 +942,7 @@ inline void p9_cme_pstate_register() // void p9_cme_pstate_db0_start() { - PK_TRACE_INF("PSTATE: DB0 Start Enter"); + PK_TRACE_DBG("PSTATE: DB0 Start Enter"); p9_cme_pstate_update(); uint32_t ack; @@ -989,7 +989,7 @@ void p9_cme_pstate_db0_start() // void p9_cme_pstate_db0_glb_bcast() { - PK_TRACE_INF("PSTATE: DB0 GlbBcast Enter"); + PK_TRACE_DBG("PSTATE: DB0 GlbBcast Enter"); p9_cme_pstate_update(); uint32_t ack; @@ -1015,7 +1015,7 @@ void p9_cme_pstate_db0_glb_bcast() // inline void p9_cme_pstate_db0_stop() { - PK_TRACE_INF("PSTATE: DB0 Stop Enter"); + PK_TRACE_DBG("PSTATE: DB0 Stop Enter"); out32(G_CME_LCL_FLAGS_CLR, BIT32(24));//Set Pstates Disabled @@ -1045,7 +1045,7 @@ inline void p9_cme_pstate_db0_stop() void p9_cme_pstate_db0_clip_bcast() { - PK_TRACE_INF("PSTATE: DB0 Clip Enter"); + PK_TRACE_DBG("PSTATE: DB0 Clip Enter"); uint32_t dbBit8_15 = (G_dbData.value & BITS64(8, 8)) >> SHIFT64(15); @@ -1082,7 +1082,7 @@ void p9_cme_pstate_db0_clip_bcast() inline void p9_cme_pstate_db0_pmsr_updt() { - PK_TRACE_INF("PSTATE: DB0 Pmsr Updt Enter"); + PK_TRACE_DBG("PSTATE: DB0 Pmsr Updt Enter"); uint32_t dbBit8_15 = (G_dbData.value & BITS64(8, 8)) >> SHIFT64(15); @@ -1129,7 +1129,7 @@ inline void p9_cme_pstate_freq_update(uint32_t cme_flags) } else { - PK_TRACE_INF("PSTATE: Freq Updt Enter"); + PK_TRACE_DBG("PSTATE: Freq Updt Enter"); PK_TRACE_DBG("PSTATE: Dpll0=0x%x", G_lppb->dpll_pstate0_value); //Adjust DPLL @@ -1237,7 +1237,7 @@ void p9_cme_pstate_update() { PkMachineContext ctx; - PK_TRACE_INF("PSTATE: Pstate Updt Enter"); + PK_TRACE_DBG("PSTATE: Pstate Updt Enter"); G_cme_pstate_record.nextPstate = (G_dbData.value >> (in32(G_CME_LCL_SRTCH0) & (BITS32(CME_SCRATCH_LOCAL_PSTATE_IDX_START, diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_pmcr.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_pmcr.c index f47658f1f..05d78e1ef 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_pmcr.c +++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_pmcr.c @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2016,2018 */ +/* COPYRIGHT 2016,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -94,7 +94,7 @@ void p9_cme_pstate_pmcr_handler(void) // void p9_cme_init_done() { - PK_TRACE_INF("CME INIT DONE: Enter"); + PK_TRACE_DBG("CME INIT DONE: Enter"); uint32_t msg; // Synchronization between QM and Sibling diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.c index 8daf99db4..52619ba59 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.c @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2015,2018 */ +/* COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -179,8 +179,8 @@ void bce_irr_run() if (l_data32 != G_bce_irr.data.word) { - PKTRACE("miscompare between bce irr read[%x] and cme shadow copy[%x]", - l_data32, G_bce_irr.data.word); + PK_TRACE_DBG("miscompare between bce irr read[%x] and cme shadow copy[%x]", + l_data32, G_bce_irr.data.word); pk_halt(); } diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c index ab2e92d1e..a2bec1ba9 100755 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2015,2019 */ +/* COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -224,6 +224,8 @@ void p9_cme_pcbmux_savior_epilogue(uint32_t core) void p9_cme_stop_entry() { + int i = 0; + uint32_t timeout = 0; int catchup_ongoing = 0; int entry_ongoing = 1; uint8_t target_level = 0; @@ -1441,9 +1443,39 @@ p9_cme_stop_entry() PK_PANIC(CME_STOP_ENTRY_TRAP_INJECT); } + //500Mhz gives 2ns per ppe cycle + //pfet or stop should finish within 1ms + //set delay to 20ns +#define PFET_DELAY 20 +#define PFET_TIMEOUT 20000 + + timeout = PFET_TIMEOUT; + do { CME_GETSCOM_AND(PPM_PFSNS, core, scom_data.value); + + timeout--; + + if( !timeout ) + { + CME_PUTSCOM_NOP(CPPM_CPMMR_OR, core, ((uint64_t)(core) << SHIFT64(6))); + //PK_TRACE_ERR("PFET SENSE TIMED OUT, HALT CME!"); + +// if( in32(G_CME_LCL_FLAGS) & BIT32(CME_FLAGS_PFET_DELAY_TO_TIMEOUT) ) +// { + PK_PANIC(CME_PFET_ENTRY_SENSE_TIMEOUT); +// } +// else +// { +// break; +// } + } + + for(i = 0; i < PFET_DELAY; i++) + { + asm volatile ("tw 0, 0, 0"); + } } while(!(scom_data.words.upper & BIT32(1))); @@ -1451,7 +1483,7 @@ p9_cme_stop_entry() // vdd_pfet_force_state = 00 (Nop) CME_PUTSCOM(PPM_PFCS_CLR, core, BITS64(0, 2)); - PK_TRACE_INF("SE.4A: Core[%d] Powered Off", core); + PK_TRACE_DBG("SE.4A: Core[%d] Powered Off", core); #endif diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c index ab305ff42..ca8ea5fc0 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c @@ -1251,13 +1251,13 @@ p9_cme_stop_self_execute(uint32_t core, uint32_t i_saveRestore ) #else CME_PUTSCOM(URMOR, core, scom_data.value); - PK_TRACE_INF("SMF core wakes up, write URMOR with HOMER address" ); + PK_TRACE_DBG("SMF core wakes up, write URMOR with HOMER address" ); scom_data.words.upper = scom_data.words.upper & ~BIT32(15); if( SPR_SELF_SAVE == i_saveRestore ) { scom_data.value = pCmeImgHdr->g_cme_unsec_cpmr_PhyAddr & BITS64(13, 30); //Unsecure HOMER - PKTRACE("SMF core self save, write un-secure HOMER address"); + PK_TRACE_DBG("SMF core self save, write un-secure HOMER address"); } CME_PUTSCOM(HRMOR, core, scom_data.value); @@ -1271,7 +1271,7 @@ p9_cme_stop_self_execute(uint32_t core, uint32_t i_saveRestore ) CME_PUTSCOM(HRMOR, core, 0xA200000); #else - PK_TRACE_INF("Non SMF core wakes up, write HRMOR with HOMER address"); + PK_TRACE_DBG("Non SMF core wakes up, write HRMOR with HOMER address"); scom_data.words.upper = scom_data.words.upper & ~BIT32(15); CME_PUTSCOM(HRMOR, core, scom_data.value); @@ -1353,7 +1353,7 @@ p9_cme_stop_self_execute(uint32_t core, uint32_t i_saveRestore ) wrteei(1); - PK_TRACE_INF("Allow threads to run(pm_exit=0)"); + PK_TRACE_DBG("Allow threads to run(pm_exit=0)"); out32(G_CME_LCL_SICR_CLR, core << SHIFT32(5)); } diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c index 7f82bb8de..7c9b7653b 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2015,2019 */ +/* COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -165,7 +165,7 @@ p9_cme_stop_spwu_handler(void) else { out32(G_CME_LCL_SICR_CLR, BIT32((4 + core_index))); - PK_TRACE_INF("SPWU drop confirmed, now drop pm_exit"); + PK_TRACE_DBG("SPWU drop confirmed, now drop pm_exit"); // Core is now out of spwu, allow pm_active // block entry mode is handled via eimr override diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_threads.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_threads.c index b03b11a66..d10f14672 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_threads.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_threads.c @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2015,2018 */ +/* COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -352,7 +352,7 @@ void periodic_core_quiesce_workaround(uint32_t core_instruction_running) } else { - PK_TRACE_INF("PCQW: Error while trying to Quiesce Cores. Bad Error %d, QuiesceTime (ns) %d", sample_error, + PK_TRACE_DBG("PCQW: Error while trying to Quiesce Cores. Bad Error %d, QuiesceTime (ns) %d", sample_error, (G_cme_fit_record.core_quiesce_time_latest << 5)); G_cme_fit_record.core_quiesce_failed_count++; } diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c index 3e762b8e9..cfd2bceb5 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2015,2018 */ +/* COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -29,6 +29,9 @@ inline __attribute__((always_inline)) void p9_hcd_core_poweron(uint32_t core) { + uint32_t timeout = 0; + uint32_t i = 0; + PK_TRACE("Assert PCB fence via NET_CTRL0[25]"); CME_PUTSCOM(CPPM_NC0INDIR_OR, core, BIT64(25)); @@ -46,23 +49,53 @@ p9_hcd_core_poweron(uint32_t core) // vdd_pfet_val/sel_override = 0 (disbaled) // vdd_pfet_regulation_finger_en = 0 (controled by FSM) - PK_TRACE("Prepare PFET Controls"); + // PK_TRACE("Prepare PFET Controls"); CME_PUTSCOM(PPM_PFCS_CLR, core, BIT64(4) | BIT64(5) | BIT64(8)); // vdd_pfet_force_state = 11 (Force Von) - PK_TRACE("Power On Core VDD"); + // PK_TRACE("Power On Core VDD"); CME_PUTSCOM(PPM_PFCS_OR, core, BITS64(0, 2)); PK_TRACE("Poll for vdd_pfets_enabled_sense"); + if( in32(G_CME_LCL_FLAGS) & BIT32(CME_FLAGS_PFET_TIMEOUT_INJECTION) ) + { + //PK_TRACE_ERR("INJECT PFET SENSE TIMED OUT, HALT CME!"); + // Inject Core 1 as bad + CME_PUTSCOM_NOP(CPPM_CPMMR_OR, core, BIT64(6)); + PK_PANIC(CME_PFET_EXIT_SENSE_TIMEOUT_INJECT); + } + + //500Mhz gives 2ns per ppe cycle + //pfet or stop should finish within 1ms + //set delay to 20ns +#define PFET_DELAY 20 +#define PFET_TIMEOUT 20000 + + timeout = PFET_TIMEOUT; + do { CME_GETSCOM_AND(PPM_PFSNS, core, scom_data); + + timeout--; + + if( !timeout ) + { + CME_PUTSCOM_NOP(CPPM_CPMMR_OR, core, ((uint64_t)(core) << SHIFT64(6))); + //PK_TRACE_ERR("PFET SENSE TIMED OUT, HALT CME!"); + PK_PANIC(CME_PFET_EXIT_SENSE_TIMEOUT); + } + + for(i = 0; i < PFET_DELAY; i++) + { + asm volatile ("tw 0, 0, 0"); + } } while(!(scom_data & BIT64(0))); // vdd_pfet_force_state = 00 (Nop) - PK_TRACE("Turn Off Force Von"); + // PK_TRACE("Turn Off Force Von"); CME_PUTSCOM(PPM_PFCS_CLR, core, BITS64(0, 2)); #endif } diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c index 322727957..a0577a574 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c +++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2016,2019 */ +/* COPYRIGHT 2016,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -448,8 +448,11 @@ void p9_pgpe_irq_handler_cme_err() uint64_t value, baseVal, coreSsh; qppm_dpll_freq_t dpllFreq; ocb_qcsr_t qcsr; + ocb_ccsr_t ccsr; qcsr.value = in32(G_OCB_QCSR); + ccsr.value = in32(OCB_CCSR); uint64_t cme_flags = 0; + uint64_t cme_cpmmr = 0; //Optrace G_pgpe_optrace_data.word[0] = (G_pgpe_pstate_record.activeQuads << 24) | @@ -483,18 +486,46 @@ void p9_pgpe_irq_handler_cme_err() PK_TRACE_INF("CER:Quad[%d]", q); - //1.1 Halt both CMEs in the quad containing faulted CME, if (qcsr.fields.ex_config & QUAD_EX0_MASK(q)) { GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_XIXCR, q, 0), BIT64(3)); //XCR[1:3] = 001(Halt the CME) GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_FLAGS, q, 0), cme_flags); + + for (c = FIRST_CORE_FROM_QUAD(q); c < LAST_CORE_FROM_QUAD(q); c++) + { + if (ccsr.value & CORE_MASK(c)) + { + GPE_GETSCOM(GPE_SCOM_ADDR_CORE(CPPM_CPMMR, c), cme_cpmmr); + + if( cme_cpmmr & BITS64(5, 2) ) + { + GPE_PUTSCOM(OCB_OCCLFIR_OR, BIT64(61)); + } + } + } + } if (qcsr.fields.ex_config & QUAD_EX1_MASK(q)) { GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_XIXCR, q, 1), BIT64(3)); //XCR[1:3] = 001(Halt the CME) + for (c = FIRST_CORE_FROM_QUAD(q); c < LAST_CORE_FROM_QUAD(q); c++) + { + if (ccsr.value & CORE_MASK(c)) + { + GPE_GETSCOM(GPE_SCOM_ADDR_CORE(CPPM_CPMMR, c), cme_cpmmr); + + if( cme_cpmmr & BITS64(5, 2) ) + { + GPE_PUTSCOM(OCB_OCCLFIR_OR, BIT64(61)); + } + } + } + + + //Read CME1 CME_FLAGS, if CME0 not configured if (!(qcsr.fields.ex_config & QUAD_EX0_MASK(q))) { diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c index 65e8533ee..23226085b 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2015,2018 */ +/* COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -384,6 +384,14 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme ) continue; } + /* + uint64_t DavidData = in32(G_OCB_OCCS2) & BITS32(20, 2); + DavidData = DavidData << 32; + + GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_FLAGS_OR, + (l_cmeIndex >> 1), (l_cmeIndex % 2)), DavidData); + */ + // Clear CME LFIR[5] (ppe_halted) upon respective CME boot GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LFIR_AND, (l_cmeIndex >> 1), (l_cmeIndex % 2)), ~BIT64(5));